1 From 66caecfcf414d8e5153a0725195413db3c992dae Mon Sep 17 00:00:00 2001
2 From: kFYatek <4499762+kFYatek@users.noreply.github.com>
3 Date: Wed, 23 Jun 2021 01:11:26 +0200
4 Subject: [PATCH] drm/vc4: Fix timings for interlaced modes
6 Increase the number of post-sync blanking lines on odd fields instead of
7 decreasing it on even fields. This makes the total number of lines
8 properly match the modelines.
10 Additionally fix the value of PV_VCONTROL_ODD_DELAY, which did not take
11 pixels_per_clock into account, causing some displays to invert the
12 fields when driven by bcm2711.
14 Signed-off-by: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com>
16 drivers/gpu/drm/vc4/vc4_crtc.c | 7 ++++---
17 drivers/gpu/drm/vc4/vc4_hdmi.c | 12 ++++++------
18 2 files changed, 10 insertions(+), 9 deletions(-)
20 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
21 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
22 @@ -344,7 +344,8 @@ static void vc4_crtc_config_pv(struct dr
26 - VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
27 + VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
30 VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
32 @@ -356,7 +357,7 @@ static void vc4_crtc_config_pv(struct dr
34 CRTC_WRITE(PV_VERTA_EVEN,
35 VC4_SET_FIELD(mode->crtc_vtotal -
36 - mode->crtc_vsync_end - 1,
37 + mode->crtc_vsync_end,
39 VC4_SET_FIELD(mode->crtc_vsync_end -
40 mode->crtc_vsync_start,
41 @@ -376,7 +377,7 @@ static void vc4_crtc_config_pv(struct dr
42 PV_VCONTROL_CONTINUOUS |
43 (is_dsi ? PV_VCONTROL_DSI : 0) |
44 PV_VCONTROL_INTERLACE |
45 - VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
46 + VC4_SET_FIELD(mode->htotal * pixel_rep / (2 * ppc),
47 PV_VCONTROL_ODD_DELAY));
48 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
50 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
51 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
52 @@ -840,12 +840,12 @@ static void vc4_hdmi_set_timings(struct
54 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
55 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
56 - VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
57 + VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
60 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
61 VC4_SET_FIELD(mode->crtc_vtotal -
62 - mode->crtc_vsync_end -
64 + mode->crtc_vsync_end,
68 @@ -891,12 +891,12 @@ static void vc5_hdmi_set_timings(struct
70 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
71 u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
72 - VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
73 + VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
76 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
77 VC4_SET_FIELD(mode->crtc_vtotal -
78 - mode->crtc_vsync_end -
80 + mode->crtc_vsync_end,