1 From ef94081204ede8c11a28b3c3713c54fee6bc6fea Mon Sep 17 00:00:00 2001
2 From: Maxime Ripard <maxime@cerno.tech>
3 Date: Fri, 4 Dec 2020 17:12:06 +0100
4 Subject: [PATCH] drm/vc4: hdmi: Support HDMI YUV output
6 In addition to the RGB444 output, the BCM2711 HDMI controller supports
7 the YUV444 and YUV422 output formats.
9 Let's add support for them in the driver, but still use RGB as the
12 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
14 drivers/gpu/drm/vc4/vc4_hdmi.c | 289 ++++++++++++++++++++++++++--
15 drivers/gpu/drm/vc4/vc4_hdmi.h | 14 ++
16 drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 6 +
17 drivers/gpu/drm/vc4/vc4_regs.h | 16 ++
18 4 files changed, 309 insertions(+), 16 deletions(-)
20 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
21 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
24 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000)
26 +static const char * const output_format_str[] = {
27 + [VC4_HDMI_OUTPUT_RGB] = "RGB",
28 + [VC4_HDMI_OUTPUT_YUV420] = "YUV 4:2:0",
29 + [VC4_HDMI_OUTPUT_YUV422] = "YUV 4:2:2",
30 + [VC4_HDMI_OUTPUT_YUV444] = "YUV 4:4:4",
33 +static const char *vc4_hdmi_output_fmt_str(enum vc4_hdmi_output_format fmt)
35 + if (fmt >= ARRAY_SIZE(output_format_str))
38 + return output_format_str[fmt];
41 static unsigned long long
42 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
44 + unsigned int bpc, enum vc4_hdmi_output_format fmt);
46 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode,
49 + enum vc4_hdmi_output_format fmt)
51 - unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc);
52 + unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
54 return clock > HDMI_14_MAX_TMDS_CLK;
56 @@ -285,7 +300,7 @@ static int vc4_hdmi_connector_get_modes(
57 struct drm_display_mode *mode;
59 list_for_each_entry(mode, &connector->probed_modes, head) {
60 - if (vc4_hdmi_mode_needs_scrambling(mode, 8)) {
61 + if (vc4_hdmi_mode_needs_scrambling(mode, 8, VC4_HDMI_OUTPUT_RGB)) {
62 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
63 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
65 @@ -342,6 +357,7 @@ static void vc4_hdmi_connector_reset(str
67 new_state->base.max_bpc = 8;
68 new_state->base.max_requested_bpc = 8;
69 + new_state->output_format = VC4_HDMI_OUTPUT_RGB;
70 drm_atomic_helper_connector_tv_reset(connector);
73 @@ -358,6 +374,7 @@ vc4_hdmi_connector_duplicate_state(struc
75 new_state->pixel_rate = vc4_state->pixel_rate;
76 new_state->output_bpc = vc4_state->output_bpc;
77 + new_state->output_format = vc4_state->output_format;
78 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
80 return &new_state->base;
81 @@ -511,11 +528,38 @@ static void vc4_hdmi_write_infoframe(str
82 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
85 +static void vc4_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
86 + enum vc4_hdmi_output_format fmt)
89 + case VC4_HDMI_OUTPUT_RGB:
90 + frame->colorspace = HDMI_COLORSPACE_RGB;
93 + case VC4_HDMI_OUTPUT_YUV420:
94 + frame->colorspace = HDMI_COLORSPACE_YUV420;
97 + case VC4_HDMI_OUTPUT_YUV422:
98 + frame->colorspace = HDMI_COLORSPACE_YUV422;
101 + case VC4_HDMI_OUTPUT_YUV444:
102 + frame->colorspace = HDMI_COLORSPACE_YUV444;
110 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
112 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
113 struct drm_connector *connector = &vc4_hdmi->connector;
114 struct drm_connector_state *cstate = connector->state;
115 + struct vc4_hdmi_connector_state *vc4_state =
116 + conn_state_to_vc4_hdmi_conn_state(cstate);
117 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
118 union hdmi_infoframe frame;
120 @@ -535,6 +579,7 @@ static void vc4_hdmi_set_avi_infoframe(s
121 HDMI_QUANTIZATION_RANGE_FULL :
122 HDMI_QUANTIZATION_RANGE_LIMITED);
123 drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate);
124 + vc4_hdmi_avi_infoframe_colorspace(&frame.avi, vc4_state->output_format);
125 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
127 vc4_hdmi_write_infoframe(encoder, &frame);
128 @@ -637,7 +682,9 @@ static void vc4_hdmi_enable_scrambling(s
129 if (!vc4_hdmi_supports_scrambling(encoder, mode))
132 - if (!vc4_hdmi_mode_needs_scrambling(mode, vc4_hdmi->output_bpc))
133 + if (!vc4_hdmi_mode_needs_scrambling(mode,
134 + vc4_hdmi->output_bpc,
135 + vc4_hdmi->output_format))
138 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
139 @@ -825,6 +872,38 @@ static const u16 vc5_hdmi_csc_full_rgb_t
140 { 0x0000, 0x0000, 0x1b80, 0x0400 },
144 + * Conversion between Full Range RGB and Full Range YUV422 using the
145 + * BT.709 Colorspace
147 + * [ 0.212639 0.715169 0.072192 0 ]
148 + * [ -0.117208 -0.394207 0.511416 128 ]
149 + * [ 0.511416 -0.464524 -0.046891 128 ]
151 + * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
153 +static const u16 vc5_hdmi_csc_full_rgb_to_full_yuv422_bt709[3][4] = {
154 + { 0x06ce, 0x16e3, 0x024f, 0x0000 },
155 + { 0xfc41, 0xf364, 0x105e, 0x2000 },
156 + { 0x105e, 0xf124, 0xfe81, 0x2000 },
160 + * Conversion between Full Range RGB and Full Range YUV444 using the
161 + * BT.709 Colorspace
163 + * [ -0.117208 -0.394207 0.511416 128 ]
164 + * [ 0.511416 -0.464524 -0.046891 128 ]
165 + * [ 0.212639 0.715169 0.072192 0 ]
167 + * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
169 +static const u16 vc5_hdmi_csc_full_rgb_to_full_yuv444_bt709[3][4] = {
170 + { 0xfc41, 0xf364, 0x105e, 0x2000 },
171 + { 0x105e, 0xf124, 0xfe81, 0x2000 },
172 + { 0x06ce, 0x16e3, 0x024f, 0x0000 },
175 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi,
176 const u16 coeffs[3][4])
178 @@ -842,19 +921,53 @@ static void vc5_hdmi_csc_setup(struct vc
179 struct drm_connector_state *state,
180 const struct drm_display_mode *mode)
182 + struct vc4_hdmi_connector_state *vc4_state =
183 + conn_state_to_vc4_hdmi_conn_state(state);
186 + u32 if_xbar = 0x543210;
187 + u32 csc_chan_ctl = 0;
188 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
189 VC5_MT_CP_CSC_CTL_MODE);
191 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
193 - HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
194 + switch (vc4_state->output_format) {
195 + case VC4_HDMI_OUTPUT_YUV444:
196 + vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_full_yuv444_bt709);
199 + case VC4_HDMI_OUTPUT_YUV422:
200 + csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD,
201 + VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) |
202 + VC5_MT_CP_CSC_CTL_USE_444_TO_422 |
203 + VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION;
205 - if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode))
206 - vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_rgb);
208 - vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_unity);
209 + csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE,
210 + VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP);
212 + if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY,
213 + VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422);
215 + vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_full_yuv422_bt709);
218 + case VC4_HDMI_OUTPUT_RGB:
219 + if_xbar = 0x354021;
221 + if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode))
222 + vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_rgb);
224 + vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_unity);
231 + HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg);
232 + HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar);
233 + HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl);
234 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
236 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
237 @@ -980,6 +1093,15 @@ static void vc5_hdmi_set_timings(struct
242 + * YCC422 is always 36-bit and not considered deep colour so
243 + * doesn't signal in GCP
245 + if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) {
250 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
251 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
252 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
253 @@ -1259,12 +1381,97 @@ static void vc4_hdmi_encoder_atomic_mode
255 mutex_lock(&vc4_hdmi->mutex);
256 vc4_hdmi->output_bpc = vc4_state->output_bpc;
257 + vc4_hdmi->output_format = vc4_state->output_format;
258 memcpy(&vc4_hdmi->saved_adjusted_mode,
259 &crtc_state->adjusted_mode,
260 sizeof(vc4_hdmi->saved_adjusted_mode));
261 mutex_unlock(&vc4_hdmi->mutex);
265 +vc4_hdmi_sink_supports_format_bpc(const struct vc4_hdmi *vc4_hdmi,
266 + const struct drm_display_info *info,
267 + const struct drm_display_mode *mode,
268 + unsigned int format, unsigned int bpc)
270 + struct drm_device *dev = vc4_hdmi->connector.dev;
271 + u8 vic = drm_match_cea_mode(mode);
273 + if (vic == 1 && bpc != 8) {
274 + drm_dbg(dev, "VIC1 requires a bpc of 8, got %u\n", bpc);
278 + if (!info->is_hdmi &&
279 + (format != VC4_HDMI_OUTPUT_RGB || bpc != 8)) {
280 + drm_dbg(dev, "DVI Monitors require an RGB output at 8 bpc\n");
285 + case VC4_HDMI_OUTPUT_RGB:
286 + drm_dbg(dev, "RGB Format, checking the constraints.\n");
288 + if (!(info->color_formats & DRM_COLOR_FORMAT_RGB444))
291 + if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) {
292 + drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
296 + if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) {
297 + drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
301 + drm_dbg(dev, "RGB format supported in that configuration.\n");
305 + case VC4_HDMI_OUTPUT_YUV422:
306 + drm_dbg(dev, "YUV422 format, checking the constraints.\n");
308 + if (!(info->color_formats & DRM_COLOR_FORMAT_YCRCB422)) {
309 + drm_dbg(dev, "Sink doesn't support YUV422.\n");
314 + drm_dbg(dev, "YUV422 only supports 12 bpc.\n");
318 + drm_dbg(dev, "YUV422 format supported in that configuration.\n");
322 + case VC4_HDMI_OUTPUT_YUV444:
323 + drm_dbg(dev, "YUV444 format, checking the constraints.\n");
325 + if (!(info->color_formats & DRM_COLOR_FORMAT_YCRCB444)) {
326 + drm_dbg(dev, "Sink doesn't support YUV444.\n");
330 + if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) {
331 + drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
335 + if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) {
336 + drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
340 + drm_dbg(dev, "YUV444 format supported in that configuration.\n");
348 static enum drm_mode_status
349 vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi,
350 unsigned long long clock)
351 @@ -1286,13 +1493,17 @@ vc4_hdmi_encoder_clock_valid(const struc
353 static unsigned long long
354 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
357 + enum vc4_hdmi_output_format fmt)
359 unsigned long long clock = mode->crtc_clock * 1000;
361 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
364 + if (fmt == VC4_HDMI_OUTPUT_YUV422)
367 return clock * bpc / 8;
370 @@ -1300,11 +1511,11 @@ static int
371 vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi,
372 struct vc4_hdmi_connector_state *vc4_state,
373 const struct drm_display_mode *mode,
375 + unsigned int bpc, unsigned int fmt)
377 unsigned long long clock;
379 - clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc);
380 + clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
381 if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, clock) != MODE_OK)
384 @@ -1314,10 +1525,55 @@ vc4_hdmi_encoder_compute_clock(const str
388 +vc4_hdmi_encoder_compute_format(const struct vc4_hdmi *vc4_hdmi,
389 + struct vc4_hdmi_connector_state *vc4_state,
390 + const struct drm_display_mode *mode,
393 + struct drm_device *dev = vc4_hdmi->connector.dev;
394 + const struct drm_connector *connector = &vc4_hdmi->connector;
395 + const struct drm_display_info *info = &connector->display_info;
396 + unsigned int format;
398 + drm_dbg(dev, "Trying with an RGB output\n");
400 + format = VC4_HDMI_OUTPUT_RGB;
401 + if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
404 + ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
405 + mode, bpc, format);
407 + vc4_state->output_format = format;
412 + drm_dbg(dev, "Failed, Trying with an YUV422 output\n");
414 + format = VC4_HDMI_OUTPUT_YUV422;
415 + if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
418 + ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
419 + mode, bpc, format);
421 + vc4_state->output_format = format;
426 + drm_dbg(dev, "Failed. No Format Supported for that bpc count.\n");
432 vc4_hdmi_encoder_compute_config(const struct vc4_hdmi *vc4_hdmi,
433 struct vc4_hdmi_connector_state *vc4_state,
434 const struct drm_display_mode *mode)
436 + struct drm_device *dev = vc4_hdmi->connector.dev;
437 struct drm_connector_state *conn_state = &vc4_state->base;
438 unsigned int max_bpc = clamp_t(unsigned int, conn_state->max_bpc, 8, 12);
440 @@ -1326,17 +1582,18 @@ vc4_hdmi_encoder_compute_config(const st
441 for (bpc = max_bpc; bpc >= 8; bpc -= 2) {
442 drm_dbg(dev, "Trying with a %d bpc output\n", bpc);
444 - ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
446 + ret = vc4_hdmi_encoder_compute_format(vc4_hdmi, vc4_state,
451 vc4_state->output_bpc = bpc;
454 - "Mode %ux%u @ %uHz: Found configuration: bpc: %u, clock: %llu\n",
455 + "Mode %ux%u @ %uHz: Found configuration: bpc: %u, fmt: %s, clock: %llu\n",
456 mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode),
457 vc4_state->output_bpc,
458 + vc4_hdmi_output_fmt_str(vc4_state->output_format),
459 vc4_state->pixel_rate);
462 --- a/drivers/gpu/drm/vc4/vc4_hdmi.h
463 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
464 @@ -121,6 +121,13 @@ struct vc4_hdmi_audio {
468 +enum vc4_hdmi_output_format {
469 + VC4_HDMI_OUTPUT_RGB,
470 + VC4_HDMI_OUTPUT_YUV422,
471 + VC4_HDMI_OUTPUT_YUV444,
472 + VC4_HDMI_OUTPUT_YUV420,
475 /* General HDMI hardware state. */
477 struct vc4_hdmi_audio audio;
478 @@ -227,6 +234,12 @@ struct vc4_hdmi {
480 unsigned int output_bpc;
483 + * @output_format: Copy of @vc4_connector_state.output_format
484 + * for use outside of KMS hooks. Protected by @mutex.
486 + enum vc4_hdmi_output_format output_format;
488 /* VC5 debugfs regset */
489 struct debugfs_regset32 cec_regset;
490 struct debugfs_regset32 csc_regset;
491 @@ -254,6 +267,7 @@ struct vc4_hdmi_connector_state {
492 struct drm_connector_state base;
493 unsigned long long pixel_rate;
494 unsigned int output_bpc;
495 + enum vc4_hdmi_output_format output_format;
498 static inline struct vc4_hdmi_connector_state *
499 --- a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
500 +++ b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
501 @@ -54,6 +54,7 @@ enum vc4_hdmi_field {
505 + HDMI_CSC_CHANNEL_CTL,
509 @@ -119,6 +120,7 @@ enum vc4_hdmi_field {
510 HDMI_TX_PHY_POWERDOWN_CTL,
511 HDMI_TX_PHY_RESET_CTL,
512 HDMI_TX_PHY_TMDS_CLK_WORD_SEL,
513 + HDMI_VEC_INTERFACE_CFG,
514 HDMI_VEC_INTERFACE_XBAR,
517 @@ -246,6 +248,7 @@ static const struct vc4_hdmi_register __
518 VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1c4),
520 VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
521 + VC5_DVP_REG(HDMI_VEC_INTERFACE_CFG, 0x0ec),
522 VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0),
524 VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
525 @@ -291,6 +294,7 @@ static const struct vc4_hdmi_register __
526 VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
527 VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
528 VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
529 + VC5_CSC_REG(HDMI_CSC_CHANNEL_CTL, 0x02c),
532 static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi1_fields[] = {
533 @@ -327,6 +331,7 @@ static const struct vc4_hdmi_register __
534 VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1c4),
536 VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
537 + VC5_DVP_REG(HDMI_VEC_INTERFACE_CFG, 0x0ec),
538 VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0),
540 VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
541 @@ -372,6 +377,7 @@ static const struct vc4_hdmi_register __
542 VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
543 VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
544 VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
545 + VC5_CSC_REG(HDMI_CSC_CHANNEL_CTL, 0x02c),
549 --- a/drivers/gpu/drm/vc4/vc4_regs.h
550 +++ b/drivers/gpu/drm/vc4/vc4_regs.h
551 @@ -804,11 +804,27 @@ enum {
552 # define VC4_HD_CSC_CTL_RGB2YCC BIT(1)
553 # define VC4_HD_CSC_CTL_ENABLE BIT(0)
555 +# define VC5_MT_CP_CSC_CTL_USE_444_TO_422 BIT(6)
556 +# define VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_MASK \
558 +# define VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD \
560 +# define VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION BIT(3)
561 # define VC5_MT_CP_CSC_CTL_ENABLE BIT(2)
562 # define VC5_MT_CP_CSC_CTL_MODE_MASK VC4_MASK(1, 0)
564 +# define VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_MASK \
566 +# define VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE \
569 # define VC4_DVP_HT_CLOCK_STOP_PIXEL BIT(1)
571 +# define VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_MASK \
573 +# define VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY \
576 /* HVS display list information. */
577 #define HVS_BOOTLOADER_DLIST_END 32