1 From 4ece96fb20967c2723b0e3f9c915199b5817de7e Mon Sep 17 00:00:00 2001
2 From: popcornmix <popcornmix@gmail.com>
3 Date: Wed, 1 May 2013 19:46:17 +0100
4 Subject: [PATCH] Add dwc_otg driver
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
9 Signed-off-by: popcornmix <popcornmix@gmail.com>
11 usb: dwc: fix lockdep false positive
13 Signed-off-by: Kari Suvanto <karis79@gmail.com>
15 usb: dwc: fix inconsistent lock state
17 Signed-off-by: Kari Suvanto <karis79@gmail.com>
19 Add FIQ patch to dwc_otg driver. Enable with dwc_otg.fiq_fix_enable=1. Should give about 10% more ARM performance.
20 Thanks to Gordon and Costas
22 Avoid dynamic memory allocation for channel lock in USB driver. Thanks ddv2005.
24 Add NAK holdoff scheme. Enabled by default, disable with dwc_otg.nak_holdoff_enable=0. Thanks gsh
26 Make sure we wait for the reset to finish
28 dwc_otg: fix bug in dwc_otg_hcd.c resulting in silent kernel
29 memory corruption, escalating to OOPS under high USB load.
31 dwc_otg: Fix unsafe access of QTD during URB enqueue
33 In dwc_otg_hcd_urb_enqueue during qtd creation, it was possible that the
34 transaction could complete almost immediately after the qtd was assigned
35 to a host channel during URB enqueue, which meant the qtd pointer was no
36 longer valid having been completed and removed. Usually, this resulted in
37 an OOPS during URB submission. By predetermining whether transactions
38 need to be queued or not, this unsafe pointer access is avoided.
40 This bug was only evident on the Pi model A where a device was attached
41 that had no periodic endpoints (e.g. USB pendrive or some wlan devices).
43 dwc_otg: Fix incorrect URB allocation error handling
45 If the memory allocation for a dwc_otg_urb failed, the kernel would OOPS
46 because for some reason a member of the *unallocated* struct was set to
47 zero. Error handling changed to fail correctly.
49 dwc_otg: fix potential use-after-free case in interrupt handler
51 If a transaction had previously aborted, certain interrupts are
52 enabled to track error counts and reset where necessary. On IN
53 endpoints the host generates an ACK interrupt near-simultaneously
54 with completion of transfer. In the case where this transfer had
55 previously had an error, this results in a use-after-free on
56 the QTD memory space with a 1-byte length being overwritten to
59 dwc_otg: add handling of SPLIT transaction data toggle errors
61 Previously a data toggle error on packets from a USB1.1 device behind
62 a TT would result in the Pi locking up as the driver never handled
63 the associated interrupt. Patch adds basic retry mechanism and
64 interrupt acknowledgement to cater for either a chance toggle error or
65 for devices that have a broken initial toggle state (FT8U232/FT232BM).
67 dwc_otg: implement tasklet for returning URBs to usbcore hcd layer
69 The dwc_otg driver interrupt handler for transfer completion will spend
70 a very long time with interrupts disabled when a URB is completed -
71 this is because usb_hcd_giveback_urb is called from within the handler
72 which for a USB device driver with complicated processing (e.g. webcam)
73 will take an exorbitant amount of time to complete. This results in
74 missed completion interrupts for other USB packets which lead to them
75 being dropped due to microframe overruns.
77 This patch splits returning the URB to the usb hcd layer into a
78 high-priority tasklet. This will have most benefit for isochronous IN
79 transfers but will also have incidental benefit where multiple periodic
80 devices are active at once.
82 dwc_otg: fix NAK holdoff and allow on split transactions only
84 This corrects a bug where if a single active non-periodic endpoint
85 had at least one transaction in its qh, on frnum == MAX_FRNUM the qh
86 would get skipped and never get queued again. This would result in
87 a silent device until error detection (automatic or otherwise) would
88 either reset the device or flush and requeue the URBs.
90 Additionally the NAK holdoff was enabled for all transactions - this
91 would potentially stall a HS endpoint for 1ms if a previous error state
92 enabled this interrupt and the next response was a NAK. Fix so that
93 only split transactions get held off.
95 dwc_otg: Call usb_hcd_unlink_urb_from_ep with lock held in completion handler
97 usb_hcd_unlink_urb_from_ep must be called with the HCD lock held. Calling it
98 asynchronously in the tasklet was not safe (regression in
99 c4564d4a1a0a9b10d4419e48239f5d99e88d2667).
101 This change unlinks it from the endpoint prior to queueing it for handling in
102 the tasklet, and also adds a check to ensure the urb is OK to be unlinked
105 NULL pointer dereference kernel oopses had been observed in usb_hcd_giveback_urb
106 when a USB device was unplugged/replugged during data transfer. This effect
107 was reproduced using automated USB port power control, hundreds of replug
108 events were performed during active transfers to confirm that the problem was
111 USB fix using a FIQ to implement split transactions
113 This commit adds a FIQ implementaion that schedules
114 the split transactions using a FIQ so we don't get
115 held off by the interrupt latency of Linux
117 dwc_otg: fix device attributes and avoid kernel warnings on boot
119 dcw_otg: avoid logging function that can cause panics
121 See: https://github.com/raspberrypi/firmware/issues/21
122 Thanks to cleverca22 for fix
124 dwc_otg: mask correct interrupts after transaction error recovery
126 The dwc_otg driver will unmask certain interrupts on a transaction
127 that previously halted in the error state in order to reset the
128 QTD error count. The various fine-grained interrupt handlers do not
129 consider that other interrupts besides themselves were unmasked.
131 By disabling the two other interrupts only ever enabled in DMA mode
132 for this purpose, we can avoid unnecessary function calls in the
133 IRQ handler. This will also prevent an unneccesary FIQ interrupt
134 from being generated if the FIQ is enabled.
136 dwc_otg: fiq: prevent FIQ thrash and incorrect state passing to IRQ
138 In the case of a transaction to a device that had previously aborted
139 due to an error, several interrupts are enabled to reset the error
140 count when a device responds. This has the side-effect of making the
141 FIQ thrash because the hardware will generate multiple instances of
142 a NAK on an IN bulk/interrupt endpoint and multiple instances of ACK
143 on an OUT bulk/interrupt endpoint. Make the FIQ mask and clear the
144 associated interrupts.
146 Additionally, on non-split transactions make sure that only unmasked
147 interrupts are cleared. This caused a hard-to-trigger but serious
148 race condition when you had the combination of an endpoint awaiting
149 error recovery and a transaction completed on an endpoint - due to
150 the sequencing and timing of interrupts generated by the dwc_otg core,
151 it was possible to confuse the IRQ handler.
155 dwc_otg: whitespace cleanup in dwc_otg_urb_enqueue
157 dwc_otg: prevent OOPSes during device disconnects
159 The dwc_otg_urb_enqueue function is thread-unsafe. In particular the
160 access of urb->hcpriv, usb_hcd_link_urb_to_ep, dwc_otg_urb->qtd and
161 friends does not occur within a critical section and so if a device
162 was unplugged during activity there was a high chance that the
163 usbcore hub_thread would try to disable the endpoint with partially-
164 formed entries in the URB queue. This would result in BUG() or null
165 pointer dereferences.
167 Fix so that access of urb->hcpriv, enqueuing to the hardware and
168 adding to usbcore endpoint URB lists is contained within a single
171 dwc_otg: prevent BUG() in TT allocation if hub address is > 16
173 A fixed-size array is used to track TT allocation. This was
174 previously set to 16 which caused a crash because
175 dwc_otg_hcd_allocate_port would read past the end of the array.
177 This was hit if a hub was plugged in which enumerated as addr > 16,
178 due to previous device resets or unplugs.
180 Also add #ifdef FIQ_DEBUG around hcd->hub_port_alloc[], which grows
181 to a large size if 128 hub addresses are supported. This field is
182 for debug only for tracking which frame an allocate happened in.
184 dwc_otg: make channel halts with unknown state less damaging
186 If the IRQ received a channel halt interrupt through the FIQ
187 with no other bits set, the IRQ would not release the host
188 channel and never complete the URB.
190 Add catchall handling to treat as a transaction error and retry.
192 dwc_otg: fiq_split: use TTs with more granularity
194 This fixes certain issues with split transaction scheduling.
196 - Isochronous multi-packet OUT transactions now hog the TT until
197 they are completed - this prevents hubs aborting transactions
198 if they get a periodic start-split out-of-order
199 - Don't perform TT allocation on non-periodic endpoints - this
200 allows simultaneous use of the TT's bulk/control and periodic
203 This commit will mainly affect USB audio playback.
205 dwc_otg: fix potential sleep while atomic during urb enqueue
207 Fixes a regression introduced with eb1b482a. Kmalloc called from
208 dwc_otg_hcd_qtd_add / dwc_otg_hcd_qtd_create did not always have
209 the GPF_ATOMIC flag set. Force this flag when inside the larger
212 dwc_otg: make fiq_split_enable imply fiq_fix_enable
214 Failing to set up the FIQ correctly would result in
215 "IRQ 32: nobody cared" errors in dmesg.
217 dwc_otg: prevent crashes on host port disconnects
219 Fix several issues resulting in crashes or inconsistent state
220 if a Model A root port was disconnected.
222 - Clean up queue heads properly in kill_urbs_in_qh_list by
223 removing the empty QHs from the schedule lists
224 - Set the halt status properly to prevent IRQ handlers from
226 - Add fiq_split related cleanup for saved registers
227 - Make microframe scheduling reclaim host channels if
228 active during a disconnect
229 - Abort URBs with -ESHUTDOWN status response, informing
230 device drivers so they respond in a more correct fashion
231 and don't try to resubmit URBs
232 - Prevent IRQ handlers from attempting to handle channel
233 interrupts if the associated URB was dequeued (and the
234 driver state was cleared)
236 dwc_otg: prevent leaking URBs during enqueue
238 A dwc_otg_urb would get leaked if the HCD enqueue function
239 failed for any reason. Free the URB at the appropriate points.
241 dwc_otg: Enable NAK holdoff for control split transactions
243 Certain low-speed devices take a very long time to complete a
244 data or status stage of a control transaction, producing NAK
245 responses until they complete internal processing - the USB2.0
246 spec limit is up to 500mS. This causes the same type of interrupt
247 storm as seen with USB-serial dongles prior to c8edb238.
249 In certain circumstances, usually while booting, this interrupt
250 storm could cause SD card timeouts.
252 dwc_otg: Fix for occasional lockup on boot when doing a USB reset
254 dwc_otg: Don't issue traffic to LS devices in FS mode
256 Issuing low-speed packets when the root port is in full-speed mode
257 causes the root port to stop responding. Explicitly fail when
258 enqueuing URBs to a LS endpoint on a FS bus.
260 Fix ARM architecture issue with local_irq_restore()
262 If local_fiq_enable() is called before a local_irq_restore(flags) where
263 the flags variable has the F bit set, the FIQ will be erroneously disabled.
265 Fixup arch_local_irq_restore to avoid trampling the F bit in CPSR.
267 Also fix some of the hacks previously implemented for previous dwc_otg
270 dwc_otg: fiq_fsm: Base commit for driver rewrite
272 This commit removes the previous FIQ fixes entirely and adds fiq_fsm.
274 This rewrite features much more complete support for split transactions
275 and takes into account several OTG hardware bugs. High-speed
276 isochronous transactions are also capable of being performed by fiq_fsm.
278 All driver options have been removed and replaced with:
279 - dwc_otg.fiq_enable (bool)
280 - dwc_otg.fiq_fsm_enable (bool)
281 - dwc_otg.fiq_fsm_mask (bitmask)
282 - dwc_otg.nak_holdoff (unsigned int)
284 Defaults are specified such that fiq_fsm behaves similarly to the
285 previously implemented FIQ fixes.
287 fiq_fsm: Push error recovery into the FIQ when fiq_fsm is used
289 If the transfer associated with a QTD failed due to a bus error, the HCD
290 would retry the transfer up to 3 times (implementing the USB2.0
291 three-strikes retry in software).
293 Due to the masking mechanism used by fiq_fsm, it is only possible to pass
294 a single interrupt through to the HCD per-transfer.
296 In this instance host channels would fall off the radar because the error
297 reset would function, but the subsequent channel halt would be lost.
299 Push the error count reset into the FIQ handler.
301 fiq_fsm: Implement timeout mechanism
303 For full-speed endpoints with a large packet size, interrupt latency
304 runs the risk of the FIQ starting a transaction too late in a full-speed
305 frame. If the device is still transmitting data when EOF2 for the
306 downstream frame occurs, the hub will disable the port. This change is
307 not reflected in the hub status endpoint and the device becomes
310 Prevent high-bandwidth transactions from being started too late in a
311 frame. The mechanism is not guaranteed: a combination of bit stuffing
312 and hub latency may still result in a device overrunning.
314 fiq_fsm: fix bounce buffer utilisation for Isochronous OUT
316 Multi-packet isochronous OUT transactions were subject to a few bounday
319 Audio playback is now much more robust: however, an issue stands with
320 devices that have adaptive sinks - ALSA plays samples too fast.
322 dwc_otg: Return full-speed frame numbers in HS mode
324 The frame counter increments on every *microframe* in high-speed mode.
325 Most device drivers expect this number to be in full-speed frames - this
326 caused considerable confusion to e.g. snd_usb_audio which uses the
327 frame counter to estimate the number of samples played.
329 fiq_fsm: save PID on completion of interrupt OUT transfers
331 Also add edge case handling for interrupt transports.
333 Note that for periodic split IN, data toggles are unimplemented in the
334 OTG host hardware - it unconditionally accepts any PID.
336 fiq_fsm: add missing case for fiq_fsm_tt_in_use()
338 Certain combinations of bitrate and endpoint activity could
339 result in a periodic transaction erroneously getting started
340 while the previous Isochronous OUT was still active.
342 fiq_fsm: clear hcintmsk for aborted transactions
344 Prevents the FIQ from erroneously handling interrupts
345 on a timed out channel.
347 fiq_fsm: enable by default
349 fiq_fsm: fix dequeues for non-periodic split transactions
351 If a dequeue happened between the SSPLIT and CSPLIT phases of the
352 transaction, the HCD would never receive an interrupt.
354 fiq_fsm: Disable by default
356 fiq_fsm: Handle HC babble errors
358 The HCTSIZ transfer size field raises a babble interrupt if
359 the counter wraps. Handle the resulting interrupt in this case.
361 dwc_otg: fix interrupt registration for fiq_enable=0
363 Additionally make the module parameter conditional for wherever
364 hcd->fiq_state is touched.
366 fiq_fsm: Enable by default
368 dwc_otg: Fix various issues with root port and transaction errors
370 Process the host port interrupts correctly (and don't trample them).
371 Root port hotplug now functional again.
373 Fix a few thinkos with the transaction error passthrough for fiq_fsm.
375 fiq_fsm: Implement hack for Split Interrupt transactions
377 Hubs aren't too picky about which endpoint we send Control type split
378 transactions to. By treating Interrupt transfers as Control, it is
379 possible to use the non-periodic queue in the OTG core as well as the
380 non-periodic FIFOs in the hub itself. This massively reduces the
381 microframe exclusivity/contention that periodic split transactions
382 otherwise have to enforce.
384 It goes without saying that this is a fairly egregious USB specification
385 violation, but it works.
387 Original idea by Hans Petter Selasky @ FreeBSD.org.
389 dwc_otg: FIQ support on SMP. Set up FIQ stack and handler on Core 0 only.
391 dwc_otg: introduce fiq_fsm_spin(un|)lock()
393 SMP safety for the FIQ relies on register read-modify write cycles being
394 completed in the correct order. Several places in the DWC code modify
395 registers also touched by the FIQ. Protect these by a bare-bones lock
398 This also makes it possible to run the FIQ and IRQ handlers on different
401 fiq_fsm: fix build on bcm2708 and bcm2709 platforms
403 dwc_otg: put some barriers back where they should be for UP
405 bcm2709/dwc_otg: Setup FIQ on core 1 if >1 core active
407 dwc_otg: fixup read-modify-write in critical paths
409 Be more careful about read-modify-write on registers that the FIQ
412 Guard fiq_fsm_spin_lock with fiq_enable check
414 fiq_fsm: Falling out of the state machine isn't fatal
416 This edge case can be hit if the port is disabled while the FIQ is
417 in the middle of a transaction. Make the effects less severe.
419 Also get rid of the useless return value.
421 squash: dwc_otg: Allow to build without SMP
423 usb: core: make overcurrent messages more prominent
425 Hub overcurrent messages are more serious than "debug". Increase loglevel.
427 usb: dwc_otg: Don't use dma_to_virt()
429 Commit 6ce0d20 changes dma_to_virt() which breaks this driver.
430 Open code the old dma_to_virt() implementation to work around this.
432 Limit the use of __bus_to_virt() to cases where transfer_buffer_length
433 is set and transfer_buffer is not set. This is done to increase the
434 chance that this driver will also work on ARCH_BCM2835.
436 transfer_buffer should not be NULL if the length is set, but the
437 comment in the code indicates that there are situations where this
438 might happen. drivers/usb/isp1760/isp1760-hcd.c also has a similar
439 comment pointing to a possible: 'usb storage / SCSI bug'.
441 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
443 dwc_otg: Fix crash when fiq_enable=0
445 dwc_otg: fiq_fsm: Make high-speed isochronous strided transfers work properly
447 Certain low-bandwidth high-speed USB devices (specialist audio devices,
448 compressed-frame webcams) have packet intervals > 1 microframe.
450 Stride these transfers in the FIQ by using the start-of-frame interrupt
451 to restart the channel at the right time.
453 dwc_otg: Force host mode to fix incorrect compute module boards
455 dwc_otg: Add ARCH_BCM2835 support
457 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
459 dwc_otg: Simplify FIQ irq number code
461 Dropping ATAGS means we can simplify the FIQ irq number code.
462 Also add error checking on the returned irq number.
464 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
466 dwc_otg: Remove duplicate gadget probe/unregister function
468 dwc_otg: Properly set the HFIR
470 Douglas Anderson reported:
472 According to the most up to date version of the dwc2 databook, the FRINT
473 field of the HFIR register should be programmed to:
474 * 125 us * (PHY clock freq for HS) - 1
475 * 1000 us * (PHY clock freq for FS/LS) - 1
477 This is opposed to older versions of the doc that claimed it should be:
478 * 125 us * (PHY clock freq for HS)
479 * 1000 us * (PHY clock freq for FS/LS)
481 and reported lower timing jitter on a USB analyser
483 dcw_otg: trim xfer length when buffer larger than allocated size is received
485 dwc_otg: Don't free qh align buffers in atomic context
487 dwc_otg: Enable the hack for Split Interrupt transactions by default
489 dwc_otg.fiq_fsm_mask=0xF has long been a suggestion for users with audio stutters or other USB bandwidth issues.
490 So far we are aware of many success stories but no failure caused by this setting.
491 Make it a default to learn more.
493 See: https://www.raspberrypi.org/forums/viewtopic.php?f=28&t=70437
495 Signed-off-by: popcornmix <popcornmix@gmail.com>
497 dwc_otg: Use kzalloc when suitable
499 dwc_otg: Pass struct device to dma_alloc*()
501 This makes it possible to get the bus address from Device Tree.
503 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
505 dwc_otg: fix summarize urb->actual_length for isochronous transfers
507 Kernel does not copy input data of ISO transfers to userspace
508 if actual_length is set only in ISO transfers and not summarized
509 in urb->actual_length. Fixes raspberrypi/linux#903
511 fiq_fsm: Use correct states when starting isoc OUT transfers
513 In fiq_fsm_start_next_periodic() if an isochronous OUT transfer
514 was selected, no regard was given as to whether this was a single-packet
515 transfer or a multi-packet staged transfer.
517 For single-packet transfers, this had the effect of repeatedly sending
518 OUT packets with bogus data and lengths.
520 Eventually if the channel was repeatedly enabled enough times, this
521 would lock up the OTG core and no further bus transfers would happen.
523 Set the FSM state up properly if we select a single-packet transfer.
525 Fixes https://github.com/raspberrypi/linux/issues/1842
527 dwc_otg: make nak_holdoff work as intended with empty queues
529 If URBs reading from non-periodic split endpoints were dequeued and
530 the last transfer from the endpoint was a NAK handshake, the resulting
531 qh->nak_frame value was stale which would result in unnecessarily long
532 polling intervals for the first subsequent transfer with a fresh URB.
534 Fixup qh->nak_frame in dwc_otg_hcd_urb_dequeue and also guard against
535 a case where a single URB is submitted to the endpoint, a NAK was
536 received on the transfer immediately prior to receiving data and the
537 device subsequently resubmits another URB past the qh->nak_frame interval.
539 Fixes https://github.com/raspberrypi/linux/issues/1709
541 dwc_otg: fix split transaction data toggle handling around dequeues
543 See https://github.com/raspberrypi/linux/issues/1709
545 Fix several issues regarding endpoint state when URBs are dequeued
546 - If the HCD is disconnected, flush FIQ-enabled channels properly
547 - Save the data toggle state for bulk endpoints if the last transfer
548 from an endpoint where URBs were dequeued returned a data packet
549 - Reset hc->start_pkt_count properly in assign_and_init_hc()
551 dwc_otg: fix several potential crash sources
553 On root port disconnect events, the host driver state is cleared and
554 in-progress host channels are forcibly stopped. This doesn't play
555 well with the FIQ running in the background, so:
556 - Guard the disconnect callback with both the host spinlock and FIQ
558 - Move qtd dereference in dwc_otg_handle_hc_fsm() after the early-out
559 so we don't dereference a qtd that has gone away
560 - Turn catch-all BUG()s in dwc_otg_handle_hc_fsm() into warnings.
562 dwc_otg: delete hcd->channel_lock
564 The lock serves no purpose as it is only held while the HCD spinlock
565 is already being held.
567 dwc_otg: remove unnecessary dma-mode channel halts on disconnect interrupt
569 Host channels are already halted in kill_urbs_in_qh_list() with the
570 subsequent interrupt processing behaving as if the URB was dequeued
573 There's no need to clobber the host channel registers a second time
574 as this exposes races between the driver and host channel resulting
575 in hcd->free_hc_list becoming corrupted.
577 dwcotg: Allow to build without FIQ on ARM64
579 Signed-off-by: popcornmix <popcornmix@gmail.com>
581 dwc_otg: make periodic scheduling behave properly for FS buses
583 If the root port is in full-speed mode, transfer times at 12mbit/s
584 would be calculated but matched against high-speed quotas.
586 Reinitialise hcd->frame_usecs[i] on each port enable event so that
587 full-speed bandwidth can be tracked sensibly.
589 Also, don't bother using the FIQ for transfers when in full-speed
590 mode - at the slower bus speed, interrupt frequency is reduced by
591 an order of magnitude.
593 Related issue: https://github.com/raspberrypi/linux/issues/2020
595 dwc_otg: fiq_fsm: Make isochronous compatibility checks work properly
597 Get rid of the spammy printk and local pointer mangling.
598 Also, there is a nominal benefit for using fiq_fsm for isochronous
599 transfers in FS mode (~1.1k IRQs per second vs 2.1k IRQs per second)
600 so remove the root port speed check.
602 dwc_otg: add module parameter int_ep_interval_min
604 Add a module parameter (defaulting to ignored) that clamps the polling rate
605 of high-speed Interrupt endpoints to a minimum microframe interval.
607 The parameter is modifiable at runtime as it is used when activating new
608 endpoints (such as on device connect).
610 dwc_otg: fiq_fsm: Add non-periodic TT exclusivity constraints
612 Certain hub types do not discriminate between pipe direction (IN or OUT)
613 when considering non-periodic transfers. Therefore these hubs get confused
614 if multiple transfers are issued in different directions with the same
615 device address and endpoint number.
617 Constrain queuing non-periodic split transactions so they are performed
618 serially in such cases.
620 Related: https://github.com/raspberrypi/linux/issues/2024
622 dwc_otg: Fixup change to DRIVER_ATTR interface
624 dwc_otg: Fix compilation warnings
626 Signed-off-by: Phil Elwell <phil@raspberrypi.org>
628 USB_DWCOTG: Disable building dwc_otg as a module (#2265)
630 When dwc_otg is built as a module, build will fail with the following
633 ERROR: "DWC_TASK_HI_SCHEDULE" [drivers/usb/host/dwc_otg/dwc_otg.ko] undefined!
634 scripts/Makefile.modpost:91: recipe for target '__modpost' failed
635 make[1]: *** [__modpost] Error 1
636 Makefile:1199: recipe for target 'modules' failed
637 make: *** [modules] Error 2
639 Even if the error is solved by including the missing
640 DWC_TASK_HI_SCHEDULE function, the kernel will panic when loading
643 As a workaround, simply prevent user from building dwc_otg as a module
644 as the current kernel does not support it.
646 See: https://github.com/raspberrypi/linux/issues/2258
648 Signed-off-by: Malik Olivier Boussejra <malik@boussejra.com>
650 dwc_otg: New timer API
652 dwc_otg: Fix removed ACCESS_ONCE->READ_ONCE
654 dwc_otg: don't unconditionally force host mode in dwc_otg_cil_init()
656 Add the ability to disable force_host_mode for those that want to use
657 dwc_otg in both device and host modes.
659 dwc_otg: Fix a regression when dequeueing isochronous transfers
661 In 282bed95 (dwc_otg: make nak_holdoff work as intended with empty queues)
662 the dequeue mechanism was changed to leave FIQ-enabled transfers to run
663 to completion - to avoid leaving hub TT buffers with stale packets lying
666 This broke FIQ-accelerated isochronous transfers, as this then meant that
667 dozens of transfers were performed after the dequeue function returned.
669 Restore the state machine fence for isochronous transfers.
671 fiq_fsm: rewind DMA pointer for OUT transactions that fail (#2288)
673 See: https://github.com/raspberrypi/linux/issues/2140
675 dwc_otg: add smp_mb() to prevent driver state corruption on boot
677 Occasional crashes have been seen where the FIQ code dereferences
678 invalid/random pointers immediately after being set up, leading to
681 The crash occurs as the FIQ code races against hcd_init_fiq() and
682 the hcd_init_fiq() code races against the outstanding memory stores
683 from dwc_otg_hcd_init(). Use explicit barriers after touching
686 usb: dwc_otg: fix memory corruption in dwc_otg driver
688 [Upstream commit 51b1b6491752ac066ee8d32cc66042fcc955fef6]
690 The move from the staging tree to the main tree exposed a
691 longstanding memory corruption bug in the dwc2 driver. The
692 reordering of the driver initialization caused the dwc2 driver
693 to corrupt the initialization data of the sdhci driver on the
694 Raspberry Pi platform, which made the bug show up.
696 The error is in calling to_usb_device(hsotg->dev), since ->dev
697 is not a member of struct usb_device. The easiest fix is to
698 just remove the offending code, since it is not really needed.
700 Thanks to Stephen Warren for tracking down the cause of this.
702 Reported-by: Andre Heider <a.heider@gmail.com>
703 Tested-by: Stephen Warren <swarren@wwwdotorg.org>
704 Signed-off-by: Paul Zimmerman <paulz@synopsys.com>
705 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
706 [lukas: port from upstream dwc2 to out-of-tree dwc_otg driver]
707 Signed-off-by: Lukas Wunner <lukas@wunner.de>
709 usb: dwb_otg: Fix unreachable switch statement warning
711 This warning appears with GCC 7.3.0 from toolchains.bootlin.com:
713 ../drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c: In function ‘fiq_fsm_update_hs_isoc’:
714 ../drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c:595:61: warning: statement will never be executed [-Wswitch-unreachable]
715 st->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps;
716 ~~~~~~~~~~~~~~~~~^~~~
718 Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
720 dwc_otg: fiq_fsm: fix incorrect DMA register offset calculation
722 Rationalise the offset and update all call sites.
724 Fixes https://github.com/raspberrypi/linux/issues/2408
726 dwc_otg: fix bug with port_addr assignment for single-TT hubs
728 See https://github.com/raspberrypi/linux/issues/2734
730 The "Hub Port" field in the split transaction packet was always set
731 to 1 for single-TT hubs. The majority of single-TT hub products
732 apparently ignore this field and broadcast to all downstream enabled
733 ports, which masked the issue. A subset of hub devices apparently
734 need the port number to be exact or split transactions will fail.
736 usb: dwc_otg: Clean up build warnings on 64bit kernels
738 No functional changes. Almost all are changes to logging lines.
740 Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
742 usb: dwc_otg: Use dma allocation for mphi dummy_send buffer
744 The FIQ driver used a kzalloc'ed buffer for dummy_send,
745 passing a kernel virtual address to the hardware block.
746 The buffer is only ever used for a dummy read, so it
747 should be harmless, but there is the chance that it will
750 Use a dma allocation so that we have a genuine bus address,
752 Free the allocation when done for good measure.
754 Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
756 dwc_otg: only do_split when we actually need to do a split
758 The previous test would fail if the root port was in fullspeed mode
759 and there was a hub between the FS device and the root port. While
760 the transfer worked, the schedule mangling performed for high-speed
761 split transfers would break leading to an 8ms polling interval.
763 dwc_otg: fix locking around dequeueing and killing URBs
765 kill_urbs_in_qh_list() is practically only ever called with the fiq lock
766 already held, so don't spinlock twice in the case where we need to cancel
767 an isochronous transfer.
769 Also fix up a case where the global interrupt register could be read with
770 the fiq lock not held.
772 Fixes the deadlock seen in https://github.com/raspberrypi/linux/issues/2907
774 ARM64/DWC_OTG: Port dwc_otg driver to ARM64
776 In ARM64, the FIQ mechanism used by this driver is not current
777 implemented. As a workaround, reqular IRQ is used instead
780 In a separate change, the IRQ-CPU mapping is round robined
781 on ARM64 to increase concurrency and allow multiple interrupts
782 to be serviced at a time. This reduces the need for FIQ.
786 This mechanism is most likely to break when multiple USB devices
787 are attached at the same time. So the system was tested under
792 1. USB Speakers playing back a FLAC audio through VLC
793 at 96KHz.(Higher then typically, but supported on my speakers).
795 2. sftp transferring large files through the buildin ethernet
796 connection which is connected through USB.
798 3. Keyboard and mouse attached and being used.
800 Although I do occasionally hear some glitches, the music seems to
803 Signed-off-by: Michael Zoran <mzoran@crowfest.net>
805 usb: dwc_otg: Clean up interrupt claiming code
807 The FIQ/IRQ interrupt number identification code is scattered through
808 the dwc_otg driver. Rationalise it, simplifying the code and solving
811 See: https://github.com/raspberrypi/linux/issues/2612
813 Signed-off-by: Phil Elwell <phil@raspberrypi.org>
815 dwc_otg: Choose appropriate IRQ handover strategy
817 2711 has no MPHI peripheral, but the ARM Control block can fake
818 interrupts. Use the size of the DTB "mphi" reg block to determine
821 Signed-off-by: Phil Elwell <phil@raspberrypi.org>
823 usb: host: dwc_otg: fix compiling in separate directory
825 The dwc_otg Makefile does not respect the O=path argument correctly:
826 include paths in CFLAGS are given relatively to object path, not source
827 path. Compiling in a separate directory yields #include errors.
829 Signed-off-by: Marek Behún <marek.behun@nic.cz>
831 dwc_otg: use align_buf for small IN control transfers (#3150)
833 The hardware will do a 4-byte write to memory on any IN packet received
834 that is between 1 and 3 bytes long. This tramples memory in the uvcvideo
835 driver, as it uses a sequence of 1- and 2-byte control transfers to
836 query the min/max/range/step of each individual camera control and
837 gives us buffers that are offsets into a struct.
839 Catch small control transfers in the data phase and use the align_buf
840 to bounce the correct number of bytes into the URB's buffer.
842 In general, short packets on non-control endpoints should be OK as URBs
843 should have enough buffer space for a wMaxPacket size transfer.
845 See: https://github.com/raspberrypi/linux/issues/3148
847 Signed-off-by: Jonathan Bell <jonathan@raspberrypi.org>
849 arch/arm/include/asm/irqflags.h | 16 +-
850 arch/arm/kernel/fiqasm.S | 4 +
851 drivers/usb/Makefile | 1 +
852 drivers/usb/core/generic.c | 1 +
853 drivers/usb/core/hub.c | 2 +-
854 drivers/usb/core/message.c | 79 +
855 drivers/usb/core/otg_whitelist.h | 114 +-
856 drivers/usb/gadget/file_storage.c | 3676 +++++++++
857 drivers/usb/host/Kconfig | 10 +
858 drivers/usb/host/Makefile | 1 +
859 drivers/usb/host/dwc_common_port/Makefile | 58 +
860 .../usb/host/dwc_common_port/Makefile.fbsd | 17 +
861 .../usb/host/dwc_common_port/Makefile.linux | 49 +
862 drivers/usb/host/dwc_common_port/changes.txt | 174 +
863 .../usb/host/dwc_common_port/doc/doxygen.cfg | 270 +
864 drivers/usb/host/dwc_common_port/dwc_cc.c | 532 ++
865 drivers/usb/host/dwc_common_port/dwc_cc.h | 224 +
866 .../host/dwc_common_port/dwc_common_fbsd.c | 1308 +++
867 .../host/dwc_common_port/dwc_common_linux.c | 1409 ++++
868 .../host/dwc_common_port/dwc_common_nbsd.c | 1275 +++
869 drivers/usb/host/dwc_common_port/dwc_crypto.c | 308 +
870 drivers/usb/host/dwc_common_port/dwc_crypto.h | 111 +
871 drivers/usb/host/dwc_common_port/dwc_dh.c | 291 +
872 drivers/usb/host/dwc_common_port/dwc_dh.h | 106 +
873 drivers/usb/host/dwc_common_port/dwc_list.h | 594 ++
874 drivers/usb/host/dwc_common_port/dwc_mem.c | 245 +
875 drivers/usb/host/dwc_common_port/dwc_modpow.c | 636 ++
876 drivers/usb/host/dwc_common_port/dwc_modpow.h | 34 +
877 .../usb/host/dwc_common_port/dwc_notifier.c | 319 +
878 .../usb/host/dwc_common_port/dwc_notifier.h | 122 +
879 drivers/usb/host/dwc_common_port/dwc_os.h | 1276 +++
880 drivers/usb/host/dwc_common_port/usb.h | 946 +++
881 drivers/usb/host/dwc_otg/Makefile | 85 +
882 drivers/usb/host/dwc_otg/doc/doxygen.cfg | 224 +
883 drivers/usb/host/dwc_otg/dummy_audio.c | 1574 ++++
884 drivers/usb/host/dwc_otg/dwc_cfi_common.h | 142 +
885 drivers/usb/host/dwc_otg/dwc_otg_adp.c | 854 ++
886 drivers/usb/host/dwc_otg/dwc_otg_adp.h | 80 +
887 drivers/usb/host/dwc_otg/dwc_otg_attr.c | 1212 +++
888 drivers/usb/host/dwc_otg/dwc_otg_attr.h | 89 +
889 drivers/usb/host/dwc_otg/dwc_otg_cfi.c | 1876 +++++
890 drivers/usb/host/dwc_otg/dwc_otg_cfi.h | 320 +
891 drivers/usb/host/dwc_otg/dwc_otg_cil.c | 7146 +++++++++++++++++
892 drivers/usb/host/dwc_otg/dwc_otg_cil.h | 1464 ++++
893 drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c | 1601 ++++
894 drivers/usb/host/dwc_otg/dwc_otg_core_if.h | 705 ++
895 drivers/usb/host/dwc_otg/dwc_otg_dbg.h | 117 +
896 drivers/usb/host/dwc_otg/dwc_otg_driver.c | 1772 ++++
897 drivers/usb/host/dwc_otg/dwc_otg_driver.h | 86 +
898 drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c | 1425 ++++
899 drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h | 399 +
900 drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S | 80 +
901 drivers/usb/host/dwc_otg/dwc_otg_hcd.c | 4327 ++++++++++
902 drivers/usb/host/dwc_otg/dwc_otg_hcd.h | 870 ++
903 drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c | 1134 +++
904 drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h | 421 +
905 drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 2757 +++++++
906 drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c | 1083 +++
907 drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c | 970 +++
908 drivers/usb/host/dwc_otg/dwc_otg_os_dep.h | 199 +
909 drivers/usb/host/dwc_otg/dwc_otg_pcd.c | 2725 +++++++
910 drivers/usb/host/dwc_otg/dwc_otg_pcd.h | 273 +
911 drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h | 361 +
912 drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c | 5148 ++++++++++++
913 drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c | 1262 +++
914 drivers/usb/host/dwc_otg/dwc_otg_regs.h | 2550 ++++++
915 drivers/usb/host/dwc_otg/test/Makefile | 16 +
916 drivers/usb/host/dwc_otg/test/dwc_otg_test.pm | 337 +
917 .../usb/host/dwc_otg/test/test_mod_param.pl | 133 +
918 drivers/usb/host/dwc_otg/test/test_sysfs.pl | 193 +
919 70 files changed, 60202 insertions(+), 16 deletions(-)
920 create mode 100644 drivers/usb/gadget/file_storage.c
921 create mode 100644 drivers/usb/host/dwc_common_port/Makefile
922 create mode 100644 drivers/usb/host/dwc_common_port/Makefile.fbsd
923 create mode 100644 drivers/usb/host/dwc_common_port/Makefile.linux
924 create mode 100644 drivers/usb/host/dwc_common_port/changes.txt
925 create mode 100644 drivers/usb/host/dwc_common_port/doc/doxygen.cfg
926 create mode 100644 drivers/usb/host/dwc_common_port/dwc_cc.c
927 create mode 100644 drivers/usb/host/dwc_common_port/dwc_cc.h
928 create mode 100644 drivers/usb/host/dwc_common_port/dwc_common_fbsd.c
929 create mode 100644 drivers/usb/host/dwc_common_port/dwc_common_linux.c
930 create mode 100644 drivers/usb/host/dwc_common_port/dwc_common_nbsd.c
931 create mode 100644 drivers/usb/host/dwc_common_port/dwc_crypto.c
932 create mode 100644 drivers/usb/host/dwc_common_port/dwc_crypto.h
933 create mode 100644 drivers/usb/host/dwc_common_port/dwc_dh.c
934 create mode 100644 drivers/usb/host/dwc_common_port/dwc_dh.h
935 create mode 100644 drivers/usb/host/dwc_common_port/dwc_list.h
936 create mode 100644 drivers/usb/host/dwc_common_port/dwc_mem.c
937 create mode 100644 drivers/usb/host/dwc_common_port/dwc_modpow.c
938 create mode 100644 drivers/usb/host/dwc_common_port/dwc_modpow.h
939 create mode 100644 drivers/usb/host/dwc_common_port/dwc_notifier.c
940 create mode 100644 drivers/usb/host/dwc_common_port/dwc_notifier.h
941 create mode 100644 drivers/usb/host/dwc_common_port/dwc_os.h
942 create mode 100644 drivers/usb/host/dwc_common_port/usb.h
943 create mode 100644 drivers/usb/host/dwc_otg/Makefile
944 create mode 100644 drivers/usb/host/dwc_otg/doc/doxygen.cfg
945 create mode 100644 drivers/usb/host/dwc_otg/dummy_audio.c
946 create mode 100644 drivers/usb/host/dwc_otg/dwc_cfi_common.h
947 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_adp.c
948 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_adp.h
949 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_attr.c
950 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_attr.h
951 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cfi.c
952 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cfi.h
953 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cil.c
954 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cil.h
955 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c
956 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_core_if.h
957 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_dbg.h
958 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_driver.c
959 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_driver.h
960 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
961 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h
962 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S
963 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd.c
964 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd.h
965 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c
966 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h
967 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
968 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
969 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c
970 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_os_dep.h
971 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd.c
972 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd.h
973 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h
974 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c
975 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c
976 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_regs.h
977 create mode 100644 drivers/usb/host/dwc_otg/test/Makefile
978 create mode 100644 drivers/usb/host/dwc_otg/test/dwc_otg_test.pm
979 create mode 100644 drivers/usb/host/dwc_otg/test/test_mod_param.pl
980 create mode 100644 drivers/usb/host/dwc_otg/test/test_sysfs.pl
982 --- a/arch/arm/include/asm/irqflags.h
983 +++ b/arch/arm/include/asm/irqflags.h
984 @@ -163,13 +163,23 @@ static inline unsigned long arch_local_s
988 - * restore saved IRQ & FIQ state
989 + * restore saved IRQ state
991 #define arch_local_irq_restore arch_local_irq_restore
992 static inline void arch_local_irq_restore(unsigned long flags)
995 - " msr " IRQMASK_REG_NAME_W ", %0 @ local_irq_restore"
996 + unsigned long temp = 0;
997 + flags &= ~(1 << 6);
1002 + : "memory", "cc");
1003 + /* Preserve FIQ bit */
1005 + flags = flags | temp;
1007 + " msr cpsr_c, %0 @ local_irq_restore"
1011 --- a/arch/arm/kernel/fiqasm.S
1012 +++ b/arch/arm/kernel/fiqasm.S
1013 @@ -47,3 +47,7 @@ ENTRY(__get_fiq_regs)
1014 mov r0, r0 @ avoid hazard prior to ARMv4
1016 ENDPROC(__get_fiq_regs)
1018 +ENTRY(__FIQ_Branch)
1020 +ENDPROC(__FIQ_Branch)
1021 --- a/drivers/usb/Makefile
1022 +++ b/drivers/usb/Makefile
1023 @@ -9,6 +9,7 @@ obj-$(CONFIG_USB_COMMON) += common/
1024 obj-$(CONFIG_USB) += core/
1025 obj-$(CONFIG_USB_SUPPORT) += phy/
1027 +obj-$(CONFIG_USB_DWCOTG) += host/
1028 obj-$(CONFIG_USB_DWC3) += dwc3/
1029 obj-$(CONFIG_USB_DWC2) += dwc2/
1030 obj-$(CONFIG_USB_ISP1760) += isp1760/
1031 --- a/drivers/usb/core/generic.c
1032 +++ b/drivers/usb/core/generic.c
1033 @@ -190,6 +190,7 @@ int usb_choose_configuration(struct usb_
1034 dev_warn(&udev->dev,
1035 "no configuration chosen from %d choice%s\n",
1036 num_configs, plural(num_configs));
1037 + dev_warn(&udev->dev, "No support over %dmA\n", udev->bus_mA);
1041 --- a/drivers/usb/core/hub.c
1042 +++ b/drivers/usb/core/hub.c
1043 @@ -5321,7 +5321,7 @@ static void port_event(struct usb_hub *h
1044 port_dev->over_current_count++;
1045 port_over_current_notify(port_dev);
1047 - dev_dbg(&port_dev->dev, "over-current change #%u\n",
1048 + dev_notice(&port_dev->dev, "over-current change #%u\n",
1049 port_dev->over_current_count);
1050 usb_clear_port_feature(hdev, port1,
1051 USB_PORT_FEAT_C_OVER_CURRENT);
1052 --- a/drivers/usb/core/message.c
1053 +++ b/drivers/usb/core/message.c
1054 @@ -1993,6 +1993,85 @@ free_interfaces:
1055 if (cp->string == NULL &&
1056 !(dev->quirks & USB_QUIRK_CONFIG_INTF_STRINGS))
1057 cp->string = usb_cache_string(dev, cp->desc.iConfiguration);
1058 +/* Uncomment this define to enable the HS Electrical Test support */
1059 +#define DWC_HS_ELECT_TST 1
1060 +#ifdef DWC_HS_ELECT_TST
1061 + /* Here we implement the HS Electrical Test support. The
1062 + * tester uses a vendor ID of 0x1A0A to indicate we should
1063 + * run a special test sequence. The product ID tells us
1064 + * which sequence to run. We invoke the test sequence by
1065 + * sending a non-standard SetFeature command to our root
1066 + * hub port. Our dwc_otg_hcd_hub_control() routine will
1067 + * recognize the command and perform the desired test
1070 + if (dev->descriptor.idVendor == 0x1A0A) {
1071 + /* HSOTG Electrical Test */
1072 + dev_warn(&dev->dev, "VID from HSOTG Electrical Test Fixture\n");
1074 + if (dev->bus && dev->bus->root_hub) {
1075 + struct usb_device *hdev = dev->bus->root_hub;
1076 + dev_warn(&dev->dev, "Got PID 0x%x\n", dev->descriptor.idProduct);
1078 + switch (dev->descriptor.idProduct) {
1079 + case 0x0101: /* TEST_SE0_NAK */
1080 + dev_warn(&dev->dev, "TEST_SE0_NAK\n");
1081 + usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
1082 + USB_REQ_SET_FEATURE, USB_RT_PORT,
1083 + USB_PORT_FEAT_TEST, 0x300, NULL, 0, HZ);
1086 + case 0x0102: /* TEST_J */
1087 + dev_warn(&dev->dev, "TEST_J\n");
1088 + usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
1089 + USB_REQ_SET_FEATURE, USB_RT_PORT,
1090 + USB_PORT_FEAT_TEST, 0x100, NULL, 0, HZ);
1093 + case 0x0103: /* TEST_K */
1094 + dev_warn(&dev->dev, "TEST_K\n");
1095 + usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
1096 + USB_REQ_SET_FEATURE, USB_RT_PORT,
1097 + USB_PORT_FEAT_TEST, 0x200, NULL, 0, HZ);
1100 + case 0x0104: /* TEST_PACKET */
1101 + dev_warn(&dev->dev, "TEST_PACKET\n");
1102 + usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
1103 + USB_REQ_SET_FEATURE, USB_RT_PORT,
1104 + USB_PORT_FEAT_TEST, 0x400, NULL, 0, HZ);
1107 + case 0x0105: /* TEST_FORCE_ENABLE */
1108 + dev_warn(&dev->dev, "TEST_FORCE_ENABLE\n");
1109 + usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
1110 + USB_REQ_SET_FEATURE, USB_RT_PORT,
1111 + USB_PORT_FEAT_TEST, 0x500, NULL, 0, HZ);
1114 + case 0x0106: /* HS_HOST_PORT_SUSPEND_RESUME */
1115 + dev_warn(&dev->dev, "HS_HOST_PORT_SUSPEND_RESUME\n");
1116 + usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
1117 + USB_REQ_SET_FEATURE, USB_RT_PORT,
1118 + USB_PORT_FEAT_TEST, 0x600, NULL, 0, 40 * HZ);
1121 + case 0x0107: /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
1122 + dev_warn(&dev->dev, "SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup\n");
1123 + usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
1124 + USB_REQ_SET_FEATURE, USB_RT_PORT,
1125 + USB_PORT_FEAT_TEST, 0x700, NULL, 0, 40 * HZ);
1128 + case 0x0108: /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
1129 + dev_warn(&dev->dev, "SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute\n");
1130 + usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
1131 + USB_REQ_SET_FEATURE, USB_RT_PORT,
1132 + USB_PORT_FEAT_TEST, 0x800, NULL, 0, 40 * HZ);
1136 +#endif /* DWC_HS_ELECT_TST */
1138 /* Now that the interfaces are installed, re-enable LPM. */
1139 usb_unlocked_enable_lpm(dev);
1140 --- a/drivers/usb/core/otg_whitelist.h
1141 +++ b/drivers/usb/core/otg_whitelist.h
1143 static struct usb_device_id whitelist_table[] = {
1145 /* hubs are optional in OTG, but very handy ... */
1146 +#define CERT_WITHOUT_HUBS
1147 +#if defined(CERT_WITHOUT_HUBS)
1148 +{ USB_DEVICE( 0x0000, 0x0000 ), }, /* Root HUB Only*/
1150 { USB_DEVICE_INFO(USB_CLASS_HUB, 0, 0), },
1151 { USB_DEVICE_INFO(USB_CLASS_HUB, 0, 1), },
1152 +{ USB_DEVICE_INFO(USB_CLASS_HUB, 0, 2), },
1155 #ifdef CONFIG_USB_PRINTER /* ignoring nonstatic linkage! */
1156 /* FIXME actually, printers are NOT supposed to use device classes;
1157 * they're supposed to use interface classes...
1159 -{ USB_DEVICE_INFO(7, 1, 1) },
1160 -{ USB_DEVICE_INFO(7, 1, 2) },
1161 -{ USB_DEVICE_INFO(7, 1, 3) },
1162 +//{ USB_DEVICE_INFO(7, 1, 1) },
1163 +//{ USB_DEVICE_INFO(7, 1, 2) },
1164 +//{ USB_DEVICE_INFO(7, 1, 3) },
1167 #ifdef CONFIG_USB_NET_CDCETHER
1168 /* Linux-USB CDC Ethernet gadget */
1169 -{ USB_DEVICE(0x0525, 0xa4a1), },
1170 +//{ USB_DEVICE(0x0525, 0xa4a1), },
1171 /* Linux-USB CDC Ethernet + RNDIS gadget */
1172 -{ USB_DEVICE(0x0525, 0xa4a2), },
1173 +//{ USB_DEVICE(0x0525, 0xa4a2), },
1176 #if IS_ENABLED(CONFIG_USB_TEST)
1177 /* gadget zero, for testing */
1178 -{ USB_DEVICE(0x0525, 0xa4a0), },
1179 +//{ USB_DEVICE(0x0525, 0xa4a0), },
1183 +{ USB_DEVICE( 0x1a0a, 0x0101 ), }, /* TEST_SE0_NAK */
1184 +{ USB_DEVICE( 0x1a0a, 0x0102 ), }, /* Test_J */
1185 +{ USB_DEVICE( 0x1a0a, 0x0103 ), }, /* Test_K */
1186 +{ USB_DEVICE( 0x1a0a, 0x0104 ), }, /* Test_PACKET */
1187 +{ USB_DEVICE( 0x1a0a, 0x0105 ), }, /* Test_FORCE_ENABLE */
1188 +{ USB_DEVICE( 0x1a0a, 0x0106 ), }, /* HS_PORT_SUSPEND_RESUME */
1189 +{ USB_DEVICE( 0x1a0a, 0x0107 ), }, /* SINGLE_STEP_GET_DESCRIPTOR setup */
1190 +{ USB_DEVICE( 0x1a0a, 0x0108 ), }, /* SINGLE_STEP_GET_DESCRIPTOR execute */
1193 +{ USB_DEVICE_VER(0x054c,0x0010,0x0410, 0x0500), },
1195 +/* Memory Devices */
1196 +//{ USB_DEVICE( 0x0781, 0x5150 ), }, /* SanDisk */
1197 +//{ USB_DEVICE( 0x05DC, 0x0080 ), }, /* Lexar */
1198 +//{ USB_DEVICE( 0x4146, 0x9281 ), }, /* IOMEGA */
1199 +//{ USB_DEVICE( 0x067b, 0x2507 ), }, /* Hammer 20GB External HD */
1200 +{ USB_DEVICE( 0x0EA0, 0x2168 ), }, /* Ours Technology Inc. (BUFFALO ClipDrive)*/
1201 +//{ USB_DEVICE( 0x0457, 0x0150 ), }, /* Silicon Integrated Systems Corp. */
1204 +//{ USB_DEVICE( 0x03F0, 0x1102 ), }, /* HP Photosmart 245 */
1205 +//{ USB_DEVICE( 0x03F0, 0x1302 ), }, /* HP Photosmart 370 Series */
1208 +//{ USB_DEVICE( 0x0499, 0x3002 ), }, /* YAMAHA YST-MS35D USB Speakers */
1209 +//{ USB_DEVICE( 0x0672, 0x1041 ), }, /* Labtec USB Headset */
1211 { } /* Terminating entry */
1214 +static inline void report_errors(struct usb_device *dev)
1216 + /* OTG MESSAGE: report errors here, customize to match your product */
1217 + dev_info(&dev->dev, "device Vendor:%04x Product:%04x is not supported\n",
1218 + le16_to_cpu(dev->descriptor.idVendor),
1219 + le16_to_cpu(dev->descriptor.idProduct));
1220 + if (USB_CLASS_HUB == dev->descriptor.bDeviceClass){
1221 + dev_printk(KERN_CRIT, &dev->dev, "Unsupported Hub Topology\n");
1223 + dev_printk(KERN_CRIT, &dev->dev, "Attached Device is not Supported\n");
1228 static int is_targeted(struct usb_device *dev)
1230 struct usb_device_id *id = whitelist_table;
1231 @@ -91,16 +140,57 @@ static int is_targeted(struct usb_device
1236 + /* NOTE: can't use usb_match_id() since interface caches
1237 + * aren't set up yet. this is cut/paste from that code.
1239 + for (id = whitelist_table; id->match_flags; id++) {
1241 + dev_dbg(&dev->dev,
1242 + "ID: V:%04x P:%04x DC:%04x SC:%04x PR:%04x \n",
1246 + id->bDeviceSubClass,
1247 + id->bDeviceProtocol);
1250 - /* add other match criteria here ... */
1251 + if ((id->match_flags & USB_DEVICE_ID_MATCH_VENDOR) &&
1252 + id->idVendor != le16_to_cpu(dev->descriptor.idVendor))
1255 + if ((id->match_flags & USB_DEVICE_ID_MATCH_PRODUCT) &&
1256 + id->idProduct != le16_to_cpu(dev->descriptor.idProduct))
1259 + /* No need to test id->bcdDevice_lo != 0, since 0 is never
1260 + greater than any unsigned number. */
1261 + if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_LO) &&
1262 + (id->bcdDevice_lo > le16_to_cpu(dev->descriptor.bcdDevice)))
1265 + if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_HI) &&
1266 + (id->bcdDevice_hi < le16_to_cpu(dev->descriptor.bcdDevice)))
1269 + if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_CLASS) &&
1270 + (id->bDeviceClass != dev->descriptor.bDeviceClass))
1273 + if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_SUBCLASS) &&
1274 + (id->bDeviceSubClass != dev->descriptor.bDeviceSubClass))
1277 + if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_PROTOCOL) &&
1278 + (id->bDeviceProtocol != dev->descriptor.bDeviceProtocol))
1285 - /* OTG MESSAGE: report errors here, customize to match your product */
1286 - dev_err(&dev->dev, "device v%04x p%04x is not supported\n",
1287 - le16_to_cpu(dev->descriptor.idVendor),
1288 - le16_to_cpu(dev->descriptor.idProduct));
1289 + /* add other match criteria here ... */
1291 + report_errors(dev);
1296 +++ b/drivers/usb/gadget/file_storage.c
1299 + * file_storage.c -- File-backed USB Storage Gadget, for USB development
1301 + * Copyright (C) 2003-2008 Alan Stern
1302 + * All rights reserved.
1304 + * Redistribution and use in source and binary forms, with or without
1305 + * modification, are permitted provided that the following conditions
1307 + * 1. Redistributions of source code must retain the above copyright
1308 + * notice, this list of conditions, and the following disclaimer,
1309 + * without modification.
1310 + * 2. Redistributions in binary form must reproduce the above copyright
1311 + * notice, this list of conditions and the following disclaimer in the
1312 + * documentation and/or other materials provided with the distribution.
1313 + * 3. The names of the above-listed copyright holders may not be used
1314 + * to endorse or promote products derived from this software without
1315 + * specific prior written permission.
1317 + * ALTERNATIVELY, this software may be distributed under the terms of the
1318 + * GNU General Public License ("GPL") as published by the Free Software
1319 + * Foundation, either version 2 of that License or (at your option) any
1322 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
1323 + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
1324 + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
1325 + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
1326 + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
1327 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
1328 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
1329 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
1330 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
1331 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
1332 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1337 + * The File-backed Storage Gadget acts as a USB Mass Storage device,
1338 + * appearing to the host as a disk drive or as a CD-ROM drive. In addition
1339 + * to providing an example of a genuinely useful gadget driver for a USB
1340 + * device, it also illustrates a technique of double-buffering for increased
1341 + * throughput. Last but not least, it gives an easy way to probe the
1342 + * behavior of the Mass Storage drivers in a USB host.
1344 + * Backing storage is provided by a regular file or a block device, specified
1345 + * by the "file" module parameter. Access can be limited to read-only by
1346 + * setting the optional "ro" module parameter. (For CD-ROM emulation,
1347 + * access is always read-only.) The gadget will indicate that it has
1348 + * removable media if the optional "removable" module parameter is set.
1350 + * The gadget supports the Control-Bulk (CB), Control-Bulk-Interrupt (CBI),
1351 + * and Bulk-Only (also known as Bulk-Bulk-Bulk or BBB) transports, selected
1352 + * by the optional "transport" module parameter. It also supports the
1353 + * following protocols: RBC (0x01), ATAPI or SFF-8020i (0x02), QIC-157 (0c03),
1354 + * UFI (0x04), SFF-8070i (0x05), and transparent SCSI (0x06), selected by
1355 + * the optional "protocol" module parameter. In addition, the default
1356 + * Vendor ID, Product ID, release number and serial number can be overridden.
1358 + * There is support for multiple logical units (LUNs), each of which has
1359 + * its own backing file. The number of LUNs can be set using the optional
1360 + * "luns" module parameter (anywhere from 1 to 8), and the corresponding
1361 + * files are specified using comma-separated lists for "file" and "ro".
1362 + * The default number of LUNs is taken from the number of "file" elements;
1363 + * it is 1 if "file" is not given. If "removable" is not set then a backing
1364 + * file must be specified for each LUN. If it is set, then an unspecified
1365 + * or empty backing filename means the LUN's medium is not loaded. Ideally
1366 + * each LUN would be settable independently as a disk drive or a CD-ROM
1367 + * drive, but currently all LUNs have to be the same type. The CD-ROM
1368 + * emulation includes a single data track and no audio tracks; hence there
1369 + * need be only one backing file per LUN.
1371 + * Requirements are modest; only a bulk-in and a bulk-out endpoint are
1372 + * needed (an interrupt-out endpoint is also needed for CBI). The memory
1373 + * requirement amounts to two 16K buffers, size configurable by a parameter.
1374 + * Support is included for both full-speed and high-speed operation.
1376 + * Note that the driver is slightly non-portable in that it assumes a
1377 + * single memory/DMA buffer will be useable for bulk-in, bulk-out, and
1378 + * interrupt-in endpoints. With most device controllers this isn't an
1379 + * issue, but there may be some with hardware restrictions that prevent
1380 + * a buffer from being used by more than one endpoint.
1384 + * file=filename[,filename...]
1385 + * Required if "removable" is not set, names of
1386 + * the files or block devices used for
1388 + * serial=HHHH... Required serial number (string of hex chars)
1389 + * ro=b[,b...] Default false, booleans for read-only access
1390 + * removable Default false, boolean for removable media
1391 + * luns=N Default N = number of filenames, number of
1393 + * nofua=b[,b...] Default false, booleans for ignore FUA flag
1394 + * in SCSI WRITE(10,12) commands
1395 + * stall Default determined according to the type of
1396 + * USB device controller (usually true),
1397 + * boolean to permit the driver to halt
1399 + * cdrom Default false, boolean for whether to emulate
1401 + * transport=XXX Default BBB, transport name (CB, CBI, or BBB)
1402 + * protocol=YYY Default SCSI, protocol name (RBC, 8020 or
1403 + * ATAPI, QIC, UFI, 8070, or SCSI;
1405 + * vendor=0xVVVV Default 0x0525 (NetChip), USB Vendor ID
1406 + * product=0xPPPP Default 0xa4a5 (FSG), USB Product ID
1407 + * release=0xRRRR Override the USB release number (bcdDevice)
1408 + * buflen=N Default N=16384, buffer size used (will be
1409 + * rounded down to a multiple of
1410 + * PAGE_CACHE_SIZE)
1412 + * If CONFIG_USB_FILE_STORAGE_TEST is not set, only the "file", "serial", "ro",
1413 + * "removable", "luns", "nofua", "stall", and "cdrom" options are available;
1414 + * default values are used for everything else.
1416 + * The pathnames of the backing files and the ro settings are available in
1417 + * the attribute files "file", "nofua", and "ro" in the lun<n> subdirectory of
1418 + * the gadget's sysfs directory. If the "removable" option is set, writing to
1419 + * these files will simulate ejecting/loading the medium (writing an empty
1420 + * line means eject) and adjusting a write-enable tab. Changes to the ro
1421 + * setting are not allowed when the medium is loaded or if CD-ROM emulation
1424 + * This gadget driver is heavily based on "Gadget Zero" by David Brownell.
1425 + * The driver's SCSI command interface was based on the "Information
1426 + * technology - Small Computer System Interface - 2" document from
1427 + * X3T9.2 Project 375D, Revision 10L, 7-SEP-93, available at
1428 + * <http://www.t10.org/ftp/t10/drafts/s2/s2-r10l.pdf>. The single exception
1429 + * is opcode 0x23 (READ FORMAT CAPACITIES), which was based on the
1430 + * "Universal Serial Bus Mass Storage Class UFI Command Specification"
1431 + * document, Revision 1.0, December 14, 1998, available at
1432 + * <http://www.usb.org/developers/devclass_docs/usbmass-ufi10.pdf>.
1439 + * The FSG driver is fairly straightforward. There is a main kernel
1440 + * thread that handles most of the work. Interrupt routines field
1441 + * callbacks from the controller driver: bulk- and interrupt-request
1442 + * completion notifications, endpoint-0 events, and disconnect events.
1443 + * Completion events are passed to the main thread by wakeup calls. Many
1444 + * ep0 requests are handled at interrupt time, but SetInterface,
1445 + * SetConfiguration, and device reset requests are forwarded to the
1446 + * thread in the form of "exceptions" using SIGUSR1 signals (since they
1447 + * should interrupt any ongoing file I/O operations).
1449 + * The thread's main routine implements the standard command/data/status
1450 + * parts of a SCSI interaction. It and its subroutines are full of tests
1451 + * for pending signals/exceptions -- all this polling is necessary since
1452 + * the kernel has no setjmp/longjmp equivalents. (Maybe this is an
1453 + * indication that the driver really wants to be running in userspace.)
1454 + * An important point is that so long as the thread is alive it keeps an
1455 + * open reference to the backing file. This will prevent unmounting
1456 + * the backing file's underlying filesystem and could cause problems
1457 + * during system shutdown, for example. To prevent such problems, the
1458 + * thread catches INT, TERM, and KILL signals and converts them into
1459 + * an EXIT exception.
1461 + * In normal operation the main thread is started during the gadget's
1462 + * fsg_bind() callback and stopped during fsg_unbind(). But it can also
1463 + * exit when it receives a signal, and there's no point leaving the
1464 + * gadget running when the thread is dead. So just before the thread
1465 + * exits, it deregisters the gadget driver. This makes things a little
1466 + * tricky: The driver is deregistered at two places, and the exiting
1467 + * thread can indirectly call fsg_unbind() which in turn can tell the
1468 + * thread to exit. The first problem is resolved through the use of the
1469 + * REGISTERED atomic bitflag; the driver will only be deregistered once.
1470 + * The second problem is resolved by having fsg_unbind() check
1471 + * fsg->state; it won't try to stop the thread if the state is already
1472 + * FSG_STATE_TERMINATED.
1474 + * To provide maximum throughput, the driver uses a circular pipeline of
1475 + * buffer heads (struct fsg_buffhd). In principle the pipeline can be
1476 + * arbitrarily long; in practice the benefits don't justify having more
1477 + * than 2 stages (i.e., double buffering). But it helps to think of the
1478 + * pipeline as being a long one. Each buffer head contains a bulk-in and
1479 + * a bulk-out request pointer (since the buffer can be used for both
1480 + * output and input -- directions always are given from the host's
1481 + * point of view) as well as a pointer to the buffer and various state
1484 + * Use of the pipeline follows a simple protocol. There is a variable
1485 + * (fsg->next_buffhd_to_fill) that points to the next buffer head to use.
1486 + * At any time that buffer head may still be in use from an earlier
1487 + * request, so each buffer head has a state variable indicating whether
1488 + * it is EMPTY, FULL, or BUSY. Typical use involves waiting for the
1489 + * buffer head to be EMPTY, filling the buffer either by file I/O or by
1490 + * USB I/O (during which the buffer head is BUSY), and marking the buffer
1491 + * head FULL when the I/O is complete. Then the buffer will be emptied
1492 + * (again possibly by USB I/O, during which it is marked BUSY) and
1493 + * finally marked EMPTY again (possibly by a completion routine).
1495 + * A module parameter tells the driver to avoid stalling the bulk
1496 + * endpoints wherever the transport specification allows. This is
1497 + * necessary for some UDCs like the SuperH, which cannot reliably clear a
1498 + * halt on a bulk endpoint. However, under certain circumstances the
1499 + * Bulk-only specification requires a stall. In such cases the driver
1500 + * will halt the endpoint and set a flag indicating that it should clear
1501 + * the halt in software during the next device reset. Hopefully this
1502 + * will permit everything to work correctly. Furthermore, although the
1503 + * specification allows the bulk-out endpoint to halt when the host sends
1504 + * too much data, implementing this would cause an unavoidable race.
1505 + * The driver will always use the "no-stall" approach for OUT transfers.
1507 + * One subtle point concerns sending status-stage responses for ep0
1508 + * requests. Some of these requests, such as device reset, can involve
1509 + * interrupting an ongoing file I/O operation, which might take an
1510 + * arbitrarily long time. During that delay the host might give up on
1511 + * the original ep0 request and issue a new one. When that happens the
1512 + * driver should not notify the host about completion of the original
1513 + * request, as the host will no longer be waiting for it. So the driver
1514 + * assigns to each ep0 request a unique tag, and it keeps track of the
1515 + * tag value of the request associated with a long-running exception
1516 + * (device-reset, interface-change, or configuration-change). When the
1517 + * exception handler is finished, the status-stage response is submitted
1518 + * only if the current ep0 request tag is equal to the exception request
1519 + * tag. Thus only the most recently received ep0 request will get a
1520 + * status-stage response.
1522 + * Warning: This driver source file is too long. It ought to be split up
1523 + * into a header file plus about 3 separate .c files, to handle the details
1524 + * of the Gadget, USB Mass Storage, and SCSI protocols.
1528 +/* #define VERBOSE_DEBUG */
1529 +/* #define DUMP_MSGS */
1532 +#include <linux/blkdev.h>
1533 +#include <linux/completion.h>
1534 +#include <linux/dcache.h>
1535 +#include <linux/delay.h>
1536 +#include <linux/device.h>
1537 +#include <linux/fcntl.h>
1538 +#include <linux/file.h>
1539 +#include <linux/fs.h>
1540 +#include <linux/kref.h>
1541 +#include <linux/kthread.h>
1542 +#include <linux/limits.h>
1543 +#include <linux/module.h>
1544 +#include <linux/rwsem.h>
1545 +#include <linux/slab.h>
1546 +#include <linux/spinlock.h>
1547 +#include <linux/string.h>
1548 +#include <linux/freezer.h>
1549 +#include <linux/utsname.h>
1551 +#include <linux/usb/ch9.h>
1552 +#include <linux/usb/gadget.h>
1554 +#include "gadget_chips.h"
1559 + * Kbuild is not very cooperative with respect to linking separately
1560 + * compiled library objects into one module. So for now we won't use
1561 + * separate compilation ... ensuring init/exit sections work to shrink
1562 + * the runtime footprint, and giving us at least some parts of what
1563 + * a "gcc --combine ... part1.c part2.c part3.c ... " build would.
1565 +#include "usbstring.c"
1566 +#include "config.c"
1567 +#include "epautoconf.c"
1569 +/*-------------------------------------------------------------------------*/
1571 +#define DRIVER_DESC "File-backed Storage Gadget"
1572 +#define DRIVER_NAME "g_file_storage"
1573 +#define DRIVER_VERSION "1 September 2010"
1575 +static char fsg_string_manufacturer[64];
1576 +static const char fsg_string_product[] = DRIVER_DESC;
1577 +static const char fsg_string_config[] = "Self-powered";
1578 +static const char fsg_string_interface[] = "Mass Storage";
1581 +#include "storage_common.c"
1584 +MODULE_DESCRIPTION(DRIVER_DESC);
1585 +MODULE_AUTHOR("Alan Stern");
1586 +MODULE_LICENSE("Dual BSD/GPL");
1589 + * This driver assumes self-powered hardware and has no way for users to
1590 + * trigger remote wakeup. It uses autoconfiguration to select endpoints
1591 + * and endpoint addresses.
1595 +/*-------------------------------------------------------------------------*/
1598 +/* Encapsulate the module parameter settings */
1601 + char *file[FSG_MAX_LUNS];
1603 + bool ro[FSG_MAX_LUNS];
1604 + bool nofua[FSG_MAX_LUNS];
1605 + unsigned int num_filenames;
1606 + unsigned int num_ros;
1607 + unsigned int num_nofuas;
1608 + unsigned int nluns;
1614 + char *transport_parm;
1615 + char *protocol_parm;
1616 + unsigned short vendor;
1617 + unsigned short product;
1618 + unsigned short release;
1619 + unsigned int buflen;
1621 + int transport_type;
1622 + char *transport_name;
1623 + int protocol_type;
1624 + char *protocol_name;
1626 +} mod_data = { // Default values
1627 + .transport_parm = "BBB",
1628 + .protocol_parm = "SCSI",
1632 + .vendor = FSG_VENDOR_ID,
1633 + .product = FSG_PRODUCT_ID,
1634 + .release = 0xffff, // Use controller chip type
1639 +module_param_array_named(file, mod_data.file, charp, &mod_data.num_filenames,
1641 +MODULE_PARM_DESC(file, "names of backing files or devices");
1643 +module_param_named(serial, mod_data.serial, charp, S_IRUGO);
1644 +MODULE_PARM_DESC(serial, "USB serial number");
1646 +module_param_array_named(ro, mod_data.ro, bool, &mod_data.num_ros, S_IRUGO);
1647 +MODULE_PARM_DESC(ro, "true to force read-only");
1649 +module_param_array_named(nofua, mod_data.nofua, bool, &mod_data.num_nofuas,
1651 +MODULE_PARM_DESC(nofua, "true to ignore SCSI WRITE(10,12) FUA bit");
1653 +module_param_named(luns, mod_data.nluns, uint, S_IRUGO);
1654 +MODULE_PARM_DESC(luns, "number of LUNs");
1656 +module_param_named(removable, mod_data.removable, bool, S_IRUGO);
1657 +MODULE_PARM_DESC(removable, "true to simulate removable media");
1659 +module_param_named(stall, mod_data.can_stall, bool, S_IRUGO);
1660 +MODULE_PARM_DESC(stall, "false to prevent bulk stalls");
1662 +module_param_named(cdrom, mod_data.cdrom, bool, S_IRUGO);
1663 +MODULE_PARM_DESC(cdrom, "true to emulate cdrom instead of disk");
1665 +/* In the non-TEST version, only the module parameters listed above
1666 + * are available. */
1667 +#ifdef CONFIG_USB_FILE_STORAGE_TEST
1669 +module_param_named(transport, mod_data.transport_parm, charp, S_IRUGO);
1670 +MODULE_PARM_DESC(transport, "type of transport (BBB, CBI, or CB)");
1672 +module_param_named(protocol, mod_data.protocol_parm, charp, S_IRUGO);
1673 +MODULE_PARM_DESC(protocol, "type of protocol (RBC, 8020, QIC, UFI, "
1674 + "8070, or SCSI)");
1676 +module_param_named(vendor, mod_data.vendor, ushort, S_IRUGO);
1677 +MODULE_PARM_DESC(vendor, "USB Vendor ID");
1679 +module_param_named(product, mod_data.product, ushort, S_IRUGO);
1680 +MODULE_PARM_DESC(product, "USB Product ID");
1682 +module_param_named(release, mod_data.release, ushort, S_IRUGO);
1683 +MODULE_PARM_DESC(release, "USB release number");
1685 +module_param_named(buflen, mod_data.buflen, uint, S_IRUGO);
1686 +MODULE_PARM_DESC(buflen, "I/O buffer size");
1688 +#endif /* CONFIG_USB_FILE_STORAGE_TEST */
1692 + * These definitions will permit the compiler to avoid generating code for
1693 + * parts of the driver that aren't used in the non-TEST version. Even gcc
1694 + * can recognize when a test of a constant expression yields a dead code
1698 +#ifdef CONFIG_USB_FILE_STORAGE_TEST
1700 +#define transport_is_bbb() (mod_data.transport_type == USB_PR_BULK)
1701 +#define transport_is_cbi() (mod_data.transport_type == USB_PR_CBI)
1702 +#define protocol_is_scsi() (mod_data.protocol_type == USB_SC_SCSI)
1706 +#define transport_is_bbb() 1
1707 +#define transport_is_cbi() 0
1708 +#define protocol_is_scsi() 1
1710 +#endif /* CONFIG_USB_FILE_STORAGE_TEST */
1713 +/*-------------------------------------------------------------------------*/
1717 + /* lock protects: state, all the req_busy's, and cbbuf_cmnd */
1719 + struct usb_gadget *gadget;
1721 + /* filesem protects: backing files in use */
1722 + struct rw_semaphore filesem;
1724 + /* reference counting: wait until all LUNs are released */
1727 + struct usb_ep *ep0; // Handy copy of gadget->ep0
1728 + struct usb_request *ep0req; // For control responses
1729 + unsigned int ep0_req_tag;
1730 + const char *ep0req_name;
1732 + struct usb_request *intreq; // For interrupt responses
1734 + struct fsg_buffhd *intr_buffhd;
1736 + unsigned int bulk_out_maxpacket;
1737 + enum fsg_state state; // For exception handling
1738 + unsigned int exception_req_tag;
1740 + u8 config, new_config;
1742 + unsigned int running : 1;
1743 + unsigned int bulk_in_enabled : 1;
1744 + unsigned int bulk_out_enabled : 1;
1745 + unsigned int intr_in_enabled : 1;
1746 + unsigned int phase_error : 1;
1747 + unsigned int short_packet_received : 1;
1748 + unsigned int bad_lun_okay : 1;
1750 + unsigned long atomic_bitflags;
1751 +#define REGISTERED 0
1752 +#define IGNORE_BULK_OUT 1
1753 +#define SUSPENDED 2
1755 + struct usb_ep *bulk_in;
1756 + struct usb_ep *bulk_out;
1757 + struct usb_ep *intr_in;
1759 + struct fsg_buffhd *next_buffhd_to_fill;
1760 + struct fsg_buffhd *next_buffhd_to_drain;
1762 + int thread_wakeup_needed;
1763 + struct completion thread_notifier;
1764 + struct task_struct *thread_task;
1767 + u8 cmnd[MAX_COMMAND_SIZE];
1768 + enum data_direction data_dir;
1770 + u32 data_size_from_cmnd;
1774 + u32 usb_amount_left;
1776 + /* The CB protocol offers no way for a host to know when a command
1777 + * has completed. As a result the next command may arrive early,
1778 + * and we will still have to handle it. For that reason we need
1779 + * a buffer to store new commands when using CB (or CBI, which
1780 + * does not oblige a host to wait for command completion either). */
1781 + int cbbuf_cmnd_size;
1782 + u8 cbbuf_cmnd[MAX_COMMAND_SIZE];
1784 + unsigned int nluns;
1785 + struct fsg_lun *luns;
1786 + struct fsg_lun *curlun;
1787 + /* Must be the last entry */
1788 + struct fsg_buffhd buffhds[];
1791 +typedef void (*fsg_routine_t)(struct fsg_dev *);
1793 +static int exception_in_progress(struct fsg_dev *fsg)
1795 + return (fsg->state > FSG_STATE_IDLE);
1798 +/* Make bulk-out requests be divisible by the maxpacket size */
1799 +static void set_bulk_out_req_length(struct fsg_dev *fsg,
1800 + struct fsg_buffhd *bh, unsigned int length)
1804 + bh->bulk_out_intended_length = length;
1805 + rem = length % fsg->bulk_out_maxpacket;
1807 + length += fsg->bulk_out_maxpacket - rem;
1808 + bh->outreq->length = length;
1811 +static struct fsg_dev *the_fsg;
1812 +static struct usb_gadget_driver fsg_driver;
1815 +/*-------------------------------------------------------------------------*/
1817 +static int fsg_set_halt(struct fsg_dev *fsg, struct usb_ep *ep)
1821 + if (ep == fsg->bulk_in)
1823 + else if (ep == fsg->bulk_out)
1824 + name = "bulk-out";
1827 + DBG(fsg, "%s set halt\n", name);
1828 + return usb_ep_set_halt(ep);
1832 +/*-------------------------------------------------------------------------*/
1835 + * DESCRIPTORS ... most are static, but strings and (full) configuration
1836 + * descriptors are built on demand. Also the (static) config and interface
1837 + * descriptors are adjusted during fsg_bind().
1840 +/* There is only one configuration. */
1841 +#define CONFIG_VALUE 1
1843 +static struct usb_device_descriptor
1845 + .bLength = sizeof device_desc,
1846 + .bDescriptorType = USB_DT_DEVICE,
1848 + .bcdUSB = cpu_to_le16(0x0200),
1849 + .bDeviceClass = USB_CLASS_PER_INTERFACE,
1851 + /* The next three values can be overridden by module parameters */
1852 + .idVendor = cpu_to_le16(FSG_VENDOR_ID),
1853 + .idProduct = cpu_to_le16(FSG_PRODUCT_ID),
1854 + .bcdDevice = cpu_to_le16(0xffff),
1856 + .iManufacturer = FSG_STRING_MANUFACTURER,
1857 + .iProduct = FSG_STRING_PRODUCT,
1858 + .iSerialNumber = FSG_STRING_SERIAL,
1859 + .bNumConfigurations = 1,
1862 +static struct usb_config_descriptor
1864 + .bLength = sizeof config_desc,
1865 + .bDescriptorType = USB_DT_CONFIG,
1867 + /* wTotalLength computed by usb_gadget_config_buf() */
1868 + .bNumInterfaces = 1,
1869 + .bConfigurationValue = CONFIG_VALUE,
1870 + .iConfiguration = FSG_STRING_CONFIG,
1871 + .bmAttributes = USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER,
1872 + .bMaxPower = CONFIG_USB_GADGET_VBUS_DRAW / 2,
1876 +static struct usb_qualifier_descriptor
1878 + .bLength = sizeof dev_qualifier,
1879 + .bDescriptorType = USB_DT_DEVICE_QUALIFIER,
1881 + .bcdUSB = cpu_to_le16(0x0200),
1882 + .bDeviceClass = USB_CLASS_PER_INTERFACE,
1884 + .bNumConfigurations = 1,
1887 +static int populate_bos(struct fsg_dev *fsg, u8 *buf)
1889 + memcpy(buf, &fsg_bos_desc, USB_DT_BOS_SIZE);
1890 + buf += USB_DT_BOS_SIZE;
1892 + memcpy(buf, &fsg_ext_cap_desc, USB_DT_USB_EXT_CAP_SIZE);
1893 + buf += USB_DT_USB_EXT_CAP_SIZE;
1895 + memcpy(buf, &fsg_ss_cap_desc, USB_DT_USB_SS_CAP_SIZE);
1897 + return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE
1898 + + USB_DT_USB_EXT_CAP_SIZE;
1902 + * Config descriptors must agree with the code that sets configurations
1903 + * and with code managing interfaces and their altsettings. They must
1904 + * also handle different speeds and other-speed requests.
1906 +static int populate_config_buf(struct usb_gadget *gadget,
1907 + u8 *buf, u8 type, unsigned index)
1909 + enum usb_device_speed speed = gadget->speed;
1911 + const struct usb_descriptor_header **function;
1916 + if (gadget_is_dualspeed(gadget) && type == USB_DT_OTHER_SPEED_CONFIG)
1917 + speed = (USB_SPEED_FULL + USB_SPEED_HIGH) - speed;
1918 + function = gadget_is_dualspeed(gadget) && speed == USB_SPEED_HIGH
1919 + ? (const struct usb_descriptor_header **)fsg_hs_function
1920 + : (const struct usb_descriptor_header **)fsg_fs_function;
1922 + /* for now, don't advertise srp-only devices */
1923 + if (!gadget_is_otg(gadget))
1926 + len = usb_gadget_config_buf(&config_desc, buf, EP0_BUFSIZE, function);
1927 + ((struct usb_config_descriptor *) buf)->bDescriptorType = type;
1932 +/*-------------------------------------------------------------------------*/
1934 +/* These routines may be called in process context or in_irq */
1936 +/* Caller must hold fsg->lock */
1937 +static void wakeup_thread(struct fsg_dev *fsg)
1939 + /* Tell the main thread that something has happened */
1940 + fsg->thread_wakeup_needed = 1;
1941 + if (fsg->thread_task)
1942 + wake_up_process(fsg->thread_task);
1946 +static void raise_exception(struct fsg_dev *fsg, enum fsg_state new_state)
1948 + unsigned long flags;
1950 + /* Do nothing if a higher-priority exception is already in progress.
1951 + * If a lower-or-equal priority exception is in progress, preempt it
1952 + * and notify the main thread by sending it a signal. */
1953 + spin_lock_irqsave(&fsg->lock, flags);
1954 + if (fsg->state <= new_state) {
1955 + fsg->exception_req_tag = fsg->ep0_req_tag;
1956 + fsg->state = new_state;
1957 + if (fsg->thread_task)
1958 + send_sig_info(SIGUSR1, SEND_SIG_FORCED,
1959 + fsg->thread_task);
1961 + spin_unlock_irqrestore(&fsg->lock, flags);
1965 +/*-------------------------------------------------------------------------*/
1967 +/* The disconnect callback and ep0 routines. These always run in_irq,
1968 + * except that ep0_queue() is called in the main thread to acknowledge
1969 + * completion of various requests: set config, set interface, and
1970 + * Bulk-only device reset. */
1972 +static void fsg_disconnect(struct usb_gadget *gadget)
1974 + struct fsg_dev *fsg = get_gadget_data(gadget);
1976 + DBG(fsg, "disconnect or port reset\n");
1977 + raise_exception(fsg, FSG_STATE_DISCONNECT);
1981 +static int ep0_queue(struct fsg_dev *fsg)
1985 + rc = usb_ep_queue(fsg->ep0, fsg->ep0req, GFP_ATOMIC);
1986 + if (rc != 0 && rc != -ESHUTDOWN) {
1988 + /* We can't do much more than wait for a reset */
1989 + WARNING(fsg, "error in submission: %s --> %d\n",
1990 + fsg->ep0->name, rc);
1995 +static void ep0_complete(struct usb_ep *ep, struct usb_request *req)
1997 + struct fsg_dev *fsg = ep->driver_data;
1999 + if (req->actual > 0)
2000 + dump_msg(fsg, fsg->ep0req_name, req->buf, req->actual);
2001 + if (req->status || req->actual != req->length)
2002 + DBG(fsg, "%s --> %d, %u/%u\n", __func__,
2003 + req->status, req->actual, req->length);
2004 + if (req->status == -ECONNRESET) // Request was cancelled
2005 + usb_ep_fifo_flush(ep);
2007 + if (req->status == 0 && req->context)
2008 + ((fsg_routine_t) (req->context))(fsg);
2012 +/*-------------------------------------------------------------------------*/
2014 +/* Bulk and interrupt endpoint completion handlers.
2015 + * These always run in_irq. */
2017 +static void bulk_in_complete(struct usb_ep *ep, struct usb_request *req)
2019 + struct fsg_dev *fsg = ep->driver_data;
2020 + struct fsg_buffhd *bh = req->context;
2022 + if (req->status || req->actual != req->length)
2023 + DBG(fsg, "%s --> %d, %u/%u\n", __func__,
2024 + req->status, req->actual, req->length);
2025 + if (req->status == -ECONNRESET) // Request was cancelled
2026 + usb_ep_fifo_flush(ep);
2028 + /* Hold the lock while we update the request and buffer states */
2030 + spin_lock(&fsg->lock);
2031 + bh->inreq_busy = 0;
2032 + bh->state = BUF_STATE_EMPTY;
2033 + wakeup_thread(fsg);
2034 + spin_unlock(&fsg->lock);
2037 +static void bulk_out_complete(struct usb_ep *ep, struct usb_request *req)
2039 + struct fsg_dev *fsg = ep->driver_data;
2040 + struct fsg_buffhd *bh = req->context;
2042 + dump_msg(fsg, "bulk-out", req->buf, req->actual);
2043 + if (req->status || req->actual != bh->bulk_out_intended_length)
2044 + DBG(fsg, "%s --> %d, %u/%u\n", __func__,
2045 + req->status, req->actual,
2046 + bh->bulk_out_intended_length);
2047 + if (req->status == -ECONNRESET) // Request was cancelled
2048 + usb_ep_fifo_flush(ep);
2050 + /* Hold the lock while we update the request and buffer states */
2052 + spin_lock(&fsg->lock);
2053 + bh->outreq_busy = 0;
2054 + bh->state = BUF_STATE_FULL;
2055 + wakeup_thread(fsg);
2056 + spin_unlock(&fsg->lock);
2060 +#ifdef CONFIG_USB_FILE_STORAGE_TEST
2061 +static void intr_in_complete(struct usb_ep *ep, struct usb_request *req)
2063 + struct fsg_dev *fsg = ep->driver_data;
2064 + struct fsg_buffhd *bh = req->context;
2066 + if (req->status || req->actual != req->length)
2067 + DBG(fsg, "%s --> %d, %u/%u\n", __func__,
2068 + req->status, req->actual, req->length);
2069 + if (req->status == -ECONNRESET) // Request was cancelled
2070 + usb_ep_fifo_flush(ep);
2072 + /* Hold the lock while we update the request and buffer states */
2074 + spin_lock(&fsg->lock);
2075 + fsg->intreq_busy = 0;
2076 + bh->state = BUF_STATE_EMPTY;
2077 + wakeup_thread(fsg);
2078 + spin_unlock(&fsg->lock);
2082 +static void intr_in_complete(struct usb_ep *ep, struct usb_request *req)
2084 +#endif /* CONFIG_USB_FILE_STORAGE_TEST */
2087 +/*-------------------------------------------------------------------------*/
2089 +/* Ep0 class-specific handlers. These always run in_irq. */
2091 +#ifdef CONFIG_USB_FILE_STORAGE_TEST
2092 +static void received_cbi_adsc(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2094 + struct usb_request *req = fsg->ep0req;
2095 + static u8 cbi_reset_cmnd[6] = {
2096 + SEND_DIAGNOSTIC, 4, 0xff, 0xff, 0xff, 0xff};
2098 + /* Error in command transfer? */
2099 + if (req->status || req->length != req->actual ||
2100 + req->actual < 6 || req->actual > MAX_COMMAND_SIZE) {
2102 + /* Not all controllers allow a protocol stall after
2103 + * receiving control-out data, but we'll try anyway. */
2104 + fsg_set_halt(fsg, fsg->ep0);
2105 + return; // Wait for reset
2108 + /* Is it the special reset command? */
2109 + if (req->actual >= sizeof cbi_reset_cmnd &&
2110 + memcmp(req->buf, cbi_reset_cmnd,
2111 + sizeof cbi_reset_cmnd) == 0) {
2113 + /* Raise an exception to stop the current operation
2114 + * and reinitialize our state. */
2115 + DBG(fsg, "cbi reset request\n");
2116 + raise_exception(fsg, FSG_STATE_RESET);
2120 + VDBG(fsg, "CB[I] accept device-specific command\n");
2121 + spin_lock(&fsg->lock);
2123 + /* Save the command for later */
2124 + if (fsg->cbbuf_cmnd_size)
2125 + WARNING(fsg, "CB[I] overwriting previous command\n");
2126 + fsg->cbbuf_cmnd_size = req->actual;
2127 + memcpy(fsg->cbbuf_cmnd, req->buf, fsg->cbbuf_cmnd_size);
2129 + wakeup_thread(fsg);
2130 + spin_unlock(&fsg->lock);
2134 +static void received_cbi_adsc(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2136 +#endif /* CONFIG_USB_FILE_STORAGE_TEST */
2139 +static int class_setup_req(struct fsg_dev *fsg,
2140 + const struct usb_ctrlrequest *ctrl)
2142 + struct usb_request *req = fsg->ep0req;
2143 + int value = -EOPNOTSUPP;
2144 + u16 w_index = le16_to_cpu(ctrl->wIndex);
2145 + u16 w_value = le16_to_cpu(ctrl->wValue);
2146 + u16 w_length = le16_to_cpu(ctrl->wLength);
2151 + /* Handle Bulk-only class-specific requests */
2152 + if (transport_is_bbb()) {
2153 + switch (ctrl->bRequest) {
2155 + case US_BULK_RESET_REQUEST:
2156 + if (ctrl->bRequestType != (USB_DIR_OUT |
2157 + USB_TYPE_CLASS | USB_RECIP_INTERFACE))
2159 + if (w_index != 0 || w_value != 0 || w_length != 0) {
2164 + /* Raise an exception to stop the current operation
2165 + * and reinitialize our state. */
2166 + DBG(fsg, "bulk reset request\n");
2167 + raise_exception(fsg, FSG_STATE_RESET);
2168 + value = DELAYED_STATUS;
2171 + case US_BULK_GET_MAX_LUN:
2172 + if (ctrl->bRequestType != (USB_DIR_IN |
2173 + USB_TYPE_CLASS | USB_RECIP_INTERFACE))
2175 + if (w_index != 0 || w_value != 0 || w_length != 1) {
2179 + VDBG(fsg, "get max LUN\n");
2180 + *(u8 *) req->buf = fsg->nluns - 1;
2186 + /* Handle CBI class-specific requests */
2188 + switch (ctrl->bRequest) {
2190 + case USB_CBI_ADSC_REQUEST:
2191 + if (ctrl->bRequestType != (USB_DIR_OUT |
2192 + USB_TYPE_CLASS | USB_RECIP_INTERFACE))
2194 + if (w_index != 0 || w_value != 0) {
2198 + if (w_length > MAX_COMMAND_SIZE) {
2199 + value = -EOVERFLOW;
2203 + fsg->ep0req->context = received_cbi_adsc;
2208 + if (value == -EOPNOTSUPP)
2210 + "unknown class-specific control req "
2211 + "%02x.%02x v%04x i%04x l%u\n",
2212 + ctrl->bRequestType, ctrl->bRequest,
2213 + le16_to_cpu(ctrl->wValue), w_index, w_length);
2218 +/*-------------------------------------------------------------------------*/
2220 +/* Ep0 standard request handlers. These always run in_irq. */
2222 +static int standard_setup_req(struct fsg_dev *fsg,
2223 + const struct usb_ctrlrequest *ctrl)
2225 + struct usb_request *req = fsg->ep0req;
2226 + int value = -EOPNOTSUPP;
2227 + u16 w_index = le16_to_cpu(ctrl->wIndex);
2228 + u16 w_value = le16_to_cpu(ctrl->wValue);
2230 + /* Usually this just stores reply data in the pre-allocated ep0 buffer,
2231 + * but config change events will also reconfigure hardware. */
2232 + switch (ctrl->bRequest) {
2234 + case USB_REQ_GET_DESCRIPTOR:
2235 + if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD |
2236 + USB_RECIP_DEVICE))
2238 + switch (w_value >> 8) {
2240 + case USB_DT_DEVICE:
2241 + VDBG(fsg, "get device descriptor\n");
2242 + device_desc.bMaxPacketSize0 = fsg->ep0->maxpacket;
2243 + value = sizeof device_desc;
2244 + memcpy(req->buf, &device_desc, value);
2246 + case USB_DT_DEVICE_QUALIFIER:
2247 + VDBG(fsg, "get device qualifier\n");
2248 + if (!gadget_is_dualspeed(fsg->gadget) ||
2249 + fsg->gadget->speed == USB_SPEED_SUPER)
2252 + * Assume ep0 uses the same maxpacket value for both
2255 + dev_qualifier.bMaxPacketSize0 = fsg->ep0->maxpacket;
2256 + value = sizeof dev_qualifier;
2257 + memcpy(req->buf, &dev_qualifier, value);
2260 + case USB_DT_OTHER_SPEED_CONFIG:
2261 + VDBG(fsg, "get other-speed config descriptor\n");
2262 + if (!gadget_is_dualspeed(fsg->gadget) ||
2263 + fsg->gadget->speed == USB_SPEED_SUPER)
2266 + case USB_DT_CONFIG:
2267 + VDBG(fsg, "get configuration descriptor\n");
2269 + value = populate_config_buf(fsg->gadget,
2275 + case USB_DT_STRING:
2276 + VDBG(fsg, "get string descriptor\n");
2278 + /* wIndex == language code */
2279 + value = usb_gadget_get_string(&fsg_stringtab,
2280 + w_value & 0xff, req->buf);
2284 + VDBG(fsg, "get bos descriptor\n");
2286 + if (gadget_is_superspeed(fsg->gadget))
2287 + value = populate_bos(fsg, req->buf);
2293 + /* One config, two speeds */
2294 + case USB_REQ_SET_CONFIGURATION:
2295 + if (ctrl->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD |
2296 + USB_RECIP_DEVICE))
2298 + VDBG(fsg, "set configuration\n");
2299 + if (w_value == CONFIG_VALUE || w_value == 0) {
2300 + fsg->new_config = w_value;
2302 + /* Raise an exception to wipe out previous transaction
2303 + * state (queued bufs, etc) and set the new config. */
2304 + raise_exception(fsg, FSG_STATE_CONFIG_CHANGE);
2305 + value = DELAYED_STATUS;
2308 + case USB_REQ_GET_CONFIGURATION:
2309 + if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD |
2310 + USB_RECIP_DEVICE))
2312 + VDBG(fsg, "get configuration\n");
2313 + *(u8 *) req->buf = fsg->config;
2317 + case USB_REQ_SET_INTERFACE:
2318 + if (ctrl->bRequestType != (USB_DIR_OUT| USB_TYPE_STANDARD |
2319 + USB_RECIP_INTERFACE))
2321 + if (fsg->config && w_index == 0) {
2323 + /* Raise an exception to wipe out previous transaction
2324 + * state (queued bufs, etc) and install the new
2325 + * interface altsetting. */
2326 + raise_exception(fsg, FSG_STATE_INTERFACE_CHANGE);
2327 + value = DELAYED_STATUS;
2330 + case USB_REQ_GET_INTERFACE:
2331 + if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD |
2332 + USB_RECIP_INTERFACE))
2336 + if (w_index != 0) {
2340 + VDBG(fsg, "get interface\n");
2341 + *(u8 *) req->buf = 0;
2347 + "unknown control req %02x.%02x v%04x i%04x l%u\n",
2348 + ctrl->bRequestType, ctrl->bRequest,
2349 + w_value, w_index, le16_to_cpu(ctrl->wLength));
2356 +static int fsg_setup(struct usb_gadget *gadget,
2357 + const struct usb_ctrlrequest *ctrl)
2359 + struct fsg_dev *fsg = get_gadget_data(gadget);
2361 + int w_length = le16_to_cpu(ctrl->wLength);
2363 + ++fsg->ep0_req_tag; // Record arrival of a new request
2364 + fsg->ep0req->context = NULL;
2365 + fsg->ep0req->length = 0;
2366 + dump_msg(fsg, "ep0-setup", (u8 *) ctrl, sizeof(*ctrl));
2368 + if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_CLASS)
2369 + rc = class_setup_req(fsg, ctrl);
2371 + rc = standard_setup_req(fsg, ctrl);
2373 + /* Respond with data/status or defer until later? */
2374 + if (rc >= 0 && rc != DELAYED_STATUS) {
2375 + rc = min(rc, w_length);
2376 + fsg->ep0req->length = rc;
2377 + fsg->ep0req->zero = rc < w_length;
2378 + fsg->ep0req_name = (ctrl->bRequestType & USB_DIR_IN ?
2379 + "ep0-in" : "ep0-out");
2380 + rc = ep0_queue(fsg);
2383 + /* Device either stalls (rc < 0) or reports success */
2388 +/*-------------------------------------------------------------------------*/
2390 +/* All the following routines run in process context */
2393 +/* Use this for bulk or interrupt transfers, not ep0 */
2394 +static void start_transfer(struct fsg_dev *fsg, struct usb_ep *ep,
2395 + struct usb_request *req, int *pbusy,
2396 + enum fsg_buffer_state *state)
2400 + if (ep == fsg->bulk_in)
2401 + dump_msg(fsg, "bulk-in", req->buf, req->length);
2402 + else if (ep == fsg->intr_in)
2403 + dump_msg(fsg, "intr-in", req->buf, req->length);
2405 + spin_lock_irq(&fsg->lock);
2407 + *state = BUF_STATE_BUSY;
2408 + spin_unlock_irq(&fsg->lock);
2409 + rc = usb_ep_queue(ep, req, GFP_KERNEL);
2412 + *state = BUF_STATE_EMPTY;
2414 + /* We can't do much more than wait for a reset */
2416 + /* Note: currently the net2280 driver fails zero-length
2417 + * submissions if DMA is enabled. */
2418 + if (rc != -ESHUTDOWN && !(rc == -EOPNOTSUPP &&
2419 + req->length == 0))
2420 + WARNING(fsg, "error in submission: %s --> %d\n",
2426 +static int sleep_thread(struct fsg_dev *fsg)
2430 + /* Wait until a signal arrives or we are woken up */
2433 + set_current_state(TASK_INTERRUPTIBLE);
2434 + if (signal_pending(current)) {
2438 + if (fsg->thread_wakeup_needed)
2442 + __set_current_state(TASK_RUNNING);
2443 + fsg->thread_wakeup_needed = 0;
2448 +/*-------------------------------------------------------------------------*/
2450 +static int do_read(struct fsg_dev *fsg)
2452 + struct fsg_lun *curlun = fsg->curlun;
2454 + struct fsg_buffhd *bh;
2457 + loff_t file_offset, file_offset_tmp;
2458 + unsigned int amount;
2461 + /* Get the starting Logical Block Address and check that it's
2463 + if (fsg->cmnd[0] == READ_6)
2464 + lba = get_unaligned_be24(&fsg->cmnd[1]);
2466 + lba = get_unaligned_be32(&fsg->cmnd[2]);
2468 + /* We allow DPO (Disable Page Out = don't save data in the
2469 + * cache) and FUA (Force Unit Access = don't read from the
2470 + * cache), but we don't implement them. */
2471 + if ((fsg->cmnd[1] & ~0x18) != 0) {
2472 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2476 + if (lba >= curlun->num_sectors) {
2477 + curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
2480 + file_offset = ((loff_t) lba) << curlun->blkbits;
2482 + /* Carry out the file reads */
2483 + amount_left = fsg->data_size_from_cmnd;
2484 + if (unlikely(amount_left == 0))
2485 + return -EIO; // No default reply
2489 + /* Figure out how much we need to read:
2490 + * Try to read the remaining amount.
2491 + * But don't read more than the buffer size.
2492 + * And don't try to read past the end of the file.
2494 + amount = min((unsigned int) amount_left, mod_data.buflen);
2495 + amount = min((loff_t) amount,
2496 + curlun->file_length - file_offset);
2498 + /* Wait for the next buffer to become available */
2499 + bh = fsg->next_buffhd_to_fill;
2500 + while (bh->state != BUF_STATE_EMPTY) {
2501 + rc = sleep_thread(fsg);
2506 + /* If we were asked to read past the end of file,
2507 + * end with an empty buffer. */
2508 + if (amount == 0) {
2509 + curlun->sense_data =
2510 + SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
2511 + curlun->sense_data_info = file_offset >> curlun->blkbits;
2512 + curlun->info_valid = 1;
2513 + bh->inreq->length = 0;
2514 + bh->state = BUF_STATE_FULL;
2518 + /* Perform the read */
2519 + file_offset_tmp = file_offset;
2520 + nread = vfs_read(curlun->filp,
2521 + (char __user *) bh->buf,
2522 + amount, &file_offset_tmp);
2523 + VLDBG(curlun, "file read %u @ %llu -> %d\n", amount,
2524 + (unsigned long long) file_offset,
2526 + if (signal_pending(current))
2530 + LDBG(curlun, "error in file read: %d\n",
2533 + } else if (nread < amount) {
2534 + LDBG(curlun, "partial file read: %d/%u\n",
2535 + (int) nread, amount);
2536 + nread = round_down(nread, curlun->blksize);
2538 + file_offset += nread;
2539 + amount_left -= nread;
2540 + fsg->residue -= nread;
2542 + /* Except at the end of the transfer, nread will be
2543 + * equal to the buffer size, which is divisible by the
2544 + * bulk-in maxpacket size.
2546 + bh->inreq->length = nread;
2547 + bh->state = BUF_STATE_FULL;
2549 + /* If an error occurred, report it and its position */
2550 + if (nread < amount) {
2551 + curlun->sense_data = SS_UNRECOVERED_READ_ERROR;
2552 + curlun->sense_data_info = file_offset >> curlun->blkbits;
2553 + curlun->info_valid = 1;
2557 + if (amount_left == 0)
2558 + break; // No more left to read
2560 + /* Send this buffer and go read some more */
2561 + bh->inreq->zero = 0;
2562 + start_transfer(fsg, fsg->bulk_in, bh->inreq,
2563 + &bh->inreq_busy, &bh->state);
2564 + fsg->next_buffhd_to_fill = bh->next;
2567 + return -EIO; // No default reply
2571 +/*-------------------------------------------------------------------------*/
2573 +static int do_write(struct fsg_dev *fsg)
2575 + struct fsg_lun *curlun = fsg->curlun;
2577 + struct fsg_buffhd *bh;
2578 + int get_some_more;
2579 + u32 amount_left_to_req, amount_left_to_write;
2580 + loff_t usb_offset, file_offset, file_offset_tmp;
2581 + unsigned int amount;
2586 + curlun->sense_data = SS_WRITE_PROTECTED;
2589 + spin_lock(&curlun->filp->f_lock);
2590 + curlun->filp->f_flags &= ~O_SYNC; // Default is not to wait
2591 + spin_unlock(&curlun->filp->f_lock);
2593 + /* Get the starting Logical Block Address and check that it's
2595 + if (fsg->cmnd[0] == WRITE_6)
2596 + lba = get_unaligned_be24(&fsg->cmnd[1]);
2598 + lba = get_unaligned_be32(&fsg->cmnd[2]);
2600 + /* We allow DPO (Disable Page Out = don't save data in the
2601 + * cache) and FUA (Force Unit Access = write directly to the
2602 + * medium). We don't implement DPO; we implement FUA by
2603 + * performing synchronous output. */
2604 + if ((fsg->cmnd[1] & ~0x18) != 0) {
2605 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2609 + if (!curlun->nofua && (fsg->cmnd[1] & 0x08)) {
2610 + spin_lock(&curlun->filp->f_lock);
2611 + curlun->filp->f_flags |= O_DSYNC;
2612 + spin_unlock(&curlun->filp->f_lock);
2615 + if (lba >= curlun->num_sectors) {
2616 + curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
2620 + /* Carry out the file writes */
2621 + get_some_more = 1;
2622 + file_offset = usb_offset = ((loff_t) lba) << curlun->blkbits;
2623 + amount_left_to_req = amount_left_to_write = fsg->data_size_from_cmnd;
2625 + while (amount_left_to_write > 0) {
2627 + /* Queue a request for more data from the host */
2628 + bh = fsg->next_buffhd_to_fill;
2629 + if (bh->state == BUF_STATE_EMPTY && get_some_more) {
2631 + /* Figure out how much we want to get:
2632 + * Try to get the remaining amount,
2633 + * but not more than the buffer size.
2635 + amount = min(amount_left_to_req, mod_data.buflen);
2637 + /* Beyond the end of the backing file? */
2638 + if (usb_offset >= curlun->file_length) {
2639 + get_some_more = 0;
2640 + curlun->sense_data =
2641 + SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
2642 + curlun->sense_data_info = usb_offset >> curlun->blkbits;
2643 + curlun->info_valid = 1;
2647 + /* Get the next buffer */
2648 + usb_offset += amount;
2649 + fsg->usb_amount_left -= amount;
2650 + amount_left_to_req -= amount;
2651 + if (amount_left_to_req == 0)
2652 + get_some_more = 0;
2654 + /* Except at the end of the transfer, amount will be
2655 + * equal to the buffer size, which is divisible by
2656 + * the bulk-out maxpacket size.
2658 + set_bulk_out_req_length(fsg, bh, amount);
2659 + start_transfer(fsg, fsg->bulk_out, bh->outreq,
2660 + &bh->outreq_busy, &bh->state);
2661 + fsg->next_buffhd_to_fill = bh->next;
2665 + /* Write the received data to the backing file */
2666 + bh = fsg->next_buffhd_to_drain;
2667 + if (bh->state == BUF_STATE_EMPTY && !get_some_more)
2668 + break; // We stopped early
2669 + if (bh->state == BUF_STATE_FULL) {
2671 + fsg->next_buffhd_to_drain = bh->next;
2672 + bh->state = BUF_STATE_EMPTY;
2674 + /* Did something go wrong with the transfer? */
2675 + if (bh->outreq->status != 0) {
2676 + curlun->sense_data = SS_COMMUNICATION_FAILURE;
2677 + curlun->sense_data_info = file_offset >> curlun->blkbits;
2678 + curlun->info_valid = 1;
2682 + amount = bh->outreq->actual;
2683 + if (curlun->file_length - file_offset < amount) {
2685 + "write %u @ %llu beyond end %llu\n",
2686 + amount, (unsigned long long) file_offset,
2687 + (unsigned long long) curlun->file_length);
2688 + amount = curlun->file_length - file_offset;
2691 + /* Don't accept excess data. The spec doesn't say
2692 + * what to do in this case. We'll ignore the error.
2694 + amount = min(amount, bh->bulk_out_intended_length);
2696 + /* Don't write a partial block */
2697 + amount = round_down(amount, curlun->blksize);
2701 + /* Perform the write */
2702 + file_offset_tmp = file_offset;
2703 + nwritten = vfs_write(curlun->filp,
2704 + (char __user *) bh->buf,
2705 + amount, &file_offset_tmp);
2706 + VLDBG(curlun, "file write %u @ %llu -> %d\n", amount,
2707 + (unsigned long long) file_offset,
2709 + if (signal_pending(current))
2710 + return -EINTR; // Interrupted!
2712 + if (nwritten < 0) {
2713 + LDBG(curlun, "error in file write: %d\n",
2716 + } else if (nwritten < amount) {
2717 + LDBG(curlun, "partial file write: %d/%u\n",
2718 + (int) nwritten, amount);
2719 + nwritten = round_down(nwritten, curlun->blksize);
2721 + file_offset += nwritten;
2722 + amount_left_to_write -= nwritten;
2723 + fsg->residue -= nwritten;
2725 + /* If an error occurred, report it and its position */
2726 + if (nwritten < amount) {
2727 + curlun->sense_data = SS_WRITE_ERROR;
2728 + curlun->sense_data_info = file_offset >> curlun->blkbits;
2729 + curlun->info_valid = 1;
2734 + /* Did the host decide to stop early? */
2735 + if (bh->outreq->actual < bh->bulk_out_intended_length) {
2736 + fsg->short_packet_received = 1;
2742 + /* Wait for something to happen */
2743 + rc = sleep_thread(fsg);
2748 + return -EIO; // No default reply
2752 +/*-------------------------------------------------------------------------*/
2754 +static int do_synchronize_cache(struct fsg_dev *fsg)
2756 + struct fsg_lun *curlun = fsg->curlun;
2759 + /* We ignore the requested LBA and write out all file's
2760 + * dirty data buffers. */
2761 + rc = fsg_lun_fsync_sub(curlun);
2763 + curlun->sense_data = SS_WRITE_ERROR;
2768 +/*-------------------------------------------------------------------------*/
2770 +static void invalidate_sub(struct fsg_lun *curlun)
2772 + struct file *filp = curlun->filp;
2773 + struct inode *inode = filp->f_path.dentry->d_inode;
2776 + rc = invalidate_mapping_pages(inode->i_mapping, 0, -1);
2777 + VLDBG(curlun, "invalidate_mapping_pages -> %ld\n", rc);
2780 +static int do_verify(struct fsg_dev *fsg)
2782 + struct fsg_lun *curlun = fsg->curlun;
2784 + u32 verification_length;
2785 + struct fsg_buffhd *bh = fsg->next_buffhd_to_fill;
2786 + loff_t file_offset, file_offset_tmp;
2788 + unsigned int amount;
2791 + /* Get the starting Logical Block Address and check that it's
2793 + lba = get_unaligned_be32(&fsg->cmnd[2]);
2794 + if (lba >= curlun->num_sectors) {
2795 + curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
2799 + /* We allow DPO (Disable Page Out = don't save data in the
2800 + * cache) but we don't implement it. */
2801 + if ((fsg->cmnd[1] & ~0x10) != 0) {
2802 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2806 + verification_length = get_unaligned_be16(&fsg->cmnd[7]);
2807 + if (unlikely(verification_length == 0))
2808 + return -EIO; // No default reply
2810 + /* Prepare to carry out the file verify */
2811 + amount_left = verification_length << curlun->blkbits;
2812 + file_offset = ((loff_t) lba) << curlun->blkbits;
2814 + /* Write out all the dirty buffers before invalidating them */
2815 + fsg_lun_fsync_sub(curlun);
2816 + if (signal_pending(current))
2819 + invalidate_sub(curlun);
2820 + if (signal_pending(current))
2823 + /* Just try to read the requested blocks */
2824 + while (amount_left > 0) {
2826 + /* Figure out how much we need to read:
2827 + * Try to read the remaining amount, but not more than
2828 + * the buffer size.
2829 + * And don't try to read past the end of the file.
2831 + amount = min((unsigned int) amount_left, mod_data.buflen);
2832 + amount = min((loff_t) amount,
2833 + curlun->file_length - file_offset);
2834 + if (amount == 0) {
2835 + curlun->sense_data =
2836 + SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
2837 + curlun->sense_data_info = file_offset >> curlun->blkbits;
2838 + curlun->info_valid = 1;
2842 + /* Perform the read */
2843 + file_offset_tmp = file_offset;
2844 + nread = vfs_read(curlun->filp,
2845 + (char __user *) bh->buf,
2846 + amount, &file_offset_tmp);
2847 + VLDBG(curlun, "file read %u @ %llu -> %d\n", amount,
2848 + (unsigned long long) file_offset,
2850 + if (signal_pending(current))
2854 + LDBG(curlun, "error in file verify: %d\n",
2857 + } else if (nread < amount) {
2858 + LDBG(curlun, "partial file verify: %d/%u\n",
2859 + (int) nread, amount);
2860 + nread = round_down(nread, curlun->blksize);
2863 + curlun->sense_data = SS_UNRECOVERED_READ_ERROR;
2864 + curlun->sense_data_info = file_offset >> curlun->blkbits;
2865 + curlun->info_valid = 1;
2868 + file_offset += nread;
2869 + amount_left -= nread;
2875 +/*-------------------------------------------------------------------------*/
2877 +static int do_inquiry(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2879 + u8 *buf = (u8 *) bh->buf;
2881 + static char vendor_id[] = "Linux ";
2882 + static char product_disk_id[] = "File-Stor Gadget";
2883 + static char product_cdrom_id[] = "File-CD Gadget ";
2885 + if (!fsg->curlun) { // Unsupported LUNs are okay
2886 + fsg->bad_lun_okay = 1;
2887 + memset(buf, 0, 36);
2888 + buf[0] = 0x7f; // Unsupported, no device-type
2889 + buf[4] = 31; // Additional length
2893 + memset(buf, 0, 8);
2894 + buf[0] = (mod_data.cdrom ? TYPE_ROM : TYPE_DISK);
2895 + if (mod_data.removable)
2897 + buf[2] = 2; // ANSI SCSI level 2
2898 + buf[3] = 2; // SCSI-2 INQUIRY data format
2899 + buf[4] = 31; // Additional length
2900 + // No special options
2901 + sprintf(buf + 8, "%-8s%-16s%04x", vendor_id,
2902 + (mod_data.cdrom ? product_cdrom_id :
2904 + mod_data.release);
2909 +static int do_request_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2911 + struct fsg_lun *curlun = fsg->curlun;
2912 + u8 *buf = (u8 *) bh->buf;
2917 + * From the SCSI-2 spec., section 7.9 (Unit attention condition):
2919 + * If a REQUEST SENSE command is received from an initiator
2920 + * with a pending unit attention condition (before the target
2921 + * generates the contingent allegiance condition), then the
2922 + * target shall either:
2923 + * a) report any pending sense data and preserve the unit
2924 + * attention condition on the logical unit, or,
2925 + * b) report the unit attention condition, may discard any
2926 + * pending sense data, and clear the unit attention
2927 + * condition on the logical unit for that initiator.
2929 + * FSG normally uses option a); enable this code to use option b).
2932 + if (curlun && curlun->unit_attention_data != SS_NO_SENSE) {
2933 + curlun->sense_data = curlun->unit_attention_data;
2934 + curlun->unit_attention_data = SS_NO_SENSE;
2938 + if (!curlun) { // Unsupported LUNs are okay
2939 + fsg->bad_lun_okay = 1;
2940 + sd = SS_LOGICAL_UNIT_NOT_SUPPORTED;
2944 + sd = curlun->sense_data;
2945 + sdinfo = curlun->sense_data_info;
2946 + valid = curlun->info_valid << 7;
2947 + curlun->sense_data = SS_NO_SENSE;
2948 + curlun->sense_data_info = 0;
2949 + curlun->info_valid = 0;
2952 + memset(buf, 0, 18);
2953 + buf[0] = valid | 0x70; // Valid, current error
2955 + put_unaligned_be32(sdinfo, &buf[3]); /* Sense information */
2956 + buf[7] = 18 - 8; // Additional sense length
2957 + buf[12] = ASC(sd);
2958 + buf[13] = ASCQ(sd);
2963 +static int do_read_capacity(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2965 + struct fsg_lun *curlun = fsg->curlun;
2966 + u32 lba = get_unaligned_be32(&fsg->cmnd[2]);
2967 + int pmi = fsg->cmnd[8];
2968 + u8 *buf = (u8 *) bh->buf;
2970 + /* Check the PMI and LBA fields */
2971 + if (pmi > 1 || (pmi == 0 && lba != 0)) {
2972 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2976 + put_unaligned_be32(curlun->num_sectors - 1, &buf[0]);
2977 + /* Max logical block */
2978 + put_unaligned_be32(curlun->blksize, &buf[4]); /* Block length */
2983 +static int do_read_header(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2985 + struct fsg_lun *curlun = fsg->curlun;
2986 + int msf = fsg->cmnd[1] & 0x02;
2987 + u32 lba = get_unaligned_be32(&fsg->cmnd[2]);
2988 + u8 *buf = (u8 *) bh->buf;
2990 + if ((fsg->cmnd[1] & ~0x02) != 0) { /* Mask away MSF */
2991 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2994 + if (lba >= curlun->num_sectors) {
2995 + curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
2999 + memset(buf, 0, 8);
3000 + buf[0] = 0x01; /* 2048 bytes of user data, rest is EC */
3001 + store_cdrom_address(&buf[4], msf, lba);
3006 +static int do_read_toc(struct fsg_dev *fsg, struct fsg_buffhd *bh)
3008 + struct fsg_lun *curlun = fsg->curlun;
3009 + int msf = fsg->cmnd[1] & 0x02;
3010 + int start_track = fsg->cmnd[6];
3011 + u8 *buf = (u8 *) bh->buf;
3013 + if ((fsg->cmnd[1] & ~0x02) != 0 || /* Mask away MSF */
3014 + start_track > 1) {
3015 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
3019 + memset(buf, 0, 20);
3020 + buf[1] = (20-2); /* TOC data length */
3021 + buf[2] = 1; /* First track number */
3022 + buf[3] = 1; /* Last track number */
3023 + buf[5] = 0x16; /* Data track, copying allowed */
3024 + buf[6] = 0x01; /* Only track is number 1 */
3025 + store_cdrom_address(&buf[8], msf, 0);
3027 + buf[13] = 0x16; /* Lead-out track is data */
3028 + buf[14] = 0xAA; /* Lead-out track number */
3029 + store_cdrom_address(&buf[16], msf, curlun->num_sectors);
3034 +static int do_mode_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
3036 + struct fsg_lun *curlun = fsg->curlun;
3037 + int mscmnd = fsg->cmnd[0];
3038 + u8 *buf = (u8 *) bh->buf;
3040 + int pc, page_code;
3041 + int changeable_values, all_pages;
3042 + int valid_page = 0;
3045 + if ((fsg->cmnd[1] & ~0x08) != 0) { // Mask away DBD
3046 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
3049 + pc = fsg->cmnd[2] >> 6;
3050 + page_code = fsg->cmnd[2] & 0x3f;
3052 + curlun->sense_data = SS_SAVING_PARAMETERS_NOT_SUPPORTED;
3055 + changeable_values = (pc == 1);
3056 + all_pages = (page_code == 0x3f);
3058 + /* Write the mode parameter header. Fixed values are: default
3059 + * medium type, no cache control (DPOFUA), and no block descriptors.
3060 + * The only variable value is the WriteProtect bit. We will fill in
3061 + * the mode data length later. */
3062 + memset(buf, 0, 8);
3063 + if (mscmnd == MODE_SENSE) {
3064 + buf[2] = (curlun->ro ? 0x80 : 0x00); // WP, DPOFUA
3067 + } else { // MODE_SENSE_10
3068 + buf[3] = (curlun->ro ? 0x80 : 0x00); // WP, DPOFUA
3070 + limit = 65535; // Should really be mod_data.buflen
3073 + /* No block descriptors */
3075 + /* The mode pages, in numerical order. The only page we support
3076 + * is the Caching page. */
3077 + if (page_code == 0x08 || all_pages) {
3079 + buf[0] = 0x08; // Page code
3080 + buf[1] = 10; // Page length
3081 + memset(buf+2, 0, 10); // None of the fields are changeable
3083 + if (!changeable_values) {
3084 + buf[2] = 0x04; // Write cache enable,
3085 + // Read cache not disabled
3086 + // No cache retention priorities
3087 + put_unaligned_be16(0xffff, &buf[4]);
3088 + /* Don't disable prefetch */
3089 + /* Minimum prefetch = 0 */
3090 + put_unaligned_be16(0xffff, &buf[8]);
3091 + /* Maximum prefetch */
3092 + put_unaligned_be16(0xffff, &buf[10]);
3093 + /* Maximum prefetch ceiling */
3098 + /* Check that a valid page was requested and the mode data length
3099 + * isn't too long. */
3101 + if (!valid_page || len > limit) {
3102 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
3106 + /* Store the mode data length */
3107 + if (mscmnd == MODE_SENSE)
3108 + buf0[0] = len - 1;
3110 + put_unaligned_be16(len - 2, buf0);
3115 +static int do_start_stop(struct fsg_dev *fsg)
3117 + struct fsg_lun *curlun = fsg->curlun;
3120 + if (!mod_data.removable) {
3121 + curlun->sense_data = SS_INVALID_COMMAND;
3125 + // int immed = fsg->cmnd[1] & 0x01;
3126 + loej = fsg->cmnd[4] & 0x02;
3127 + start = fsg->cmnd[4] & 0x01;
3129 +#ifdef CONFIG_USB_FILE_STORAGE_TEST
3130 + if ((fsg->cmnd[1] & ~0x01) != 0 || // Mask away Immed
3131 + (fsg->cmnd[4] & ~0x03) != 0) { // Mask LoEj, Start
3132 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
3138 + /* Are we allowed to unload the media? */
3139 + if (curlun->prevent_medium_removal) {
3140 + LDBG(curlun, "unload attempt prevented\n");
3141 + curlun->sense_data = SS_MEDIUM_REMOVAL_PREVENTED;
3144 + if (loej) { // Simulate an unload/eject
3145 + up_read(&fsg->filesem);
3146 + down_write(&fsg->filesem);
3147 + fsg_lun_close(curlun);
3148 + up_write(&fsg->filesem);
3149 + down_read(&fsg->filesem);
3153 + /* Our emulation doesn't support mounting; the medium is
3154 + * available for use as soon as it is loaded. */
3155 + if (!fsg_lun_is_open(curlun)) {
3156 + curlun->sense_data = SS_MEDIUM_NOT_PRESENT;
3165 +static int do_prevent_allow(struct fsg_dev *fsg)
3167 + struct fsg_lun *curlun = fsg->curlun;
3170 + if (!mod_data.removable) {
3171 + curlun->sense_data = SS_INVALID_COMMAND;
3175 + prevent = fsg->cmnd[4] & 0x01;
3176 + if ((fsg->cmnd[4] & ~0x01) != 0) { // Mask away Prevent
3177 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
3181 + if (curlun->prevent_medium_removal && !prevent)
3182 + fsg_lun_fsync_sub(curlun);
3183 + curlun->prevent_medium_removal = prevent;
3188 +static int do_read_format_capacities(struct fsg_dev *fsg,
3189 + struct fsg_buffhd *bh)
3191 + struct fsg_lun *curlun = fsg->curlun;
3192 + u8 *buf = (u8 *) bh->buf;
3194 + buf[0] = buf[1] = buf[2] = 0;
3195 + buf[3] = 8; // Only the Current/Maximum Capacity Descriptor
3198 + put_unaligned_be32(curlun->num_sectors, &buf[0]);
3199 + /* Number of blocks */
3200 + put_unaligned_be32(curlun->blksize, &buf[4]); /* Block length */
3201 + buf[4] = 0x02; /* Current capacity */
3206 +static int do_mode_select(struct fsg_dev *fsg, struct fsg_buffhd *bh)
3208 + struct fsg_lun *curlun = fsg->curlun;
3210 + /* We don't support MODE SELECT */
3211 + curlun->sense_data = SS_INVALID_COMMAND;
3216 +/*-------------------------------------------------------------------------*/
3218 +static int halt_bulk_in_endpoint(struct fsg_dev *fsg)
3222 + rc = fsg_set_halt(fsg, fsg->bulk_in);
3223 + if (rc == -EAGAIN)
3224 + VDBG(fsg, "delayed bulk-in endpoint halt\n");
3226 + if (rc != -EAGAIN) {
3227 + WARNING(fsg, "usb_ep_set_halt -> %d\n", rc);
3232 + /* Wait for a short time and then try again */
3233 + if (msleep_interruptible(100) != 0)
3235 + rc = usb_ep_set_halt(fsg->bulk_in);
3240 +static int wedge_bulk_in_endpoint(struct fsg_dev *fsg)
3244 + DBG(fsg, "bulk-in set wedge\n");
3245 + rc = usb_ep_set_wedge(fsg->bulk_in);
3246 + if (rc == -EAGAIN)
3247 + VDBG(fsg, "delayed bulk-in endpoint wedge\n");
3249 + if (rc != -EAGAIN) {
3250 + WARNING(fsg, "usb_ep_set_wedge -> %d\n", rc);
3255 + /* Wait for a short time and then try again */
3256 + if (msleep_interruptible(100) != 0)
3258 + rc = usb_ep_set_wedge(fsg->bulk_in);
3263 +static int throw_away_data(struct fsg_dev *fsg)
3265 + struct fsg_buffhd *bh;
3269 + while ((bh = fsg->next_buffhd_to_drain)->state != BUF_STATE_EMPTY ||
3270 + fsg->usb_amount_left > 0) {
3272 + /* Throw away the data in a filled buffer */
3273 + if (bh->state == BUF_STATE_FULL) {
3275 + bh->state = BUF_STATE_EMPTY;
3276 + fsg->next_buffhd_to_drain = bh->next;
3278 + /* A short packet or an error ends everything */
3279 + if (bh->outreq->actual < bh->bulk_out_intended_length ||
3280 + bh->outreq->status != 0) {
3281 + raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);
3287 + /* Try to submit another request if we need one */
3288 + bh = fsg->next_buffhd_to_fill;
3289 + if (bh->state == BUF_STATE_EMPTY && fsg->usb_amount_left > 0) {
3290 + amount = min(fsg->usb_amount_left,
3291 + (u32) mod_data.buflen);
3293 + /* Except at the end of the transfer, amount will be
3294 + * equal to the buffer size, which is divisible by
3295 + * the bulk-out maxpacket size.
3297 + set_bulk_out_req_length(fsg, bh, amount);
3298 + start_transfer(fsg, fsg->bulk_out, bh->outreq,
3299 + &bh->outreq_busy, &bh->state);
3300 + fsg->next_buffhd_to_fill = bh->next;
3301 + fsg->usb_amount_left -= amount;
3305 + /* Otherwise wait for something to happen */
3306 + rc = sleep_thread(fsg);
3314 +static int finish_reply(struct fsg_dev *fsg)
3316 + struct fsg_buffhd *bh = fsg->next_buffhd_to_fill;
3319 + switch (fsg->data_dir) {
3320 + case DATA_DIR_NONE:
3321 + break; // Nothing to send
3323 + /* If we don't know whether the host wants to read or write,
3324 + * this must be CB or CBI with an unknown command. We mustn't
3325 + * try to send or receive any data. So stall both bulk pipes
3326 + * if we can and wait for a reset. */
3327 + case DATA_DIR_UNKNOWN:
3328 + if (mod_data.can_stall) {
3329 + fsg_set_halt(fsg, fsg->bulk_out);
3330 + rc = halt_bulk_in_endpoint(fsg);
3334 + /* All but the last buffer of data must have already been sent */
3335 + case DATA_DIR_TO_HOST:
3336 + if (fsg->data_size == 0)
3337 + ; // Nothing to send
3339 + /* If there's no residue, simply send the last buffer */
3340 + else if (fsg->residue == 0) {
3341 + bh->inreq->zero = 0;
3342 + start_transfer(fsg, fsg->bulk_in, bh->inreq,
3343 + &bh->inreq_busy, &bh->state);
3344 + fsg->next_buffhd_to_fill = bh->next;
3347 + /* There is a residue. For CB and CBI, simply mark the end
3348 + * of the data with a short packet. However, if we are
3349 + * allowed to stall, there was no data at all (residue ==
3350 + * data_size), and the command failed (invalid LUN or
3351 + * sense data is set), then halt the bulk-in endpoint
3353 + else if (!transport_is_bbb()) {
3354 + if (mod_data.can_stall &&
3355 + fsg->residue == fsg->data_size &&
3356 + (!fsg->curlun || fsg->curlun->sense_data != SS_NO_SENSE)) {
3357 + bh->state = BUF_STATE_EMPTY;
3358 + rc = halt_bulk_in_endpoint(fsg);
3360 + bh->inreq->zero = 1;
3361 + start_transfer(fsg, fsg->bulk_in, bh->inreq,
3362 + &bh->inreq_busy, &bh->state);
3363 + fsg->next_buffhd_to_fill = bh->next;
3368 + * For Bulk-only, mark the end of the data with a short
3369 + * packet. If we are allowed to stall, halt the bulk-in
3370 + * endpoint. (Note: This violates the Bulk-Only Transport
3371 + * specification, which requires us to pad the data if we
3372 + * don't halt the endpoint. Presumably nobody will mind.)
3375 + bh->inreq->zero = 1;
3376 + start_transfer(fsg, fsg->bulk_in, bh->inreq,
3377 + &bh->inreq_busy, &bh->state);
3378 + fsg->next_buffhd_to_fill = bh->next;
3379 + if (mod_data.can_stall)
3380 + rc = halt_bulk_in_endpoint(fsg);
3384 + /* We have processed all we want from the data the host has sent.
3385 + * There may still be outstanding bulk-out requests. */
3386 + case DATA_DIR_FROM_HOST:
3387 + if (fsg->residue == 0)
3388 + ; // Nothing to receive
3390 + /* Did the host stop sending unexpectedly early? */
3391 + else if (fsg->short_packet_received) {
3392 + raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);
3396 + /* We haven't processed all the incoming data. Even though
3397 + * we may be allowed to stall, doing so would cause a race.
3398 + * The controller may already have ACK'ed all the remaining
3399 + * bulk-out packets, in which case the host wouldn't see a
3400 + * STALL. Not realizing the endpoint was halted, it wouldn't
3401 + * clear the halt -- leading to problems later on. */
3403 + else if (mod_data.can_stall) {
3404 + fsg_set_halt(fsg, fsg->bulk_out);
3405 + raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);
3410 + /* We can't stall. Read in the excess data and throw it
3413 + rc = throw_away_data(fsg);
3420 +static int send_status(struct fsg_dev *fsg)
3422 + struct fsg_lun *curlun = fsg->curlun;
3423 + struct fsg_buffhd *bh;
3425 + u8 status = US_BULK_STAT_OK;
3426 + u32 sd, sdinfo = 0;
3428 + /* Wait for the next buffer to become available */
3429 + bh = fsg->next_buffhd_to_fill;
3430 + while (bh->state != BUF_STATE_EMPTY) {
3431 + rc = sleep_thread(fsg);
3437 + sd = curlun->sense_data;
3438 + sdinfo = curlun->sense_data_info;
3439 + } else if (fsg->bad_lun_okay)
3442 + sd = SS_LOGICAL_UNIT_NOT_SUPPORTED;
3444 + if (fsg->phase_error) {
3445 + DBG(fsg, "sending phase-error status\n");
3446 + status = US_BULK_STAT_PHASE;
3447 + sd = SS_INVALID_COMMAND;
3448 + } else if (sd != SS_NO_SENSE) {
3449 + DBG(fsg, "sending command-failure status\n");
3450 + status = US_BULK_STAT_FAIL;
3451 + VDBG(fsg, " sense data: SK x%02x, ASC x%02x, ASCQ x%02x;"
3453 + SK(sd), ASC(sd), ASCQ(sd), sdinfo);
3456 + if (transport_is_bbb()) {
3457 + struct bulk_cs_wrap *csw = bh->buf;
3459 + /* Store and send the Bulk-only CSW */
3460 + csw->Signature = cpu_to_le32(US_BULK_CS_SIGN);
3461 + csw->Tag = fsg->tag;
3462 + csw->Residue = cpu_to_le32(fsg->residue);
3463 + csw->Status = status;
3465 + bh->inreq->length = US_BULK_CS_WRAP_LEN;
3466 + bh->inreq->zero = 0;
3467 + start_transfer(fsg, fsg->bulk_in, bh->inreq,
3468 + &bh->inreq_busy, &bh->state);
3470 + } else if (mod_data.transport_type == USB_PR_CB) {
3472 + /* Control-Bulk transport has no status phase! */
3475 + } else { // USB_PR_CBI
3476 + struct interrupt_data *buf = bh->buf;
3478 + /* Store and send the Interrupt data. UFI sends the ASC
3479 + * and ASCQ bytes. Everything else sends a Type (which
3480 + * is always 0) and the status Value. */
3481 + if (mod_data.protocol_type == USB_SC_UFI) {
3482 + buf->bType = ASC(sd);
3483 + buf->bValue = ASCQ(sd);
3486 + buf->bValue = status;
3488 + fsg->intreq->length = CBI_INTERRUPT_DATA_LEN;
3490 + fsg->intr_buffhd = bh; // Point to the right buffhd
3491 + fsg->intreq->buf = bh->inreq->buf;
3492 + fsg->intreq->context = bh;
3493 + start_transfer(fsg, fsg->intr_in, fsg->intreq,
3494 + &fsg->intreq_busy, &bh->state);
3497 + fsg->next_buffhd_to_fill = bh->next;
3502 +/*-------------------------------------------------------------------------*/
3504 +/* Check whether the command is properly formed and whether its data size
3505 + * and direction agree with the values we already have. */
3506 +static int check_command(struct fsg_dev *fsg, int cmnd_size,
3507 + enum data_direction data_dir, unsigned int mask,
3508 + int needs_medium, const char *name)
3511 + int lun = fsg->cmnd[1] >> 5;
3512 + static const char dirletter[4] = {'u', 'o', 'i', 'n'};
3514 + struct fsg_lun *curlun;
3516 + /* Adjust the expected cmnd_size for protocol encapsulation padding.
3517 + * Transparent SCSI doesn't pad. */
3518 + if (protocol_is_scsi())
3521 + /* There's some disagreement as to whether RBC pads commands or not.
3522 + * We'll play it safe and accept either form. */
3523 + else if (mod_data.protocol_type == USB_SC_RBC) {
3524 + if (fsg->cmnd_size == 12)
3527 + /* All the other protocols pad to 12 bytes */
3532 + if (fsg->data_dir != DATA_DIR_UNKNOWN)
3533 + sprintf(hdlen, ", H%c=%u", dirletter[(int) fsg->data_dir],
3535 + VDBG(fsg, "SCSI command: %s; Dc=%d, D%c=%u; Hc=%d%s\n",
3536 + name, cmnd_size, dirletter[(int) data_dir],
3537 + fsg->data_size_from_cmnd, fsg->cmnd_size, hdlen);
3539 + /* We can't reply at all until we know the correct data direction
3541 + if (fsg->data_size_from_cmnd == 0)
3542 + data_dir = DATA_DIR_NONE;
3543 + if (fsg->data_dir == DATA_DIR_UNKNOWN) { // CB or CBI
3544 + fsg->data_dir = data_dir;
3545 + fsg->data_size = fsg->data_size_from_cmnd;
3547 + } else { // Bulk-only
3548 + if (fsg->data_size < fsg->data_size_from_cmnd) {
3550 + /* Host data size < Device data size is a phase error.
3551 + * Carry out the command, but only transfer as much
3552 + * as we are allowed. */
3553 + fsg->data_size_from_cmnd = fsg->data_size;
3554 + fsg->phase_error = 1;
3557 + fsg->residue = fsg->usb_amount_left = fsg->data_size;
3559 + /* Conflicting data directions is a phase error */
3560 + if (fsg->data_dir != data_dir && fsg->data_size_from_cmnd > 0) {
3561 + fsg->phase_error = 1;
3565 + /* Verify the length of the command itself */
3566 + if (cmnd_size != fsg->cmnd_size) {
3568 + /* Special case workaround: There are plenty of buggy SCSI
3569 + * implementations. Many have issues with cbw->Length
3570 + * field passing a wrong command size. For those cases we
3571 + * always try to work around the problem by using the length
3572 + * sent by the host side provided it is at least as large
3573 + * as the correct command length.
3574 + * Examples of such cases would be MS-Windows, which issues
3575 + * REQUEST SENSE with cbw->Length == 12 where it should
3576 + * be 6, and xbox360 issuing INQUIRY, TEST UNIT READY and
3577 + * REQUEST SENSE with cbw->Length == 10 where it should
3580 + if (cmnd_size <= fsg->cmnd_size) {
3581 + DBG(fsg, "%s is buggy! Expected length %d "
3582 + "but we got %d\n", name,
3583 + cmnd_size, fsg->cmnd_size);
3584 + cmnd_size = fsg->cmnd_size;
3586 + fsg->phase_error = 1;
3591 + /* Check that the LUN values are consistent */
3592 + if (transport_is_bbb()) {
3593 + if (fsg->lun != lun)
3594 + DBG(fsg, "using LUN %d from CBW, "
3595 + "not LUN %d from CDB\n",
3599 + /* Check the LUN */
3600 + curlun = fsg->curlun;
3602 + if (fsg->cmnd[0] != REQUEST_SENSE) {
3603 + curlun->sense_data = SS_NO_SENSE;
3604 + curlun->sense_data_info = 0;
3605 + curlun->info_valid = 0;
3608 + fsg->bad_lun_okay = 0;
3610 + /* INQUIRY and REQUEST SENSE commands are explicitly allowed
3611 + * to use unsupported LUNs; all others may not. */
3612 + if (fsg->cmnd[0] != INQUIRY &&
3613 + fsg->cmnd[0] != REQUEST_SENSE) {
3614 + DBG(fsg, "unsupported LUN %d\n", fsg->lun);
3619 + /* If a unit attention condition exists, only INQUIRY and
3620 + * REQUEST SENSE commands are allowed; anything else must fail. */
3621 + if (curlun && curlun->unit_attention_data != SS_NO_SENSE &&
3622 + fsg->cmnd[0] != INQUIRY &&
3623 + fsg->cmnd[0] != REQUEST_SENSE) {
3624 + curlun->sense_data = curlun->unit_attention_data;
3625 + curlun->unit_attention_data = SS_NO_SENSE;
3629 + /* Check that only command bytes listed in the mask are non-zero */
3630 + fsg->cmnd[1] &= 0x1f; // Mask away the LUN
3631 + for (i = 1; i < cmnd_size; ++i) {
3632 + if (fsg->cmnd[i] && !(mask & (1 << i))) {
3634 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
3639 + /* If the medium isn't mounted and the command needs to access
3640 + * it, return an error. */
3641 + if (curlun && !fsg_lun_is_open(curlun) && needs_medium) {
3642 + curlun->sense_data = SS_MEDIUM_NOT_PRESENT;
3649 +/* wrapper of check_command for data size in blocks handling */
3650 +static int check_command_size_in_blocks(struct fsg_dev *fsg, int cmnd_size,
3651 + enum data_direction data_dir, unsigned int mask,
3652 + int needs_medium, const char *name)
3655 + fsg->data_size_from_cmnd <<= fsg->curlun->blkbits;
3656 + return check_command(fsg, cmnd_size, data_dir,
3657 + mask, needs_medium, name);
3660 +static int do_scsi_command(struct fsg_dev *fsg)
3662 + struct fsg_buffhd *bh;
3664 + int reply = -EINVAL;
3666 + static char unknown[16];
3670 + /* Wait for the next buffer to become available for data or status */
3671 + bh = fsg->next_buffhd_to_drain = fsg->next_buffhd_to_fill;
3672 + while (bh->state != BUF_STATE_EMPTY) {
3673 + rc = sleep_thread(fsg);
3677 + fsg->phase_error = 0;
3678 + fsg->short_packet_received = 0;
3680 + down_read(&fsg->filesem); // We're using the backing file
3681 + switch (fsg->cmnd[0]) {
3684 + fsg->data_size_from_cmnd = fsg->cmnd[4];
3685 + if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,
3688 + reply = do_inquiry(fsg, bh);
3692 + fsg->data_size_from_cmnd = fsg->cmnd[4];
3693 + if ((reply = check_command(fsg, 6, DATA_DIR_FROM_HOST,
3694 + (1<<1) | (1<<4), 0,
3695 + "MODE SELECT(6)")) == 0)
3696 + reply = do_mode_select(fsg, bh);
3699 + case MODE_SELECT_10:
3700 + fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
3701 + if ((reply = check_command(fsg, 10, DATA_DIR_FROM_HOST,
3702 + (1<<1) | (3<<7), 0,
3703 + "MODE SELECT(10)")) == 0)
3704 + reply = do_mode_select(fsg, bh);
3708 + fsg->data_size_from_cmnd = fsg->cmnd[4];
3709 + if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,
3710 + (1<<1) | (1<<2) | (1<<4), 0,
3711 + "MODE SENSE(6)")) == 0)
3712 + reply = do_mode_sense(fsg, bh);
3715 + case MODE_SENSE_10:
3716 + fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
3717 + if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
3718 + (1<<1) | (1<<2) | (3<<7), 0,
3719 + "MODE SENSE(10)")) == 0)
3720 + reply = do_mode_sense(fsg, bh);
3723 + case ALLOW_MEDIUM_REMOVAL:
3724 + fsg->data_size_from_cmnd = 0;
3725 + if ((reply = check_command(fsg, 6, DATA_DIR_NONE,
3727 + "PREVENT-ALLOW MEDIUM REMOVAL")) == 0)
3728 + reply = do_prevent_allow(fsg);
3733 + fsg->data_size_from_cmnd = (i == 0) ? 256 : i;
3734 + if ((reply = check_command_size_in_blocks(fsg, 6,
3736 + (7<<1) | (1<<4), 1,
3738 + reply = do_read(fsg);
3742 + fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
3743 + if ((reply = check_command_size_in_blocks(fsg, 10,
3745 + (1<<1) | (0xf<<2) | (3<<7), 1,
3746 + "READ(10)")) == 0)
3747 + reply = do_read(fsg);
3751 + fsg->data_size_from_cmnd = get_unaligned_be32(&fsg->cmnd[6]);
3752 + if ((reply = check_command_size_in_blocks(fsg, 12,
3754 + (1<<1) | (0xf<<2) | (0xf<<6), 1,
3755 + "READ(12)")) == 0)
3756 + reply = do_read(fsg);
3759 + case READ_CAPACITY:
3760 + fsg->data_size_from_cmnd = 8;
3761 + if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
3762 + (0xf<<2) | (1<<8), 1,
3763 + "READ CAPACITY")) == 0)
3764 + reply = do_read_capacity(fsg, bh);
3768 + if (!mod_data.cdrom)
3769 + goto unknown_cmnd;
3770 + fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
3771 + if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
3772 + (3<<7) | (0x1f<<1), 1,
3773 + "READ HEADER")) == 0)
3774 + reply = do_read_header(fsg, bh);
3778 + if (!mod_data.cdrom)
3779 + goto unknown_cmnd;
3780 + fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
3781 + if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
3782 + (7<<6) | (1<<1), 1,
3783 + "READ TOC")) == 0)
3784 + reply = do_read_toc(fsg, bh);
3787 + case READ_FORMAT_CAPACITIES:
3788 + fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
3789 + if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
3791 + "READ FORMAT CAPACITIES")) == 0)
3792 + reply = do_read_format_capacities(fsg, bh);
3795 + case REQUEST_SENSE:
3796 + fsg->data_size_from_cmnd = fsg->cmnd[4];
3797 + if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,
3799 + "REQUEST SENSE")) == 0)
3800 + reply = do_request_sense(fsg, bh);
3804 + fsg->data_size_from_cmnd = 0;
3805 + if ((reply = check_command(fsg, 6, DATA_DIR_NONE,
3806 + (1<<1) | (1<<4), 0,
3807 + "START-STOP UNIT")) == 0)
3808 + reply = do_start_stop(fsg);
3811 + case SYNCHRONIZE_CACHE:
3812 + fsg->data_size_from_cmnd = 0;
3813 + if ((reply = check_command(fsg, 10, DATA_DIR_NONE,
3814 + (0xf<<2) | (3<<7), 1,
3815 + "SYNCHRONIZE CACHE")) == 0)
3816 + reply = do_synchronize_cache(fsg);
3819 + case TEST_UNIT_READY:
3820 + fsg->data_size_from_cmnd = 0;
3821 + reply = check_command(fsg, 6, DATA_DIR_NONE,
3823 + "TEST UNIT READY");
3826 + /* Although optional, this command is used by MS-Windows. We
3827 + * support a minimal version: BytChk must be 0. */
3829 + fsg->data_size_from_cmnd = 0;
3830 + if ((reply = check_command(fsg, 10, DATA_DIR_NONE,
3831 + (1<<1) | (0xf<<2) | (3<<7), 1,
3833 + reply = do_verify(fsg);
3838 + fsg->data_size_from_cmnd = (i == 0) ? 256 : i;
3839 + if ((reply = check_command_size_in_blocks(fsg, 6,
3840 + DATA_DIR_FROM_HOST,
3841 + (7<<1) | (1<<4), 1,
3842 + "WRITE(6)")) == 0)
3843 + reply = do_write(fsg);
3847 + fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
3848 + if ((reply = check_command_size_in_blocks(fsg, 10,
3849 + DATA_DIR_FROM_HOST,
3850 + (1<<1) | (0xf<<2) | (3<<7), 1,
3851 + "WRITE(10)")) == 0)
3852 + reply = do_write(fsg);
3856 + fsg->data_size_from_cmnd = get_unaligned_be32(&fsg->cmnd[6]);
3857 + if ((reply = check_command_size_in_blocks(fsg, 12,
3858 + DATA_DIR_FROM_HOST,
3859 + (1<<1) | (0xf<<2) | (0xf<<6), 1,
3860 + "WRITE(12)")) == 0)
3861 + reply = do_write(fsg);
3864 + /* Some mandatory commands that we recognize but don't implement.
3865 + * They don't mean much in this setting. It's left as an exercise
3866 + * for anyone interested to implement RESERVE and RELEASE in terms
3867 + * of Posix locks. */
3871 + case SEND_DIAGNOSTIC:
3876 + fsg->data_size_from_cmnd = 0;
3877 + sprintf(unknown, "Unknown x%02x", fsg->cmnd[0]);
3878 + if ((reply = check_command(fsg, fsg->cmnd_size,
3879 + DATA_DIR_UNKNOWN, ~0, 0, unknown)) == 0) {
3880 + fsg->curlun->sense_data = SS_INVALID_COMMAND;
3885 + up_read(&fsg->filesem);
3887 + if (reply == -EINTR || signal_pending(current))
3890 + /* Set up the single reply buffer for finish_reply() */
3891 + if (reply == -EINVAL)
3892 + reply = 0; // Error reply length
3893 + if (reply >= 0 && fsg->data_dir == DATA_DIR_TO_HOST) {
3894 + reply = min((u32) reply, fsg->data_size_from_cmnd);
3895 + bh->inreq->length = reply;
3896 + bh->state = BUF_STATE_FULL;
3897 + fsg->residue -= reply;
3898 + } // Otherwise it's already set
3904 +/*-------------------------------------------------------------------------*/
3906 +static int received_cbw(struct fsg_dev *fsg, struct fsg_buffhd *bh)
3908 + struct usb_request *req = bh->outreq;
3909 + struct bulk_cb_wrap *cbw = req->buf;
3911 + /* Was this a real packet? Should it be ignored? */
3912 + if (req->status || test_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags))
3915 + /* Is the CBW valid? */
3916 + if (req->actual != US_BULK_CB_WRAP_LEN ||
3917 + cbw->Signature != cpu_to_le32(
3918 + US_BULK_CB_SIGN)) {
3919 + DBG(fsg, "invalid CBW: len %u sig 0x%x\n",
3921 + le32_to_cpu(cbw->Signature));
3923 + /* The Bulk-only spec says we MUST stall the IN endpoint
3924 + * (6.6.1), so it's unavoidable. It also says we must
3925 + * retain this state until the next reset, but there's
3926 + * no way to tell the controller driver it should ignore
3927 + * Clear-Feature(HALT) requests.
3929 + * We aren't required to halt the OUT endpoint; instead
3930 + * we can simply accept and discard any data received
3931 + * until the next reset. */
3932 + wedge_bulk_in_endpoint(fsg);
3933 + set_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags);
3937 + /* Is the CBW meaningful? */
3938 + if (cbw->Lun >= FSG_MAX_LUNS || cbw->Flags & ~US_BULK_FLAG_IN ||
3939 + cbw->Length <= 0 || cbw->Length > MAX_COMMAND_SIZE) {
3940 + DBG(fsg, "non-meaningful CBW: lun = %u, flags = 0x%x, "
3942 + cbw->Lun, cbw->Flags, cbw->Length);
3944 + /* We can do anything we want here, so let's stall the
3945 + * bulk pipes if we are allowed to. */
3946 + if (mod_data.can_stall) {
3947 + fsg_set_halt(fsg, fsg->bulk_out);
3948 + halt_bulk_in_endpoint(fsg);
3953 + /* Save the command for later */
3954 + fsg->cmnd_size = cbw->Length;
3955 + memcpy(fsg->cmnd, cbw->CDB, fsg->cmnd_size);
3956 + if (cbw->Flags & US_BULK_FLAG_IN)
3957 + fsg->data_dir = DATA_DIR_TO_HOST;
3959 + fsg->data_dir = DATA_DIR_FROM_HOST;
3960 + fsg->data_size = le32_to_cpu(cbw->DataTransferLength);
3961 + if (fsg->data_size == 0)
3962 + fsg->data_dir = DATA_DIR_NONE;
3963 + fsg->lun = cbw->Lun;
3964 + fsg->tag = cbw->Tag;
3969 +static int get_next_command(struct fsg_dev *fsg)
3971 + struct fsg_buffhd *bh;
3974 + if (transport_is_bbb()) {
3976 + /* Wait for the next buffer to become available */
3977 + bh = fsg->next_buffhd_to_fill;
3978 + while (bh->state != BUF_STATE_EMPTY) {
3979 + rc = sleep_thread(fsg);
3984 + /* Queue a request to read a Bulk-only CBW */
3985 + set_bulk_out_req_length(fsg, bh, US_BULK_CB_WRAP_LEN);
3986 + start_transfer(fsg, fsg->bulk_out, bh->outreq,
3987 + &bh->outreq_busy, &bh->state);
3989 + /* We will drain the buffer in software, which means we
3990 + * can reuse it for the next filling. No need to advance
3991 + * next_buffhd_to_fill. */
3993 + /* Wait for the CBW to arrive */
3994 + while (bh->state != BUF_STATE_FULL) {
3995 + rc = sleep_thread(fsg);
4000 + rc = received_cbw(fsg, bh);
4001 + bh->state = BUF_STATE_EMPTY;
4003 + } else { // USB_PR_CB or USB_PR_CBI
4005 + /* Wait for the next command to arrive */
4006 + while (fsg->cbbuf_cmnd_size == 0) {
4007 + rc = sleep_thread(fsg);
4012 + /* Is the previous status interrupt request still busy?
4013 + * The host is allowed to skip reading the status,
4014 + * so we must cancel it. */
4015 + if (fsg->intreq_busy)
4016 + usb_ep_dequeue(fsg->intr_in, fsg->intreq);
4018 + /* Copy the command and mark the buffer empty */
4019 + fsg->data_dir = DATA_DIR_UNKNOWN;
4020 + spin_lock_irq(&fsg->lock);
4021 + fsg->cmnd_size = fsg->cbbuf_cmnd_size;
4022 + memcpy(fsg->cmnd, fsg->cbbuf_cmnd, fsg->cmnd_size);
4023 + fsg->cbbuf_cmnd_size = 0;
4024 + spin_unlock_irq(&fsg->lock);
4026 + /* Use LUN from the command */
4027 + fsg->lun = fsg->cmnd[1] >> 5;
4030 + /* Update current lun */
4031 + if (fsg->lun >= 0 && fsg->lun < fsg->nluns)
4032 + fsg->curlun = &fsg->luns[fsg->lun];
4034 + fsg->curlun = NULL;
4040 +/*-------------------------------------------------------------------------*/
4042 +static int enable_endpoint(struct fsg_dev *fsg, struct usb_ep *ep,
4043 + const struct usb_endpoint_descriptor *d)
4047 + ep->driver_data = fsg;
4049 + rc = usb_ep_enable(ep);
4051 + ERROR(fsg, "can't enable %s, result %d\n", ep->name, rc);
4055 +static int alloc_request(struct fsg_dev *fsg, struct usb_ep *ep,
4056 + struct usb_request **preq)
4058 + *preq = usb_ep_alloc_request(ep, GFP_ATOMIC);
4061 + ERROR(fsg, "can't allocate request for %s\n", ep->name);
4066 + * Reset interface setting and re-init endpoint state (toggle etc).
4067 + * Call with altsetting < 0 to disable the interface. The only other
4068 + * available altsetting is 0, which enables the interface.
4070 +static int do_set_interface(struct fsg_dev *fsg, int altsetting)
4074 + const struct usb_endpoint_descriptor *d;
4077 + DBG(fsg, "reset interface\n");
4080 + /* Deallocate the requests */
4081 + for (i = 0; i < fsg_num_buffers; ++i) {
4082 + struct fsg_buffhd *bh = &fsg->buffhds[i];
4085 + usb_ep_free_request(fsg->bulk_in, bh->inreq);
4089 + usb_ep_free_request(fsg->bulk_out, bh->outreq);
4090 + bh->outreq = NULL;
4093 + if (fsg->intreq) {
4094 + usb_ep_free_request(fsg->intr_in, fsg->intreq);
4095 + fsg->intreq = NULL;
4098 + /* Disable the endpoints */
4099 + if (fsg->bulk_in_enabled) {
4100 + usb_ep_disable(fsg->bulk_in);
4101 + fsg->bulk_in_enabled = 0;
4103 + if (fsg->bulk_out_enabled) {
4104 + usb_ep_disable(fsg->bulk_out);
4105 + fsg->bulk_out_enabled = 0;
4107 + if (fsg->intr_in_enabled) {
4108 + usb_ep_disable(fsg->intr_in);
4109 + fsg->intr_in_enabled = 0;
4113 + if (altsetting < 0 || rc != 0)
4116 + DBG(fsg, "set interface %d\n", altsetting);
4118 + /* Enable the endpoints */
4119 + d = fsg_ep_desc(fsg->gadget,
4120 + &fsg_fs_bulk_in_desc, &fsg_hs_bulk_in_desc,
4121 + &fsg_ss_bulk_in_desc);
4122 + if ((rc = enable_endpoint(fsg, fsg->bulk_in, d)) != 0)
4124 + fsg->bulk_in_enabled = 1;
4126 + d = fsg_ep_desc(fsg->gadget,
4127 + &fsg_fs_bulk_out_desc, &fsg_hs_bulk_out_desc,
4128 + &fsg_ss_bulk_out_desc);
4129 + if ((rc = enable_endpoint(fsg, fsg->bulk_out, d)) != 0)
4131 + fsg->bulk_out_enabled = 1;
4132 + fsg->bulk_out_maxpacket = usb_endpoint_maxp(d);
4133 + clear_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags);
4135 + if (transport_is_cbi()) {
4136 + d = fsg_ep_desc(fsg->gadget,
4137 + &fsg_fs_intr_in_desc, &fsg_hs_intr_in_desc,
4138 + &fsg_ss_intr_in_desc);
4139 + if ((rc = enable_endpoint(fsg, fsg->intr_in, d)) != 0)
4141 + fsg->intr_in_enabled = 1;
4144 + /* Allocate the requests */
4145 + for (i = 0; i < fsg_num_buffers; ++i) {
4146 + struct fsg_buffhd *bh = &fsg->buffhds[i];
4148 + if ((rc = alloc_request(fsg, fsg->bulk_in, &bh->inreq)) != 0)
4150 + if ((rc = alloc_request(fsg, fsg->bulk_out, &bh->outreq)) != 0)
4152 + bh->inreq->buf = bh->outreq->buf = bh->buf;
4153 + bh->inreq->context = bh->outreq->context = bh;
4154 + bh->inreq->complete = bulk_in_complete;
4155 + bh->outreq->complete = bulk_out_complete;
4157 + if (transport_is_cbi()) {
4158 + if ((rc = alloc_request(fsg, fsg->intr_in, &fsg->intreq)) != 0)
4160 + fsg->intreq->complete = intr_in_complete;
4164 + for (i = 0; i < fsg->nluns; ++i)
4165 + fsg->luns[i].unit_attention_data = SS_RESET_OCCURRED;
4171 + * Change our operational configuration. This code must agree with the code
4172 + * that returns config descriptors, and with interface altsetting code.
4174 + * It's also responsible for power management interactions. Some
4175 + * configurations might not work with our current power sources.
4176 + * For now we just assume the gadget is always self-powered.
4178 +static int do_set_config(struct fsg_dev *fsg, u8 new_config)
4182 + /* Disable the single interface */
4183 + if (fsg->config != 0) {
4184 + DBG(fsg, "reset config\n");
4186 + rc = do_set_interface(fsg, -1);
4189 + /* Enable the interface */
4190 + if (new_config != 0) {
4191 + fsg->config = new_config;
4192 + if ((rc = do_set_interface(fsg, 0)) != 0)
4193 + fsg->config = 0; // Reset on errors
4195 + INFO(fsg, "%s config #%d\n",
4196 + usb_speed_string(fsg->gadget->speed),
4203 +/*-------------------------------------------------------------------------*/
4205 +static void handle_exception(struct fsg_dev *fsg)
4211 + struct fsg_buffhd *bh;
4212 + enum fsg_state old_state;
4214 + struct fsg_lun *curlun;
4215 + unsigned int exception_req_tag;
4218 + /* Clear the existing signals. Anything but SIGUSR1 is converted
4219 + * into a high-priority EXIT exception. */
4221 + sig = dequeue_signal_lock(current, ¤t->blocked, &info);
4224 + if (sig != SIGUSR1) {
4225 + if (fsg->state < FSG_STATE_EXIT)
4226 + DBG(fsg, "Main thread exiting on signal\n");
4227 + raise_exception(fsg, FSG_STATE_EXIT);
4231 + /* Cancel all the pending transfers */
4232 + if (fsg->intreq_busy)
4233 + usb_ep_dequeue(fsg->intr_in, fsg->intreq);
4234 + for (i = 0; i < fsg_num_buffers; ++i) {
4235 + bh = &fsg->buffhds[i];
4236 + if (bh->inreq_busy)
4237 + usb_ep_dequeue(fsg->bulk_in, bh->inreq);
4238 + if (bh->outreq_busy)
4239 + usb_ep_dequeue(fsg->bulk_out, bh->outreq);
4242 + /* Wait until everything is idle */
4244 + num_active = fsg->intreq_busy;
4245 + for (i = 0; i < fsg_num_buffers; ++i) {
4246 + bh = &fsg->buffhds[i];
4247 + num_active += bh->inreq_busy + bh->outreq_busy;
4249 + if (num_active == 0)
4251 + if (sleep_thread(fsg))
4255 + /* Clear out the controller's fifos */
4256 + if (fsg->bulk_in_enabled)
4257 + usb_ep_fifo_flush(fsg->bulk_in);
4258 + if (fsg->bulk_out_enabled)
4259 + usb_ep_fifo_flush(fsg->bulk_out);
4260 + if (fsg->intr_in_enabled)
4261 + usb_ep_fifo_flush(fsg->intr_in);
4263 + /* Reset the I/O buffer states and pointers, the SCSI
4264 + * state, and the exception. Then invoke the handler. */
4265 + spin_lock_irq(&fsg->lock);
4267 + for (i = 0; i < fsg_num_buffers; ++i) {
4268 + bh = &fsg->buffhds[i];
4269 + bh->state = BUF_STATE_EMPTY;
4271 + fsg->next_buffhd_to_fill = fsg->next_buffhd_to_drain =
4274 + exception_req_tag = fsg->exception_req_tag;
4275 + new_config = fsg->new_config;
4276 + old_state = fsg->state;
4278 + if (old_state == FSG_STATE_ABORT_BULK_OUT)
4279 + fsg->state = FSG_STATE_STATUS_PHASE;
4281 + for (i = 0; i < fsg->nluns; ++i) {
4282 + curlun = &fsg->luns[i];
4283 + curlun->prevent_medium_removal = 0;
4284 + curlun->sense_data = curlun->unit_attention_data =
4286 + curlun->sense_data_info = 0;
4287 + curlun->info_valid = 0;
4289 + fsg->state = FSG_STATE_IDLE;
4291 + spin_unlock_irq(&fsg->lock);
4293 + /* Carry out any extra actions required for the exception */
4294 + switch (old_state) {
4298 + case FSG_STATE_ABORT_BULK_OUT:
4300 + spin_lock_irq(&fsg->lock);
4301 + if (fsg->state == FSG_STATE_STATUS_PHASE)
4302 + fsg->state = FSG_STATE_IDLE;
4303 + spin_unlock_irq(&fsg->lock);
4306 + case FSG_STATE_RESET:
4307 + /* In case we were forced against our will to halt a
4308 + * bulk endpoint, clear the halt now. (The SuperH UDC
4309 + * requires this.) */
4310 + if (test_and_clear_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags))
4311 + usb_ep_clear_halt(fsg->bulk_in);
4313 + if (transport_is_bbb()) {
4314 + if (fsg->ep0_req_tag == exception_req_tag)
4315 + ep0_queue(fsg); // Complete the status stage
4317 + } else if (transport_is_cbi())
4318 + send_status(fsg); // Status by interrupt pipe
4320 + /* Technically this should go here, but it would only be
4321 + * a waste of time. Ditto for the INTERFACE_CHANGE and
4322 + * CONFIG_CHANGE cases. */
4323 + // for (i = 0; i < fsg->nluns; ++i)
4324 + // fsg->luns[i].unit_attention_data = SS_RESET_OCCURRED;
4327 + case FSG_STATE_INTERFACE_CHANGE:
4328 + rc = do_set_interface(fsg, 0);
4329 + if (fsg->ep0_req_tag != exception_req_tag)
4331 + if (rc != 0) // STALL on errors
4332 + fsg_set_halt(fsg, fsg->ep0);
4333 + else // Complete the status stage
4337 + case FSG_STATE_CONFIG_CHANGE:
4338 + rc = do_set_config(fsg, new_config);
4339 + if (fsg->ep0_req_tag != exception_req_tag)
4341 + if (rc != 0) // STALL on errors
4342 + fsg_set_halt(fsg, fsg->ep0);
4343 + else // Complete the status stage
4347 + case FSG_STATE_DISCONNECT:
4348 + for (i = 0; i < fsg->nluns; ++i)
4349 + fsg_lun_fsync_sub(fsg->luns + i);
4350 + do_set_config(fsg, 0); // Unconfigured state
4353 + case FSG_STATE_EXIT:
4354 + case FSG_STATE_TERMINATED:
4355 + do_set_config(fsg, 0); // Free resources
4356 + spin_lock_irq(&fsg->lock);
4357 + fsg->state = FSG_STATE_TERMINATED; // Stop the thread
4358 + spin_unlock_irq(&fsg->lock);
4364 +/*-------------------------------------------------------------------------*/
4366 +static int fsg_main_thread(void *fsg_)
4368 + struct fsg_dev *fsg = fsg_;
4370 + /* Allow the thread to be killed by a signal, but set the signal mask
4371 + * to block everything but INT, TERM, KILL, and USR1. */
4372 + allow_signal(SIGINT);
4373 + allow_signal(SIGTERM);
4374 + allow_signal(SIGKILL);
4375 + allow_signal(SIGUSR1);
4377 + /* Allow the thread to be frozen */
4380 + /* Arrange for userspace references to be interpreted as kernel
4381 + * pointers. That way we can pass a kernel pointer to a routine
4382 + * that expects a __user pointer and it will work okay. */
4385 + /* The main loop */
4386 + while (fsg->state != FSG_STATE_TERMINATED) {
4387 + if (exception_in_progress(fsg) || signal_pending(current)) {
4388 + handle_exception(fsg);
4392 + if (!fsg->running) {
4393 + sleep_thread(fsg);
4397 + if (get_next_command(fsg))
4400 + spin_lock_irq(&fsg->lock);
4401 + if (!exception_in_progress(fsg))
4402 + fsg->state = FSG_STATE_DATA_PHASE;
4403 + spin_unlock_irq(&fsg->lock);
4405 + if (do_scsi_command(fsg) || finish_reply(fsg))
4408 + spin_lock_irq(&fsg->lock);
4409 + if (!exception_in_progress(fsg))
4410 + fsg->state = FSG_STATE_STATUS_PHASE;
4411 + spin_unlock_irq(&fsg->lock);
4413 + if (send_status(fsg))
4416 + spin_lock_irq(&fsg->lock);
4417 + if (!exception_in_progress(fsg))
4418 + fsg->state = FSG_STATE_IDLE;
4419 + spin_unlock_irq(&fsg->lock);
4422 + spin_lock_irq(&fsg->lock);
4423 + fsg->thread_task = NULL;
4424 + spin_unlock_irq(&fsg->lock);
4426 + /* If we are exiting because of a signal, unregister the
4427 + * gadget driver. */
4428 + if (test_and_clear_bit(REGISTERED, &fsg->atomic_bitflags))
4429 + usb_gadget_unregister_driver(&fsg_driver);
4431 + /* Let the unbind and cleanup routines know the thread has exited */
4432 + complete_and_exit(&fsg->thread_notifier, 0);
4436 +/*-------------------------------------------------------------------------*/
4439 +/* The write permissions and store_xxx pointers are set in fsg_bind() */
4440 +static DEVICE_ATTR(ro, 0444, fsg_show_ro, NULL);
4441 +static DEVICE_ATTR(nofua, 0644, fsg_show_nofua, NULL);
4442 +static DEVICE_ATTR(file, 0444, fsg_show_file, NULL);
4445 +/*-------------------------------------------------------------------------*/
4447 +static void fsg_release(struct kref *ref)
4449 + struct fsg_dev *fsg = container_of(ref, struct fsg_dev, ref);
4455 +static void lun_release(struct device *dev)
4457 + struct rw_semaphore *filesem = dev_get_drvdata(dev);
4458 + struct fsg_dev *fsg =
4459 + container_of(filesem, struct fsg_dev, filesem);
4461 + kref_put(&fsg->ref, fsg_release);
4464 +static void /* __init_or_exit */ fsg_unbind(struct usb_gadget *gadget)
4466 + struct fsg_dev *fsg = get_gadget_data(gadget);
4468 + struct fsg_lun *curlun;
4469 + struct usb_request *req = fsg->ep0req;
4471 + DBG(fsg, "unbind\n");
4472 + clear_bit(REGISTERED, &fsg->atomic_bitflags);
4474 + /* If the thread isn't already dead, tell it to exit now */
4475 + if (fsg->state != FSG_STATE_TERMINATED) {
4476 + raise_exception(fsg, FSG_STATE_EXIT);
4477 + wait_for_completion(&fsg->thread_notifier);
4479 + /* The cleanup routine waits for this completion also */
4480 + complete(&fsg->thread_notifier);
4483 + /* Unregister the sysfs attribute files and the LUNs */
4484 + for (i = 0; i < fsg->nluns; ++i) {
4485 + curlun = &fsg->luns[i];
4486 + if (curlun->registered) {
4487 + device_remove_file(&curlun->dev, &dev_attr_nofua);
4488 + device_remove_file(&curlun->dev, &dev_attr_ro);
4489 + device_remove_file(&curlun->dev, &dev_attr_file);
4490 + fsg_lun_close(curlun);
4491 + device_unregister(&curlun->dev);
4492 + curlun->registered = 0;
4496 + /* Free the data buffers */
4497 + for (i = 0; i < fsg_num_buffers; ++i)
4498 + kfree(fsg->buffhds[i].buf);
4500 + /* Free the request and buffer for endpoint 0 */
4503 + usb_ep_free_request(fsg->ep0, req);
4506 + set_gadget_data(gadget, NULL);
4510 +static int __init check_parameters(struct fsg_dev *fsg)
4515 + /* Store the default values */
4516 + mod_data.transport_type = USB_PR_BULK;
4517 + mod_data.transport_name = "Bulk-only";
4518 + mod_data.protocol_type = USB_SC_SCSI;
4519 + mod_data.protocol_name = "Transparent SCSI";
4521 + /* Some peripheral controllers are known not to be able to
4522 + * halt bulk endpoints correctly. If one of them is present,
4525 + if (gadget_is_at91(fsg->gadget))
4526 + mod_data.can_stall = 0;
4528 + if (mod_data.release == 0xffff) { // Parameter wasn't set
4529 + gcnum = usb_gadget_controller_number(fsg->gadget);
4531 + mod_data.release = 0x0300 + gcnum;
4533 + WARNING(fsg, "controller '%s' not recognized\n",
4534 + fsg->gadget->name);
4535 + mod_data.release = 0x0399;
4539 + prot = simple_strtol(mod_data.protocol_parm, NULL, 0);
4541 +#ifdef CONFIG_USB_FILE_STORAGE_TEST
4542 + if (strnicmp(mod_data.transport_parm, "BBB", 10) == 0) {
4543 + ; // Use default setting
4544 + } else if (strnicmp(mod_data.transport_parm, "CB", 10) == 0) {
4545 + mod_data.transport_type = USB_PR_CB;
4546 + mod_data.transport_name = "Control-Bulk";
4547 + } else if (strnicmp(mod_data.transport_parm, "CBI", 10) == 0) {
4548 + mod_data.transport_type = USB_PR_CBI;
4549 + mod_data.transport_name = "Control-Bulk-Interrupt";
4551 + ERROR(fsg, "invalid transport: %s\n", mod_data.transport_parm);
4555 + if (strnicmp(mod_data.protocol_parm, "SCSI", 10) == 0 ||
4556 + prot == USB_SC_SCSI) {
4557 + ; // Use default setting
4558 + } else if (strnicmp(mod_data.protocol_parm, "RBC", 10) == 0 ||
4559 + prot == USB_SC_RBC) {
4560 + mod_data.protocol_type = USB_SC_RBC;
4561 + mod_data.protocol_name = "RBC";
4562 + } else if (strnicmp(mod_data.protocol_parm, "8020", 4) == 0 ||
4563 + strnicmp(mod_data.protocol_parm, "ATAPI", 10) == 0 ||
4564 + prot == USB_SC_8020) {
4565 + mod_data.protocol_type = USB_SC_8020;
4566 + mod_data.protocol_name = "8020i (ATAPI)";
4567 + } else if (strnicmp(mod_data.protocol_parm, "QIC", 3) == 0 ||
4568 + prot == USB_SC_QIC) {
4569 + mod_data.protocol_type = USB_SC_QIC;
4570 + mod_data.protocol_name = "QIC-157";
4571 + } else if (strnicmp(mod_data.protocol_parm, "UFI", 10) == 0 ||
4572 + prot == USB_SC_UFI) {
4573 + mod_data.protocol_type = USB_SC_UFI;
4574 + mod_data.protocol_name = "UFI";
4575 + } else if (strnicmp(mod_data.protocol_parm, "8070", 4) == 0 ||
4576 + prot == USB_SC_8070) {
4577 + mod_data.protocol_type = USB_SC_8070;
4578 + mod_data.protocol_name = "8070i";
4580 + ERROR(fsg, "invalid protocol: %s\n", mod_data.protocol_parm);
4584 + mod_data.buflen &= PAGE_CACHE_MASK;
4585 + if (mod_data.buflen <= 0) {
4586 + ERROR(fsg, "invalid buflen\n");
4587 + return -ETOOSMALL;
4590 +#endif /* CONFIG_USB_FILE_STORAGE_TEST */
4592 + /* Serial string handling.
4593 + * On a real device, the serial string would be loaded
4594 + * from permanent storage. */
4595 + if (mod_data.serial) {
4600 + * The CB[I] specification limits the serial string to
4601 + * 12 uppercase hexadecimal characters.
4602 + * BBB need at least 12 uppercase hexadecimal characters,
4603 + * with a maximum of 126. */
4604 + for (ch = mod_data.serial; *ch; ++ch) {
4606 + if ((*ch < '0' || *ch > '9') &&
4607 + (*ch < 'A' || *ch > 'F')) { /* not uppercase hex */
4609 + "Invalid serial string character: %c\n",
4615 + (mod_data.transport_type == USB_PR_BULK && len < 12) ||
4616 + (mod_data.transport_type != USB_PR_BULK && len > 12)) {
4617 + WARNING(fsg, "Invalid serial string length!\n");
4620 + fsg_strings[FSG_STRING_SERIAL - 1].s = mod_data.serial;
4622 + WARNING(fsg, "No serial-number string provided!\n");
4624 + device_desc.iSerialNumber = 0;
4631 +static int __init fsg_bind(struct usb_gadget *gadget)
4633 + struct fsg_dev *fsg = the_fsg;
4636 + struct fsg_lun *curlun;
4637 + struct usb_ep *ep;
4638 + struct usb_request *req;
4639 + char *pathbuf, *p;
4641 + fsg->gadget = gadget;
4642 + set_gadget_data(gadget, fsg);
4643 + fsg->ep0 = gadget->ep0;
4644 + fsg->ep0->driver_data = fsg;
4646 + if ((rc = check_parameters(fsg)) != 0)
4649 + if (mod_data.removable) { // Enable the store_xxx attributes
4650 + dev_attr_file.attr.mode = 0644;
4651 + dev_attr_file.store = fsg_store_file;
4652 + if (!mod_data.cdrom) {
4653 + dev_attr_ro.attr.mode = 0644;
4654 + dev_attr_ro.store = fsg_store_ro;
4658 + /* Only for removable media? */
4659 + dev_attr_nofua.attr.mode = 0644;
4660 + dev_attr_nofua.store = fsg_store_nofua;
4662 + /* Find out how many LUNs there should be */
4663 + i = mod_data.nluns;
4665 + i = max(mod_data.num_filenames, 1u);
4666 + if (i > FSG_MAX_LUNS) {
4667 + ERROR(fsg, "invalid number of LUNs: %d\n", i);
4672 + /* Create the LUNs, open their backing files, and register the
4673 + * LUN devices in sysfs. */
4674 + fsg->luns = kzalloc(i * sizeof(struct fsg_lun), GFP_KERNEL);
4681 + for (i = 0; i < fsg->nluns; ++i) {
4682 + curlun = &fsg->luns[i];
4683 + curlun->cdrom = !!mod_data.cdrom;
4684 + curlun->ro = mod_data.cdrom || mod_data.ro[i];
4685 + curlun->initially_ro = curlun->ro;
4686 + curlun->removable = mod_data.removable;
4687 + curlun->nofua = mod_data.nofua[i];
4688 + curlun->dev.release = lun_release;
4689 + curlun->dev.parent = &gadget->dev;
4690 + curlun->dev.driver = &fsg_driver.driver;
4691 + dev_set_drvdata(&curlun->dev, &fsg->filesem);
4692 + dev_set_name(&curlun->dev,"%s-lun%d",
4693 + dev_name(&gadget->dev), i);
4695 + kref_get(&fsg->ref);
4696 + rc = device_register(&curlun->dev);
4698 + INFO(fsg, "failed to register LUN%d: %d\n", i, rc);
4699 + put_device(&curlun->dev);
4702 + curlun->registered = 1;
4704 + rc = device_create_file(&curlun->dev, &dev_attr_ro);
4707 + rc = device_create_file(&curlun->dev, &dev_attr_nofua);
4710 + rc = device_create_file(&curlun->dev, &dev_attr_file);
4714 + if (mod_data.file[i] && *mod_data.file[i]) {
4715 + rc = fsg_lun_open(curlun, mod_data.file[i]);
4718 + } else if (!mod_data.removable) {
4719 + ERROR(fsg, "no file given for LUN%d\n", i);
4725 + /* Find all the endpoints we will use */
4726 + usb_ep_autoconfig_reset(gadget);
4727 + ep = usb_ep_autoconfig(gadget, &fsg_fs_bulk_in_desc);
4729 + goto autoconf_fail;
4730 + ep->driver_data = fsg; // claim the endpoint
4731 + fsg->bulk_in = ep;
4733 + ep = usb_ep_autoconfig(gadget, &fsg_fs_bulk_out_desc);
4735 + goto autoconf_fail;
4736 + ep->driver_data = fsg; // claim the endpoint
4737 + fsg->bulk_out = ep;
4739 + if (transport_is_cbi()) {
4740 + ep = usb_ep_autoconfig(gadget, &fsg_fs_intr_in_desc);
4742 + goto autoconf_fail;
4743 + ep->driver_data = fsg; // claim the endpoint
4744 + fsg->intr_in = ep;
4747 + /* Fix up the descriptors */
4748 + device_desc.idVendor = cpu_to_le16(mod_data.vendor);
4749 + device_desc.idProduct = cpu_to_le16(mod_data.product);
4750 + device_desc.bcdDevice = cpu_to_le16(mod_data.release);
4752 + i = (transport_is_cbi() ? 3 : 2); // Number of endpoints
4753 + fsg_intf_desc.bNumEndpoints = i;
4754 + fsg_intf_desc.bInterfaceSubClass = mod_data.protocol_type;
4755 + fsg_intf_desc.bInterfaceProtocol = mod_data.transport_type;
4756 + fsg_fs_function[i + FSG_FS_FUNCTION_PRE_EP_ENTRIES] = NULL;
4758 + if (gadget_is_dualspeed(gadget)) {
4759 + fsg_hs_function[i + FSG_HS_FUNCTION_PRE_EP_ENTRIES] = NULL;
4761 + /* Assume endpoint addresses are the same for both speeds */
4762 + fsg_hs_bulk_in_desc.bEndpointAddress =
4763 + fsg_fs_bulk_in_desc.bEndpointAddress;
4764 + fsg_hs_bulk_out_desc.bEndpointAddress =
4765 + fsg_fs_bulk_out_desc.bEndpointAddress;
4766 + fsg_hs_intr_in_desc.bEndpointAddress =
4767 + fsg_fs_intr_in_desc.bEndpointAddress;
4770 + if (gadget_is_superspeed(gadget)) {
4771 + unsigned max_burst;
4773 + fsg_ss_function[i + FSG_SS_FUNCTION_PRE_EP_ENTRIES] = NULL;
4775 + /* Calculate bMaxBurst, we know packet size is 1024 */
4776 + max_burst = min_t(unsigned, mod_data.buflen / 1024, 15);
4778 + /* Assume endpoint addresses are the same for both speeds */
4779 + fsg_ss_bulk_in_desc.bEndpointAddress =
4780 + fsg_fs_bulk_in_desc.bEndpointAddress;
4781 + fsg_ss_bulk_in_comp_desc.bMaxBurst = max_burst;
4783 + fsg_ss_bulk_out_desc.bEndpointAddress =
4784 + fsg_fs_bulk_out_desc.bEndpointAddress;
4785 + fsg_ss_bulk_out_comp_desc.bMaxBurst = max_burst;
4788 + if (gadget_is_otg(gadget))
4789 + fsg_otg_desc.bmAttributes |= USB_OTG_HNP;
4793 + /* Allocate the request and buffer for endpoint 0 */
4794 + fsg->ep0req = req = usb_ep_alloc_request(fsg->ep0, GFP_KERNEL);
4797 + req->buf = kmalloc(EP0_BUFSIZE, GFP_KERNEL);
4800 + req->complete = ep0_complete;
4802 + /* Allocate the data buffers */
4803 + for (i = 0; i < fsg_num_buffers; ++i) {
4804 + struct fsg_buffhd *bh = &fsg->buffhds[i];
4806 + /* Allocate for the bulk-in endpoint. We assume that
4807 + * the buffer will also work with the bulk-out (and
4808 + * interrupt-in) endpoint. */
4809 + bh->buf = kmalloc(mod_data.buflen, GFP_KERNEL);
4812 + bh->next = bh + 1;
4814 + fsg->buffhds[fsg_num_buffers - 1].next = &fsg->buffhds[0];
4816 + /* This should reflect the actual gadget power source */
4817 + usb_gadget_set_selfpowered(gadget);
4819 + snprintf(fsg_string_manufacturer, sizeof fsg_string_manufacturer,
4821 + init_utsname()->sysname, init_utsname()->release,
4824 + fsg->thread_task = kthread_create(fsg_main_thread, fsg,
4825 + "file-storage-gadget");
4826 + if (IS_ERR(fsg->thread_task)) {
4827 + rc = PTR_ERR(fsg->thread_task);
4831 + INFO(fsg, DRIVER_DESC ", version: " DRIVER_VERSION "\n");
4832 + INFO(fsg, "NOTE: This driver is deprecated. "
4833 + "Consider using g_mass_storage instead.\n");
4834 + INFO(fsg, "Number of LUNs=%d\n", fsg->nluns);
4836 + pathbuf = kmalloc(PATH_MAX, GFP_KERNEL);
4837 + for (i = 0; i < fsg->nluns; ++i) {
4838 + curlun = &fsg->luns[i];
4839 + if (fsg_lun_is_open(curlun)) {
4842 + p = d_path(&curlun->filp->f_path,
4843 + pathbuf, PATH_MAX);
4847 + LINFO(curlun, "ro=%d, nofua=%d, file: %s\n",
4848 + curlun->ro, curlun->nofua, (p ? p : "(error)"));
4853 + DBG(fsg, "transport=%s (x%02x)\n",
4854 + mod_data.transport_name, mod_data.transport_type);
4855 + DBG(fsg, "protocol=%s (x%02x)\n",
4856 + mod_data.protocol_name, mod_data.protocol_type);
4857 + DBG(fsg, "VendorID=x%04x, ProductID=x%04x, Release=x%04x\n",
4858 + mod_data.vendor, mod_data.product, mod_data.release);
4859 + DBG(fsg, "removable=%d, stall=%d, cdrom=%d, buflen=%u\n",
4860 + mod_data.removable, mod_data.can_stall,
4861 + mod_data.cdrom, mod_data.buflen);
4862 + DBG(fsg, "I/O thread pid: %d\n", task_pid_nr(fsg->thread_task));
4864 + set_bit(REGISTERED, &fsg->atomic_bitflags);
4866 + /* Tell the thread to start working */
4867 + wake_up_process(fsg->thread_task);
4871 + ERROR(fsg, "unable to autoconfigure all endpoints\n");
4875 + fsg->state = FSG_STATE_TERMINATED; // The thread is dead
4876 + fsg_unbind(gadget);
4877 + complete(&fsg->thread_notifier);
4882 +/*-------------------------------------------------------------------------*/
4884 +static void fsg_suspend(struct usb_gadget *gadget)
4886 + struct fsg_dev *fsg = get_gadget_data(gadget);
4888 + DBG(fsg, "suspend\n");
4889 + set_bit(SUSPENDED, &fsg->atomic_bitflags);
4892 +static void fsg_resume(struct usb_gadget *gadget)
4894 + struct fsg_dev *fsg = get_gadget_data(gadget);
4896 + DBG(fsg, "resume\n");
4897 + clear_bit(SUSPENDED, &fsg->atomic_bitflags);
4901 +/*-------------------------------------------------------------------------*/
4903 +static struct usb_gadget_driver fsg_driver = {
4904 + .max_speed = USB_SPEED_SUPER,
4905 + .function = (char *) fsg_string_product,
4906 + .unbind = fsg_unbind,
4907 + .disconnect = fsg_disconnect,
4908 + .setup = fsg_setup,
4909 + .suspend = fsg_suspend,
4910 + .resume = fsg_resume,
4913 + .name = DRIVER_NAME,
4914 + .owner = THIS_MODULE,
4922 +static int __init fsg_alloc(void)
4924 + struct fsg_dev *fsg;
4926 + fsg = kzalloc(sizeof *fsg +
4927 + fsg_num_buffers * sizeof *(fsg->buffhds), GFP_KERNEL);
4931 + spin_lock_init(&fsg->lock);
4932 + init_rwsem(&fsg->filesem);
4933 + kref_init(&fsg->ref);
4934 + init_completion(&fsg->thread_notifier);
4941 +static int __init fsg_init(void)
4944 + struct fsg_dev *fsg;
4946 + rc = fsg_num_buffers_validate();
4950 + if ((rc = fsg_alloc()) != 0)
4953 + if ((rc = usb_gadget_probe_driver(&fsg_driver, fsg_bind)) != 0)
4954 + kref_put(&fsg->ref, fsg_release);
4957 +module_init(fsg_init);
4960 +static void __exit fsg_cleanup(void)
4962 + struct fsg_dev *fsg = the_fsg;
4964 + /* Unregister the driver iff the thread hasn't already done so */
4965 + if (test_and_clear_bit(REGISTERED, &fsg->atomic_bitflags))
4966 + usb_gadget_unregister_driver(&fsg_driver);
4968 + /* Wait for the thread to finish up */
4969 + wait_for_completion(&fsg->thread_notifier);
4971 + kref_put(&fsg->ref, fsg_release);
4973 +module_exit(fsg_cleanup);
4974 --- a/drivers/usb/host/Kconfig
4975 +++ b/drivers/usb/host/Kconfig
4976 @@ -712,6 +712,16 @@ config USB_RENESAS_USBHS_HCD
4977 To compile this driver as a module, choose M here: the
4978 module will be called renesas-usbhs.
4981 + bool "Synopsis DWC host support"
4982 + depends on USB && (FIQ || ARM64)
4984 + The Synopsis DWC controller is a dual-role
4985 + host/peripheral/OTG ("On The Go") USB controllers.
4987 + Enable this option to support this IP in host controller mode.
4990 config USB_IMX21_HCD
4991 tristate "i.MX21 HCD support"
4992 depends on ARM && ARCH_MXC
4993 --- a/drivers/usb/host/Makefile
4994 +++ b/drivers/usb/host/Makefile
4995 @@ -79,6 +79,7 @@ obj-$(CONFIG_USB_SL811_HCD) += sl811-hcd
4996 obj-$(CONFIG_USB_SL811_CS) += sl811_cs.o
4997 obj-$(CONFIG_USB_U132_HCD) += u132-hcd.o
4998 obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o
4999 +obj-$(CONFIG_USB_DWCOTG) += dwc_otg/ dwc_common_port/
5000 obj-$(CONFIG_USB_IMX21_HCD) += imx21-hcd.o
5001 obj-$(CONFIG_USB_FSL_USB2) += fsl-mph-dr-of.o
5002 obj-$(CONFIG_USB_EHCI_FSL) += fsl-mph-dr-of.o
5004 +++ b/drivers/usb/host/dwc_common_port/Makefile
5007 +# Makefile for DWC_common library
5010 +ifneq ($(KERNELRELEASE),)
5012 +ccflags-y += -DDWC_LINUX
5013 +#ccflags-y += -DDEBUG
5014 +#ccflags-y += -DDWC_DEBUG_REGS
5015 +#ccflags-y += -DDWC_DEBUG_MEMORY
5017 +ccflags-y += -DDWC_LIBMODULE
5018 +ccflags-y += -DDWC_CCLIB
5019 +#ccflags-y += -DDWC_CRYPTOLIB
5020 +ccflags-y += -DDWC_NOTIFYLIB
5021 +ccflags-y += -DDWC_UTFLIB
5023 +obj-$(CONFIG_USB_DWCOTG) += dwc_common_port_lib.o
5024 +dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \
5025 + dwc_crypto.o dwc_notifier.o \
5026 + dwc_common_linux.o dwc_mem.o
5028 +kernrelwd := $(subst ., ,$(KERNELRELEASE))
5029 +kernrel3 := $(word 1,$(kernrelwd)).$(word 2,$(kernrelwd)).$(word 3,$(kernrelwd))
5031 +ifneq ($(kernrel3),2.6.20)
5032 +# grayg - I only know that we use ccflags-y in 2.6.31 actually
5033 +ccflags-y += $(CPPFLAGS)
5039 +#$(error Must give "KDIR=/path/to/kernel/source" on command line or in environment)
5043 +$(error Must give "ARCH=<arch>" on command line or in environment. Also, if \
5044 + cross-compiling, must give "CROSS_COMPILE=/path/to/compiler/plus/tool-prefix-")
5052 + $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
5054 +docs: $(wildcard *.[hc]) doc/doxygen.cfg
5055 + $(DOXYGEN) doc/doxygen.cfg
5057 +tags: $(wildcard *.[hc])
5058 + $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)
5063 + rm -rf *.o *.ko .*.cmd *.mod.c .*.o.d .*.o.tmp modules.order Module.markers Module.symvers .tmp_versions/
5065 +++ b/drivers/usb/host/dwc_common_port/Makefile.fbsd
5067 +CFLAGS += -I/sys/i386/compile/GENERIC -I/sys/i386/include -I/usr/include
5068 +CFLAGS += -DDWC_FREEBSD
5070 +#CFLAGS += -DDWC_DEBUG_REGS
5071 +#CFLAGS += -DDWC_DEBUG_MEMORY
5073 +#CFLAGS += -DDWC_LIBMODULE
5074 +#CFLAGS += -DDWC_CCLIB
5075 +#CFLAGS += -DDWC_CRYPTOLIB
5076 +#CFLAGS += -DDWC_NOTIFYLIB
5077 +#CFLAGS += -DDWC_UTFLIB
5079 +KMOD = dwc_common_port_lib
5080 +SRCS = dwc_cc.c dwc_modpow.c dwc_dh.c dwc_crypto.c dwc_notifier.c \
5081 + dwc_common_fbsd.c dwc_mem.c
5083 +.include <bsd.kmod.mk>
5085 +++ b/drivers/usb/host/dwc_common_port/Makefile.linux
5088 +# Makefile for DWC_common library
5090 +ifneq ($(KERNELRELEASE),)
5092 +ccflags-y += -DDWC_LINUX
5093 +#ccflags-y += -DDEBUG
5094 +#ccflags-y += -DDWC_DEBUG_REGS
5095 +#ccflags-y += -DDWC_DEBUG_MEMORY
5097 +ccflags-y += -DDWC_LIBMODULE
5098 +ccflags-y += -DDWC_CCLIB
5099 +ccflags-y += -DDWC_CRYPTOLIB
5100 +ccflags-y += -DDWC_NOTIFYLIB
5101 +ccflags-y += -DDWC_UTFLIB
5103 +obj-m := dwc_common_port_lib.o
5104 +dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \
5105 + dwc_crypto.o dwc_notifier.o \
5106 + dwc_common_linux.o dwc_mem.o
5111 +$(error Must give "KDIR=/path/to/kernel/source" on command line or in environment)
5115 +$(error Must give "ARCH=<arch>" on command line or in environment. Also, if \
5116 + cross-compiling, must give "CROSS_COMPILE=/path/to/compiler/plus/tool-prefix-")
5124 + $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
5126 +docs: $(wildcard *.[hc]) doc/doxygen.cfg
5127 + $(DOXYGEN) doc/doxygen.cfg
5129 +tags: $(wildcard *.[hc])
5130 + $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)
5135 + rm -rf *.o *.ko .*.cmd *.mod.c .*.o.d .*.o.tmp modules.order Module.markers Module.symvers .tmp_versions/
5137 +++ b/drivers/usb/host/dwc_common_port/changes.txt
5140 +dwc_read_reg32() and friends now take an additional parameter, a pointer to an
5141 +IO context struct. The IO context struct should live in an os-dependent struct
5142 +in your driver. As an example, the dwc_usb3 driver has an os-dependent struct
5143 +named 'os_dep' embedded in the main device struct. So there these calls look
5146 + dwc_read_reg32(&usb3_dev->os_dep.ioctx, &pcd->dev_global_regs->dcfg);
5148 + dwc_write_reg32(&usb3_dev->os_dep.ioctx,
5149 + &pcd->dev_global_regs->dcfg, 0);
5151 +Note that for the existing Linux driver ports, it is not necessary to actually
5152 +define the 'ioctx' member in the os-dependent struct. Since Linux does not
5153 +require an IO context, its macros for dwc_read_reg32() and friends do not
5154 +use the context pointer, so it is optimized away by the compiler. But it is
5155 +necessary to add the pointer parameter to all of the call sites, to be ready
5156 +for any future ports (such as FreeBSD) which do require an IO context.
5159 +Similarly, dwc_alloc(), dwc_alloc_atomic(), dwc_strdup(), and dwc_free() now
5160 +take an additional parameter, a pointer to a memory context. Examples:
5162 + addr = dwc_alloc(&usb3_dev->os_dep.memctx, size);
5164 + dwc_free(&usb3_dev->os_dep.memctx, addr);
5166 +Again, for the Linux ports, it is not necessary to actually define the memctx
5167 +member, but it is necessary to add the pointer parameter to all of the call
5171 +Same for dwc_dma_alloc() and dwc_dma_free(). Examples:
5173 + virt_addr = dwc_dma_alloc(&usb3_dev->os_dep.dmactx, size, &phys_addr);
5175 + dwc_dma_free(&usb3_dev->os_dep.dmactx, size, virt_addr, phys_addr);
5178 +Same for dwc_mutex_alloc() and dwc_mutex_free(). Examples:
5180 + mutex = dwc_mutex_alloc(&usb3_dev->os_dep.mtxctx);
5182 + dwc_mutex_free(&usb3_dev->os_dep.mtxctx, mutex);
5185 +Same for dwc_spinlock_alloc() and dwc_spinlock_free(). Examples:
5187 + lock = dwc_spinlock_alloc(&usb3_dev->osdep.splctx);
5189 + dwc_spinlock_free(&usb3_dev->osdep.splctx, lock);
5192 +Same for dwc_timer_alloc(). Example:
5194 + timer = dwc_timer_alloc(&usb3_dev->os_dep.tmrctx, "dwc_usb3_tmr1",
5195 + cb_func, cb_data);
5198 +Same for dwc_waitq_alloc(). Example:
5200 + waitq = dwc_waitq_alloc(&usb3_dev->os_dep.wtqctx);
5203 +Same for dwc_thread_run(). Example:
5205 + thread = dwc_thread_run(&usb3_dev->os_dep.thdctx, func,
5206 + "dwc_usb3_thd1", data);
5209 +Same for dwc_workq_alloc(). Example:
5211 + workq = dwc_workq_alloc(&usb3_dev->osdep.wkqctx, "dwc_usb3_wkq1");
5214 +Same for dwc_task_alloc(). Example:
5216 + task = dwc_task_alloc(&usb3_dev->os_dep.tskctx, "dwc_usb3_tsk1",
5217 + cb_func, cb_data);
5220 +In addition to the context pointer additions, a few core functions have had
5221 +other changes made to their parameters:
5223 +The 'flags' parameter to dwc_spinlock_irqsave() and dwc_spinunlock_irqrestore()
5224 +has been changed from a uint64_t to a dwc_irqflags_t.
5226 +dwc_thread_should_stop() now takes a 'dwc_thread_t *' parameter, because the
5227 +FreeBSD equivalent of that function requires it.
5229 +And, in addition to the context pointer, dwc_task_alloc() also adds a
5230 +'char *name' parameter, to be consistent with dwc_thread_run() and
5231 +dwc_workq_alloc(), and because the FreeBSD equivalent of that function
5232 +requires a unique name.
5235 +Here is a complete list of the core functions that now take a pointer to a
5236 +context as their first parameter:
5252 + dwc_spinlock_alloc
5258 + dwc_task_alloc Also adds a 'char *name' as its 2nd parameter
5260 +And here are the core functions that have other changes to their parameters:
5262 + dwc_spinlock_irqsave 'flags' param is now a 'dwc_irqflags_t *'
5263 + dwc_spinunlock_irqrestore 'flags' param is now a 'dwc_irqflags_t'
5264 + dwc_thread_should_stop Adds a 'dwc_thread_t *' parameter
5268 +The changes to the core functions also require some of the other library
5269 +functions to change:
5271 + dwc_cc_if_alloc() and dwc_cc_if_free() now take a 'void *memctx'
5272 + (for memory allocation) as the 1st param and a 'void *mtxctx'
5273 + (for mutex allocation) as the 2nd param.
5275 + dwc_cc_clear(), dwc_cc_add(), dwc_cc_change(), dwc_cc_remove(),
5276 + dwc_cc_data_for_save(), and dwc_cc_restore_from_data() now take a
5277 + 'void *memctx' as the 1st param.
5279 + dwc_dh_modpow(), dwc_dh_pk(), and dwc_dh_derive_keys() now take a
5280 + 'void *memctx' as the 1st param.
5282 + dwc_modpow() now takes a 'void *memctx' as the 1st param.
5284 + dwc_alloc_notification_manager() now takes a 'void *memctx' as the
5285 + 1st param and a 'void *wkqctx' (for work queue allocation) as the 2nd
5286 + param, and also now returns an integer value that is non-zero if
5287 + allocation of its data structures or work queue fails.
5289 + dwc_register_notifier() now takes a 'void *memctx' as the 1st param.
5291 + dwc_memory_debug_start() now takes a 'void *mem_ctx' as the first
5292 + param, and also now returns an integer value that is non-zero if
5293 + allocation of its data structures fails.
5297 +Other miscellaneous changes:
5299 +The DEBUG_MEMORY and DEBUG_REGS #define's have been renamed to
5300 +DWC_DEBUG_MEMORY and DWC_DEBUG_REGS.
5302 +The following #define's have been added to allow selectively compiling library
5310 +A DWC_LIBMODULE #define has also been added. If this is not defined, then the
5311 +module code in dwc_common_linux.c is not compiled in. This allows linking the
5312 +library code directly into a driver module, instead of as a standalone module.
5314 +++ b/drivers/usb/host/dwc_common_port/doc/doxygen.cfg
5318 +#---------------------------------------------------------------------------
5319 +# Project related configuration options
5320 +#---------------------------------------------------------------------------
5321 +PROJECT_NAME = "Synopsys DWC Portability and Common Library for UWB"
5323 +OUTPUT_DIRECTORY = doc
5324 +CREATE_SUBDIRS = NO
5325 +OUTPUT_LANGUAGE = English
5326 +BRIEF_MEMBER_DESC = YES
5328 +ABBREVIATE_BRIEF = "The $name class" \
5329 + "The $name widget" \
5330 + "The $name file" \
5339 +ALWAYS_DETAILED_SEC = YES
5340 +INLINE_INHERITED_MEMB = NO
5341 +FULL_PATH_NAMES = NO
5342 +STRIP_FROM_PATH = ..
5343 +STRIP_FROM_INC_PATH =
5345 +JAVADOC_AUTOBRIEF = YES
5346 +MULTILINE_CPP_IS_BRIEF = NO
5347 +DETAILS_AT_TOP = YES
5349 +SEPARATE_MEMBER_PAGES = NO
5352 +OPTIMIZE_OUTPUT_FOR_C = YES
5353 +OPTIMIZE_OUTPUT_JAVA = NO
5354 +BUILTIN_STL_SUPPORT = NO
5355 +DISTRIBUTE_GROUP_DOC = NO
5357 +#---------------------------------------------------------------------------
5358 +# Build related configuration options
5359 +#---------------------------------------------------------------------------
5361 +EXTRACT_PRIVATE = NO
5362 +EXTRACT_STATIC = YES
5363 +EXTRACT_LOCAL_CLASSES = NO
5364 +EXTRACT_LOCAL_METHODS = NO
5365 +HIDE_UNDOC_MEMBERS = NO
5366 +HIDE_UNDOC_CLASSES = NO
5367 +HIDE_FRIEND_COMPOUNDS = NO
5368 +HIDE_IN_BODY_DOCS = NO
5370 +CASE_SENSE_NAMES = YES
5371 +HIDE_SCOPE_NAMES = NO
5372 +SHOW_INCLUDE_FILES = NO
5374 +SORT_MEMBER_DOCS = NO
5375 +SORT_BRIEF_DOCS = NO
5376 +SORT_BY_SCOPE_NAME = NO
5377 +GENERATE_TODOLIST = YES
5378 +GENERATE_TESTLIST = YES
5379 +GENERATE_BUGLIST = YES
5380 +GENERATE_DEPRECATEDLIST= YES
5382 +MAX_INITIALIZER_LINES = 30
5383 +SHOW_USED_FILES = YES
5384 +SHOW_DIRECTORIES = YES
5385 +FILE_VERSION_FILTER =
5386 +#---------------------------------------------------------------------------
5387 +# configuration options related to warning and progress messages
5388 +#---------------------------------------------------------------------------
5391 +WARN_IF_UNDOCUMENTED = NO
5392 +WARN_IF_DOC_ERROR = YES
5393 +WARN_NO_PARAMDOC = YES
5394 +WARN_FORMAT = "$file:$line: $text"
5396 +#---------------------------------------------------------------------------
5397 +# configuration options related to the input files
5398 +#---------------------------------------------------------------------------
5400 +FILE_PATTERNS = *.c \
5443 +EXCLUDE_SYMLINKS = NO
5446 +EXAMPLE_PATTERNS = *
5447 +EXAMPLE_RECURSIVE = NO
5451 +FILTER_SOURCE_FILES = NO
5452 +#---------------------------------------------------------------------------
5453 +# configuration options related to source browsing
5454 +#---------------------------------------------------------------------------
5455 +SOURCE_BROWSER = NO
5456 +INLINE_SOURCES = NO
5457 +STRIP_CODE_COMMENTS = YES
5458 +REFERENCED_BY_RELATION = YES
5459 +REFERENCES_RELATION = YES
5461 +VERBATIM_HEADERS = NO
5462 +#---------------------------------------------------------------------------
5463 +# configuration options related to the alphabetical class index
5464 +#---------------------------------------------------------------------------
5465 +ALPHABETICAL_INDEX = NO
5466 +COLS_IN_ALPHA_INDEX = 5
5468 +#---------------------------------------------------------------------------
5469 +# configuration options related to the HTML output
5470 +#---------------------------------------------------------------------------
5471 +GENERATE_HTML = YES
5473 +HTML_FILE_EXTENSION = .html
5477 +HTML_ALIGN_MEMBERS = YES
5478 +GENERATE_HTMLHELP = NO
5485 +ENUM_VALUES_PER_LINE = 4
5486 +GENERATE_TREEVIEW = YES
5487 +TREEVIEW_WIDTH = 250
5488 +#---------------------------------------------------------------------------
5489 +# configuration options related to the LaTeX output
5490 +#---------------------------------------------------------------------------
5491 +GENERATE_LATEX = NO
5492 +LATEX_OUTPUT = latex
5493 +LATEX_CMD_NAME = latex
5494 +MAKEINDEX_CMD_NAME = makeindex
5496 +PAPER_TYPE = a4wide
5499 +PDF_HYPERLINKS = NO
5501 +LATEX_BATCHMODE = NO
5502 +LATEX_HIDE_INDICES = NO
5503 +#---------------------------------------------------------------------------
5504 +# configuration options related to the RTF output
5505 +#---------------------------------------------------------------------------
5509 +RTF_HYPERLINKS = NO
5510 +RTF_STYLESHEET_FILE =
5511 +RTF_EXTENSIONS_FILE =
5512 +#---------------------------------------------------------------------------
5513 +# configuration options related to the man page output
5514 +#---------------------------------------------------------------------------
5519 +#---------------------------------------------------------------------------
5520 +# configuration options related to the XML output
5521 +#---------------------------------------------------------------------------
5526 +XML_PROGRAMLISTING = YES
5527 +#---------------------------------------------------------------------------
5528 +# configuration options for the AutoGen Definitions output
5529 +#---------------------------------------------------------------------------
5530 +GENERATE_AUTOGEN_DEF = NO
5531 +#---------------------------------------------------------------------------
5532 +# configuration options related to the Perl module output
5533 +#---------------------------------------------------------------------------
5534 +GENERATE_PERLMOD = NO
5536 +PERLMOD_PRETTY = YES
5537 +PERLMOD_MAKEVAR_PREFIX =
5538 +#---------------------------------------------------------------------------
5539 +# Configuration options related to the preprocessor
5540 +#---------------------------------------------------------------------------
5541 +ENABLE_PREPROCESSING = YES
5542 +MACRO_EXPANSION = NO
5543 +EXPAND_ONLY_PREDEF = NO
5544 +SEARCH_INCLUDES = YES
5546 +INCLUDE_FILE_PATTERNS =
5547 +PREDEFINED = DEBUG DEBUG_MEMORY
5548 +EXPAND_AS_DEFINED =
5549 +SKIP_FUNCTION_MACROS = YES
5550 +#---------------------------------------------------------------------------
5551 +# Configuration::additions related to external references
5552 +#---------------------------------------------------------------------------
5556 +EXTERNAL_GROUPS = YES
5557 +PERL_PATH = /usr/bin/perl
5558 +#---------------------------------------------------------------------------
5559 +# Configuration options related to the dot tool
5560 +#---------------------------------------------------------------------------
5561 +CLASS_DIAGRAMS = YES
5562 +HIDE_UNDOC_RELATIONS = YES
5565 +COLLABORATION_GRAPH = YES
5568 +TEMPLATE_RELATIONS = NO
5570 +INCLUDED_BY_GRAPH = YES
5572 +GRAPHICAL_HIERARCHY = YES
5573 +DIRECTORY_GRAPH = YES
5574 +DOT_IMAGE_FORMAT = png
5577 +MAX_DOT_GRAPH_DEPTH = 1000
5578 +DOT_TRANSPARENT = NO
5579 +DOT_MULTI_TARGETS = NO
5580 +GENERATE_LEGEND = YES
5582 +#---------------------------------------------------------------------------
5583 +# Configuration::additions related to the search engine
5584 +#---------------------------------------------------------------------------
5587 +++ b/drivers/usb/host/dwc_common_port/dwc_cc.c
5589 +/* =========================================================================
5590 + * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_cc.c $
5592 + * $Date: 2010/11/04 $
5593 + * $Change: 1621692 $
5595 + * Synopsys Portability Library Software and documentation
5596 + * (hereinafter, "Software") is an Unsupported proprietary work of
5597 + * Synopsys, Inc. unless otherwise expressly agreed to in writing
5598 + * between Synopsys and you.
5600 + * The Software IS NOT an item of Licensed Software or Licensed Product
5601 + * under any End User Software License Agreement or Agreement for
5602 + * Licensed Product with Synopsys or any supplement thereto. You are
5603 + * permitted to use and redistribute this Software in source and binary
5604 + * forms, with or without modification, provided that redistributions
5605 + * of source code must retain this notice. You may not view, use,
5606 + * disclose, copy or distribute this file or any information contained
5607 + * herein except pursuant to this license grant from Synopsys. If you
5608 + * do not agree with this notice, including the disclaimer below, then
5609 + * you are not authorized to use the Software.
5611 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
5612 + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
5613 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
5614 + * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
5615 + * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
5616 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
5617 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
5618 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
5619 + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5620 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
5621 + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
5623 + * ========================================================================= */
5626 +#include "dwc_cc.h"
5628 +typedef struct dwc_cc
5636 + DWC_CIRCLEQ_ENTRY(dwc_cc) list_entry;
5639 +DWC_CIRCLEQ_HEAD(context_list, dwc_cc);
5641 +/** The main structure for CC management. */
5644 + dwc_mutex_t *mutex;
5647 + unsigned is_host:1;
5649 + dwc_notifier_t *notifier;
5651 + struct context_list list;
5655 +static inline void dump_bytes(char *name, uint8_t *bytes, int len)
5658 + DWC_PRINTF("%s: ", name);
5659 + for (i=0; i<len; i++) {
5660 + DWC_PRINTF("%02x ", bytes[i]);
5665 +#define dump_bytes(x...)
5668 +static dwc_cc_t *alloc_cc(void *mem_ctx, uint8_t *name, uint32_t length)
5670 + dwc_cc_t *cc = dwc_alloc(mem_ctx, sizeof(dwc_cc_t));
5674 + DWC_MEMSET(cc, 0, sizeof(dwc_cc_t));
5677 + cc->length = length;
5678 + cc->name = dwc_alloc(mem_ctx, length);
5680 + dwc_free(mem_ctx, cc);
5684 + DWC_MEMCPY(cc->name, name, length);
5690 +static void free_cc(void *mem_ctx, dwc_cc_t *cc)
5693 + dwc_free(mem_ctx, cc->name);
5695 + dwc_free(mem_ctx, cc);
5698 +static uint32_t next_uid(dwc_cc_if_t *cc_if)
5702 + DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
5703 + if (cc->uid > uid) {
5715 +static dwc_cc_t *cc_find(dwc_cc_if_t *cc_if, uint32_t uid)
5718 + DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
5719 + if (cc->uid == uid) {
5726 +static unsigned int cc_data_size(dwc_cc_if_t *cc_if)
5728 + unsigned int size = 0;
5730 + DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
5733 + size += cc->length;
5739 +static uint32_t cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid)
5744 + DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
5745 + if (DWC_MEMCMP(cc->chid, chid, 16) == 0) {
5752 +static uint32_t cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid)
5757 + DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
5758 + if (DWC_MEMCMP(cc->cdid, cdid, 16) == 0) {
5766 +/* Internal cc_add */
5767 +static int32_t cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid,
5768 + uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
5773 + if (cc_if->is_host) {
5774 + uid = cc_match_cdid(cc_if, cdid);
5777 + uid = cc_match_chid(cc_if, chid);
5781 + DWC_DEBUGC("Replacing previous connection context id=%d name=%p name_len=%d", uid, name, length);
5782 + cc = cc_find(cc_if, uid);
5785 + cc = alloc_cc(mem_ctx, name, length);
5786 + cc->uid = next_uid(cc_if);
5787 + DWC_CIRCLEQ_INSERT_TAIL(&cc_if->list, cc, list_entry);
5790 + DWC_MEMCPY(&(cc->chid[0]), chid, 16);
5791 + DWC_MEMCPY(&(cc->cdid[0]), cdid, 16);
5792 + DWC_MEMCPY(&(cc->ck[0]), ck, 16);
5794 + DWC_DEBUGC("Added connection context id=%d name=%p name_len=%d", cc->uid, name, length);
5795 + dump_bytes("CHID", cc->chid, 16);
5796 + dump_bytes("CDID", cc->cdid, 16);
5797 + dump_bytes("CK", cc->ck, 16);
5801 +/* Internal cc_clear */
5802 +static void cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if)
5804 + while (!DWC_CIRCLEQ_EMPTY(&cc_if->list)) {
5805 + dwc_cc_t *cc = DWC_CIRCLEQ_FIRST(&cc_if->list);
5806 + DWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry);
5807 + free_cc(mem_ctx, cc);
5811 +dwc_cc_if_t *dwc_cc_if_alloc(void *mem_ctx, void *mtx_ctx,
5812 + dwc_notifier_t *notifier, unsigned is_host)
5814 + dwc_cc_if_t *cc_if = NULL;
5816 + /* Allocate a common_cc_if structure */
5817 + cc_if = dwc_alloc(mem_ctx, sizeof(dwc_cc_if_t));
5822 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
5823 + DWC_MUTEX_ALLOC_LINUX_DEBUG(cc_if->mutex);
5825 + cc_if->mutex = dwc_mutex_alloc(mtx_ctx);
5827 + if (!cc_if->mutex) {
5828 + dwc_free(mem_ctx, cc_if);
5832 + DWC_CIRCLEQ_INIT(&cc_if->list);
5833 + cc_if->is_host = is_host;
5834 + cc_if->notifier = notifier;
5838 +void dwc_cc_if_free(void *mem_ctx, void *mtx_ctx, dwc_cc_if_t *cc_if)
5840 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
5841 + DWC_MUTEX_FREE(cc_if->mutex);
5843 + dwc_mutex_free(mtx_ctx, cc_if->mutex);
5845 + cc_clear(mem_ctx, cc_if);
5846 + dwc_free(mem_ctx, cc_if);
5849 +static void cc_changed(dwc_cc_if_t *cc_if)
5851 + if (cc_if->notifier) {
5852 + dwc_notify(cc_if->notifier, DWC_CC_LIST_CHANGED_NOTIFICATION, cc_if);
5856 +void dwc_cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if)
5858 + DWC_MUTEX_LOCK(cc_if->mutex);
5859 + cc_clear(mem_ctx, cc_if);
5860 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5861 + cc_changed(cc_if);
5864 +int32_t dwc_cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid,
5865 + uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
5869 + DWC_MUTEX_LOCK(cc_if->mutex);
5870 + uid = cc_add(mem_ctx, cc_if, chid, cdid, ck, name, length);
5871 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5872 + cc_changed(cc_if);
5877 +void dwc_cc_change(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id, uint8_t *chid,
5878 + uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
5882 + DWC_DEBUGC("Change connection context %d", id);
5884 + DWC_MUTEX_LOCK(cc_if->mutex);
5885 + cc = cc_find(cc_if, id);
5887 + DWC_ERROR("Uid %d not found in cc list\n", id);
5888 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5893 + DWC_MEMCPY(&(cc->chid[0]), chid, 16);
5896 + DWC_MEMCPY(&(cc->cdid[0]), cdid, 16);
5899 + DWC_MEMCPY(&(cc->ck[0]), ck, 16);
5904 + dwc_free(mem_ctx, cc->name);
5906 + cc->name = dwc_alloc(mem_ctx, length);
5908 + DWC_ERROR("Out of memory in dwc_cc_change()\n");
5909 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5912 + cc->length = length;
5913 + DWC_MEMCPY(cc->name, name, length);
5916 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5918 + cc_changed(cc_if);
5920 + DWC_DEBUGC("Changed connection context id=%d\n", id);
5921 + dump_bytes("New CHID", cc->chid, 16);
5922 + dump_bytes("New CDID", cc->cdid, 16);
5923 + dump_bytes("New CK", cc->ck, 16);
5926 +void dwc_cc_remove(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id)
5930 + DWC_DEBUGC("Removing connection context %d", id);
5932 + DWC_MUTEX_LOCK(cc_if->mutex);
5933 + cc = cc_find(cc_if, id);
5935 + DWC_ERROR("Uid %d not found in cc list\n", id);
5936 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5940 + DWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry);
5941 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5942 + free_cc(mem_ctx, cc);
5944 + cc_changed(cc_if);
5947 +uint8_t *dwc_cc_data_for_save(void *mem_ctx, dwc_cc_if_t *cc_if, unsigned int *length)
5953 + DWC_MUTEX_LOCK(cc_if->mutex);
5954 + *length = cc_data_size(cc_if);
5956 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5960 + DWC_DEBUGC("Creating data for saving (length=%d)", *length);
5962 + buf = dwc_alloc(mem_ctx, *length);
5965 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5970 + DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
5971 + DWC_MEMCPY(x, cc->chid, 16);
5973 + DWC_MEMCPY(x, cc->cdid, 16);
5975 + DWC_MEMCPY(x, cc->ck, 16);
5978 + DWC_MEMCPY(x, &cc->length, 1);
5980 + DWC_MEMCPY(x, cc->name, cc->length);
5984 + DWC_MEMCPY(x, &zero, 1);
5988 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5993 +void dwc_cc_restore_from_data(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *data, uint32_t length)
5995 + uint8_t name_length;
6002 + DWC_MUTEX_LOCK(cc_if->mutex);
6003 + cc_clear(mem_ctx, cc_if);
6005 + while (i < length) {
6013 + name_length = data[i];
6016 + if (name_length) {
6024 + /* check to see if we haven't overflown the buffer */
6026 + DWC_ERROR("Data format error while attempting to load CCs "
6027 + "(nlen=%d, iter=%d, buflen=%d).\n", name_length, i, length);
6031 + cc_add(mem_ctx, cc_if, chid, cdid, ck, name, name_length);
6033 + DWC_MUTEX_UNLOCK(cc_if->mutex);
6035 + cc_changed(cc_if);
6038 +uint32_t dwc_cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid)
6042 + DWC_MUTEX_LOCK(cc_if->mutex);
6043 + uid = cc_match_chid(cc_if, chid);
6044 + DWC_MUTEX_UNLOCK(cc_if->mutex);
6047 +uint32_t dwc_cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid)
6051 + DWC_MUTEX_LOCK(cc_if->mutex);
6052 + uid = cc_match_cdid(cc_if, cdid);
6053 + DWC_MUTEX_UNLOCK(cc_if->mutex);
6057 +uint8_t *dwc_cc_ck(dwc_cc_if_t *cc_if, int32_t id)
6059 + uint8_t *ck = NULL;
6062 + DWC_MUTEX_LOCK(cc_if->mutex);
6063 + cc = cc_find(cc_if, id);
6067 + DWC_MUTEX_UNLOCK(cc_if->mutex);
6073 +uint8_t *dwc_cc_chid(dwc_cc_if_t *cc_if, int32_t id)
6075 + uint8_t *retval = NULL;
6078 + DWC_MUTEX_LOCK(cc_if->mutex);
6079 + cc = cc_find(cc_if, id);
6081 + retval = cc->chid;
6083 + DWC_MUTEX_UNLOCK(cc_if->mutex);
6088 +uint8_t *dwc_cc_cdid(dwc_cc_if_t *cc_if, int32_t id)
6090 + uint8_t *retval = NULL;
6093 + DWC_MUTEX_LOCK(cc_if->mutex);
6094 + cc = cc_find(cc_if, id);
6096 + retval = cc->cdid;
6098 + DWC_MUTEX_UNLOCK(cc_if->mutex);
6103 +uint8_t *dwc_cc_name(dwc_cc_if_t *cc_if, int32_t id, uint8_t *length)
6105 + uint8_t *retval = NULL;
6108 + DWC_MUTEX_LOCK(cc_if->mutex);
6110 + cc = cc_find(cc_if, id);
6112 + *length = cc->length;
6113 + retval = cc->name;
6115 + DWC_MUTEX_UNLOCK(cc_if->mutex);
6120 +#endif /* DWC_CCLIB */
6122 +++ b/drivers/usb/host/dwc_common_port/dwc_cc.h
6124 +/* =========================================================================
6125 + * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_cc.h $
6127 + * $Date: 2010/09/28 $
6128 + * $Change: 1596182 $
6130 + * Synopsys Portability Library Software and documentation
6131 + * (hereinafter, "Software") is an Unsupported proprietary work of
6132 + * Synopsys, Inc. unless otherwise expressly agreed to in writing
6133 + * between Synopsys and you.
6135 + * The Software IS NOT an item of Licensed Software or Licensed Product
6136 + * under any End User Software License Agreement or Agreement for
6137 + * Licensed Product with Synopsys or any supplement thereto. You are
6138 + * permitted to use and redistribute this Software in source and binary
6139 + * forms, with or without modification, provided that redistributions
6140 + * of source code must retain this notice. You may not view, use,
6141 + * disclose, copy or distribute this file or any information contained
6142 + * herein except pursuant to this license grant from Synopsys. If you
6143 + * do not agree with this notice, including the disclaimer below, then
6144 + * you are not authorized to use the Software.
6146 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
6147 + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
6148 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
6149 + * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
6150 + * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
6151 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
6152 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
6153 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
6154 + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6155 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
6156 + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
6158 + * ========================================================================= */
6168 + * This file defines the Context Context library.
6170 + * The main data structure is dwc_cc_if_t which is returned by either the
6171 + * dwc_cc_if_alloc function or returned by the module to the user via a provided
6172 + * function. The data structure is opaque and should only be manipulated via the
6173 + * functions provied in this API.
6175 + * It manages a list of connection contexts and operations can be performed to
6176 + * add, remove, query, search, and change, those contexts. Additionally,
6177 + * a dwc_notifier_t object can be requested from the manager so that
6178 + * the user can be notified whenever the context list has changed.
6181 +#include "dwc_os.h"
6182 +#include "dwc_list.h"
6183 +#include "dwc_notifier.h"
6186 +/* Notifications */
6187 +#define DWC_CC_LIST_CHANGED_NOTIFICATION "DWC_CC_LIST_CHANGED_NOTIFICATION"
6190 +typedef struct dwc_cc_if dwc_cc_if_t;
6193 +/** @name Connection Context Operations */
6196 +/** This function allocates memory for a dwc_cc_if_t structure, initializes
6197 + * fields to default values, and returns a pointer to the structure or NULL on
6199 +extern dwc_cc_if_t *dwc_cc_if_alloc(void *mem_ctx, void *mtx_ctx,
6200 + dwc_notifier_t *notifier, unsigned is_host);
6202 +/** Frees the memory for the specified CC structure allocated from
6203 + * dwc_cc_if_alloc(). */
6204 +extern void dwc_cc_if_free(void *mem_ctx, void *mtx_ctx, dwc_cc_if_t *cc_if);
6206 +/** Removes all contexts from the connection context list */
6207 +extern void dwc_cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if);
6209 +/** Adds a connection context (CHID, CK, CDID, Name) to the connection context list.
6210 + * If a CHID already exists, the CK and name are overwritten. Statistics are
6211 + * not overwritten.
6213 + * @param cc_if The cc_if structure.
6214 + * @param chid A pointer to the 16-byte CHID. This value will be copied.
6215 + * @param ck A pointer to the 16-byte CK. This value will be copied.
6216 + * @param cdid A pointer to the 16-byte CDID. This value will be copied.
6217 + * @param name An optional host friendly name as defined in the association model
6218 + * spec. Must be a UTF16-LE unicode string. Can be NULL to indicated no name.
6219 + * @param length The length othe unicode string.
6220 + * @return A unique identifier used to refer to this context that is valid for
6221 + * as long as this context is still in the list. */
6222 +extern int32_t dwc_cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid,
6223 + uint8_t *cdid, uint8_t *ck, uint8_t *name,
6226 +/** Changes the CHID, CK, CDID, or Name values of a connection context in the
6227 + * list, preserving any accumulated statistics. This would typically be called
6228 + * if the host decideds to change the context with a SET_CONNECTION request.
6230 + * @param cc_if The cc_if structure.
6231 + * @param id The identifier of the connection context.
6232 + * @param chid A pointer to the 16-byte CHID. This value will be copied. NULL
6233 + * indicates no change.
6234 + * @param cdid A pointer to the 16-byte CDID. This value will be copied. NULL
6235 + * indicates no change.
6236 + * @param ck A pointer to the 16-byte CK. This value will be copied. NULL
6237 + * indicates no change.
6238 + * @param name Host friendly name UTF16-LE. NULL indicates no change.
6239 + * @param length Length of name. */
6240 +extern void dwc_cc_change(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id,
6241 + uint8_t *chid, uint8_t *cdid, uint8_t *ck,
6242 + uint8_t *name, uint8_t length);
6244 +/** Remove the specified connection context.
6245 + * @param cc_if The cc_if structure.
6246 + * @param id The identifier of the connection context to remove. */
6247 +extern void dwc_cc_remove(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id);
6249 +/** Get a binary block of data for the connection context list and attributes.
6250 + * This data can be used by the OS specific driver to save the connection
6251 + * context list into non-volatile memory.
6253 + * @param cc_if The cc_if structure.
6254 + * @param length Return the length of the data buffer.
6255 + * @return A pointer to the data buffer. The memory for this buffer should be
6256 + * freed with DWC_FREE() after use. */
6257 +extern uint8_t *dwc_cc_data_for_save(void *mem_ctx, dwc_cc_if_t *cc_if,
6258 + unsigned int *length);
6260 +/** Restore the connection context list from the binary data that was previously
6261 + * returned from a call to dwc_cc_data_for_save. This can be used by the OS specific
6262 + * driver to load a connection context list from non-volatile memory.
6264 + * @param cc_if The cc_if structure.
6265 + * @param data The data bytes as returned from dwc_cc_data_for_save.
6266 + * @param length The length of the data. */
6267 +extern void dwc_cc_restore_from_data(void *mem_ctx, dwc_cc_if_t *cc_if,
6268 + uint8_t *data, unsigned int length);
6270 +/** Find the connection context from the specified CHID.
6272 + * @param cc_if The cc_if structure.
6273 + * @param chid A pointer to the CHID data.
6274 + * @return A non-zero identifier of the connection context if the CHID matches.
6275 + * Otherwise returns 0. */
6276 +extern uint32_t dwc_cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid);
6278 +/** Find the connection context from the specified CDID.
6280 + * @param cc_if The cc_if structure.
6281 + * @param cdid A pointer to the CDID data.
6282 + * @return A non-zero identifier of the connection context if the CHID matches.
6283 + * Otherwise returns 0. */
6284 +extern uint32_t dwc_cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid);
6286 +/** Retrieve the CK from the specified connection context.
6288 + * @param cc_if The cc_if structure.
6289 + * @param id The identifier of the connection context.
6290 + * @return A pointer to the CK data. The memory does not need to be freed. */
6291 +extern uint8_t *dwc_cc_ck(dwc_cc_if_t *cc_if, int32_t id);
6293 +/** Retrieve the CHID from the specified connection context.
6295 + * @param cc_if The cc_if structure.
6296 + * @param id The identifier of the connection context.
6297 + * @return A pointer to the CHID data. The memory does not need to be freed. */
6298 +extern uint8_t *dwc_cc_chid(dwc_cc_if_t *cc_if, int32_t id);
6300 +/** Retrieve the CDID from the specified connection context.
6302 + * @param cc_if The cc_if structure.
6303 + * @param id The identifier of the connection context.
6304 + * @return A pointer to the CDID data. The memory does not need to be freed. */
6305 +extern uint8_t *dwc_cc_cdid(dwc_cc_if_t *cc_if, int32_t id);
6307 +extern uint8_t *dwc_cc_name(dwc_cc_if_t *cc_if, int32_t id, uint8_t *length);
6309 +/** Checks a buffer for non-zero.
6310 + * @param id A pointer to a 16 byte buffer.
6311 + * @return true if the 16 byte value is non-zero. */
6312 +static inline unsigned dwc_assoc_is_not_zero_id(uint8_t *id) {
6314 + for (i=0; i<16; i++) {
6315 + if (id[i]) return 1;
6320 +/** Checks a buffer for zero.
6321 + * @param id A pointer to a 16 byte buffer.
6322 + * @return true if the 16 byte value is zero. */
6323 +static inline unsigned dwc_assoc_is_zero_id(uint8_t *id) {
6324 + return !dwc_assoc_is_not_zero_id(id);
6327 +/** Prints an ASCII representation for the 16-byte chid, cdid, or ck, into
6329 +static inline int dwc_print_id_string(char *buffer, uint8_t *id) {
6330 + char *ptr = buffer;
6332 + for (i=0; i<16; i++) {
6333 + ptr += DWC_SPRINTF(ptr, "%02x", id[i]);
6335 + ptr += DWC_SPRINTF(ptr, " ");
6338 + return ptr - buffer;
6347 +#endif /* _DWC_CC_H_ */
6349 +++ b/drivers/usb/host/dwc_common_port/dwc_common_fbsd.c
6351 +#include "dwc_os.h"
6352 +#include "dwc_list.h"
6355 +# include "dwc_cc.h"
6358 +#ifdef DWC_CRYPTOLIB
6359 +# include "dwc_modpow.h"
6360 +# include "dwc_dh.h"
6361 +# include "dwc_crypto.h"
6364 +#ifdef DWC_NOTIFYLIB
6365 +# include "dwc_notifier.h"
6368 +/* OS-Level Implementations */
6370 +/* This is the FreeBSD 7.0 kernel implementation of the DWC platform library. */
6375 +void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size)
6377 + return memset(dest, byte, size);
6380 +void *DWC_MEMCPY(void *dest, void const *src, uint32_t size)
6382 + return memcpy(dest, src, size);
6385 +void *DWC_MEMMOVE(void *dest, void *src, uint32_t size)
6387 + bcopy(src, dest, size);
6391 +int DWC_MEMCMP(void *m1, void *m2, uint32_t size)
6393 + return memcmp(m1, m2, size);
6396 +int DWC_STRNCMP(void *s1, void *s2, uint32_t size)
6398 + return strncmp(s1, s2, size);
6401 +int DWC_STRCMP(void *s1, void *s2)
6403 + return strcmp(s1, s2);
6406 +int DWC_STRLEN(char const *str)
6408 + return strlen(str);
6411 +char *DWC_STRCPY(char *to, char const *from)
6413 + return strcpy(to, from);
6416 +char *DWC_STRDUP(char const *str)
6418 + int len = DWC_STRLEN(str) + 1;
6419 + char *new = DWC_ALLOC_ATOMIC(len);
6425 + DWC_MEMCPY(new, str, len);
6429 +int DWC_ATOI(char *str, int32_t *value)
6433 + *value = strtol(str, &end, 0);
6434 + if (*end == '\0') {
6441 +int DWC_ATOUI(char *str, uint32_t *value)
6445 + *value = strtoul(str, &end, 0);
6446 + if (*end == '\0') {
6455 +/* From usbstring.c */
6457 +int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len)
6463 + /* this insists on correct encodings, though not minimal ones.
6464 + * BUT it currently rejects legit 4-byte UTF-8 code points,
6465 + * which need surrogate pairs. (Unicode 3.1 can use them.)
6467 + while (len != 0 && (c = (u8) *s++) != 0) {
6468 + if (unlikely(c & 0x80)) {
6469 + // 2-byte sequence:
6470 + // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
6471 + if ((c & 0xe0) == 0xc0) {
6472 + uchar = (c & 0x1f) << 6;
6475 + if ((c & 0xc0) != 0xc0)
6480 + // 3-byte sequence (most CJKV characters):
6481 + // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
6482 + } else if ((c & 0xf0) == 0xe0) {
6483 + uchar = (c & 0x0f) << 12;
6486 + if ((c & 0xc0) != 0xc0)
6492 + if ((c & 0xc0) != 0xc0)
6497 + /* no bogus surrogates */
6498 + if (0xd800 <= uchar && uchar <= 0xdfff)
6501 + // 4-byte sequence (surrogate pairs, currently rare):
6502 + // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
6503 + // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
6504 + // (uuuuu = wwww + 1)
6505 + // FIXME accept the surrogate code points (only)
6510 + put_unaligned (cpu_to_le16 (uchar), cp++);
6519 +#endif /* DWC_UTFLIB */
6524 +dwc_bool_t DWC_IN_IRQ(void)
6526 +// return in_irq();
6530 +dwc_bool_t DWC_IN_BH(void)
6532 +// return in_softirq();
6536 +void DWC_VPRINTF(char *format, va_list args)
6538 + vprintf(format, args);
6541 +int DWC_VSNPRINTF(char *str, int size, char *format, va_list args)
6543 + return vsnprintf(str, size, format, args);
6546 +void DWC_PRINTF(char *format, ...)
6550 + va_start(args, format);
6551 + DWC_VPRINTF(format, args);
6555 +int DWC_SPRINTF(char *buffer, char *format, ...)
6560 + va_start(args, format);
6561 + retval = vsprintf(buffer, format, args);
6566 +int DWC_SNPRINTF(char *buffer, int size, char *format, ...)
6571 + va_start(args, format);
6572 + retval = vsnprintf(buffer, size, format, args);
6577 +void __DWC_WARN(char *format, ...)
6581 + va_start(args, format);
6582 + DWC_VPRINTF(format, args);
6586 +void __DWC_ERROR(char *format, ...)
6590 + va_start(args, format);
6591 + DWC_VPRINTF(format, args);
6595 +void DWC_EXCEPTION(char *format, ...)
6599 + va_start(args, format);
6600 + DWC_VPRINTF(format, args);
6606 +void __DWC_DEBUG(char *format, ...)
6610 + va_start(args, format);
6611 + DWC_VPRINTF(format, args);
6620 +dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size,
6624 + struct dma_pool *pool = dma_pool_create("Pool", NULL,
6625 + size, align, alloc);
6626 + return (dwc_pool_t *)pool;
6629 +void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool)
6631 + dma_pool_destroy((struct dma_pool *)pool);
6634 +void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
6636 +// return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr);
6637 + return dma_pool_alloc((struct dma_pool *)pool, M_WAITOK, dma_addr);
6640 +void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
6642 + void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr);
6646 +void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr)
6648 + dma_pool_free(pool, vaddr, daddr);
6652 +static void dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
6656 + *(bus_addr_t *)arg = segs[0].ds_addr;
6659 +void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
6661 + dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
6664 + error = bus_dma_tag_create(
6665 +#if __FreeBSD_version >= 700000
6666 + bus_get_dma_tag(dma->dev), /* parent */
6668 + NULL, /* parent */
6670 + 4, 0, /* alignment, bounds */
6671 + BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
6672 + BUS_SPACE_MAXADDR, /* highaddr */
6673 + NULL, NULL, /* filter, filterarg */
6674 + size, /* maxsize */
6675 + 1, /* nsegments */
6676 + size, /* maxsegsize */
6678 + NULL, /* lockfunc */
6679 + NULL, /* lockarg */
6682 + device_printf(dma->dev, "%s: bus_dma_tag_create failed: %d\n",
6687 + error = bus_dmamem_alloc(dma->dma_tag, &dma->dma_vaddr,
6688 + BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map);
6690 + device_printf(dma->dev, "%s: bus_dmamem_alloc(%ju) failed: %d\n",
6691 + __func__, (uintmax_t)size, error);
6695 + dma->dma_paddr = 0;
6696 + error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, size,
6697 + dmamap_cb, &dma->dma_paddr, BUS_DMA_NOWAIT);
6698 + if (error || dma->dma_paddr == 0) {
6699 + device_printf(dma->dev, "%s: bus_dmamap_load failed: %d\n",
6704 + *dma_addr = dma->dma_paddr;
6705 + return dma->dma_vaddr;
6708 + bus_dmamap_unload(dma->dma_tag, dma->dma_map);
6710 + bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
6711 + bus_dma_tag_destroy(dma->dma_tag);
6713 + dma->dma_map = NULL;
6714 + dma->dma_tag = NULL;
6719 +void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr)
6721 + dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
6723 + if (dma->dma_tag == NULL)
6725 + if (dma->dma_map != NULL) {
6726 + bus_dmamap_sync(dma->dma_tag, dma->dma_map,
6727 + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6728 + bus_dmamap_unload(dma->dma_tag, dma->dma_map);
6729 + bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
6730 + dma->dma_map = NULL;
6733 + bus_dma_tag_destroy(dma->dma_tag);
6734 + dma->dma_tag = NULL;
6737 +void *__DWC_ALLOC(void *mem_ctx, uint32_t size)
6739 + return malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
6742 +void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size)
6744 + return malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
6747 +void __DWC_FREE(void *mem_ctx, void *addr)
6749 + free(addr, M_DEVBUF);
6753 +#ifdef DWC_CRYPTOLIB
6756 +void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length)
6758 + get_random_bytes(buffer, length);
6761 +int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)
6763 + struct crypto_blkcipher *tfm;
6764 + struct blkcipher_desc desc;
6765 + struct scatterlist sgd;
6766 + struct scatterlist sgs;
6768 + tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC);
6769 + if (tfm == NULL) {
6770 + printk("failed to load transform for aes CBC\n");
6774 + crypto_blkcipher_setkey(tfm, key, keylen);
6775 + crypto_blkcipher_set_iv(tfm, iv, 16);
6777 + sg_init_one(&sgd, out, messagelen);
6778 + sg_init_one(&sgs, message, messagelen);
6783 + if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) {
6784 + crypto_free_blkcipher(tfm);
6785 + DWC_ERROR("AES CBC encryption failed");
6789 + crypto_free_blkcipher(tfm);
6793 +int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out)
6795 + struct crypto_hash *tfm;
6796 + struct hash_desc desc;
6797 + struct scatterlist sg;
6799 + tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC);
6800 + if (IS_ERR(tfm)) {
6801 + DWC_ERROR("Failed to load transform for sha256: %ld", PTR_ERR(tfm));
6807 + sg_init_one(&sg, message, len);
6808 + crypto_hash_digest(&desc, &sg, len, out);
6809 + crypto_free_hash(tfm);
6814 +int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen,
6815 + uint8_t *key, uint32_t keylen, uint8_t *out)
6817 + struct crypto_hash *tfm;
6818 + struct hash_desc desc;
6819 + struct scatterlist sg;
6821 + tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC);
6822 + if (IS_ERR(tfm)) {
6823 + DWC_ERROR("Failed to load transform for hmac(sha256): %ld", PTR_ERR(tfm));
6829 + sg_init_one(&sg, message, messagelen);
6830 + crypto_hash_setkey(tfm, key, keylen);
6831 + crypto_hash_digest(&desc, &sg, messagelen, out);
6832 + crypto_free_hash(tfm);
6837 +#endif /* DWC_CRYPTOLIB */
6840 +/* Byte Ordering Conversions */
6842 +uint32_t DWC_CPU_TO_LE32(uint32_t *p)
6844 +#ifdef __LITTLE_ENDIAN
6847 + uint8_t *u_p = (uint8_t *)p;
6849 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
6853 +uint32_t DWC_CPU_TO_BE32(uint32_t *p)
6855 +#ifdef __BIG_ENDIAN
6858 + uint8_t *u_p = (uint8_t *)p;
6860 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
6864 +uint32_t DWC_LE32_TO_CPU(uint32_t *p)
6866 +#ifdef __LITTLE_ENDIAN
6869 + uint8_t *u_p = (uint8_t *)p;
6871 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
6875 +uint32_t DWC_BE32_TO_CPU(uint32_t *p)
6877 +#ifdef __BIG_ENDIAN
6880 + uint8_t *u_p = (uint8_t *)p;
6882 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
6886 +uint16_t DWC_CPU_TO_LE16(uint16_t *p)
6888 +#ifdef __LITTLE_ENDIAN
6891 + uint8_t *u_p = (uint8_t *)p;
6892 + return (u_p[1] | (u_p[0] << 8));
6896 +uint16_t DWC_CPU_TO_BE16(uint16_t *p)
6898 +#ifdef __BIG_ENDIAN
6901 + uint8_t *u_p = (uint8_t *)p;
6902 + return (u_p[1] | (u_p[0] << 8));
6906 +uint16_t DWC_LE16_TO_CPU(uint16_t *p)
6908 +#ifdef __LITTLE_ENDIAN
6911 + uint8_t *u_p = (uint8_t *)p;
6912 + return (u_p[1] | (u_p[0] << 8));
6916 +uint16_t DWC_BE16_TO_CPU(uint16_t *p)
6918 +#ifdef __BIG_ENDIAN
6921 + uint8_t *u_p = (uint8_t *)p;
6922 + return (u_p[1] | (u_p[0] << 8));
6929 +uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg)
6931 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
6932 + bus_size_t ior = (bus_size_t)reg;
6934 + return bus_space_read_4(io->iot, io->ioh, ior);
6938 +uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg)
6940 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
6941 + bus_size_t ior = (bus_size_t)reg;
6943 + return bus_space_read_8(io->iot, io->ioh, ior);
6947 +void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value)
6949 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
6950 + bus_size_t ior = (bus_size_t)reg;
6952 + bus_space_write_4(io->iot, io->ioh, ior, value);
6956 +void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value)
6958 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
6959 + bus_size_t ior = (bus_size_t)reg;
6961 + bus_space_write_8(io->iot, io->ioh, ior, value);
6965 +void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask,
6966 + uint32_t set_mask)
6968 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
6969 + bus_size_t ior = (bus_size_t)reg;
6971 + bus_space_write_4(io->iot, io->ioh, ior,
6972 + (bus_space_read_4(io->iot, io->ioh, ior) &
6973 + ~clear_mask) | set_mask);
6977 +void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask,
6978 + uint64_t set_mask)
6980 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
6981 + bus_size_t ior = (bus_size_t)reg;
6983 + bus_space_write_8(io->iot, io->ioh, ior,
6984 + (bus_space_read_8(io->iot, io->ioh, ior) &
6985 + ~clear_mask) | set_mask);
6992 +dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void)
6994 + struct mtx *sl = DWC_ALLOC(sizeof(*sl));
6997 + DWC_ERROR("Cannot allocate memory for spinlock");
7001 + mtx_init(sl, "dw3spn", NULL, MTX_SPIN);
7002 + return (dwc_spinlock_t *)sl;
7005 +void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock)
7007 + struct mtx *sl = (struct mtx *)lock;
7013 +void DWC_SPINLOCK(dwc_spinlock_t *lock)
7015 + mtx_lock_spin((struct mtx *)lock); // ???
7018 +void DWC_SPINUNLOCK(dwc_spinlock_t *lock)
7020 + mtx_unlock_spin((struct mtx *)lock); // ???
7023 +void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags)
7025 + mtx_lock_spin((struct mtx *)lock);
7028 +void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags)
7030 + mtx_unlock_spin((struct mtx *)lock);
7033 +dwc_mutex_t *DWC_MUTEX_ALLOC(void)
7036 + dwc_mutex_t *mutex = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mtx));
7039 + DWC_ERROR("Cannot allocate memory for mutex");
7043 + m = (struct mtx *)mutex;
7044 + mtx_init(m, "dw3mtx", NULL, MTX_DEF);
7048 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
7050 +void DWC_MUTEX_FREE(dwc_mutex_t *mutex)
7052 + mtx_destroy((struct mtx *)mutex);
7057 +void DWC_MUTEX_LOCK(dwc_mutex_t *mutex)
7059 + struct mtx *m = (struct mtx *)mutex;
7064 +int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex)
7066 + struct mtx *m = (struct mtx *)mutex;
7068 + return mtx_trylock(m);
7071 +void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex)
7073 + struct mtx *m = (struct mtx *)mutex;
7081 +void DWC_UDELAY(uint32_t usecs)
7086 +void DWC_MDELAY(uint32_t msecs)
7090 + } while (--msecs);
7093 +void DWC_MSLEEP(uint32_t msecs)
7095 + struct timeval tv;
7097 + tv.tv_sec = msecs / 1000;
7098 + tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
7099 + pause("dw3slp", tvtohz(&tv));
7102 +uint32_t DWC_TIME(void)
7104 + struct timeval tv;
7106 + microuptime(&tv); // or getmicrouptime? (less precise, but faster)
7107 + return tv.tv_sec * 1000 + tv.tv_usec / 1000;
7116 + dwc_spinlock_t *lock;
7117 + dwc_timer_callback_t cb;
7121 +dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data)
7123 + dwc_timer_t *t = DWC_ALLOC(sizeof(*t));
7126 + DWC_ERROR("Cannot allocate memory for timer");
7130 + callout_init(&t->t, 1);
7132 + t->name = DWC_STRDUP(name);
7134 + DWC_ERROR("Cannot allocate memory for timer->name");
7138 + t->lock = DWC_SPINLOCK_ALLOC();
7140 + DWC_ERROR("Cannot allocate memory for lock");
7150 + DWC_FREE(t->name);
7157 +void DWC_TIMER_FREE(dwc_timer_t *timer)
7159 + callout_stop(&timer->t);
7160 + DWC_SPINLOCK_FREE(timer->lock);
7161 + DWC_FREE(timer->name);
7165 +void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time)
7167 + struct timeval tv;
7169 + tv.tv_sec = time / 1000;
7170 + tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
7171 + callout_reset(&timer->t, tvtohz(&tv), timer->cb, timer->data);
7174 +void DWC_TIMER_CANCEL(dwc_timer_t *timer)
7176 + callout_stop(&timer->t);
7187 +dwc_waitq_t *DWC_WAITQ_ALLOC(void)
7189 + dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq));
7192 + DWC_ERROR("Cannot allocate memory for waitqueue");
7196 + mtx_init(&wq->lock, "dw3wtq", NULL, MTX_DEF);
7202 +void DWC_WAITQ_FREE(dwc_waitq_t *wq)
7204 + mtx_destroy(&wq->lock);
7208 +int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data)
7213 + mtx_lock(&wq->lock);
7216 + /* Skip the sleep if already aborted or triggered */
7217 + if (!wq->abort && !cond(data)) {
7219 + result = msleep(wq, &wq->lock, PCATCH, "dw3wat", 0); // infinite timeout
7223 + if (result == ERESTART) { // signaled - restart
7224 + result = -DWC_E_RESTART;
7226 + } else if (result == EINTR) { // signaled - interrupt
7227 + result = -DWC_E_ABORT;
7229 + } else if (wq->abort) {
7230 + result = -DWC_E_ABORT;
7238 + mtx_unlock(&wq->lock);
7242 +int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
7243 + void *data, int32_t msecs)
7245 + struct timeval tv, tv1, tv2;
7249 + tv.tv_sec = msecs / 1000;
7250 + tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
7252 + mtx_lock(&wq->lock);
7255 + /* Skip the sleep if already aborted or triggered */
7256 + if (!wq->abort && !cond(data)) {
7258 + getmicrouptime(&tv1);
7259 + result = msleep(wq, &wq->lock, PCATCH, "dw3wto", tvtohz(&tv));
7260 + getmicrouptime(&tv2);
7264 + if (result == 0) { // awoken
7266 + result = -DWC_E_ABORT;
7268 + tv2.tv_usec -= tv1.tv_usec;
7269 + if (tv2.tv_usec < 0) {
7270 + tv2.tv_usec += 1000000;
7274 + tv2.tv_sec -= tv1.tv_sec;
7275 + result = tv2.tv_sec * 1000 + tv2.tv_usec / 1000;
7276 + result = msecs - result;
7280 + } else if (result == ERESTART) { // signaled - restart
7281 + result = -DWC_E_RESTART;
7283 + } else if (result == EINTR) { // signaled - interrupt
7284 + result = -DWC_E_ABORT;
7286 + } else { // timed out
7287 + result = -DWC_E_TIMEOUT;
7292 + mtx_unlock(&wq->lock);
7296 +void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq)
7301 +void DWC_WAITQ_ABORT(dwc_waitq_t *wq)
7305 + mtx_lock(&wq->lock);
7310 + mtx_unlock(&wq->lock);
7316 +struct dwc_thread {
7317 + struct proc *proc;
7321 +dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data)
7324 + dwc_thread_t *thread = DWC_ALLOC(sizeof(*thread));
7330 + thread->abort = 0;
7331 + retval = kthread_create((void (*)(void *))func, data, &thread->proc,
7332 + RFPROC | RFNOWAIT, 0, "%s", name);
7341 +int DWC_THREAD_STOP(dwc_thread_t *thread)
7345 + thread->abort = 1;
7346 + retval = tsleep(&thread->abort, 0, "dw3stp", 60 * hz);
7348 + if (retval == 0) {
7349 + /* DWC_THREAD_EXIT() will free the thread struct */
7353 + /* NOTE: We leak the thread struct if thread doesn't die */
7355 + if (retval == EWOULDBLOCK) {
7356 + return -DWC_E_TIMEOUT;
7359 + return -DWC_E_UNKNOWN;
7362 +dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread)
7364 + return thread->abort;
7367 +void DWC_THREAD_EXIT(dwc_thread_t *thread)
7369 + wakeup(&thread->abort);
7376 + - Runs in interrupt context (cannot sleep)
7377 + - Each tasklet runs on a single CPU [ How can we ensure this on FreeBSD? Does it matter? ]
7378 + - Different tasklets can be running simultaneously on different CPUs [ shouldn't matter ]
7380 +struct dwc_tasklet {
7382 + dwc_tasklet_callback_t cb;
7386 +static void tasklet_callback(void *data, int pending) // what to do with pending ???
7388 + dwc_tasklet_t *task = (dwc_tasklet_t *)data;
7390 + task->cb(task->data);
7393 +dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data)
7395 + dwc_tasklet_t *task = DWC_ALLOC(sizeof(*task));
7399 + task->data = data;
7400 + TASK_INIT(&task->t, 0, tasklet_callback, task);
7402 + DWC_ERROR("Cannot allocate memory for tasklet");
7408 +void DWC_TASK_FREE(dwc_tasklet_t *task)
7410 + taskqueue_drain(taskqueue_fast, &task->t); // ???
7414 +void DWC_TASK_SCHEDULE(dwc_tasklet_t *task)
7416 + /* Uses predefined system queue */
7417 + taskqueue_enqueue_fast(taskqueue_fast, &task->t);
7422 + - Runs in process context (can sleep)
7424 +typedef struct work_container {
7425 + dwc_work_callback_t cb;
7432 + DWC_CIRCLEQ_ENTRY(work_container) entry;
7435 +} work_container_t;
7438 +DWC_CIRCLEQ_HEAD(work_container_queue, work_container);
7442 + struct taskqueue *taskq;
7443 + dwc_spinlock_t *lock;
7444 + dwc_waitq_t *waitq;
7448 + struct work_container_queue entries;
7452 +static void do_work(void *data, int pending) // what to do with pending ???
7454 + work_container_t *container = (work_container_t *)data;
7455 + dwc_workq_t *wq = container->wq;
7456 + dwc_irqflags_t flags;
7458 + if (container->hz) {
7459 + pause("dw3wrk", container->hz);
7462 + container->cb(container->data);
7463 + DWC_DEBUG("Work done: %s, container=%p", container->name, container);
7465 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
7468 + DWC_CIRCLEQ_REMOVE(&wq->entries, container, entry);
7470 + if (container->name)
7471 + DWC_FREE(container->name);
7472 + DWC_FREE(container);
7474 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
7475 + DWC_WAITQ_TRIGGER(wq->waitq);
7478 +static int work_done(void *data)
7480 + dwc_workq_t *workq = (dwc_workq_t *)data;
7482 + return workq->pending == 0;
7485 +int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout)
7487 + return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout);
7490 +dwc_workq_t *DWC_WORKQ_ALLOC(char *name)
7492 + dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq));
7495 + DWC_ERROR("Cannot allocate memory for workqueue");
7499 + wq->taskq = taskqueue_create(name, M_NOWAIT, taskqueue_thread_enqueue, &wq->taskq);
7501 + DWC_ERROR("Cannot allocate memory for taskqueue");
7507 + wq->lock = DWC_SPINLOCK_ALLOC();
7509 + DWC_ERROR("Cannot allocate memory for spinlock");
7513 + wq->waitq = DWC_WAITQ_ALLOC();
7515 + DWC_ERROR("Cannot allocate memory for waitqueue");
7519 + taskqueue_start_threads(&wq->taskq, 1, PWAIT, "%s taskq", "dw3tsk");
7522 + DWC_CIRCLEQ_INIT(&wq->entries);
7527 + DWC_SPINLOCK_FREE(wq->lock);
7529 + taskqueue_free(wq->taskq);
7536 +void DWC_WORKQ_FREE(dwc_workq_t *wq)
7539 + dwc_irqflags_t flags;
7541 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
7543 + if (wq->pending != 0) {
7544 + struct work_container *container;
7546 + DWC_ERROR("Destroying work queue with pending work");
7548 + DWC_CIRCLEQ_FOREACH(container, &wq->entries, entry) {
7549 + DWC_ERROR("Work %s still pending", container->name);
7553 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
7555 + DWC_WAITQ_FREE(wq->waitq);
7556 + DWC_SPINLOCK_FREE(wq->lock);
7557 + taskqueue_free(wq->taskq);
7561 +void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data,
7562 + char *format, ...)
7564 + dwc_irqflags_t flags;
7565 + work_container_t *container;
7566 + static char name[128];
7569 + va_start(args, format);
7570 + DWC_VSNPRINTF(name, 128, format, args);
7573 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
7575 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
7576 + DWC_WAITQ_TRIGGER(wq->waitq);
7578 + container = DWC_ALLOC_ATOMIC(sizeof(*container));
7580 + DWC_ERROR("Cannot allocate memory for container");
7584 + container->name = DWC_STRDUP(name);
7585 + if (!container->name) {
7586 + DWC_ERROR("Cannot allocate memory for container->name");
7587 + DWC_FREE(container);
7591 + container->cb = cb;
7592 + container->data = data;
7593 + container->wq = wq;
7594 + container->hz = 0;
7596 + DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
7598 + TASK_INIT(&container->task, 0, do_work, container);
7601 + DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
7603 + taskqueue_enqueue_fast(wq->taskq, &container->task);
7606 +void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb,
7607 + void *data, uint32_t time, char *format, ...)
7609 + dwc_irqflags_t flags;
7610 + work_container_t *container;
7611 + static char name[128];
7612 + struct timeval tv;
7615 + va_start(args, format);
7616 + DWC_VSNPRINTF(name, 128, format, args);
7619 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
7621 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
7622 + DWC_WAITQ_TRIGGER(wq->waitq);
7624 + container = DWC_ALLOC_ATOMIC(sizeof(*container));
7626 + DWC_ERROR("Cannot allocate memory for container");
7630 + container->name = DWC_STRDUP(name);
7631 + if (!container->name) {
7632 + DWC_ERROR("Cannot allocate memory for container->name");
7633 + DWC_FREE(container);
7637 + container->cb = cb;
7638 + container->data = data;
7639 + container->wq = wq;
7641 + tv.tv_sec = time / 1000;
7642 + tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
7643 + container->hz = tvtohz(&tv);
7645 + DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
7647 + TASK_INIT(&container->task, 0, do_work, container);
7650 + DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
7652 + taskqueue_enqueue_fast(wq->taskq, &container->task);
7655 +int DWC_WORKQ_PENDING(dwc_workq_t *wq)
7657 + return wq->pending;
7660 +++ b/drivers/usb/host/dwc_common_port/dwc_common_linux.c
7662 +#include <linux/kernel.h>
7663 +#include <linux/init.h>
7664 +#include <linux/module.h>
7665 +#include <linux/kthread.h>
7668 +# include "dwc_cc.h"
7671 +#ifdef DWC_CRYPTOLIB
7672 +# include "dwc_modpow.h"
7673 +# include "dwc_dh.h"
7674 +# include "dwc_crypto.h"
7677 +#ifdef DWC_NOTIFYLIB
7678 +# include "dwc_notifier.h"
7681 +/* OS-Level Implementations */
7683 +/* This is the Linux kernel implementation of the DWC platform library. */
7684 +#include <linux/moduleparam.h>
7685 +#include <linux/ctype.h>
7686 +#include <linux/crypto.h>
7687 +#include <linux/delay.h>
7688 +#include <linux/device.h>
7689 +#include <linux/dma-mapping.h>
7690 +#include <linux/cdev.h>
7691 +#include <linux/errno.h>
7692 +#include <linux/interrupt.h>
7693 +#include <linux/jiffies.h>
7694 +#include <linux/list.h>
7695 +#include <linux/pci.h>
7696 +#include <linux/random.h>
7697 +#include <linux/scatterlist.h>
7698 +#include <linux/slab.h>
7699 +#include <linux/stat.h>
7700 +#include <linux/string.h>
7701 +#include <linux/timer.h>
7702 +#include <linux/usb.h>
7704 +#include <linux/version.h>
7706 +# include <linux/usb/gadget.h>
7708 +#include <asm/io.h>
7709 +#include <asm/page.h>
7710 +#include <asm/uaccess.h>
7711 +#include <asm/unaligned.h>
7713 +#include "dwc_os.h"
7714 +#include "dwc_list.h"
7719 +void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size)
7721 + return memset(dest, byte, size);
7724 +void *DWC_MEMCPY(void *dest, void const *src, uint32_t size)
7726 + return memcpy(dest, src, size);
7729 +void *DWC_MEMMOVE(void *dest, void *src, uint32_t size)
7731 + return memmove(dest, src, size);
7734 +int DWC_MEMCMP(void *m1, void *m2, uint32_t size)
7736 + return memcmp(m1, m2, size);
7739 +int DWC_STRNCMP(void *s1, void *s2, uint32_t size)
7741 + return strncmp(s1, s2, size);
7744 +int DWC_STRCMP(void *s1, void *s2)
7746 + return strcmp(s1, s2);
7749 +int DWC_STRLEN(char const *str)
7751 + return strlen(str);
7754 +char *DWC_STRCPY(char *to, char const *from)
7756 + return strcpy(to, from);
7759 +char *DWC_STRDUP(char const *str)
7761 + int len = DWC_STRLEN(str) + 1;
7762 + char *new = DWC_ALLOC_ATOMIC(len);
7768 + DWC_MEMCPY(new, str, len);
7772 +int DWC_ATOI(const char *str, int32_t *value)
7776 + *value = simple_strtol(str, &end, 0);
7777 + if (*end == '\0') {
7784 +int DWC_ATOUI(const char *str, uint32_t *value)
7788 + *value = simple_strtoul(str, &end, 0);
7789 + if (*end == '\0') {
7798 +/* From usbstring.c */
7800 +int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len)
7806 + /* this insists on correct encodings, though not minimal ones.
7807 + * BUT it currently rejects legit 4-byte UTF-8 code points,
7808 + * which need surrogate pairs. (Unicode 3.1 can use them.)
7810 + while (len != 0 && (c = (u8) *s++) != 0) {
7811 + if (unlikely(c & 0x80)) {
7812 + // 2-byte sequence:
7813 + // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
7814 + if ((c & 0xe0) == 0xc0) {
7815 + uchar = (c & 0x1f) << 6;
7818 + if ((c & 0xc0) != 0xc0)
7823 + // 3-byte sequence (most CJKV characters):
7824 + // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
7825 + } else if ((c & 0xf0) == 0xe0) {
7826 + uchar = (c & 0x0f) << 12;
7829 + if ((c & 0xc0) != 0xc0)
7835 + if ((c & 0xc0) != 0xc0)
7840 + /* no bogus surrogates */
7841 + if (0xd800 <= uchar && uchar <= 0xdfff)
7844 + // 4-byte sequence (surrogate pairs, currently rare):
7845 + // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
7846 + // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
7847 + // (uuuuu = wwww + 1)
7848 + // FIXME accept the surrogate code points (only)
7853 + put_unaligned (cpu_to_le16 (uchar), cp++);
7861 +#endif /* DWC_UTFLIB */
7866 +dwc_bool_t DWC_IN_IRQ(void)
7871 +dwc_bool_t DWC_IN_BH(void)
7873 + return in_softirq();
7876 +void DWC_VPRINTF(char *format, va_list args)
7878 + vprintk(format, args);
7881 +int DWC_VSNPRINTF(char *str, int size, char *format, va_list args)
7883 + return vsnprintf(str, size, format, args);
7886 +void DWC_PRINTF(char *format, ...)
7890 + va_start(args, format);
7891 + DWC_VPRINTF(format, args);
7895 +int DWC_SPRINTF(char *buffer, char *format, ...)
7900 + va_start(args, format);
7901 + retval = vsprintf(buffer, format, args);
7906 +int DWC_SNPRINTF(char *buffer, int size, char *format, ...)
7911 + va_start(args, format);
7912 + retval = vsnprintf(buffer, size, format, args);
7917 +void __DWC_WARN(char *format, ...)
7921 + va_start(args, format);
7922 + DWC_PRINTF(KERN_WARNING);
7923 + DWC_VPRINTF(format, args);
7927 +void __DWC_ERROR(char *format, ...)
7931 + va_start(args, format);
7932 + DWC_PRINTF(KERN_ERR);
7933 + DWC_VPRINTF(format, args);
7937 +void DWC_EXCEPTION(char *format, ...)
7941 + va_start(args, format);
7942 + DWC_PRINTF(KERN_ERR);
7943 + DWC_VPRINTF(format, args);
7949 +void __DWC_DEBUG(char *format, ...)
7953 + va_start(args, format);
7954 + DWC_PRINTF(KERN_DEBUG);
7955 + DWC_VPRINTF(format, args);
7964 +dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size,
7968 + struct dma_pool *pool = dma_pool_create("Pool", NULL,
7969 + size, align, alloc);
7970 + return (dwc_pool_t *)pool;
7973 +void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool)
7975 + dma_pool_destroy((struct dma_pool *)pool);
7978 +void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
7980 + return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr);
7983 +void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
7985 + void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr);
7989 +void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr)
7991 + dma_pool_free(pool, vaddr, daddr);
7995 +void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
7997 + return dma_alloc_coherent(dma_ctx, size, dma_addr, GFP_KERNEL | GFP_DMA32);
8000 +void *__DWC_DMA_ALLOC_ATOMIC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
8002 + return dma_alloc_coherent(dma_ctx, size, dma_addr, GFP_ATOMIC);
8005 +void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr)
8007 + dma_free_coherent(dma_ctx, size, virt_addr, dma_addr);
8010 +void *__DWC_ALLOC(void *mem_ctx, uint32_t size)
8012 + return kzalloc(size, GFP_KERNEL);
8015 +void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size)
8017 + return kzalloc(size, GFP_ATOMIC);
8020 +void __DWC_FREE(void *mem_ctx, void *addr)
8026 +#ifdef DWC_CRYPTOLIB
8029 +void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length)
8031 + get_random_bytes(buffer, length);
8034 +int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)
8036 + struct crypto_blkcipher *tfm;
8037 + struct blkcipher_desc desc;
8038 + struct scatterlist sgd;
8039 + struct scatterlist sgs;
8041 + tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC);
8042 + if (tfm == NULL) {
8043 + printk("failed to load transform for aes CBC\n");
8047 + crypto_blkcipher_setkey(tfm, key, keylen);
8048 + crypto_blkcipher_set_iv(tfm, iv, 16);
8050 + sg_init_one(&sgd, out, messagelen);
8051 + sg_init_one(&sgs, message, messagelen);
8056 + if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) {
8057 + crypto_free_blkcipher(tfm);
8058 + DWC_ERROR("AES CBC encryption failed");
8062 + crypto_free_blkcipher(tfm);
8066 +int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out)
8068 + struct crypto_hash *tfm;
8069 + struct hash_desc desc;
8070 + struct scatterlist sg;
8072 + tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC);
8073 + if (IS_ERR(tfm)) {
8074 + DWC_ERROR("Failed to load transform for sha256: %ld\n", PTR_ERR(tfm));
8080 + sg_init_one(&sg, message, len);
8081 + crypto_hash_digest(&desc, &sg, len, out);
8082 + crypto_free_hash(tfm);
8087 +int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen,
8088 + uint8_t *key, uint32_t keylen, uint8_t *out)
8090 + struct crypto_hash *tfm;
8091 + struct hash_desc desc;
8092 + struct scatterlist sg;
8094 + tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC);
8095 + if (IS_ERR(tfm)) {
8096 + DWC_ERROR("Failed to load transform for hmac(sha256): %ld\n", PTR_ERR(tfm));
8102 + sg_init_one(&sg, message, messagelen);
8103 + crypto_hash_setkey(tfm, key, keylen);
8104 + crypto_hash_digest(&desc, &sg, messagelen, out);
8105 + crypto_free_hash(tfm);
8109 +#endif /* DWC_CRYPTOLIB */
8112 +/* Byte Ordering Conversions */
8114 +uint32_t DWC_CPU_TO_LE32(uint32_t *p)
8116 +#ifdef __LITTLE_ENDIAN
8119 + uint8_t *u_p = (uint8_t *)p;
8121 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
8125 +uint32_t DWC_CPU_TO_BE32(uint32_t *p)
8127 +#ifdef __BIG_ENDIAN
8130 + uint8_t *u_p = (uint8_t *)p;
8132 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
8136 +uint32_t DWC_LE32_TO_CPU(uint32_t *p)
8138 +#ifdef __LITTLE_ENDIAN
8141 + uint8_t *u_p = (uint8_t *)p;
8143 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
8147 +uint32_t DWC_BE32_TO_CPU(uint32_t *p)
8149 +#ifdef __BIG_ENDIAN
8152 + uint8_t *u_p = (uint8_t *)p;
8154 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
8158 +uint16_t DWC_CPU_TO_LE16(uint16_t *p)
8160 +#ifdef __LITTLE_ENDIAN
8163 + uint8_t *u_p = (uint8_t *)p;
8164 + return (u_p[1] | (u_p[0] << 8));
8168 +uint16_t DWC_CPU_TO_BE16(uint16_t *p)
8170 +#ifdef __BIG_ENDIAN
8173 + uint8_t *u_p = (uint8_t *)p;
8174 + return (u_p[1] | (u_p[0] << 8));
8178 +uint16_t DWC_LE16_TO_CPU(uint16_t *p)
8180 +#ifdef __LITTLE_ENDIAN
8183 + uint8_t *u_p = (uint8_t *)p;
8184 + return (u_p[1] | (u_p[0] << 8));
8188 +uint16_t DWC_BE16_TO_CPU(uint16_t *p)
8190 +#ifdef __BIG_ENDIAN
8193 + uint8_t *u_p = (uint8_t *)p;
8194 + return (u_p[1] | (u_p[0] << 8));
8201 +uint32_t DWC_READ_REG32(uint32_t volatile *reg)
8203 + return readl(reg);
8207 +uint64_t DWC_READ_REG64(uint64_t volatile *reg)
8212 +void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value)
8214 + writel(value, reg);
8218 +void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value)
8223 +void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask)
8225 + writel((readl(reg) & ~clear_mask) | set_mask, reg);
8229 +void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask)
8237 +dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void)
8239 + spinlock_t *sl = (spinlock_t *)1;
8241 +#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
8242 + sl = DWC_ALLOC(sizeof(*sl));
8244 + DWC_ERROR("Cannot allocate memory for spinlock\n");
8248 + spin_lock_init(sl);
8250 + return (dwc_spinlock_t *)sl;
8253 +void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock)
8255 +#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
8260 +void DWC_SPINLOCK(dwc_spinlock_t *lock)
8262 +#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
8263 + spin_lock((spinlock_t *)lock);
8267 +void DWC_SPINUNLOCK(dwc_spinlock_t *lock)
8269 +#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
8270 + spin_unlock((spinlock_t *)lock);
8274 +void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags)
8278 +#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
8279 + spin_lock_irqsave((spinlock_t *)lock, f);
8281 + local_irq_save(f);
8286 +void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags)
8288 +#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
8289 + spin_unlock_irqrestore((spinlock_t *)lock, flags);
8291 + local_irq_restore(flags);
8295 +dwc_mutex_t *DWC_MUTEX_ALLOC(void)
8298 + dwc_mutex_t *mutex = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex));
8301 + DWC_ERROR("Cannot allocate memory for mutex\n");
8305 + m = (struct mutex *)mutex;
8310 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
8312 +void DWC_MUTEX_FREE(dwc_mutex_t *mutex)
8314 + mutex_destroy((struct mutex *)mutex);
8319 +void DWC_MUTEX_LOCK(dwc_mutex_t *mutex)
8321 + struct mutex *m = (struct mutex *)mutex;
8325 +int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex)
8327 + struct mutex *m = (struct mutex *)mutex;
8328 + return mutex_trylock(m);
8331 +void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex)
8333 + struct mutex *m = (struct mutex *)mutex;
8340 +void DWC_UDELAY(uint32_t usecs)
8345 +void DWC_MDELAY(uint32_t msecs)
8350 +void DWC_MSLEEP(uint32_t msecs)
8355 +uint32_t DWC_TIME(void)
8357 + return jiffies_to_msecs(jiffies);
8364 + struct timer_list t;
8366 + dwc_timer_callback_t cb;
8368 + uint8_t scheduled;
8369 + dwc_spinlock_t *lock;
8372 +static void timer_callback(struct timer_list *tt)
8374 + dwc_timer_t *timer = from_timer(timer, tt, t);
8375 + dwc_irqflags_t flags;
8377 + DWC_SPINLOCK_IRQSAVE(timer->lock, &flags);
8378 + timer->scheduled = 0;
8379 + DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags);
8380 + DWC_DEBUGC("Timer %s callback", timer->name);
8381 + timer->cb(timer->data);
8384 +dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data)
8386 + dwc_timer_t *t = DWC_ALLOC(sizeof(*t));
8389 + DWC_ERROR("Cannot allocate memory for timer");
8393 + t->name = DWC_STRDUP(name);
8395 + DWC_ERROR("Cannot allocate memory for timer->name");
8399 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK))
8400 + DWC_SPINLOCK_ALLOC_LINUX_DEBUG(t->lock);
8402 + t->lock = DWC_SPINLOCK_ALLOC();
8405 + DWC_ERROR("Cannot allocate memory for lock");
8410 + t->t.expires = jiffies;
8411 + timer_setup(&t->t, timer_callback, 0);
8419 + DWC_FREE(t->name);
8425 +void DWC_TIMER_FREE(dwc_timer_t *timer)
8427 + dwc_irqflags_t flags;
8429 + DWC_SPINLOCK_IRQSAVE(timer->lock, &flags);
8431 + if (timer->scheduled) {
8432 + del_timer(&timer->t);
8433 + timer->scheduled = 0;
8436 + DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags);
8437 + DWC_SPINLOCK_FREE(timer->lock);
8438 + DWC_FREE(timer->name);
8442 +void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time)
8444 + dwc_irqflags_t flags;
8446 + DWC_SPINLOCK_IRQSAVE(timer->lock, &flags);
8448 + if (!timer->scheduled) {
8449 + timer->scheduled = 1;
8450 + DWC_DEBUGC("Scheduling timer %s to expire in +%d msec", timer->name, time);
8451 + timer->t.expires = jiffies + msecs_to_jiffies(time);
8452 + add_timer(&timer->t);
8454 + DWC_DEBUGC("Modifying timer %s to expire in +%d msec", timer->name, time);
8455 + mod_timer(&timer->t, jiffies + msecs_to_jiffies(time));
8458 + DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags);
8461 +void DWC_TIMER_CANCEL(dwc_timer_t *timer)
8463 + del_timer(&timer->t);
8470 + wait_queue_head_t queue;
8474 +dwc_waitq_t *DWC_WAITQ_ALLOC(void)
8476 + dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq));
8479 + DWC_ERROR("Cannot allocate memory for waitqueue\n");
8483 + init_waitqueue_head(&wq->queue);
8488 +void DWC_WAITQ_FREE(dwc_waitq_t *wq)
8493 +int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data)
8495 + int result = wait_event_interruptible(wq->queue,
8496 + cond(data) || wq->abort);
8497 + if (result == -ERESTARTSYS) {
8499 + return -DWC_E_RESTART;
8502 + if (wq->abort == 1) {
8504 + return -DWC_E_ABORT;
8509 + if (result == 0) {
8513 + return -DWC_E_UNKNOWN;
8516 +int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
8517 + void *data, int32_t msecs)
8520 + int result = wait_event_interruptible_timeout(wq->queue,
8521 + cond(data) || wq->abort,
8522 + msecs_to_jiffies(msecs));
8523 + if (result == -ERESTARTSYS) {
8525 + return -DWC_E_RESTART;
8528 + if (wq->abort == 1) {
8530 + return -DWC_E_ABORT;
8536 + tmsecs = jiffies_to_msecs(result);
8544 + if (result == 0) {
8545 + return -DWC_E_TIMEOUT;
8548 + return -DWC_E_UNKNOWN;
8551 +void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq)
8554 + wake_up_interruptible(&wq->queue);
8557 +void DWC_WAITQ_ABORT(dwc_waitq_t *wq)
8560 + wake_up_interruptible(&wq->queue);
8566 +dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data)
8568 + struct task_struct *thread = kthread_run(func, data, name);
8570 + if (thread == ERR_PTR(-ENOMEM)) {
8574 + return (dwc_thread_t *)thread;
8577 +int DWC_THREAD_STOP(dwc_thread_t *thread)
8579 + return kthread_stop((struct task_struct *)thread);
8582 +dwc_bool_t DWC_THREAD_SHOULD_STOP(void)
8584 + return kthread_should_stop();
8589 + - run in interrupt context (cannot sleep)
8590 + - each tasklet runs on a single CPU
8591 + - different tasklets can be running simultaneously on different CPUs
8593 +struct dwc_tasklet {
8594 + struct tasklet_struct t;
8595 + dwc_tasklet_callback_t cb;
8599 +static void tasklet_callback(unsigned long data)
8601 + dwc_tasklet_t *t = (dwc_tasklet_t *)data;
8605 +dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data)
8607 + dwc_tasklet_t *t = DWC_ALLOC(sizeof(*t));
8612 + tasklet_init(&t->t, tasklet_callback, (unsigned long)t);
8614 + DWC_ERROR("Cannot allocate memory for tasklet\n");
8620 +void DWC_TASK_FREE(dwc_tasklet_t *task)
8625 +void DWC_TASK_SCHEDULE(dwc_tasklet_t *task)
8627 + tasklet_schedule(&task->t);
8630 +void DWC_TASK_HI_SCHEDULE(dwc_tasklet_t *task)
8632 + tasklet_hi_schedule(&task->t);
8637 + - run in process context (can sleep)
8639 +typedef struct work_container {
8640 + dwc_work_callback_t cb;
8646 + DWC_CIRCLEQ_ENTRY(work_container) entry;
8648 + struct delayed_work work;
8649 +} work_container_t;
8652 +DWC_CIRCLEQ_HEAD(work_container_queue, work_container);
8656 + struct workqueue_struct *wq;
8657 + dwc_spinlock_t *lock;
8658 + dwc_waitq_t *waitq;
8662 + struct work_container_queue entries;
8666 +static void do_work(struct work_struct *work)
8668 + dwc_irqflags_t flags;
8669 + struct delayed_work *dw = container_of(work, struct delayed_work, work);
8670 + work_container_t *container = container_of(dw, struct work_container, work);
8671 + dwc_workq_t *wq = container->wq;
8673 + container->cb(container->data);
8676 + DWC_CIRCLEQ_REMOVE(&wq->entries, container, entry);
8678 + DWC_DEBUGC("Work done: %s, container=%p", container->name, container);
8679 + if (container->name) {
8680 + DWC_FREE(container->name);
8682 + DWC_FREE(container);
8684 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
8686 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
8687 + DWC_WAITQ_TRIGGER(wq->waitq);
8690 +static int work_done(void *data)
8692 + dwc_workq_t *workq = (dwc_workq_t *)data;
8693 + return workq->pending == 0;
8696 +int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout)
8698 + return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout);
8701 +dwc_workq_t *DWC_WORKQ_ALLOC(char *name)
8703 + dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq));
8709 + wq->wq = create_singlethread_workqueue(name);
8716 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK))
8717 + DWC_SPINLOCK_ALLOC_LINUX_DEBUG(wq->lock);
8719 + wq->lock = DWC_SPINLOCK_ALLOC();
8725 + wq->waitq = DWC_WAITQ_ALLOC();
8731 + DWC_CIRCLEQ_INIT(&wq->entries);
8736 + DWC_SPINLOCK_FREE(wq->lock);
8738 + destroy_workqueue(wq->wq);
8745 +void DWC_WORKQ_FREE(dwc_workq_t *wq)
8748 + if (wq->pending != 0) {
8749 + struct work_container *wc;
8750 + DWC_ERROR("Destroying work queue with pending work");
8751 + DWC_CIRCLEQ_FOREACH(wc, &wq->entries, entry) {
8752 + DWC_ERROR("Work %s still pending", wc->name);
8756 + destroy_workqueue(wq->wq);
8757 + DWC_SPINLOCK_FREE(wq->lock);
8758 + DWC_WAITQ_FREE(wq->waitq);
8762 +void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data,
8763 + char *format, ...)
8765 + dwc_irqflags_t flags;
8766 + work_container_t *container;
8767 + static char name[128];
8770 + va_start(args, format);
8771 + DWC_VSNPRINTF(name, 128, format, args);
8774 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
8776 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
8777 + DWC_WAITQ_TRIGGER(wq->waitq);
8779 + container = DWC_ALLOC_ATOMIC(sizeof(*container));
8781 + DWC_ERROR("Cannot allocate memory for container\n");
8785 + container->name = DWC_STRDUP(name);
8786 + if (!container->name) {
8787 + DWC_ERROR("Cannot allocate memory for container->name\n");
8788 + DWC_FREE(container);
8792 + container->cb = cb;
8793 + container->data = data;
8794 + container->wq = wq;
8795 + DWC_DEBUGC("Queueing work: %s, container=%p", container->name, container);
8796 + INIT_WORK(&container->work.work, do_work);
8799 + DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
8801 + queue_work(wq->wq, &container->work.work);
8804 +void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb,
8805 + void *data, uint32_t time, char *format, ...)
8807 + dwc_irqflags_t flags;
8808 + work_container_t *container;
8809 + static char name[128];
8812 + va_start(args, format);
8813 + DWC_VSNPRINTF(name, 128, format, args);
8816 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
8818 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
8819 + DWC_WAITQ_TRIGGER(wq->waitq);
8821 + container = DWC_ALLOC_ATOMIC(sizeof(*container));
8823 + DWC_ERROR("Cannot allocate memory for container\n");
8827 + container->name = DWC_STRDUP(name);
8828 + if (!container->name) {
8829 + DWC_ERROR("Cannot allocate memory for container->name\n");
8830 + DWC_FREE(container);
8834 + container->cb = cb;
8835 + container->data = data;
8836 + container->wq = wq;
8837 + DWC_DEBUGC("Queueing work: %s, container=%p", container->name, container);
8838 + INIT_DELAYED_WORK(&container->work, do_work);
8841 + DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
8843 + queue_delayed_work(wq->wq, &container->work, msecs_to_jiffies(time));
8846 +int DWC_WORKQ_PENDING(dwc_workq_t *wq)
8848 + return wq->pending;
8852 +#ifdef DWC_LIBMODULE
8856 +EXPORT_SYMBOL(dwc_cc_if_alloc);
8857 +EXPORT_SYMBOL(dwc_cc_if_free);
8858 +EXPORT_SYMBOL(dwc_cc_clear);
8859 +EXPORT_SYMBOL(dwc_cc_add);
8860 +EXPORT_SYMBOL(dwc_cc_remove);
8861 +EXPORT_SYMBOL(dwc_cc_change);
8862 +EXPORT_SYMBOL(dwc_cc_data_for_save);
8863 +EXPORT_SYMBOL(dwc_cc_restore_from_data);
8864 +EXPORT_SYMBOL(dwc_cc_match_chid);
8865 +EXPORT_SYMBOL(dwc_cc_match_cdid);
8866 +EXPORT_SYMBOL(dwc_cc_ck);
8867 +EXPORT_SYMBOL(dwc_cc_chid);
8868 +EXPORT_SYMBOL(dwc_cc_cdid);
8869 +EXPORT_SYMBOL(dwc_cc_name);
8870 +#endif /* DWC_CCLIB */
8872 +#ifdef DWC_CRYPTOLIB
8873 +# ifndef CONFIG_MACH_IPMATE
8875 +EXPORT_SYMBOL(dwc_modpow);
8878 +EXPORT_SYMBOL(dwc_dh_modpow);
8879 +EXPORT_SYMBOL(dwc_dh_derive_keys);
8880 +EXPORT_SYMBOL(dwc_dh_pk);
8881 +# endif /* CONFIG_MACH_IPMATE */
8884 +EXPORT_SYMBOL(dwc_wusb_aes_encrypt);
8885 +EXPORT_SYMBOL(dwc_wusb_cmf);
8886 +EXPORT_SYMBOL(dwc_wusb_prf);
8887 +EXPORT_SYMBOL(dwc_wusb_fill_ccm_nonce);
8888 +EXPORT_SYMBOL(dwc_wusb_gen_nonce);
8889 +EXPORT_SYMBOL(dwc_wusb_gen_key);
8890 +EXPORT_SYMBOL(dwc_wusb_gen_mic);
8891 +#endif /* DWC_CRYPTOLIB */
8894 +#ifdef DWC_NOTIFYLIB
8895 +EXPORT_SYMBOL(dwc_alloc_notification_manager);
8896 +EXPORT_SYMBOL(dwc_free_notification_manager);
8897 +EXPORT_SYMBOL(dwc_register_notifier);
8898 +EXPORT_SYMBOL(dwc_unregister_notifier);
8899 +EXPORT_SYMBOL(dwc_add_observer);
8900 +EXPORT_SYMBOL(dwc_remove_observer);
8901 +EXPORT_SYMBOL(dwc_notify);
8904 +/* Memory Debugging Routines */
8905 +#ifdef DWC_DEBUG_MEMORY
8906 +EXPORT_SYMBOL(dwc_alloc_debug);
8907 +EXPORT_SYMBOL(dwc_alloc_atomic_debug);
8908 +EXPORT_SYMBOL(dwc_free_debug);
8909 +EXPORT_SYMBOL(dwc_dma_alloc_debug);
8910 +EXPORT_SYMBOL(dwc_dma_free_debug);
8913 +EXPORT_SYMBOL(DWC_MEMSET);
8914 +EXPORT_SYMBOL(DWC_MEMCPY);
8915 +EXPORT_SYMBOL(DWC_MEMMOVE);
8916 +EXPORT_SYMBOL(DWC_MEMCMP);
8917 +EXPORT_SYMBOL(DWC_STRNCMP);
8918 +EXPORT_SYMBOL(DWC_STRCMP);
8919 +EXPORT_SYMBOL(DWC_STRLEN);
8920 +EXPORT_SYMBOL(DWC_STRCPY);
8921 +EXPORT_SYMBOL(DWC_STRDUP);
8922 +EXPORT_SYMBOL(DWC_ATOI);
8923 +EXPORT_SYMBOL(DWC_ATOUI);
8926 +EXPORT_SYMBOL(DWC_UTF8_TO_UTF16LE);
8927 +#endif /* DWC_UTFLIB */
8929 +EXPORT_SYMBOL(DWC_IN_IRQ);
8930 +EXPORT_SYMBOL(DWC_IN_BH);
8931 +EXPORT_SYMBOL(DWC_VPRINTF);
8932 +EXPORT_SYMBOL(DWC_VSNPRINTF);
8933 +EXPORT_SYMBOL(DWC_PRINTF);
8934 +EXPORT_SYMBOL(DWC_SPRINTF);
8935 +EXPORT_SYMBOL(DWC_SNPRINTF);
8936 +EXPORT_SYMBOL(__DWC_WARN);
8937 +EXPORT_SYMBOL(__DWC_ERROR);
8938 +EXPORT_SYMBOL(DWC_EXCEPTION);
8941 +EXPORT_SYMBOL(__DWC_DEBUG);
8944 +EXPORT_SYMBOL(__DWC_DMA_ALLOC);
8945 +EXPORT_SYMBOL(__DWC_DMA_ALLOC_ATOMIC);
8946 +EXPORT_SYMBOL(__DWC_DMA_FREE);
8947 +EXPORT_SYMBOL(__DWC_ALLOC);
8948 +EXPORT_SYMBOL(__DWC_ALLOC_ATOMIC);
8949 +EXPORT_SYMBOL(__DWC_FREE);
8951 +#ifdef DWC_CRYPTOLIB
8952 +EXPORT_SYMBOL(DWC_RANDOM_BYTES);
8953 +EXPORT_SYMBOL(DWC_AES_CBC);
8954 +EXPORT_SYMBOL(DWC_SHA256);
8955 +EXPORT_SYMBOL(DWC_HMAC_SHA256);
8958 +EXPORT_SYMBOL(DWC_CPU_TO_LE32);
8959 +EXPORT_SYMBOL(DWC_CPU_TO_BE32);
8960 +EXPORT_SYMBOL(DWC_LE32_TO_CPU);
8961 +EXPORT_SYMBOL(DWC_BE32_TO_CPU);
8962 +EXPORT_SYMBOL(DWC_CPU_TO_LE16);
8963 +EXPORT_SYMBOL(DWC_CPU_TO_BE16);
8964 +EXPORT_SYMBOL(DWC_LE16_TO_CPU);
8965 +EXPORT_SYMBOL(DWC_BE16_TO_CPU);
8966 +EXPORT_SYMBOL(DWC_READ_REG32);
8967 +EXPORT_SYMBOL(DWC_WRITE_REG32);
8968 +EXPORT_SYMBOL(DWC_MODIFY_REG32);
8971 +EXPORT_SYMBOL(DWC_READ_REG64);
8972 +EXPORT_SYMBOL(DWC_WRITE_REG64);
8973 +EXPORT_SYMBOL(DWC_MODIFY_REG64);
8976 +EXPORT_SYMBOL(DWC_SPINLOCK_ALLOC);
8977 +EXPORT_SYMBOL(DWC_SPINLOCK_FREE);
8978 +EXPORT_SYMBOL(DWC_SPINLOCK);
8979 +EXPORT_SYMBOL(DWC_SPINUNLOCK);
8980 +EXPORT_SYMBOL(DWC_SPINLOCK_IRQSAVE);
8981 +EXPORT_SYMBOL(DWC_SPINUNLOCK_IRQRESTORE);
8982 +EXPORT_SYMBOL(DWC_MUTEX_ALLOC);
8984 +#if (!defined(DWC_LINUX) || !defined(CONFIG_DEBUG_MUTEXES))
8985 +EXPORT_SYMBOL(DWC_MUTEX_FREE);
8988 +EXPORT_SYMBOL(DWC_MUTEX_LOCK);
8989 +EXPORT_SYMBOL(DWC_MUTEX_TRYLOCK);
8990 +EXPORT_SYMBOL(DWC_MUTEX_UNLOCK);
8991 +EXPORT_SYMBOL(DWC_UDELAY);
8992 +EXPORT_SYMBOL(DWC_MDELAY);
8993 +EXPORT_SYMBOL(DWC_MSLEEP);
8994 +EXPORT_SYMBOL(DWC_TIME);
8995 +EXPORT_SYMBOL(DWC_TIMER_ALLOC);
8996 +EXPORT_SYMBOL(DWC_TIMER_FREE);
8997 +EXPORT_SYMBOL(DWC_TIMER_SCHEDULE);
8998 +EXPORT_SYMBOL(DWC_TIMER_CANCEL);
8999 +EXPORT_SYMBOL(DWC_WAITQ_ALLOC);
9000 +EXPORT_SYMBOL(DWC_WAITQ_FREE);
9001 +EXPORT_SYMBOL(DWC_WAITQ_WAIT);
9002 +EXPORT_SYMBOL(DWC_WAITQ_WAIT_TIMEOUT);
9003 +EXPORT_SYMBOL(DWC_WAITQ_TRIGGER);
9004 +EXPORT_SYMBOL(DWC_WAITQ_ABORT);
9005 +EXPORT_SYMBOL(DWC_THREAD_RUN);
9006 +EXPORT_SYMBOL(DWC_THREAD_STOP);
9007 +EXPORT_SYMBOL(DWC_THREAD_SHOULD_STOP);
9008 +EXPORT_SYMBOL(DWC_TASK_ALLOC);
9009 +EXPORT_SYMBOL(DWC_TASK_FREE);
9010 +EXPORT_SYMBOL(DWC_TASK_SCHEDULE);
9011 +EXPORT_SYMBOL(DWC_WORKQ_WAIT_WORK_DONE);
9012 +EXPORT_SYMBOL(DWC_WORKQ_ALLOC);
9013 +EXPORT_SYMBOL(DWC_WORKQ_FREE);
9014 +EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE);
9015 +EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE_DELAYED);
9016 +EXPORT_SYMBOL(DWC_WORKQ_PENDING);
9018 +static int dwc_common_port_init_module(void)
9022 + printk(KERN_DEBUG "Module dwc_common_port init\n" );
9024 +#ifdef DWC_DEBUG_MEMORY
9025 + result = dwc_memory_debug_start(NULL);
9028 + "dwc_memory_debug_start() failed with error %d\n",
9034 +#ifdef DWC_NOTIFYLIB
9035 + result = dwc_alloc_notification_manager(NULL, NULL);
9038 + "dwc_alloc_notification_manager() failed with error %d\n",
9046 +static void dwc_common_port_exit_module(void)
9048 + printk(KERN_DEBUG "Module dwc_common_port exit\n" );
9050 +#ifdef DWC_NOTIFYLIB
9051 + dwc_free_notification_manager();
9054 +#ifdef DWC_DEBUG_MEMORY
9055 + dwc_memory_debug_stop();
9059 +module_init(dwc_common_port_init_module);
9060 +module_exit(dwc_common_port_exit_module);
9062 +MODULE_DESCRIPTION("DWC Common Library - Portable version");
9063 +MODULE_AUTHOR("Synopsys Inc.");
9064 +MODULE_LICENSE ("GPL");
9066 +#endif /* DWC_LIBMODULE */
9068 +++ b/drivers/usb/host/dwc_common_port/dwc_common_nbsd.c
9070 +#include "dwc_os.h"
9071 +#include "dwc_list.h"
9074 +# include "dwc_cc.h"
9077 +#ifdef DWC_CRYPTOLIB
9078 +# include "dwc_modpow.h"
9079 +# include "dwc_dh.h"
9080 +# include "dwc_crypto.h"
9083 +#ifdef DWC_NOTIFYLIB
9084 +# include "dwc_notifier.h"
9087 +/* OS-Level Implementations */
9089 +/* This is the NetBSD 4.0.1 kernel implementation of the DWC platform library. */
9094 +void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size)
9096 + return memset(dest, byte, size);
9099 +void *DWC_MEMCPY(void *dest, void const *src, uint32_t size)
9101 + return memcpy(dest, src, size);
9104 +void *DWC_MEMMOVE(void *dest, void *src, uint32_t size)
9106 + bcopy(src, dest, size);
9110 +int DWC_MEMCMP(void *m1, void *m2, uint32_t size)
9112 + return memcmp(m1, m2, size);
9115 +int DWC_STRNCMP(void *s1, void *s2, uint32_t size)
9117 + return strncmp(s1, s2, size);
9120 +int DWC_STRCMP(void *s1, void *s2)
9122 + return strcmp(s1, s2);
9125 +int DWC_STRLEN(char const *str)
9127 + return strlen(str);
9130 +char *DWC_STRCPY(char *to, char const *from)
9132 + return strcpy(to, from);
9135 +char *DWC_STRDUP(char const *str)
9137 + int len = DWC_STRLEN(str) + 1;
9138 + char *new = DWC_ALLOC_ATOMIC(len);
9144 + DWC_MEMCPY(new, str, len);
9148 +int DWC_ATOI(char *str, int32_t *value)
9152 + /* NetBSD doesn't have 'strtol' in the kernel, but 'strtoul'
9153 + * should be equivalent on 2's complement machines
9155 + *value = strtoul(str, &end, 0);
9156 + if (*end == '\0') {
9163 +int DWC_ATOUI(char *str, uint32_t *value)
9167 + *value = strtoul(str, &end, 0);
9168 + if (*end == '\0') {
9177 +/* From usbstring.c */
9179 +int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len)
9185 + /* this insists on correct encodings, though not minimal ones.
9186 + * BUT it currently rejects legit 4-byte UTF-8 code points,
9187 + * which need surrogate pairs. (Unicode 3.1 can use them.)
9189 + while (len != 0 && (c = (u8) *s++) != 0) {
9190 + if (unlikely(c & 0x80)) {
9191 + // 2-byte sequence:
9192 + // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
9193 + if ((c & 0xe0) == 0xc0) {
9194 + uchar = (c & 0x1f) << 6;
9197 + if ((c & 0xc0) != 0xc0)
9202 + // 3-byte sequence (most CJKV characters):
9203 + // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
9204 + } else if ((c & 0xf0) == 0xe0) {
9205 + uchar = (c & 0x0f) << 12;
9208 + if ((c & 0xc0) != 0xc0)
9214 + if ((c & 0xc0) != 0xc0)
9219 + /* no bogus surrogates */
9220 + if (0xd800 <= uchar && uchar <= 0xdfff)
9223 + // 4-byte sequence (surrogate pairs, currently rare):
9224 + // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
9225 + // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
9226 + // (uuuuu = wwww + 1)
9227 + // FIXME accept the surrogate code points (only)
9232 + put_unaligned (cpu_to_le16 (uchar), cp++);
9241 +#endif /* DWC_UTFLIB */
9246 +dwc_bool_t DWC_IN_IRQ(void)
9248 +// return in_irq();
9252 +dwc_bool_t DWC_IN_BH(void)
9254 +// return in_softirq();
9258 +void DWC_VPRINTF(char *format, va_list args)
9260 + vprintf(format, args);
9263 +int DWC_VSNPRINTF(char *str, int size, char *format, va_list args)
9265 + return vsnprintf(str, size, format, args);
9268 +void DWC_PRINTF(char *format, ...)
9272 + va_start(args, format);
9273 + DWC_VPRINTF(format, args);
9277 +int DWC_SPRINTF(char *buffer, char *format, ...)
9282 + va_start(args, format);
9283 + retval = vsprintf(buffer, format, args);
9288 +int DWC_SNPRINTF(char *buffer, int size, char *format, ...)
9293 + va_start(args, format);
9294 + retval = vsnprintf(buffer, size, format, args);
9299 +void __DWC_WARN(char *format, ...)
9303 + va_start(args, format);
9304 + DWC_VPRINTF(format, args);
9308 +void __DWC_ERROR(char *format, ...)
9312 + va_start(args, format);
9313 + DWC_VPRINTF(format, args);
9317 +void DWC_EXCEPTION(char *format, ...)
9321 + va_start(args, format);
9322 + DWC_VPRINTF(format, args);
9328 +void __DWC_DEBUG(char *format, ...)
9332 + va_start(args, format);
9333 + DWC_VPRINTF(format, args);
9342 +dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size,
9346 + struct dma_pool *pool = dma_pool_create("Pool", NULL,
9347 + size, align, alloc);
9348 + return (dwc_pool_t *)pool;
9351 +void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool)
9353 + dma_pool_destroy((struct dma_pool *)pool);
9356 +void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
9358 +// return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr);
9359 + return dma_pool_alloc((struct dma_pool *)pool, M_WAITOK, dma_addr);
9362 +void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
9364 + void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr);
9368 +void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr)
9370 + dma_pool_free(pool, vaddr, daddr);
9374 +void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
9376 + dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
9379 + error = bus_dmamem_alloc(dma->dma_tag, size, 1, size, dma->segs,
9380 + sizeof(dma->segs) / sizeof(dma->segs[0]),
9381 + &dma->nsegs, BUS_DMA_NOWAIT);
9383 + printf("%s: bus_dmamem_alloc(%ju) failed: %d\n", __func__,
9384 + (uintmax_t)size, error);
9388 + error = bus_dmamem_map(dma->dma_tag, dma->segs, dma->nsegs, size,
9389 + (caddr_t *)&dma->dma_vaddr,
9390 + BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
9392 + printf("%s: bus_dmamem_map failed: %d\n", __func__, error);
9396 + error = bus_dmamap_create(dma->dma_tag, size, 1, size, 0,
9397 + BUS_DMA_NOWAIT, &dma->dma_map);
9399 + printf("%s: bus_dmamap_create failed: %d\n", __func__, error);
9403 + error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr,
9404 + size, NULL, BUS_DMA_NOWAIT);
9406 + printf("%s: bus_dmamap_load failed: %d\n", __func__, error);
9410 + dma->dma_paddr = (bus_addr_t)dma->segs[0].ds_addr;
9411 + *dma_addr = dma->dma_paddr;
9412 + return dma->dma_vaddr;
9415 + bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
9417 + bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size);
9419 + bus_dmamem_free(dma->dma_tag, dma->segs, dma->nsegs);
9421 + dma->dma_map = NULL;
9422 + dma->dma_vaddr = NULL;
9428 +void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr)
9430 + dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
9432 + if (dma->dma_map != NULL) {
9433 + bus_dmamap_sync(dma->dma_tag, dma->dma_map, 0, size,
9434 + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
9435 + bus_dmamap_unload(dma->dma_tag, dma->dma_map);
9436 + bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
9437 + bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size);
9438 + bus_dmamem_free(dma->dma_tag, dma->segs, dma->nsegs);
9439 + dma->dma_paddr = 0;
9440 + dma->dma_map = NULL;
9441 + dma->dma_vaddr = NULL;
9446 +void *__DWC_ALLOC(void *mem_ctx, uint32_t size)
9448 + return malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
9451 +void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size)
9453 + return malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
9456 +void __DWC_FREE(void *mem_ctx, void *addr)
9458 + free(addr, M_DEVBUF);
9462 +#ifdef DWC_CRYPTOLIB
9465 +void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length)
9467 + get_random_bytes(buffer, length);
9470 +int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)
9472 + struct crypto_blkcipher *tfm;
9473 + struct blkcipher_desc desc;
9474 + struct scatterlist sgd;
9475 + struct scatterlist sgs;
9477 + tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC);
9478 + if (tfm == NULL) {
9479 + printk("failed to load transform for aes CBC\n");
9483 + crypto_blkcipher_setkey(tfm, key, keylen);
9484 + crypto_blkcipher_set_iv(tfm, iv, 16);
9486 + sg_init_one(&sgd, out, messagelen);
9487 + sg_init_one(&sgs, message, messagelen);
9492 + if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) {
9493 + crypto_free_blkcipher(tfm);
9494 + DWC_ERROR("AES CBC encryption failed");
9498 + crypto_free_blkcipher(tfm);
9502 +int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out)
9504 + struct crypto_hash *tfm;
9505 + struct hash_desc desc;
9506 + struct scatterlist sg;
9508 + tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC);
9509 + if (IS_ERR(tfm)) {
9510 + DWC_ERROR("Failed to load transform for sha256: %ld", PTR_ERR(tfm));
9516 + sg_init_one(&sg, message, len);
9517 + crypto_hash_digest(&desc, &sg, len, out);
9518 + crypto_free_hash(tfm);
9523 +int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen,
9524 + uint8_t *key, uint32_t keylen, uint8_t *out)
9526 + struct crypto_hash *tfm;
9527 + struct hash_desc desc;
9528 + struct scatterlist sg;
9530 + tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC);
9531 + if (IS_ERR(tfm)) {
9532 + DWC_ERROR("Failed to load transform for hmac(sha256): %ld", PTR_ERR(tfm));
9538 + sg_init_one(&sg, message, messagelen);
9539 + crypto_hash_setkey(tfm, key, keylen);
9540 + crypto_hash_digest(&desc, &sg, messagelen, out);
9541 + crypto_free_hash(tfm);
9546 +#endif /* DWC_CRYPTOLIB */
9549 +/* Byte Ordering Conversions */
9551 +uint32_t DWC_CPU_TO_LE32(uint32_t *p)
9553 +#ifdef __LITTLE_ENDIAN
9556 + uint8_t *u_p = (uint8_t *)p;
9558 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
9562 +uint32_t DWC_CPU_TO_BE32(uint32_t *p)
9564 +#ifdef __BIG_ENDIAN
9567 + uint8_t *u_p = (uint8_t *)p;
9569 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
9573 +uint32_t DWC_LE32_TO_CPU(uint32_t *p)
9575 +#ifdef __LITTLE_ENDIAN
9578 + uint8_t *u_p = (uint8_t *)p;
9580 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
9584 +uint32_t DWC_BE32_TO_CPU(uint32_t *p)
9586 +#ifdef __BIG_ENDIAN
9589 + uint8_t *u_p = (uint8_t *)p;
9591 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
9595 +uint16_t DWC_CPU_TO_LE16(uint16_t *p)
9597 +#ifdef __LITTLE_ENDIAN
9600 + uint8_t *u_p = (uint8_t *)p;
9601 + return (u_p[1] | (u_p[0] << 8));
9605 +uint16_t DWC_CPU_TO_BE16(uint16_t *p)
9607 +#ifdef __BIG_ENDIAN
9610 + uint8_t *u_p = (uint8_t *)p;
9611 + return (u_p[1] | (u_p[0] << 8));
9615 +uint16_t DWC_LE16_TO_CPU(uint16_t *p)
9617 +#ifdef __LITTLE_ENDIAN
9620 + uint8_t *u_p = (uint8_t *)p;
9621 + return (u_p[1] | (u_p[0] << 8));
9625 +uint16_t DWC_BE16_TO_CPU(uint16_t *p)
9627 +#ifdef __BIG_ENDIAN
9630 + uint8_t *u_p = (uint8_t *)p;
9631 + return (u_p[1] | (u_p[0] << 8));
9638 +uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg)
9640 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
9641 + bus_size_t ior = (bus_size_t)reg;
9643 + return bus_space_read_4(io->iot, io->ioh, ior);
9647 +uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg)
9649 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
9650 + bus_size_t ior = (bus_size_t)reg;
9652 + return bus_space_read_8(io->iot, io->ioh, ior);
9656 +void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value)
9658 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
9659 + bus_size_t ior = (bus_size_t)reg;
9661 + bus_space_write_4(io->iot, io->ioh, ior, value);
9665 +void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value)
9667 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
9668 + bus_size_t ior = (bus_size_t)reg;
9670 + bus_space_write_8(io->iot, io->ioh, ior, value);
9674 +void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask,
9675 + uint32_t set_mask)
9677 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
9678 + bus_size_t ior = (bus_size_t)reg;
9680 + bus_space_write_4(io->iot, io->ioh, ior,
9681 + (bus_space_read_4(io->iot, io->ioh, ior) &
9682 + ~clear_mask) | set_mask);
9686 +void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask,
9687 + uint64_t set_mask)
9689 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
9690 + bus_size_t ior = (bus_size_t)reg;
9692 + bus_space_write_8(io->iot, io->ioh, ior,
9693 + (bus_space_read_8(io->iot, io->ioh, ior) &
9694 + ~clear_mask) | set_mask);
9701 +dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void)
9703 + struct simplelock *sl = DWC_ALLOC(sizeof(*sl));
9706 + DWC_ERROR("Cannot allocate memory for spinlock");
9710 + simple_lock_init(sl);
9711 + return (dwc_spinlock_t *)sl;
9714 +void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock)
9716 + struct simplelock *sl = (struct simplelock *)lock;
9721 +void DWC_SPINLOCK(dwc_spinlock_t *lock)
9723 + simple_lock((struct simplelock *)lock);
9726 +void DWC_SPINUNLOCK(dwc_spinlock_t *lock)
9728 + simple_unlock((struct simplelock *)lock);
9731 +void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags)
9733 + simple_lock((struct simplelock *)lock);
9734 + *flags = splbio();
9737 +void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags)
9740 + simple_unlock((struct simplelock *)lock);
9743 +dwc_mutex_t *DWC_MUTEX_ALLOC(void)
9745 + dwc_mutex_t *mutex = DWC_ALLOC(sizeof(struct lock));
9748 + DWC_ERROR("Cannot allocate memory for mutex");
9752 + lockinit((struct lock *)mutex, 0, "dw3mtx", 0, 0);
9756 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
9758 +void DWC_MUTEX_FREE(dwc_mutex_t *mutex)
9764 +void DWC_MUTEX_LOCK(dwc_mutex_t *mutex)
9766 + lockmgr((struct lock *)mutex, LK_EXCLUSIVE, NULL);
9769 +int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex)
9773 + status = lockmgr((struct lock *)mutex, LK_EXCLUSIVE | LK_NOWAIT, NULL);
9774 + return status == 0;
9777 +void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex)
9779 + lockmgr((struct lock *)mutex, LK_RELEASE, NULL);
9785 +void DWC_UDELAY(uint32_t usecs)
9790 +void DWC_MDELAY(uint32_t msecs)
9794 + } while (--msecs);
9797 +void DWC_MSLEEP(uint32_t msecs)
9799 + struct timeval tv;
9801 + tv.tv_sec = msecs / 1000;
9802 + tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
9803 + tsleep(&tv, 0, "dw3slp", tvtohz(&tv));
9806 +uint32_t DWC_TIME(void)
9808 + struct timeval tv;
9810 + microuptime(&tv); // or getmicrouptime? (less precise, but faster)
9811 + return tv.tv_sec * 1000 + tv.tv_usec / 1000;
9820 + dwc_spinlock_t *lock;
9821 + dwc_timer_callback_t cb;
9825 +dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data)
9827 + dwc_timer_t *t = DWC_ALLOC(sizeof(*t));
9830 + DWC_ERROR("Cannot allocate memory for timer");
9834 + callout_init(&t->t);
9836 + t->name = DWC_STRDUP(name);
9838 + DWC_ERROR("Cannot allocate memory for timer->name");
9842 + t->lock = DWC_SPINLOCK_ALLOC();
9844 + DWC_ERROR("Cannot allocate memory for timer->lock");
9854 + DWC_FREE(t->name);
9861 +void DWC_TIMER_FREE(dwc_timer_t *timer)
9863 + callout_stop(&timer->t);
9864 + DWC_SPINLOCK_FREE(timer->lock);
9865 + DWC_FREE(timer->name);
9869 +void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time)
9871 + struct timeval tv;
9873 + tv.tv_sec = time / 1000;
9874 + tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
9875 + callout_reset(&timer->t, tvtohz(&tv), timer->cb, timer->data);
9878 +void DWC_TIMER_CANCEL(dwc_timer_t *timer)
9880 + callout_stop(&timer->t);
9887 + struct simplelock lock;
9891 +dwc_waitq_t *DWC_WAITQ_ALLOC(void)
9893 + dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq));
9896 + DWC_ERROR("Cannot allocate memory for waitqueue");
9900 + simple_lock_init(&wq->lock);
9906 +void DWC_WAITQ_FREE(dwc_waitq_t *wq)
9911 +int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data)
9916 + simple_lock(&wq->lock);
9919 + /* Skip the sleep if already aborted or triggered */
9920 + if (!wq->abort && !cond(data)) {
9922 + result = ltsleep(wq, PCATCH, "dw3wat", 0, &wq->lock); // infinite timeout
9926 + if (result == 0) { // awoken
9929 + result = -DWC_E_ABORT;
9935 + simple_unlock(&wq->lock);
9939 + simple_unlock(&wq->lock);
9941 + if (result == ERESTART) { // signaled - restart
9942 + result = -DWC_E_RESTART;
9943 + } else { // signaled - must be EINTR
9944 + result = -DWC_E_ABORT;
9951 +int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
9952 + void *data, int32_t msecs)
9954 + struct timeval tv, tv1, tv2;
9958 + tv.tv_sec = msecs / 1000;
9959 + tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
9961 + simple_lock(&wq->lock);
9964 + /* Skip the sleep if already aborted or triggered */
9965 + if (!wq->abort && !cond(data)) {
9967 + getmicrouptime(&tv1);
9968 + result = ltsleep(wq, PCATCH, "dw3wto", tvtohz(&tv), &wq->lock);
9969 + getmicrouptime(&tv2);
9973 + if (result == 0) { // awoken
9977 + simple_unlock(&wq->lock);
9978 + result = -DWC_E_ABORT;
9981 + simple_unlock(&wq->lock);
9983 + tv2.tv_usec -= tv1.tv_usec;
9984 + if (tv2.tv_usec < 0) {
9985 + tv2.tv_usec += 1000000;
9989 + tv2.tv_sec -= tv1.tv_sec;
9990 + result = tv2.tv_sec * 1000 + tv2.tv_usec / 1000;
9991 + result = msecs - result;
9998 + simple_unlock(&wq->lock);
10000 + if (result == ERESTART) { // signaled - restart
10001 + result = -DWC_E_RESTART;
10003 + } else if (result == EINTR) { // signaled - interrupt
10004 + result = -DWC_E_ABORT;
10006 + } else { // timed out
10007 + result = -DWC_E_TIMEOUT;
10014 +void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq)
10019 +void DWC_WAITQ_ABORT(dwc_waitq_t *wq)
10023 + simple_lock(&wq->lock);
10028 + simple_unlock(&wq->lock);
10034 +struct dwc_thread {
10035 + struct proc *proc;
10039 +dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data)
10042 + dwc_thread_t *thread = DWC_ALLOC(sizeof(*thread));
10048 + thread->abort = 0;
10049 + retval = kthread_create1((void (*)(void *))func, data, &thread->proc,
10052 + DWC_FREE(thread);
10059 +int DWC_THREAD_STOP(dwc_thread_t *thread)
10063 + thread->abort = 1;
10064 + retval = tsleep(&thread->abort, 0, "dw3stp", 60 * hz);
10066 + if (retval == 0) {
10067 + /* DWC_THREAD_EXIT() will free the thread struct */
10071 + /* NOTE: We leak the thread struct if thread doesn't die */
10073 + if (retval == EWOULDBLOCK) {
10074 + return -DWC_E_TIMEOUT;
10077 + return -DWC_E_UNKNOWN;
10080 +dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread)
10082 + return thread->abort;
10085 +void DWC_THREAD_EXIT(dwc_thread_t *thread)
10087 + wakeup(&thread->abort);
10088 + DWC_FREE(thread);
10093 + - Runs in interrupt context (cannot sleep)
10094 + - Each tasklet runs on a single CPU
10095 + - Different tasklets can be running simultaneously on different CPUs
10096 + [ On NetBSD there is no corresponding mechanism, drivers don't have bottom-
10097 + halves. So we just call the callback directly from DWC_TASK_SCHEDULE() ]
10099 +struct dwc_tasklet {
10100 + dwc_tasklet_callback_t cb;
10104 +static void tasklet_callback(void *data)
10106 + dwc_tasklet_t *task = (dwc_tasklet_t *)data;
10108 + task->cb(task->data);
10111 +dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data)
10113 + dwc_tasklet_t *task = DWC_ALLOC(sizeof(*task));
10117 + task->data = data;
10119 + DWC_ERROR("Cannot allocate memory for tasklet");
10125 +void DWC_TASK_FREE(dwc_tasklet_t *task)
10130 +void DWC_TASK_SCHEDULE(dwc_tasklet_t *task)
10132 + tasklet_callback(task);
10137 + - Runs in process context (can sleep)
10139 +typedef struct work_container {
10140 + dwc_work_callback_t cb;
10145 + struct work task;
10146 +} work_container_t;
10148 +struct dwc_workq {
10149 + struct workqueue *taskq;
10150 + dwc_spinlock_t *lock;
10151 + dwc_waitq_t *waitq;
10153 + struct work_container *container;
10156 +static void do_work(struct work *task, void *data)
10158 + dwc_workq_t *wq = (dwc_workq_t *)data;
10159 + work_container_t *container = wq->container;
10160 + dwc_irqflags_t flags;
10162 + if (container->hz) {
10163 + tsleep(container, 0, "dw3wrk", container->hz);
10166 + container->cb(container->data);
10167 + DWC_DEBUG("Work done: %s, container=%p", container->name, container);
10169 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
10170 + if (container->name)
10171 + DWC_FREE(container->name);
10172 + DWC_FREE(container);
10174 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
10175 + DWC_WAITQ_TRIGGER(wq->waitq);
10178 +static int work_done(void *data)
10180 + dwc_workq_t *workq = (dwc_workq_t *)data;
10182 + return workq->pending == 0;
10185 +int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout)
10187 + return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout);
10190 +dwc_workq_t *DWC_WORKQ_ALLOC(char *name)
10193 + dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq));
10196 + DWC_ERROR("Cannot allocate memory for workqueue");
10200 + result = workqueue_create(&wq->taskq, name, do_work, wq, 0 /*PWAIT*/,
10203 + DWC_ERROR("Cannot create workqueue");
10209 + wq->lock = DWC_SPINLOCK_ALLOC();
10211 + DWC_ERROR("Cannot allocate memory for spinlock");
10215 + wq->waitq = DWC_WAITQ_ALLOC();
10216 + if (!wq->waitq) {
10217 + DWC_ERROR("Cannot allocate memory for waitqueue");
10224 + DWC_SPINLOCK_FREE(wq->lock);
10226 + workqueue_destroy(wq->taskq);
10233 +void DWC_WORKQ_FREE(dwc_workq_t *wq)
10236 + dwc_irqflags_t flags;
10238 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
10240 + if (wq->pending != 0) {
10241 + struct work_container *container = wq->container;
10243 + DWC_ERROR("Destroying work queue with pending work");
10245 + if (container && container->name) {
10246 + DWC_ERROR("Work %s still pending", container->name);
10250 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
10252 + DWC_WAITQ_FREE(wq->waitq);
10253 + DWC_SPINLOCK_FREE(wq->lock);
10254 + workqueue_destroy(wq->taskq);
10258 +void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data,
10259 + char *format, ...)
10261 + dwc_irqflags_t flags;
10262 + work_container_t *container;
10263 + static char name[128];
10266 + va_start(args, format);
10267 + DWC_VSNPRINTF(name, 128, format, args);
10270 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
10272 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
10273 + DWC_WAITQ_TRIGGER(wq->waitq);
10275 + container = DWC_ALLOC_ATOMIC(sizeof(*container));
10276 + if (!container) {
10277 + DWC_ERROR("Cannot allocate memory for container");
10281 + container->name = DWC_STRDUP(name);
10282 + if (!container->name) {
10283 + DWC_ERROR("Cannot allocate memory for container->name");
10284 + DWC_FREE(container);
10288 + container->cb = cb;
10289 + container->data = data;
10290 + container->wq = wq;
10291 + container->hz = 0;
10292 + wq->container = container;
10294 + DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
10295 + workqueue_enqueue(wq->taskq, &container->task);
10298 +void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb,
10299 + void *data, uint32_t time, char *format, ...)
10301 + dwc_irqflags_t flags;
10302 + work_container_t *container;
10303 + static char name[128];
10304 + struct timeval tv;
10307 + va_start(args, format);
10308 + DWC_VSNPRINTF(name, 128, format, args);
10311 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
10313 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
10314 + DWC_WAITQ_TRIGGER(wq->waitq);
10316 + container = DWC_ALLOC_ATOMIC(sizeof(*container));
10317 + if (!container) {
10318 + DWC_ERROR("Cannot allocate memory for container");
10322 + container->name = DWC_STRDUP(name);
10323 + if (!container->name) {
10324 + DWC_ERROR("Cannot allocate memory for container->name");
10325 + DWC_FREE(container);
10329 + container->cb = cb;
10330 + container->data = data;
10331 + container->wq = wq;
10332 + tv.tv_sec = time / 1000;
10333 + tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
10334 + container->hz = tvtohz(&tv);
10335 + wq->container = container;
10337 + DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
10338 + workqueue_enqueue(wq->taskq, &container->task);
10341 +int DWC_WORKQ_PENDING(dwc_workq_t *wq)
10343 + return wq->pending;
10346 +++ b/drivers/usb/host/dwc_common_port/dwc_crypto.c
10348 +/* =========================================================================
10349 + * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_crypto.c $
10350 + * $Revision: #5 $
10351 + * $Date: 2010/09/28 $
10352 + * $Change: 1596182 $
10354 + * Synopsys Portability Library Software and documentation
10355 + * (hereinafter, "Software") is an Unsupported proprietary work of
10356 + * Synopsys, Inc. unless otherwise expressly agreed to in writing
10357 + * between Synopsys and you.
10359 + * The Software IS NOT an item of Licensed Software or Licensed Product
10360 + * under any End User Software License Agreement or Agreement for
10361 + * Licensed Product with Synopsys or any supplement thereto. You are
10362 + * permitted to use and redistribute this Software in source and binary
10363 + * forms, with or without modification, provided that redistributions
10364 + * of source code must retain this notice. You may not view, use,
10365 + * disclose, copy or distribute this file or any information contained
10366 + * herein except pursuant to this license grant from Synopsys. If you
10367 + * do not agree with this notice, including the disclaimer below, then
10368 + * you are not authorized to use the Software.
10370 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
10371 + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
10372 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
10373 + * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
10374 + * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
10375 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
10376 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
10377 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
10378 + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10379 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
10380 + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
10382 + * ========================================================================= */
10385 + * This file contains the WUSB cryptographic routines.
10388 +#ifdef DWC_CRYPTOLIB
10390 +#include "dwc_crypto.h"
10394 +static inline void dump_bytes(char *name, uint8_t *bytes, int len)
10397 + DWC_PRINTF("%s: ", name);
10398 + for (i=0; i<len; i++) {
10399 + DWC_PRINTF("%02x ", bytes[i]);
10401 + DWC_PRINTF("\n");
10404 +#define dump_bytes(x...)
10407 +/* Display a block */
10408 +void show_block(const u8 *blk, const char *prefix, const char *suffix, int a)
10410 +#ifdef DWC_DEBUG_CRYPTO
10411 + int i, blksize = 16;
10413 + DWC_DEBUG("%s", prefix);
10415 + if (suffix == NULL) {
10420 + for (i = 0; i < blksize; i++)
10421 + DWC_PRINT("%02x%s", *blk++, ((i & 3) == 3) ? " " : " ");
10422 + DWC_PRINT(suffix);
10427 + * Encrypts an array of bytes using the AES encryption engine.
10428 + * If <code>dst</code> == <code>src</code>, then the bytes will be encrypted
10431 + * @return 0 on success, negative error code on error.
10433 +int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst)
10436 + DWC_MEMSET(block_t, 0, 16);
10438 + return DWC_AES_CBC(src, 16, key, 16, block_t, dst);
10442 + * The CCM-MAC-FUNCTION described in section 6.5 of the WUSB spec.
10443 + * This function takes a data string and returns the encrypted CBC
10444 + * Counter-mode MIC.
10446 + * @param key The 128-bit symmetric key.
10447 + * @param nonce The CCM nonce.
10448 + * @param label The unique 14-byte ASCII text label.
10449 + * @param bytes The byte array to be encrypted.
10450 + * @param len Length of the byte array.
10451 + * @param result Byte array to receive the 8-byte encrypted MIC.
10453 +void dwc_wusb_cmf(u8 *key, u8 *nonce,
10454 + char *label, u8 *bytes, int len, u8 *result)
10460 + u16 la = (u16)(len + 14);
10462 + /* Set the AES-128 key */
10463 + //dwc_aes_setkey(tfm, key, 16);
10465 + /* Fill block B0 from flags = 0x59, N, and l(m) = 0 */
10466 + block_m[0] = 0x59;
10467 + for (idx = 0; idx < 13; idx++)
10468 + block_m[idx + 1] = nonce[idx];
10472 + /* Produce the CBC IV */
10473 + dwc_wusb_aes_encrypt(block_m, key, block_x);
10474 + show_block(block_m, "CBC IV in: ", "\n", 0);
10475 + show_block(block_x, "CBC IV out:", "\n", 0);
10477 + /* Fill block B1 from l(a) = Blen + 14, and A */
10478 + block_x[0] ^= (u8)(la >> 8);
10479 + block_x[1] ^= (u8)la;
10480 + for (idx = 0; idx < 14; idx++)
10481 + block_x[idx + 2] ^= label[idx];
10482 + show_block(block_x, "After xor: ", "b1\n", 16);
10484 + dwc_wusb_aes_encrypt(block_x, key, block_x);
10485 + show_block(block_x, "After AES: ", "b1\n", 16);
10490 + /* Fill remaining blocks with B */
10491 + while (len-- > 0) {
10492 + block_x[idx] ^= *bytes++;
10493 + if (++idx >= 16) {
10495 + show_block(block_x, "After xor: ", "\n", blkNum);
10496 + dwc_wusb_aes_encrypt(block_x, key, block_x);
10497 + show_block(block_x, "After AES: ", "\n", blkNum);
10502 + /* Handle partial last block */
10504 + show_block(block_x, "After xor: ", "\n", blkNum);
10505 + dwc_wusb_aes_encrypt(block_x, key, block_x);
10506 + show_block(block_x, "After AES: ", "\n", blkNum);
10509 + /* Save the MIC tag */
10510 + DWC_MEMCPY(block_t, block_x, 8);
10511 + show_block(block_t, "MIC tag : ", NULL, 8);
10513 + /* Fill block A0 from flags = 0x01, N, and counter = 0 */
10514 + block_m[0] = 0x01;
10518 + /* Encrypt the counter */
10519 + dwc_wusb_aes_encrypt(block_m, key, block_x);
10520 + show_block(block_x, "CTR[MIC] : ", NULL, 8);
10522 + /* XOR with MIC tag */
10523 + for (idx = 0; idx < 8; idx++) {
10524 + block_t[idx] ^= block_x[idx];
10527 + /* Return result to caller */
10528 + DWC_MEMCPY(result, block_t, 8);
10529 + show_block(result, "CCM-MIC : ", NULL, 8);
10534 + * The PRF function described in section 6.5 of the WUSB spec. This function
10535 + * concatenates MIC values returned from dwc_cmf() to create a value of
10536 + * the requested length.
10538 + * @param prf_len Length of the PRF function in bits (64, 128, or 256).
10539 + * @param key, nonce, label, bytes, len Same as for dwc_cmf().
10540 + * @param result Byte array to receive the result.
10542 +void dwc_wusb_prf(int prf_len, u8 *key,
10543 + u8 *nonce, char *label, u8 *bytes, int len, u8 *result)
10548 + for (i = 0; i < prf_len >> 6; i++, nonce[0]++) {
10549 + dwc_wusb_cmf(key, nonce, label, bytes, len, result);
10555 + * Fills in CCM Nonce per the WUSB spec.
10557 + * @param[in] haddr Host address.
10558 + * @param[in] daddr Device address.
10559 + * @param[in] tkid Session Key(PTK) identifier.
10560 + * @param[out] nonce Pointer to where the CCM Nonce output is to be written.
10562 +void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid,
10566 + DWC_DEBUG("%s %x %x\n", __func__, daddr, haddr);
10568 + DWC_MEMSET(&nonce[0], 0, 16);
10570 + DWC_MEMCPY(&nonce[6], tkid, 3);
10571 + nonce[9] = daddr & 0xFF;
10572 + nonce[10] = (daddr >> 8) & 0xFF;
10573 + nonce[11] = haddr & 0xFF;
10574 + nonce[12] = (haddr >> 8) & 0xFF;
10576 + dump_bytes("CCM nonce", nonce, 16);
10580 + * Generates a 16-byte cryptographic-grade random number for the Host/Device
10583 +void dwc_wusb_gen_nonce(uint16_t addr, uint8_t *nonce)
10585 + uint8_t inonce[16];
10586 + uint32_t temp[4];
10588 + /* Fill in the Nonce */
10589 + DWC_MEMSET(&inonce[0], 0, sizeof(inonce));
10590 + inonce[9] = addr & 0xFF;
10591 + inonce[10] = (addr >> 8) & 0xFF;
10592 + inonce[11] = inonce[9];
10593 + inonce[12] = inonce[10];
10595 + /* Collect "randomness samples" */
10596 + DWC_RANDOM_BYTES((uint8_t *)temp, 16);
10598 + dwc_wusb_prf_128((uint8_t *)temp, nonce,
10599 + "Random Numbers", (uint8_t *)temp, sizeof(temp),
10604 + * Generates the Session Key (PTK) and Key Confirmation Key (KCK) per the
10607 + * @param[in] ccm_nonce Pointer to CCM Nonce.
10608 + * @param[in] mk Master Key to derive the session from
10609 + * @param[in] hnonce Pointer to Host Nonce.
10610 + * @param[in] dnonce Pointer to Device Nonce.
10611 + * @param[out] kck Pointer to where the KCK output is to be written.
10612 + * @param[out] ptk Pointer to where the PTK output is to be written.
10614 +void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk, uint8_t *hnonce,
10615 + uint8_t *dnonce, uint8_t *kck, uint8_t *ptk)
10617 + uint8_t idata[32];
10618 + uint8_t odata[32];
10620 + dump_bytes("ck", mk, 16);
10621 + dump_bytes("hnonce", hnonce, 16);
10622 + dump_bytes("dnonce", dnonce, 16);
10624 + /* The data is the HNonce and DNonce concatenated */
10625 + DWC_MEMCPY(&idata[0], hnonce, 16);
10626 + DWC_MEMCPY(&idata[16], dnonce, 16);
10628 + dwc_wusb_prf_256(mk, ccm_nonce, "Pair-wise keys", idata, 32, odata);
10630 + /* Low 16 bytes of the result is the KCK, high 16 is the PTK */
10631 + DWC_MEMCPY(kck, &odata[0], 16);
10632 + DWC_MEMCPY(ptk, &odata[16], 16);
10634 + dump_bytes("kck", kck, 16);
10635 + dump_bytes("ptk", ptk, 16);
10639 + * Generates the Message Integrity Code over the Handshake data per the
10642 + * @param ccm_nonce Pointer to CCM Nonce.
10643 + * @param kck Pointer to Key Confirmation Key.
10644 + * @param data Pointer to Handshake data to be checked.
10645 + * @param mic Pointer to where the MIC output is to be written.
10647 +void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t *kck,
10648 + uint8_t *data, uint8_t *mic)
10651 + dwc_wusb_prf_64(kck, ccm_nonce, "out-of-bandMIC",
10652 + data, WUSB_HANDSHAKE_LEN_FOR_MIC, mic);
10655 +#endif /* DWC_CRYPTOLIB */
10657 +++ b/drivers/usb/host/dwc_common_port/dwc_crypto.h
10659 +/* =========================================================================
10660 + * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_crypto.h $
10661 + * $Revision: #3 $
10662 + * $Date: 2010/09/28 $
10663 + * $Change: 1596182 $
10665 + * Synopsys Portability Library Software and documentation
10666 + * (hereinafter, "Software") is an Unsupported proprietary work of
10667 + * Synopsys, Inc. unless otherwise expressly agreed to in writing
10668 + * between Synopsys and you.
10670 + * The Software IS NOT an item of Licensed Software or Licensed Product
10671 + * under any End User Software License Agreement or Agreement for
10672 + * Licensed Product with Synopsys or any supplement thereto. You are
10673 + * permitted to use and redistribute this Software in source and binary
10674 + * forms, with or without modification, provided that redistributions
10675 + * of source code must retain this notice. You may not view, use,
10676 + * disclose, copy or distribute this file or any information contained
10677 + * herein except pursuant to this license grant from Synopsys. If you
10678 + * do not agree with this notice, including the disclaimer below, then
10679 + * you are not authorized to use the Software.
10681 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
10682 + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
10683 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
10684 + * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
10685 + * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
10686 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
10687 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
10688 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
10689 + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10690 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
10691 + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
10693 + * ========================================================================= */
10695 +#ifndef _DWC_CRYPTO_H_
10696 +#define _DWC_CRYPTO_H_
10698 +#ifdef __cplusplus
10704 + * This file contains declarations for the WUSB Cryptographic routines as
10705 + * defined in the WUSB spec. They are only to be used internally by the DWC UWB
10709 +#include "dwc_os.h"
10711 +int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst);
10713 +void dwc_wusb_cmf(u8 *key, u8 *nonce,
10714 + char *label, u8 *bytes, int len, u8 *result);
10715 +void dwc_wusb_prf(int prf_len, u8 *key,
10716 + u8 *nonce, char *label, u8 *bytes, int len, u8 *result);
10719 + * The PRF-64 function described in section 6.5 of the WUSB spec.
10721 + * @param key, nonce, label, bytes, len, result Same as for dwc_prf().
10723 +static inline void dwc_wusb_prf_64(u8 *key, u8 *nonce,
10724 + char *label, u8 *bytes, int len, u8 *result)
10726 + dwc_wusb_prf(64, key, nonce, label, bytes, len, result);
10730 + * The PRF-128 function described in section 6.5 of the WUSB spec.
10732 + * @param key, nonce, label, bytes, len, result Same as for dwc_prf().
10734 +static inline void dwc_wusb_prf_128(u8 *key, u8 *nonce,
10735 + char *label, u8 *bytes, int len, u8 *result)
10737 + dwc_wusb_prf(128, key, nonce, label, bytes, len, result);
10741 + * The PRF-256 function described in section 6.5 of the WUSB spec.
10743 + * @param key, nonce, label, bytes, len, result Same as for dwc_prf().
10745 +static inline void dwc_wusb_prf_256(u8 *key, u8 *nonce,
10746 + char *label, u8 *bytes, int len, u8 *result)
10748 + dwc_wusb_prf(256, key, nonce, label, bytes, len, result);
10752 +void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid,
10754 +void dwc_wusb_gen_nonce(uint16_t addr,
10757 +void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk,
10758 + uint8_t *hnonce, uint8_t *dnonce,
10759 + uint8_t *kck, uint8_t *ptk);
10762 +void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t
10763 + *kck, uint8_t *data, uint8_t *mic);
10765 +#ifdef __cplusplus
10769 +#endif /* _DWC_CRYPTO_H_ */
10771 +++ b/drivers/usb/host/dwc_common_port/dwc_dh.c
10773 +/* =========================================================================
10774 + * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_dh.c $
10775 + * $Revision: #3 $
10776 + * $Date: 2010/09/28 $
10777 + * $Change: 1596182 $
10779 + * Synopsys Portability Library Software and documentation
10780 + * (hereinafter, "Software") is an Unsupported proprietary work of
10781 + * Synopsys, Inc. unless otherwise expressly agreed to in writing
10782 + * between Synopsys and you.
10784 + * The Software IS NOT an item of Licensed Software or Licensed Product
10785 + * under any End User Software License Agreement or Agreement for
10786 + * Licensed Product with Synopsys or any supplement thereto. You are
10787 + * permitted to use and redistribute this Software in source and binary
10788 + * forms, with or without modification, provided that redistributions
10789 + * of source code must retain this notice. You may not view, use,
10790 + * disclose, copy or distribute this file or any information contained
10791 + * herein except pursuant to this license grant from Synopsys. If you
10792 + * do not agree with this notice, including the disclaimer below, then
10793 + * you are not authorized to use the Software.
10795 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
10796 + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
10797 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
10798 + * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
10799 + * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
10800 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
10801 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
10802 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
10803 + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10804 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
10805 + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
10807 + * ========================================================================= */
10808 +#ifdef DWC_CRYPTOLIB
10810 +#ifndef CONFIG_MACH_IPMATE
10812 +#include "dwc_dh.h"
10813 +#include "dwc_modpow.h"
10816 +/* This function prints out a buffer in the format described in the Association
10817 + * Model specification. */
10818 +static void dh_dump(char *str, void *_num, int len)
10820 + uint8_t *num = _num;
10822 + DWC_PRINTF("%s\n", str);
10823 + for (i = 0; i < len; i ++) {
10824 + DWC_PRINTF("%02x", num[i]);
10825 + if (((i + 1) % 2) == 0) DWC_PRINTF(" ");
10826 + if (((i + 1) % 26) == 0) DWC_PRINTF("\n");
10829 + DWC_PRINTF("\n");
10832 +#define dh_dump(_x...) do {; } while(0)
10835 +/* Constant g value */
10836 +static __u32 dh_g[] = {
10840 +/* Constant p value */
10841 +static __u32 dh_p[] = {
10842 + 0xFFFFFFFF, 0xFFFFFFFF, 0xA2DA0FC9, 0x34C26821, 0x8B62C6C4, 0xD11CDC80, 0x084E0229, 0x74CC678A,
10843 + 0xA6BE0B02, 0x229B133B, 0x79084A51, 0xDD04348E, 0xB31995EF, 0x1B433ACD, 0x6D0A2B30, 0x37145FF2,
10844 + 0x6D35E14F, 0x45C2516D, 0x76B585E4, 0xC67E5E62, 0xE9424CF4, 0x6BED37A6, 0xB65CFF0B, 0xEDB706F4,
10845 + 0xFB6B38EE, 0xA59F895A, 0x11249FAE, 0xE61F4B7C, 0x51662849, 0x3D5BE4EC, 0xB87C00C2, 0x05BF63A1,
10846 + 0x3648DA98, 0x9AD3551C, 0xA83F1669, 0x5FCF24FD, 0x235D6583, 0x96ADA3DC, 0x56F3621C, 0xBB528520,
10847 + 0x0729D59E, 0x6D969670, 0x4E350C67, 0x0498BC4A, 0x086C74F1, 0x7C2118CA, 0x465E9032, 0x3BCE362E,
10848 + 0x2C779EE3, 0x03860E18, 0xA283279B, 0x8FA207EC, 0xF05DC5B5, 0xC9524C6F, 0xF6CB2BDE, 0x18175895,
10849 + 0x7C499539, 0xE56A95EA, 0x1826D215, 0x1005FA98, 0x5A8E7215, 0x2DC4AA8A, 0x0D1733AD, 0x337A5004,
10850 + 0xAB2155A8, 0x64BA1CDF, 0x0485FBEC, 0x0AEFDB58, 0x5771EA8A, 0x7D0C065D, 0x850F97B3, 0xC7E4E1A6,
10851 + 0x8CAEF5AB, 0xD73309DB, 0xE0948C1E, 0x9D61254A, 0x26D2E3CE, 0x6BEED21A, 0x06FA2FF1, 0x64088AD9,
10852 + 0x730276D8, 0x646AC83E, 0x182B1F52, 0x0C207B17, 0x5717E1BB, 0x6C5D617A, 0xC0880977, 0xE246D9BA,
10853 + 0xA04FE208, 0x31ABE574, 0xFC5BDB43, 0x8E10FDE0, 0x20D1824B, 0xCAD23AA9, 0xFFFFFFFF, 0xFFFFFFFF,
10856 +static void dh_swap_bytes(void *_in, void *_out, uint32_t len)
10858 + uint8_t *in = _in;
10859 + uint8_t *out = _out;
10861 + for (i=0; i<len; i++) {
10862 + out[i] = in[len-1-i];
10866 +/* Computes the modular exponentiation (num^exp % mod). num, exp, and mod are
10867 + * big endian numbers of size len, in bytes. Each len value must be a multiple
10869 +int dwc_dh_modpow(void *mem_ctx, void *num, uint32_t num_len,
10870 + void *exp, uint32_t exp_len,
10871 + void *mod, uint32_t mod_len,
10874 + /* modpow() takes little endian numbers. AM uses big-endian. This
10875 + * function swaps bytes of numbers before passing onto modpow. */
10878 + uint32_t *result;
10880 + uint32_t *bignum_num = dwc_alloc(mem_ctx, num_len + 4);
10881 + uint32_t *bignum_exp = dwc_alloc(mem_ctx, exp_len + 4);
10882 + uint32_t *bignum_mod = dwc_alloc(mem_ctx, mod_len + 4);
10884 + dh_swap_bytes(num, &bignum_num[1], num_len);
10885 + bignum_num[0] = num_len / 4;
10887 + dh_swap_bytes(exp, &bignum_exp[1], exp_len);
10888 + bignum_exp[0] = exp_len / 4;
10890 + dh_swap_bytes(mod, &bignum_mod[1], mod_len);
10891 + bignum_mod[0] = mod_len / 4;
10893 + result = dwc_modpow(mem_ctx, bignum_num, bignum_exp, bignum_mod);
10896 + goto dh_modpow_nomem;
10899 + dh_swap_bytes(&result[1], out, result[0] * 4);
10900 + dwc_free(mem_ctx, result);
10903 + dwc_free(mem_ctx, bignum_num);
10904 + dwc_free(mem_ctx, bignum_exp);
10905 + dwc_free(mem_ctx, bignum_mod);
10910 +int dwc_dh_pk(void *mem_ctx, uint8_t nd, uint8_t *exp, uint8_t *pk, uint8_t *hash)
10915 +#ifndef DH_TEST_VECTORS
10916 + DWC_RANDOM_BYTES(exp, 32);
10919 + /* Compute the pkd */
10920 + if ((retval = dwc_dh_modpow(mem_ctx, dh_g, 4,
10922 + dh_p, 384, pk))) {
10927 + DWC_MEMCPY(&m3[0], pk, 384);
10928 + DWC_SHA256(m3, 385, hash);
10930 + dh_dump("PK", pk, 384);
10931 + dh_dump("SHA-256(M3)", hash, 32);
10935 +int dwc_dh_derive_keys(void *mem_ctx, uint8_t nd, uint8_t *pkh, uint8_t *pkd,
10936 + uint8_t *exp, int is_host,
10937 + char *dd, uint8_t *ck, uint8_t *kdk)
10941 + uint8_t sha_result[32];
10942 + uint8_t dhkey[384];
10943 + uint8_t shared_secret[384];
10956 + if ((retval = dwc_dh_modpow(mem_ctx, pk, 384,
10958 + dh_p, 384, shared_secret))) {
10961 + dh_dump("Shared Secret", shared_secret, 384);
10963 + DWC_SHA256(shared_secret, 384, dhkey);
10964 + dh_dump("DHKEY", dhkey, 384);
10966 + DWC_MEMCPY(&mv[0], pkd, 384);
10967 + DWC_MEMCPY(&mv[384], pkh, 384);
10968 + DWC_MEMCPY(&mv[768], "displayed digest", 16);
10969 + dh_dump("MV", mv, 784);
10971 + DWC_SHA256(mv, 784, sha_result);
10972 + dh_dump("SHA-256(MV)", sha_result, 32);
10973 + dh_dump("First 32-bits of SHA-256(MV)", sha_result, 4);
10975 + dh_swap_bytes(sha_result, &vd, 4);
10977 + DWC_PRINTF("Vd (decimal) = %d\n", vd);
10983 + DWC_SPRINTF(dd, "%02d", vd);
10987 + DWC_SPRINTF(dd, "%03d", vd);
10991 + DWC_SPRINTF(dd, "%04d", vd);
10995 + DWC_PRINTF("Display Digits: %s\n", dd);
10998 + message = "connection key";
10999 + DWC_HMAC_SHA256(message, DWC_STRLEN(message), dhkey, 32, sha_result);
11000 + dh_dump("HMAC(SHA-256, DHKey, connection key)", sha_result, 32);
11001 + DWC_MEMCPY(ck, sha_result, 16);
11003 + message = "key derivation key";
11004 + DWC_HMAC_SHA256(message, DWC_STRLEN(message), dhkey, 32, sha_result);
11005 + dh_dump("HMAC(SHA-256, DHKey, key derivation key)", sha_result, 32);
11006 + DWC_MEMCPY(kdk, sha_result, 32);
11012 +#ifdef DH_TEST_VECTORS
11014 +static __u8 dh_a[] = {
11015 + 0x44, 0x00, 0x51, 0xd6,
11016 + 0xf0, 0xb5, 0x5e, 0xa9,
11017 + 0x67, 0xab, 0x31, 0xc6,
11018 + 0x8a, 0x8b, 0x5e, 0x37,
11019 + 0xd9, 0x10, 0xda, 0xe0,
11020 + 0xe2, 0xd4, 0x59, 0xa4,
11021 + 0x86, 0x45, 0x9c, 0xaa,
11022 + 0xdf, 0x36, 0x75, 0x16,
11025 +static __u8 dh_b[] = {
11026 + 0x5d, 0xae, 0xc7, 0x86,
11027 + 0x79, 0x80, 0xa3, 0x24,
11028 + 0x8c, 0xe3, 0x57, 0x8f,
11029 + 0xc7, 0x5f, 0x1b, 0x0f,
11030 + 0x2d, 0xf8, 0x9d, 0x30,
11031 + 0x6f, 0xa4, 0x52, 0xcd,
11032 + 0xe0, 0x7a, 0x04, 0x8a,
11033 + 0xde, 0xd9, 0x26, 0x56,
11036 +void dwc_run_dh_test_vectors(void *mem_ctx)
11038 + uint8_t pkd[384];
11039 + uint8_t pkh[384];
11040 + uint8_t hashd[32];
11041 + uint8_t hashh[32];
11046 + DWC_PRINTF("\n\n\nDH_TEST_VECTORS\n\n");
11048 + /* compute the PKd and SHA-256(PKd || Nd) */
11049 + DWC_PRINTF("Computing PKd\n");
11050 + dwc_dh_pk(mem_ctx, 2, dh_a, pkd, hashd);
11052 + /* compute the PKd and SHA-256(PKh || Nd) */
11053 + DWC_PRINTF("Computing PKh\n");
11054 + dwc_dh_pk(mem_ctx, 2, dh_b, pkh, hashh);
11056 + /* compute the dhkey */
11057 + dwc_dh_derive_keys(mem_ctx, 2, pkh, pkd, dh_a, 0, dd, ck, kdk);
11059 +#endif /* DH_TEST_VECTORS */
11061 +#endif /* !CONFIG_MACH_IPMATE */
11063 +#endif /* DWC_CRYPTOLIB */
11065 +++ b/drivers/usb/host/dwc_common_port/dwc_dh.h
11067 +/* =========================================================================
11068 + * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_dh.h $
11069 + * $Revision: #4 $
11070 + * $Date: 2010/09/28 $
11071 + * $Change: 1596182 $
11073 + * Synopsys Portability Library Software and documentation
11074 + * (hereinafter, "Software") is an Unsupported proprietary work of
11075 + * Synopsys, Inc. unless otherwise expressly agreed to in writing
11076 + * between Synopsys and you.
11078 + * The Software IS NOT an item of Licensed Software or Licensed Product
11079 + * under any End User Software License Agreement or Agreement for
11080 + * Licensed Product with Synopsys or any supplement thereto. You are
11081 + * permitted to use and redistribute this Software in source and binary
11082 + * forms, with or without modification, provided that redistributions
11083 + * of source code must retain this notice. You may not view, use,
11084 + * disclose, copy or distribute this file or any information contained
11085 + * herein except pursuant to this license grant from Synopsys. If you
11086 + * do not agree with this notice, including the disclaimer below, then
11087 + * you are not authorized to use the Software.
11089 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
11090 + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
11091 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
11092 + * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
11093 + * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
11094 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
11095 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
11096 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
11097 + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11098 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
11099 + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
11101 + * ========================================================================= */
11102 +#ifndef _DWC_DH_H_
11103 +#define _DWC_DH_H_
11105 +#ifdef __cplusplus
11109 +#include "dwc_os.h"
11113 + * This file defines the common functions on device and host for performing
11114 + * numeric association as defined in the WUSB spec. They are only to be
11115 + * used internally by the DWC UWB modules. */
11117 +extern int dwc_dh_sha256(uint8_t *message, uint32_t len, uint8_t *out);
11118 +extern int dwc_dh_hmac_sha256(uint8_t *message, uint32_t messagelen,
11119 + uint8_t *key, uint32_t keylen,
11121 +extern int dwc_dh_modpow(void *mem_ctx, void *num, uint32_t num_len,
11122 + void *exp, uint32_t exp_len,
11123 + void *mod, uint32_t mod_len,
11126 +/** Computes PKD or PKH, and SHA-256(PKd || Nd)
11128 + * PK = g^exp mod p.
11131 + * Nd = Number of digits on the device.
11134 + * exp = A 32-byte buffer to be filled with a randomly generated number.
11135 + * used as either A or B.
11136 + * pk = A 384-byte buffer to be filled with the PKH or PKD.
11137 + * hash = A 32-byte buffer to be filled with SHA-256(PK || ND).
11139 +extern int dwc_dh_pk(void *mem_ctx, uint8_t nd, uint8_t *exp, uint8_t *pkd, uint8_t *hash);
11141 +/** Computes the DHKEY, and VD.
11143 + * If called from host, then it will comput DHKEY=PKD^exp % p.
11144 + * If called from device, then it will comput DHKEY=PKH^exp % p.
11147 + * pkd = The PKD value.
11148 + * pkh = The PKH value.
11149 + * exp = The A value (if device) or B value (if host) generated in dwc_wudev_dh_pk.
11150 + * is_host = Set to non zero if a WUSB host is calling this function.
11154 + * dd = A pointer to an buffer to be set to the displayed digits string to be shown
11155 + * to the user. This buffer should be at 5 bytes long to hold 4 digits plus a
11156 + * null termination character. This buffer can be used directly for display.
11157 + * ck = A 16-byte buffer to be filled with the CK.
11158 + * kdk = A 32-byte buffer to be filled with the KDK.
11160 +extern int dwc_dh_derive_keys(void *mem_ctx, uint8_t nd, uint8_t *pkh, uint8_t *pkd,
11161 + uint8_t *exp, int is_host,
11162 + char *dd, uint8_t *ck, uint8_t *kdk);
11164 +#ifdef DH_TEST_VECTORS
11165 +extern void dwc_run_dh_test_vectors(void);
11168 +#ifdef __cplusplus
11172 +#endif /* _DWC_DH_H_ */
11174 +++ b/drivers/usb/host/dwc_common_port/dwc_list.h
11176 +/* $OpenBSD: queue.h,v 1.26 2004/05/04 16:59:32 grange Exp $ */
11177 +/* $NetBSD: queue.h,v 1.11 1996/05/16 05:17:14 mycroft Exp $ */
11180 + * Copyright (c) 1991, 1993
11181 + * The Regents of the University of California. All rights reserved.
11183 + * Redistribution and use in source and binary forms, with or without
11184 + * modification, are permitted provided that the following conditions
11186 + * 1. Redistributions of source code must retain the above copyright
11187 + * notice, this list of conditions and the following disclaimer.
11188 + * 2. Redistributions in binary form must reproduce the above copyright
11189 + * notice, this list of conditions and the following disclaimer in the
11190 + * documentation and/or other materials provided with the distribution.
11191 + * 3. Neither the name of the University nor the names of its contributors
11192 + * may be used to endorse or promote products derived from this software
11193 + * without specific prior written permission.
11195 + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
11196 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
11197 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
11198 + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
11199 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
11200 + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
11201 + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
11202 + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
11203 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
11204 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
11207 + * @(#)queue.h 8.5 (Berkeley) 8/20/94
11210 +#ifndef _DWC_LIST_H_
11211 +#define _DWC_LIST_H_
11213 +#ifdef __cplusplus
11219 + * This file defines linked list operations. It is derived from BSD with
11220 + * only the MACRO names being prefixed with DWC_. This is because a few of
11221 + * these names conflict with those on Linux. For documentation on use, see the
11222 + * inline comments in the source code. The original license for this source
11223 + * code applies and is preserved in the dwc_list.h source file.
11227 + * This file defines five types of data structures: singly-linked lists,
11228 + * lists, simple queues, tail queues, and circular queues.
11231 + * A singly-linked list is headed by a single forward pointer. The elements
11232 + * are singly linked for minimum space and pointer manipulation overhead at
11233 + * the expense of O(n) removal for arbitrary elements. New elements can be
11234 + * added to the list after an existing element or at the head of the list.
11235 + * Elements being removed from the head of the list should use the explicit
11236 + * macro for this purpose for optimum efficiency. A singly-linked list may
11237 + * only be traversed in the forward direction. Singly-linked lists are ideal
11238 + * for applications with large datasets and few or no removals or for
11239 + * implementing a LIFO queue.
11241 + * A list is headed by a single forward pointer (or an array of forward
11242 + * pointers for a hash table header). The elements are doubly linked
11243 + * so that an arbitrary element can be removed without a need to
11244 + * traverse the list. New elements can be added to the list before
11245 + * or after an existing element or at the head of the list. A list
11246 + * may only be traversed in the forward direction.
11248 + * A simple queue is headed by a pair of pointers, one the head of the
11249 + * list and the other to the tail of the list. The elements are singly
11250 + * linked to save space, so elements can only be removed from the
11251 + * head of the list. New elements can be added to the list before or after
11252 + * an existing element, at the head of the list, or at the end of the
11253 + * list. A simple queue may only be traversed in the forward direction.
11255 + * A tail queue is headed by a pair of pointers, one to the head of the
11256 + * list and the other to the tail of the list. The elements are doubly
11257 + * linked so that an arbitrary element can be removed without a need to
11258 + * traverse the list. New elements can be added to the list before or
11259 + * after an existing element, at the head of the list, or at the end of
11260 + * the list. A tail queue may be traversed in either direction.
11262 + * A circle queue is headed by a pair of pointers, one to the head of the
11263 + * list and the other to the tail of the list. The elements are doubly
11264 + * linked so that an arbitrary element can be removed without a need to
11265 + * traverse the list. New elements can be added to the list before or after
11266 + * an existing element, at the head of the list, or at the end of the list.
11267 + * A circle queue may be traversed in either direction, but has a more
11268 + * complex end of list detection.
11270 + * For details on the use of these macros, see the queue(3) manual page.
11274 + * Double-linked List.
11277 +typedef struct dwc_list_link {
11278 + struct dwc_list_link *next;
11279 + struct dwc_list_link *prev;
11280 +} dwc_list_link_t;
11282 +#define DWC_LIST_INIT(link) do { \
11283 + (link)->next = (link); \
11284 + (link)->prev = (link); \
11287 +#define DWC_LIST_FIRST(link) ((link)->next)
11288 +#define DWC_LIST_LAST(link) ((link)->prev)
11289 +#define DWC_LIST_END(link) (link)
11290 +#define DWC_LIST_NEXT(link) ((link)->next)
11291 +#define DWC_LIST_PREV(link) ((link)->prev)
11292 +#define DWC_LIST_EMPTY(link) \
11293 + (DWC_LIST_FIRST(link) == DWC_LIST_END(link))
11294 +#define DWC_LIST_ENTRY(link, type, field) \
11295 + (type *)((uint8_t *)(link) - (size_t)(&((type *)0)->field))
11298 +#define DWC_LIST_INSERT_HEAD(list, link) do { \
11299 + (link)->next = (list)->next; \
11300 + (link)->prev = (list); \
11301 + (list)->next->prev = (link); \
11302 + (list)->next = (link); \
11305 +#define DWC_LIST_INSERT_TAIL(list, link) do { \
11306 + (link)->next = (list); \
11307 + (link)->prev = (list)->prev; \
11308 + (list)->prev->next = (link); \
11309 + (list)->prev = (link); \
11312 +#define DWC_LIST_INSERT_HEAD(list, link) do { \
11313 + dwc_list_link_t *__next__ = (list)->next; \
11314 + __next__->prev = (link); \
11315 + (link)->next = __next__; \
11316 + (link)->prev = (list); \
11317 + (list)->next = (link); \
11320 +#define DWC_LIST_INSERT_TAIL(list, link) do { \
11321 + dwc_list_link_t *__prev__ = (list)->prev; \
11322 + (list)->prev = (link); \
11323 + (link)->next = (list); \
11324 + (link)->prev = __prev__; \
11325 + __prev__->next = (link); \
11330 +static inline void __list_add(struct list_head *new,
11331 + struct list_head *prev,
11332 + struct list_head *next)
11334 + next->prev = new;
11335 + new->next = next;
11336 + new->prev = prev;
11337 + prev->next = new;
11340 +static inline void list_add(struct list_head *new, struct list_head *head)
11342 + __list_add(new, head, head->next);
11345 +static inline void list_add_tail(struct list_head *new, struct list_head *head)
11347 + __list_add(new, head->prev, head);
11350 +static inline void __list_del(struct list_head * prev, struct list_head * next)
11352 + next->prev = prev;
11353 + prev->next = next;
11356 +static inline void list_del(struct list_head *entry)
11358 + __list_del(entry->prev, entry->next);
11359 + entry->next = LIST_POISON1;
11360 + entry->prev = LIST_POISON2;
11364 +#define DWC_LIST_REMOVE(link) do { \
11365 + (link)->next->prev = (link)->prev; \
11366 + (link)->prev->next = (link)->next; \
11369 +#define DWC_LIST_REMOVE_INIT(link) do { \
11370 + DWC_LIST_REMOVE(link); \
11371 + DWC_LIST_INIT(link); \
11374 +#define DWC_LIST_MOVE_HEAD(list, link) do { \
11375 + DWC_LIST_REMOVE(link); \
11376 + DWC_LIST_INSERT_HEAD(list, link); \
11379 +#define DWC_LIST_MOVE_TAIL(list, link) do { \
11380 + DWC_LIST_REMOVE(link); \
11381 + DWC_LIST_INSERT_TAIL(list, link); \
11384 +#define DWC_LIST_FOREACH(var, list) \
11385 + for((var) = DWC_LIST_FIRST(list); \
11386 + (var) != DWC_LIST_END(list); \
11387 + (var) = DWC_LIST_NEXT(var))
11389 +#define DWC_LIST_FOREACH_SAFE(var, var2, list) \
11390 + for((var) = DWC_LIST_FIRST(list), (var2) = DWC_LIST_NEXT(var); \
11391 + (var) != DWC_LIST_END(list); \
11392 + (var) = (var2), (var2) = DWC_LIST_NEXT(var2))
11394 +#define DWC_LIST_FOREACH_REVERSE(var, list) \
11395 + for((var) = DWC_LIST_LAST(list); \
11396 + (var) != DWC_LIST_END(list); \
11397 + (var) = DWC_LIST_PREV(var))
11400 + * Singly-linked List definitions.
11402 +#define DWC_SLIST_HEAD(name, type) \
11404 + struct type *slh_first; /* first element */ \
11407 +#define DWC_SLIST_HEAD_INITIALIZER(head) \
11410 +#define DWC_SLIST_ENTRY(type) \
11412 + struct type *sle_next; /* next element */ \
11416 + * Singly-linked List access methods.
11418 +#define DWC_SLIST_FIRST(head) ((head)->slh_first)
11419 +#define DWC_SLIST_END(head) NULL
11420 +#define DWC_SLIST_EMPTY(head) (SLIST_FIRST(head) == SLIST_END(head))
11421 +#define DWC_SLIST_NEXT(elm, field) ((elm)->field.sle_next)
11423 +#define DWC_SLIST_FOREACH(var, head, field) \
11424 + for((var) = SLIST_FIRST(head); \
11425 + (var) != SLIST_END(head); \
11426 + (var) = SLIST_NEXT(var, field))
11428 +#define DWC_SLIST_FOREACH_PREVPTR(var, varp, head, field) \
11429 + for((varp) = &SLIST_FIRST((head)); \
11430 + ((var) = *(varp)) != SLIST_END(head); \
11431 + (varp) = &SLIST_NEXT((var), field))
11434 + * Singly-linked List functions.
11436 +#define DWC_SLIST_INIT(head) { \
11437 + SLIST_FIRST(head) = SLIST_END(head); \
11440 +#define DWC_SLIST_INSERT_AFTER(slistelm, elm, field) do { \
11441 + (elm)->field.sle_next = (slistelm)->field.sle_next; \
11442 + (slistelm)->field.sle_next = (elm); \
11445 +#define DWC_SLIST_INSERT_HEAD(head, elm, field) do { \
11446 + (elm)->field.sle_next = (head)->slh_first; \
11447 + (head)->slh_first = (elm); \
11450 +#define DWC_SLIST_REMOVE_NEXT(head, elm, field) do { \
11451 + (elm)->field.sle_next = (elm)->field.sle_next->field.sle_next; \
11454 +#define DWC_SLIST_REMOVE_HEAD(head, field) do { \
11455 + (head)->slh_first = (head)->slh_first->field.sle_next; \
11458 +#define DWC_SLIST_REMOVE(head, elm, type, field) do { \
11459 + if ((head)->slh_first == (elm)) { \
11460 + SLIST_REMOVE_HEAD((head), field); \
11463 + struct type *curelm = (head)->slh_first; \
11464 + while( curelm->field.sle_next != (elm) ) \
11465 + curelm = curelm->field.sle_next; \
11466 + curelm->field.sle_next = \
11467 + curelm->field.sle_next->field.sle_next; \
11472 + * Simple queue definitions.
11474 +#define DWC_SIMPLEQ_HEAD(name, type) \
11476 + struct type *sqh_first; /* first element */ \
11477 + struct type **sqh_last; /* addr of last next element */ \
11480 +#define DWC_SIMPLEQ_HEAD_INITIALIZER(head) \
11481 + { NULL, &(head).sqh_first }
11483 +#define DWC_SIMPLEQ_ENTRY(type) \
11485 + struct type *sqe_next; /* next element */ \
11489 + * Simple queue access methods.
11491 +#define DWC_SIMPLEQ_FIRST(head) ((head)->sqh_first)
11492 +#define DWC_SIMPLEQ_END(head) NULL
11493 +#define DWC_SIMPLEQ_EMPTY(head) (SIMPLEQ_FIRST(head) == SIMPLEQ_END(head))
11494 +#define DWC_SIMPLEQ_NEXT(elm, field) ((elm)->field.sqe_next)
11496 +#define DWC_SIMPLEQ_FOREACH(var, head, field) \
11497 + for((var) = SIMPLEQ_FIRST(head); \
11498 + (var) != SIMPLEQ_END(head); \
11499 + (var) = SIMPLEQ_NEXT(var, field))
11502 + * Simple queue functions.
11504 +#define DWC_SIMPLEQ_INIT(head) do { \
11505 + (head)->sqh_first = NULL; \
11506 + (head)->sqh_last = &(head)->sqh_first; \
11509 +#define DWC_SIMPLEQ_INSERT_HEAD(head, elm, field) do { \
11510 + if (((elm)->field.sqe_next = (head)->sqh_first) == NULL) \
11511 + (head)->sqh_last = &(elm)->field.sqe_next; \
11512 + (head)->sqh_first = (elm); \
11515 +#define DWC_SIMPLEQ_INSERT_TAIL(head, elm, field) do { \
11516 + (elm)->field.sqe_next = NULL; \
11517 + *(head)->sqh_last = (elm); \
11518 + (head)->sqh_last = &(elm)->field.sqe_next; \
11521 +#define DWC_SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do { \
11522 + if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\
11523 + (head)->sqh_last = &(elm)->field.sqe_next; \
11524 + (listelm)->field.sqe_next = (elm); \
11527 +#define DWC_SIMPLEQ_REMOVE_HEAD(head, field) do { \
11528 + if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \
11529 + (head)->sqh_last = &(head)->sqh_first; \
11533 + * Tail queue definitions.
11535 +#define DWC_TAILQ_HEAD(name, type) \
11537 + struct type *tqh_first; /* first element */ \
11538 + struct type **tqh_last; /* addr of last next element */ \
11541 +#define DWC_TAILQ_HEAD_INITIALIZER(head) \
11542 + { NULL, &(head).tqh_first }
11544 +#define DWC_TAILQ_ENTRY(type) \
11546 + struct type *tqe_next; /* next element */ \
11547 + struct type **tqe_prev; /* address of previous next element */ \
11551 + * tail queue access methods
11553 +#define DWC_TAILQ_FIRST(head) ((head)->tqh_first)
11554 +#define DWC_TAILQ_END(head) NULL
11555 +#define DWC_TAILQ_NEXT(elm, field) ((elm)->field.tqe_next)
11556 +#define DWC_TAILQ_LAST(head, headname) \
11557 + (*(((struct headname *)((head)->tqh_last))->tqh_last))
11559 +#define DWC_TAILQ_PREV(elm, headname, field) \
11560 + (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
11561 +#define DWC_TAILQ_EMPTY(head) \
11562 + (DWC_TAILQ_FIRST(head) == DWC_TAILQ_END(head))
11564 +#define DWC_TAILQ_FOREACH(var, head, field) \
11565 + for ((var) = DWC_TAILQ_FIRST(head); \
11566 + (var) != DWC_TAILQ_END(head); \
11567 + (var) = DWC_TAILQ_NEXT(var, field))
11569 +#define DWC_TAILQ_FOREACH_REVERSE(var, head, headname, field) \
11570 + for ((var) = DWC_TAILQ_LAST(head, headname); \
11571 + (var) != DWC_TAILQ_END(head); \
11572 + (var) = DWC_TAILQ_PREV(var, headname, field))
11575 + * Tail queue functions.
11577 +#define DWC_TAILQ_INIT(head) do { \
11578 + (head)->tqh_first = NULL; \
11579 + (head)->tqh_last = &(head)->tqh_first; \
11582 +#define DWC_TAILQ_INSERT_HEAD(head, elm, field) do { \
11583 + if (((elm)->field.tqe_next = (head)->tqh_first) != NULL) \
11584 + (head)->tqh_first->field.tqe_prev = \
11585 + &(elm)->field.tqe_next; \
11587 + (head)->tqh_last = &(elm)->field.tqe_next; \
11588 + (head)->tqh_first = (elm); \
11589 + (elm)->field.tqe_prev = &(head)->tqh_first; \
11592 +#define DWC_TAILQ_INSERT_TAIL(head, elm, field) do { \
11593 + (elm)->field.tqe_next = NULL; \
11594 + (elm)->field.tqe_prev = (head)->tqh_last; \
11595 + *(head)->tqh_last = (elm); \
11596 + (head)->tqh_last = &(elm)->field.tqe_next; \
11599 +#define DWC_TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \
11600 + if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\
11601 + (elm)->field.tqe_next->field.tqe_prev = \
11602 + &(elm)->field.tqe_next; \
11604 + (head)->tqh_last = &(elm)->field.tqe_next; \
11605 + (listelm)->field.tqe_next = (elm); \
11606 + (elm)->field.tqe_prev = &(listelm)->field.tqe_next; \
11609 +#define DWC_TAILQ_INSERT_BEFORE(listelm, elm, field) do { \
11610 + (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \
11611 + (elm)->field.tqe_next = (listelm); \
11612 + *(listelm)->field.tqe_prev = (elm); \
11613 + (listelm)->field.tqe_prev = &(elm)->field.tqe_next; \
11616 +#define DWC_TAILQ_REMOVE(head, elm, field) do { \
11617 + if (((elm)->field.tqe_next) != NULL) \
11618 + (elm)->field.tqe_next->field.tqe_prev = \
11619 + (elm)->field.tqe_prev; \
11621 + (head)->tqh_last = (elm)->field.tqe_prev; \
11622 + *(elm)->field.tqe_prev = (elm)->field.tqe_next; \
11625 +#define DWC_TAILQ_REPLACE(head, elm, elm2, field) do { \
11626 + if (((elm2)->field.tqe_next = (elm)->field.tqe_next) != NULL) \
11627 + (elm2)->field.tqe_next->field.tqe_prev = \
11628 + &(elm2)->field.tqe_next; \
11630 + (head)->tqh_last = &(elm2)->field.tqe_next; \
11631 + (elm2)->field.tqe_prev = (elm)->field.tqe_prev; \
11632 + *(elm2)->field.tqe_prev = (elm2); \
11636 + * Circular queue definitions.
11638 +#define DWC_CIRCLEQ_HEAD(name, type) \
11640 + struct type *cqh_first; /* first element */ \
11641 + struct type *cqh_last; /* last element */ \
11644 +#define DWC_CIRCLEQ_HEAD_INITIALIZER(head) \
11645 + { DWC_CIRCLEQ_END(&head), DWC_CIRCLEQ_END(&head) }
11647 +#define DWC_CIRCLEQ_ENTRY(type) \
11649 + struct type *cqe_next; /* next element */ \
11650 + struct type *cqe_prev; /* previous element */ \
11654 + * Circular queue access methods
11656 +#define DWC_CIRCLEQ_FIRST(head) ((head)->cqh_first)
11657 +#define DWC_CIRCLEQ_LAST(head) ((head)->cqh_last)
11658 +#define DWC_CIRCLEQ_END(head) ((void *)(head))
11659 +#define DWC_CIRCLEQ_NEXT(elm, field) ((elm)->field.cqe_next)
11660 +#define DWC_CIRCLEQ_PREV(elm, field) ((elm)->field.cqe_prev)
11661 +#define DWC_CIRCLEQ_EMPTY(head) \
11662 + (DWC_CIRCLEQ_FIRST(head) == DWC_CIRCLEQ_END(head))
11664 +#define DWC_CIRCLEQ_EMPTY_ENTRY(elm, field) (((elm)->field.cqe_next == NULL) && ((elm)->field.cqe_prev == NULL))
11666 +#define DWC_CIRCLEQ_FOREACH(var, head, field) \
11667 + for((var) = DWC_CIRCLEQ_FIRST(head); \
11668 + (var) != DWC_CIRCLEQ_END(head); \
11669 + (var) = DWC_CIRCLEQ_NEXT(var, field))
11671 +#define DWC_CIRCLEQ_FOREACH_SAFE(var, var2, head, field) \
11672 + for((var) = DWC_CIRCLEQ_FIRST(head), var2 = DWC_CIRCLEQ_NEXT(var, field); \
11673 + (var) != DWC_CIRCLEQ_END(head); \
11674 + (var) = var2, var2 = DWC_CIRCLEQ_NEXT(var, field))
11676 +#define DWC_CIRCLEQ_FOREACH_REVERSE(var, head, field) \
11677 + for((var) = DWC_CIRCLEQ_LAST(head); \
11678 + (var) != DWC_CIRCLEQ_END(head); \
11679 + (var) = DWC_CIRCLEQ_PREV(var, field))
11682 + * Circular queue functions.
11684 +#define DWC_CIRCLEQ_INIT(head) do { \
11685 + (head)->cqh_first = DWC_CIRCLEQ_END(head); \
11686 + (head)->cqh_last = DWC_CIRCLEQ_END(head); \
11689 +#define DWC_CIRCLEQ_INIT_ENTRY(elm, field) do { \
11690 + (elm)->field.cqe_next = NULL; \
11691 + (elm)->field.cqe_prev = NULL; \
11694 +#define DWC_CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \
11695 + (elm)->field.cqe_next = (listelm)->field.cqe_next; \
11696 + (elm)->field.cqe_prev = (listelm); \
11697 + if ((listelm)->field.cqe_next == DWC_CIRCLEQ_END(head)) \
11698 + (head)->cqh_last = (elm); \
11700 + (listelm)->field.cqe_next->field.cqe_prev = (elm); \
11701 + (listelm)->field.cqe_next = (elm); \
11704 +#define DWC_CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \
11705 + (elm)->field.cqe_next = (listelm); \
11706 + (elm)->field.cqe_prev = (listelm)->field.cqe_prev; \
11707 + if ((listelm)->field.cqe_prev == DWC_CIRCLEQ_END(head)) \
11708 + (head)->cqh_first = (elm); \
11710 + (listelm)->field.cqe_prev->field.cqe_next = (elm); \
11711 + (listelm)->field.cqe_prev = (elm); \
11714 +#define DWC_CIRCLEQ_INSERT_HEAD(head, elm, field) do { \
11715 + (elm)->field.cqe_next = (head)->cqh_first; \
11716 + (elm)->field.cqe_prev = DWC_CIRCLEQ_END(head); \
11717 + if ((head)->cqh_last == DWC_CIRCLEQ_END(head)) \
11718 + (head)->cqh_last = (elm); \
11720 + (head)->cqh_first->field.cqe_prev = (elm); \
11721 + (head)->cqh_first = (elm); \
11724 +#define DWC_CIRCLEQ_INSERT_TAIL(head, elm, field) do { \
11725 + (elm)->field.cqe_next = DWC_CIRCLEQ_END(head); \
11726 + (elm)->field.cqe_prev = (head)->cqh_last; \
11727 + if ((head)->cqh_first == DWC_CIRCLEQ_END(head)) \
11728 + (head)->cqh_first = (elm); \
11730 + (head)->cqh_last->field.cqe_next = (elm); \
11731 + (head)->cqh_last = (elm); \
11734 +#define DWC_CIRCLEQ_REMOVE(head, elm, field) do { \
11735 + if ((elm)->field.cqe_next == DWC_CIRCLEQ_END(head)) \
11736 + (head)->cqh_last = (elm)->field.cqe_prev; \
11738 + (elm)->field.cqe_next->field.cqe_prev = \
11739 + (elm)->field.cqe_prev; \
11740 + if ((elm)->field.cqe_prev == DWC_CIRCLEQ_END(head)) \
11741 + (head)->cqh_first = (elm)->field.cqe_next; \
11743 + (elm)->field.cqe_prev->field.cqe_next = \
11744 + (elm)->field.cqe_next; \
11747 +#define DWC_CIRCLEQ_REMOVE_INIT(head, elm, field) do { \
11748 + DWC_CIRCLEQ_REMOVE(head, elm, field); \
11749 + DWC_CIRCLEQ_INIT_ENTRY(elm, field); \
11752 +#define DWC_CIRCLEQ_REPLACE(head, elm, elm2, field) do { \
11753 + if (((elm2)->field.cqe_next = (elm)->field.cqe_next) == \
11754 + DWC_CIRCLEQ_END(head)) \
11755 + (head).cqh_last = (elm2); \
11757 + (elm2)->field.cqe_next->field.cqe_prev = (elm2); \
11758 + if (((elm2)->field.cqe_prev = (elm)->field.cqe_prev) == \
11759 + DWC_CIRCLEQ_END(head)) \
11760 + (head).cqh_first = (elm2); \
11762 + (elm2)->field.cqe_prev->field.cqe_next = (elm2); \
11765 +#ifdef __cplusplus
11769 +#endif /* _DWC_LIST_H_ */
11771 +++ b/drivers/usb/host/dwc_common_port/dwc_mem.c
11773 +/* Memory Debugging */
11774 +#ifdef DWC_DEBUG_MEMORY
11776 +#include "dwc_os.h"
11777 +#include "dwc_list.h"
11779 +struct allocation {
11786 + DWC_CIRCLEQ_ENTRY(allocation) entry;
11789 +DWC_CIRCLEQ_HEAD(allocation_queue, allocation);
11791 +struct allocation_manager {
11793 + struct allocation_queue allocations;
11804 +static struct allocation_manager *manager = NULL;
11806 +static int add_allocation(void *ctx, uint32_t size, char const *func, int line, void *addr,
11809 + struct allocation *a;
11811 + DWC_ASSERT(manager != NULL, "manager not allocated");
11813 + a = __DWC_ALLOC_ATOMIC(manager->mem_ctx, sizeof(*a));
11815 + return -DWC_E_NO_MEMORY;
11818 + a->func = __DWC_ALLOC_ATOMIC(manager->mem_ctx, DWC_STRLEN(func) + 1);
11820 + __DWC_FREE(manager->mem_ctx, a);
11821 + return -DWC_E_NO_MEMORY;
11824 + DWC_MEMCPY(a->func, func, DWC_STRLEN(func) + 1);
11830 + DWC_CIRCLEQ_INSERT_TAIL(&manager->allocations, a, entry);
11832 + /* Update stats */
11834 + manager->num_active++;
11835 + manager->total += size;
11836 + manager->cur += size;
11838 + if (manager->max < manager->cur) {
11839 + manager->max = manager->cur;
11845 +static struct allocation *find_allocation(void *ctx, void *addr)
11847 + struct allocation *a;
11849 + DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {
11850 + if (a->ctx == ctx && a->addr == addr) {
11858 +static void free_allocation(void *ctx, void *addr, char const *func, int line)
11860 + struct allocation *a = find_allocation(ctx, addr);
11864 + "Free of address %p that was never allocated or already freed %s:%d",
11865 + addr, func, line);
11869 + DWC_CIRCLEQ_REMOVE(&manager->allocations, a, entry);
11871 + manager->num_active--;
11872 + manager->num_freed++;
11873 + manager->cur -= a->size;
11874 + __DWC_FREE(manager->mem_ctx, a->func);
11875 + __DWC_FREE(manager->mem_ctx, a);
11878 +int dwc_memory_debug_start(void *mem_ctx)
11880 + DWC_ASSERT(manager == NULL, "Memory debugging has already started\n");
11883 + return -DWC_E_BUSY;
11886 + manager = __DWC_ALLOC(mem_ctx, sizeof(*manager));
11888 + return -DWC_E_NO_MEMORY;
11891 + DWC_CIRCLEQ_INIT(&manager->allocations);
11892 + manager->mem_ctx = mem_ctx;
11893 + manager->num = 0;
11894 + manager->num_freed = 0;
11895 + manager->num_active = 0;
11896 + manager->total = 0;
11897 + manager->cur = 0;
11898 + manager->max = 0;
11903 +void dwc_memory_debug_stop(void)
11905 + struct allocation *a;
11907 + dwc_memory_debug_report();
11909 + DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {
11910 + DWC_ERROR("Memory leaked from %s:%d\n", a->func, a->line);
11911 + free_allocation(a->ctx, a->addr, NULL, -1);
11914 + __DWC_FREE(manager->mem_ctx, manager);
11917 +void dwc_memory_debug_report(void)
11919 + struct allocation *a;
11921 + DWC_PRINTF("\n\n\n----------------- Memory Debugging Report -----------------\n\n");
11922 + DWC_PRINTF("Num Allocations = %d\n", manager->num);
11923 + DWC_PRINTF("Freed = %d\n", manager->num_freed);
11924 + DWC_PRINTF("Active = %d\n", manager->num_active);
11925 + DWC_PRINTF("Current Memory Used = %d\n", manager->cur);
11926 + DWC_PRINTF("Total Memory Used = %d\n", manager->total);
11927 + DWC_PRINTF("Maximum Memory Used at Once = %d\n", manager->max);
11928 + DWC_PRINTF("Unfreed allocations:\n");
11930 + DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {
11931 + DWC_PRINTF(" addr=%p, size=%d from %s:%d, DMA=%d\n",
11932 + a->addr, a->size, a->func, a->line, a->dma);
11936 +/* The replacement functions */
11937 +void *dwc_alloc_debug(void *mem_ctx, uint32_t size, char const *func, int line)
11939 + void *addr = __DWC_ALLOC(mem_ctx, size);
11945 + if (add_allocation(mem_ctx, size, func, line, addr, 0)) {
11946 + __DWC_FREE(mem_ctx, addr);
11953 +void *dwc_alloc_atomic_debug(void *mem_ctx, uint32_t size, char const *func,
11956 + void *addr = __DWC_ALLOC_ATOMIC(mem_ctx, size);
11962 + if (add_allocation(mem_ctx, size, func, line, addr, 0)) {
11963 + __DWC_FREE(mem_ctx, addr);
11970 +void dwc_free_debug(void *mem_ctx, void *addr, char const *func, int line)
11972 + free_allocation(mem_ctx, addr, func, line);
11973 + __DWC_FREE(mem_ctx, addr);
11976 +void *dwc_dma_alloc_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,
11977 + char const *func, int line)
11979 + void *addr = __DWC_DMA_ALLOC(dma_ctx, size, dma_addr);
11985 + if (add_allocation(dma_ctx, size, func, line, addr, 1)) {
11986 + __DWC_DMA_FREE(dma_ctx, size, addr, *dma_addr);
11993 +void *dwc_dma_alloc_atomic_debug(void *dma_ctx, uint32_t size,
11994 + dwc_dma_t *dma_addr, char const *func, int line)
11996 + void *addr = __DWC_DMA_ALLOC_ATOMIC(dma_ctx, size, dma_addr);
12002 + if (add_allocation(dma_ctx, size, func, line, addr, 1)) {
12003 + __DWC_DMA_FREE(dma_ctx, size, addr, *dma_addr);
12010 +void dwc_dma_free_debug(void *dma_ctx, uint32_t size, void *virt_addr,
12011 + dwc_dma_t dma_addr, char const *func, int line)
12013 + free_allocation(dma_ctx, virt_addr, func, line);
12014 + __DWC_DMA_FREE(dma_ctx, size, virt_addr, dma_addr);
12017 +#endif /* DWC_DEBUG_MEMORY */
12019 +++ b/drivers/usb/host/dwc_common_port/dwc_modpow.c
12021 +/* Bignum routines adapted from PUTTY sources. PuTTY copyright notice follows.
12023 + * PuTTY is copyright 1997-2007 Simon Tatham.
12025 + * Portions copyright Robert de Bath, Joris van Rantwijk, Delian
12026 + * Delchev, Andreas Schultz, Jeroen Massar, Wez Furlong, Nicolas Barry,
12027 + * Justin Bradford, Ben Harris, Malcolm Smith, Ahmad Khalifa, Markus
12028 + * Kuhn, and CORE SDI S.A.
12030 + * Permission is hereby granted, free of charge, to any person
12031 + * obtaining a copy of this software and associated documentation files
12032 + * (the "Software"), to deal in the Software without restriction,
12033 + * including without limitation the rights to use, copy, modify, merge,
12034 + * publish, distribute, sublicense, and/or sell copies of the Software,
12035 + * and to permit persons to whom the Software is furnished to do so,
12036 + * subject to the following conditions:
12038 + * The above copyright notice and this permission notice shall be
12039 + * included in all copies or substantial portions of the Software.
12041 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
12042 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12043 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
12044 + * NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE
12045 + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
12046 + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
12047 + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
12050 +#ifdef DWC_CRYPTOLIB
12052 +#ifndef CONFIG_MACH_IPMATE
12054 +#include "dwc_modpow.h"
12056 +#define BIGNUM_INT_MASK 0xFFFFFFFFUL
12057 +#define BIGNUM_TOP_BIT 0x80000000UL
12058 +#define BIGNUM_INT_BITS 32
12061 +static void *snmalloc(void *mem_ctx, size_t n, size_t size)
12065 + if (size == 0) size = 1;
12066 + p = dwc_alloc(mem_ctx, size);
12070 +#define snewn(ctx, n, type) ((type *)snmalloc((ctx), (n), sizeof(type)))
12071 +#define sfree dwc_free
12075 + * * Do not call the DIVMOD_WORD macro with expressions such as array
12076 + * subscripts, as some implementations object to this (see below).
12077 + * * Note that none of the division methods below will cope if the
12078 + * quotient won't fit into BIGNUM_INT_BITS. Callers should be careful
12079 + * to avoid this case.
12080 + * If this condition occurs, in the case of the x86 DIV instruction,
12081 + * an overflow exception will occur, which (according to a correspondent)
12082 + * will manifest on Windows as something like
12083 + * 0xC0000095: Integer overflow
12084 + * The C variant won't give the right answer, either.
12087 +#define MUL_WORD(w1, w2) ((BignumDblInt)w1 * w2)
12089 +#if defined __GNUC__ && defined __i386__
12090 +#define DIVMOD_WORD(q, r, hi, lo, w) \
12091 + __asm__("div %2" : \
12092 + "=d" (r), "=a" (q) : \
12093 + "r" (w), "d" (hi), "a" (lo))
12095 +#define DIVMOD_WORD(q, r, hi, lo, w) do { \
12096 + BignumDblInt n = (((BignumDblInt)hi) << BIGNUM_INT_BITS) | lo; \
12105 +#define BIGNUM_INT_BYTES (BIGNUM_INT_BITS / 8)
12107 +#define BIGNUM_INTERNAL
12109 +static Bignum newbn(void *mem_ctx, int length)
12111 + Bignum b = snewn(mem_ctx, length + 1, BignumInt);
12113 + //abort(); /* FIXME */
12114 + DWC_MEMSET(b, 0, (length + 1) * sizeof(*b));
12119 +void freebn(void *mem_ctx, Bignum b)
12122 + * Burn the evidence, just in case.
12124 + DWC_MEMSET(b, 0, sizeof(b[0]) * (b[0] + 1));
12125 + sfree(mem_ctx, b);
12129 + * Compute c = a * b.
12130 + * Input is in the first len words of a and b.
12131 + * Result is returned in the first 2*len words of c.
12133 +static void internal_mul(BignumInt *a, BignumInt *b,
12134 + BignumInt *c, int len)
12139 + for (j = 0; j < 2 * len; j++)
12142 + for (i = len - 1; i >= 0; i--) {
12144 + for (j = len - 1; j >= 0; j--) {
12145 + t += MUL_WORD(a[i], (BignumDblInt) b[j]);
12146 + t += (BignumDblInt) c[i + j + 1];
12147 + c[i + j + 1] = (BignumInt) t;
12148 + t = t >> BIGNUM_INT_BITS;
12150 + c[i] = (BignumInt) t;
12154 +static void internal_add_shifted(BignumInt *number,
12155 + unsigned n, int shift)
12157 + int word = 1 + (shift / BIGNUM_INT_BITS);
12158 + int bshift = shift % BIGNUM_INT_BITS;
12159 + BignumDblInt addend;
12161 + addend = (BignumDblInt)n << bshift;
12164 + addend += number[word];
12165 + number[word] = (BignumInt) addend & BIGNUM_INT_MASK;
12166 + addend >>= BIGNUM_INT_BITS;
12172 + * Compute a = a % m.
12173 + * Input in first alen words of a and first mlen words of m.
12174 + * Output in first alen words of a
12175 + * (of which first alen-mlen words will be zero).
12176 + * The MSW of m MUST have its high bit set.
12177 + * Quotient is accumulated in the `quotient' array, which is a Bignum
12178 + * rather than the internal bigendian format. Quotient parts are shifted
12179 + * left by `qshift' before adding into quot.
12181 +static void internal_mod(BignumInt *a, int alen,
12182 + BignumInt *m, int mlen,
12183 + BignumInt *quot, int qshift)
12185 + BignumInt m0, m1;
12195 + for (i = 0; i <= alen - mlen; i++) {
12197 + unsigned int q, r, c, ai1;
12206 + if (i == alen - 1)
12211 + /* Find q = h:a[i] / m0 */
12216 + * To illustrate it, suppose a BignumInt is 8 bits, and
12217 + * we are dividing (say) A1:23:45:67 by A1:B2:C3. Then
12218 + * our initial division will be 0xA123 / 0xA1, which
12219 + * will give a quotient of 0x100 and a divide overflow.
12220 + * However, the invariants in this division algorithm
12221 + * are not violated, since the full number A1:23:... is
12222 + * _less_ than the quotient prefix A1:B2:... and so the
12223 + * following correction loop would have sorted it out.
12225 + * In this situation we set q to be the largest
12226 + * quotient we _can_ stomach (0xFF, of course).
12228 + q = BIGNUM_INT_MASK;
12230 + /* Macro doesn't want an array subscript expression passed
12231 + * into it (see definition), so use a temporary. */
12232 + BignumInt tmplo = a[i];
12233 + DIVMOD_WORD(q, r, h, tmplo, m0);
12235 + /* Refine our estimate of q by looking at
12236 + h:a[i]:a[i+1] / m0:m1 */
12237 + t = MUL_WORD(m1, q);
12238 + if (t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) {
12241 + r = (r + m0) & BIGNUM_INT_MASK; /* overflow? */
12242 + if (r >= (BignumDblInt) m0 &&
12243 + t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) q--;
12247 + /* Subtract q * m from a[i...] */
12249 + for (k = mlen - 1; k >= 0; k--) {
12250 + t = MUL_WORD(q, m[k]);
12252 + c = (unsigned)(t >> BIGNUM_INT_BITS);
12253 + if ((BignumInt) t > a[i + k])
12255 + a[i + k] -= (BignumInt) t;
12258 + /* Add back m in case of borrow */
12261 + for (k = mlen - 1; k >= 0; k--) {
12264 + a[i + k] = (BignumInt) t;
12265 + t = t >> BIGNUM_INT_BITS;
12270 + internal_add_shifted(quot, q, qshift + BIGNUM_INT_BITS * (alen - mlen - i));
12275 + * Compute p % mod.
12276 + * The most significant word of mod MUST be non-zero.
12277 + * We assume that the result array is the same size as the mod array.
12278 + * We optionally write out a quotient if `quotient' is non-NULL.
12279 + * We can avoid writing out the result if `result' is NULL.
12281 +void bigdivmod(void *mem_ctx, Bignum p, Bignum mod, Bignum result, Bignum quotient)
12283 + BignumInt *n, *m;
12285 + int plen, mlen, i, j;
12287 + /* Allocate m of size mlen, copy mod to m */
12288 + /* We use big endian internally */
12290 + m = snewn(mem_ctx, mlen, BignumInt);
12292 + //abort(); /* FIXME */
12293 + for (j = 0; j < mlen; j++)
12294 + m[j] = mod[mod[0] - j];
12296 + /* Shift m left to make msb bit set */
12297 + for (mshift = 0; mshift < BIGNUM_INT_BITS-1; mshift++)
12298 + if ((m[0] << mshift) & BIGNUM_TOP_BIT)
12301 + for (i = 0; i < mlen - 1; i++)
12302 + m[i] = (m[i] << mshift) | (m[i + 1] >> (BIGNUM_INT_BITS - mshift));
12303 + m[mlen - 1] = m[mlen - 1] << mshift;
12307 + /* Ensure plen > mlen */
12308 + if (plen <= mlen)
12311 + /* Allocate n of size plen, copy p to n */
12312 + n = snewn(mem_ctx, plen, BignumInt);
12314 + //abort(); /* FIXME */
12315 + for (j = 0; j < plen; j++)
12317 + for (j = 1; j <= (int)p[0]; j++)
12318 + n[plen - j] = p[j];
12320 + /* Main computation */
12321 + internal_mod(n, plen, m, mlen, quotient, mshift);
12323 + /* Fixup result in case the modulus was shifted */
12325 + for (i = plen - mlen - 1; i < plen - 1; i++)
12326 + n[i] = (n[i] << mshift) | (n[i + 1] >> (BIGNUM_INT_BITS - mshift));
12327 + n[plen - 1] = n[plen - 1] << mshift;
12328 + internal_mod(n, plen, m, mlen, quotient, 0);
12329 + for (i = plen - 1; i >= plen - mlen; i--)
12330 + n[i] = (n[i] >> mshift) | (n[i - 1] << (BIGNUM_INT_BITS - mshift));
12333 + /* Copy result to buffer */
12335 + for (i = 1; i <= (int)result[0]; i++) {
12336 + int j = plen - i;
12337 + result[i] = j >= 0 ? n[j] : 0;
12341 + /* Free temporary arrays */
12342 + for (i = 0; i < mlen; i++)
12344 + sfree(mem_ctx, m);
12345 + for (i = 0; i < plen; i++)
12347 + sfree(mem_ctx, n);
12351 + * Simple remainder.
12353 +Bignum bigmod(void *mem_ctx, Bignum a, Bignum b)
12355 + Bignum r = newbn(mem_ctx, b[0]);
12356 + bigdivmod(mem_ctx, a, b, r, NULL);
12361 + * Compute (base ^ exp) % mod.
12363 +Bignum dwc_modpow(void *mem_ctx, Bignum base_in, Bignum exp, Bignum mod)
12365 + BignumInt *a, *b, *n, *m;
12368 + Bignum base, result;
12371 + * The most significant word of mod needs to be non-zero. It
12372 + * should already be, but let's make sure.
12374 + //assert(mod[mod[0]] != 0);
12377 + * Make sure the base is smaller than the modulus, by reducing
12378 + * it modulo the modulus if not.
12380 + base = bigmod(mem_ctx, base_in, mod);
12382 + /* Allocate m of size mlen, copy mod to m */
12383 + /* We use big endian internally */
12385 + m = snewn(mem_ctx, mlen, BignumInt);
12387 + //abort(); /* FIXME */
12388 + for (j = 0; j < mlen; j++)
12389 + m[j] = mod[mod[0] - j];
12391 + /* Shift m left to make msb bit set */
12392 + for (mshift = 0; mshift < BIGNUM_INT_BITS - 1; mshift++)
12393 + if ((m[0] << mshift) & BIGNUM_TOP_BIT)
12396 + for (i = 0; i < mlen - 1; i++)
12398 + (m[i] << mshift) | (m[i + 1] >>
12399 + (BIGNUM_INT_BITS - mshift));
12400 + m[mlen - 1] = m[mlen - 1] << mshift;
12403 + /* Allocate n of size mlen, copy base to n */
12404 + n = snewn(mem_ctx, mlen, BignumInt);
12406 + //abort(); /* FIXME */
12407 + i = mlen - base[0];
12408 + for (j = 0; j < i; j++)
12410 + for (j = 0; j < base[0]; j++)
12411 + n[i + j] = base[base[0] - j];
12413 + /* Allocate a and b of size 2*mlen. Set a = 1 */
12414 + a = snewn(mem_ctx, 2 * mlen, BignumInt);
12416 + //abort(); /* FIXME */
12417 + b = snewn(mem_ctx, 2 * mlen, BignumInt);
12419 + //abort(); /* FIXME */
12420 + for (i = 0; i < 2 * mlen; i++)
12422 + a[2 * mlen - 1] = 1;
12424 + /* Skip leading zero bits of exp. */
12426 + j = BIGNUM_INT_BITS - 1;
12427 + while (i < exp[0] && (exp[exp[0] - i] & (1 << j)) == 0) {
12431 + j = BIGNUM_INT_BITS - 1;
12435 + /* Main computation */
12436 + while (i < exp[0]) {
12438 + internal_mul(a + mlen, a + mlen, b, mlen);
12439 + internal_mod(b, mlen * 2, m, mlen, NULL, 0);
12440 + if ((exp[exp[0] - i] & (1 << j)) != 0) {
12441 + internal_mul(b + mlen, n, a, mlen);
12442 + internal_mod(a, mlen * 2, m, mlen, NULL, 0);
12452 + j = BIGNUM_INT_BITS - 1;
12455 + /* Fixup result in case the modulus was shifted */
12457 + for (i = mlen - 1; i < 2 * mlen - 1; i++)
12459 + (a[i] << mshift) | (a[i + 1] >>
12460 + (BIGNUM_INT_BITS - mshift));
12461 + a[2 * mlen - 1] = a[2 * mlen - 1] << mshift;
12462 + internal_mod(a, mlen * 2, m, mlen, NULL, 0);
12463 + for (i = 2 * mlen - 1; i >= mlen; i--)
12465 + (a[i] >> mshift) | (a[i - 1] <<
12466 + (BIGNUM_INT_BITS - mshift));
12469 + /* Copy result to buffer */
12470 + result = newbn(mem_ctx, mod[0]);
12471 + for (i = 0; i < mlen; i++)
12472 + result[result[0] - i] = a[i + mlen];
12473 + while (result[0] > 1 && result[result[0]] == 0)
12476 + /* Free temporary arrays */
12477 + for (i = 0; i < 2 * mlen; i++)
12479 + sfree(mem_ctx, a);
12480 + for (i = 0; i < 2 * mlen; i++)
12482 + sfree(mem_ctx, b);
12483 + for (i = 0; i < mlen; i++)
12485 + sfree(mem_ctx, m);
12486 + for (i = 0; i < mlen; i++)
12488 + sfree(mem_ctx, n);
12490 + freebn(mem_ctx, base);
12498 +static __u32 dh_p[] = {
12598 +static __u32 dh_a[] = {
12610 +static __u32 dh_b[] = {
12622 +static __u32 dh_g[] = {
12631 + k = dwc_modpow(NULL, dh_g, dh_a, dh_p);
12634 + for (i=0; i<k[0]; i++) {
12635 + __u32 word32 = k[k[0] - i];
12636 + __u16 l = word32 & 0xffff;
12637 + __u16 m = (word32 & 0xffff0000) >> 16;
12638 + printf("%04x %04x ", m, l);
12639 + if (!((i + 1)%13)) printf("\n");
12643 + if ((k[0] == 0x60) && (k[1] == 0x28e490e5) && (k[0x60] == 0x5a0d3d4e)) {
12644 + printf("PASS\n\n");
12647 + printf("FAIL\n\n");
12652 +#endif /* UNITTEST */
12654 +#endif /* CONFIG_MACH_IPMATE */
12656 +#endif /*DWC_CRYPTOLIB */
12658 +++ b/drivers/usb/host/dwc_common_port/dwc_modpow.h
12662 + * See dwc_modpow.c for license and changes
12664 +#ifndef _DWC_MODPOW_H
12665 +#define _DWC_MODPOW_H
12667 +#ifdef __cplusplus
12671 +#include "dwc_os.h"
12675 + * This file defines the module exponentiation function which is only used
12676 + * internally by the DWC UWB modules for calculation of PKs during numeric
12677 + * association. The routine is taken from the PUTTY, an open source terminal
12678 + * emulator. The PUTTY License is preserved in the dwc_modpow.c file.
12682 +typedef uint32_t BignumInt;
12683 +typedef uint64_t BignumDblInt;
12684 +typedef BignumInt *Bignum;
12686 +/* Compute modular exponentiaion */
12687 +extern Bignum dwc_modpow(void *mem_ctx, Bignum base_in, Bignum exp, Bignum mod);
12689 +#ifdef __cplusplus
12693 +#endif /* _LINUX_BIGNUM_H */
12695 +++ b/drivers/usb/host/dwc_common_port/dwc_notifier.c
12697 +#ifdef DWC_NOTIFYLIB
12699 +#include "dwc_notifier.h"
12700 +#include "dwc_list.h"
12702 +typedef struct dwc_observer {
12704 + dwc_notifier_callback_t callback;
12706 + char *notification;
12707 + DWC_CIRCLEQ_ENTRY(dwc_observer) list_entry;
12710 +DWC_CIRCLEQ_HEAD(observer_queue, dwc_observer);
12712 +typedef struct dwc_notifier {
12715 + struct observer_queue observers;
12716 + DWC_CIRCLEQ_ENTRY(dwc_notifier) list_entry;
12719 +DWC_CIRCLEQ_HEAD(notifier_queue, dwc_notifier);
12721 +typedef struct manager {
12725 +// dwc_mutex_t *mutex;
12726 + struct notifier_queue notifiers;
12729 +static manager_t *manager = NULL;
12731 +static int create_manager(void *mem_ctx, void *wkq_ctx)
12733 + manager = dwc_alloc(mem_ctx, sizeof(manager_t));
12735 + return -DWC_E_NO_MEMORY;
12738 + DWC_CIRCLEQ_INIT(&manager->notifiers);
12740 + manager->wq = dwc_workq_alloc(wkq_ctx, "DWC Notification WorkQ");
12741 + if (!manager->wq) {
12742 + return -DWC_E_NO_MEMORY;
12748 +static void free_manager(void)
12750 + dwc_workq_free(manager->wq);
12752 + /* All notifiers must have unregistered themselves before this module
12753 + * can be removed. Hitting this assertion indicates a programmer
12755 + DWC_ASSERT(DWC_CIRCLEQ_EMPTY(&manager->notifiers),
12756 + "Notification manager being freed before all notifiers have been removed");
12757 + dwc_free(manager->mem_ctx, manager);
12761 +static void dump_manager(void)
12766 + DWC_ASSERT(manager, "Notification manager not found");
12768 + DWC_DEBUG("List of all notifiers and observers:\n");
12769 + DWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) {
12770 + DWC_DEBUG("Notifier %p has observers:\n", n->object);
12771 + DWC_CIRCLEQ_FOREACH(o, &n->observers, list_entry) {
12772 + DWC_DEBUG(" %p watching %s\n", o->observer, o->notification);
12777 +#define dump_manager(...)
12780 +static observer_t *alloc_observer(void *mem_ctx, void *observer, char *notification,
12781 + dwc_notifier_callback_t callback, void *data)
12783 + observer_t *new_observer = dwc_alloc(mem_ctx, sizeof(observer_t));
12785 + if (!new_observer) {
12789 + DWC_CIRCLEQ_INIT_ENTRY(new_observer, list_entry);
12790 + new_observer->observer = observer;
12791 + new_observer->notification = notification;
12792 + new_observer->callback = callback;
12793 + new_observer->data = data;
12794 + return new_observer;
12797 +static void free_observer(void *mem_ctx, observer_t *observer)
12799 + dwc_free(mem_ctx, observer);
12802 +static notifier_t *alloc_notifier(void *mem_ctx, void *object)
12804 + notifier_t *notifier;
12810 + notifier = dwc_alloc(mem_ctx, sizeof(notifier_t));
12815 + DWC_CIRCLEQ_INIT(¬ifier->observers);
12816 + DWC_CIRCLEQ_INIT_ENTRY(notifier, list_entry);
12818 + notifier->mem_ctx = mem_ctx;
12819 + notifier->object = object;
12823 +static void free_notifier(notifier_t *notifier)
12825 + observer_t *observer;
12827 + DWC_CIRCLEQ_FOREACH(observer, ¬ifier->observers, list_entry) {
12828 + free_observer(notifier->mem_ctx, observer);
12831 + dwc_free(notifier->mem_ctx, notifier);
12834 +static notifier_t *find_notifier(void *object)
12836 + notifier_t *notifier;
12838 + DWC_ASSERT(manager, "Notification manager not found");
12844 + DWC_CIRCLEQ_FOREACH(notifier, &manager->notifiers, list_entry) {
12845 + if (notifier->object == object) {
12853 +int dwc_alloc_notification_manager(void *mem_ctx, void *wkq_ctx)
12855 + return create_manager(mem_ctx, wkq_ctx);
12858 +void dwc_free_notification_manager(void)
12863 +dwc_notifier_t *dwc_register_notifier(void *mem_ctx, void *object)
12865 + notifier_t *notifier;
12867 + DWC_ASSERT(manager, "Notification manager not found");
12869 + notifier = find_notifier(object);
12871 + DWC_ERROR("Notifier %p is already registered\n", object);
12875 + notifier = alloc_notifier(mem_ctx, object);
12880 + DWC_CIRCLEQ_INSERT_TAIL(&manager->notifiers, notifier, list_entry);
12882 + DWC_INFO("Notifier %p registered", object);
12888 +void dwc_unregister_notifier(dwc_notifier_t *notifier)
12890 + DWC_ASSERT(manager, "Notification manager not found");
12892 + if (!DWC_CIRCLEQ_EMPTY(¬ifier->observers)) {
12895 + DWC_ERROR("Notifier %p has active observers when removing\n", notifier->object);
12896 + DWC_CIRCLEQ_FOREACH(o, ¬ifier->observers, list_entry) {
12897 + DWC_DEBUGC(" %p watching %s\n", o->observer, o->notification);
12900 + DWC_ASSERT(DWC_CIRCLEQ_EMPTY(¬ifier->observers),
12901 + "Notifier %p has active observers when removing", notifier);
12904 + DWC_CIRCLEQ_REMOVE_INIT(&manager->notifiers, notifier, list_entry);
12905 + free_notifier(notifier);
12907 + DWC_INFO("Notifier unregistered");
12911 +/* Add an observer to observe the notifier for a particular state, event, or notification. */
12912 +int dwc_add_observer(void *observer, void *object, char *notification,
12913 + dwc_notifier_callback_t callback, void *data)
12915 + notifier_t *notifier = find_notifier(object);
12916 + observer_t *new_observer;
12919 + DWC_ERROR("Notifier %p is not found when adding observer\n", object);
12920 + return -DWC_E_INVALID;
12923 + new_observer = alloc_observer(notifier->mem_ctx, observer, notification, callback, data);
12924 + if (!new_observer) {
12925 + return -DWC_E_NO_MEMORY;
12928 + DWC_CIRCLEQ_INSERT_TAIL(¬ifier->observers, new_observer, list_entry);
12930 + DWC_INFO("Added observer %p to notifier %p observing notification %s, callback=%p, data=%p",
12931 + observer, object, notification, callback, data);
12937 +int dwc_remove_observer(void *observer)
12941 + DWC_ASSERT(manager, "Notification manager not found");
12943 + DWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) {
12947 + DWC_CIRCLEQ_FOREACH_SAFE(o, o2, &n->observers, list_entry) {
12948 + if (o->observer == observer) {
12949 + DWC_CIRCLEQ_REMOVE_INIT(&n->observers, o, list_entry);
12950 + DWC_INFO("Removing observer %p from notifier %p watching notification %s:",
12951 + o->observer, n->object, o->notification);
12952 + free_observer(n->mem_ctx, o);
12961 +typedef struct callback_data {
12963 + dwc_notifier_callback_t cb;
12967 + char *notification;
12968 + void *notification_data;
12971 +static void cb_task(void *data)
12973 + cb_data_t *cb = (cb_data_t *)data;
12975 + cb->cb(cb->object, cb->notification, cb->observer, cb->notification_data, cb->data);
12976 + dwc_free(cb->mem_ctx, cb);
12979 +void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data)
12983 + DWC_ASSERT(manager, "Notification manager not found");
12985 + DWC_CIRCLEQ_FOREACH(o, ¬ifier->observers, list_entry) {
12986 + int len = DWC_STRLEN(notification);
12988 + if (DWC_STRLEN(o->notification) != len) {
12992 + if (DWC_STRNCMP(o->notification, notification, len) == 0) {
12993 + cb_data_t *cb_data = dwc_alloc(notifier->mem_ctx, sizeof(cb_data_t));
12996 + DWC_ERROR("Failed to allocate callback data\n");
13000 + cb_data->mem_ctx = notifier->mem_ctx;
13001 + cb_data->cb = o->callback;
13002 + cb_data->observer = o->observer;
13003 + cb_data->data = o->data;
13004 + cb_data->object = notifier->object;
13005 + cb_data->notification = notification;
13006 + cb_data->notification_data = notification_data;
13007 + DWC_DEBUGC("Observer found %p for notification %s\n", o->observer, notification);
13008 + DWC_WORKQ_SCHEDULE(manager->wq, cb_task, cb_data,
13009 + "Notify callback from %p for Notification %s, to observer %p",
13010 + cb_data->object, notification, cb_data->observer);
13015 +#endif /* DWC_NOTIFYLIB */
13017 +++ b/drivers/usb/host/dwc_common_port/dwc_notifier.h
13020 +#ifndef __DWC_NOTIFIER_H__
13021 +#define __DWC_NOTIFIER_H__
13023 +#ifdef __cplusplus
13027 +#include "dwc_os.h"
13031 + * A simple implementation of the Observer pattern. Any "module" can
13032 + * register as an observer or notifier. The notion of "module" is abstract and
13033 + * can mean anything used to identify either an observer or notifier. Usually
13034 + * it will be a pointer to a data structure which contains some state, ie an
13037 + * Before any notifiers can be added, the global notification manager must be
13038 + * brought up with dwc_alloc_notification_manager().
13039 + * dwc_free_notification_manager() will bring it down and free all resources.
13040 + * These would typically be called upon module load and unload. The
13041 + * notification manager is a single global instance that handles all registered
13042 + * observable modules and observers so this should be done only once.
13044 + * A module can be observable by using Notifications to publicize some general
13045 + * information about it's state or operation. It does not care who listens, or
13046 + * even if anyone listens, or what they do with the information. The observable
13047 + * modules do not need to know any information about it's observers or their
13048 + * interface, or their state or data.
13050 + * Any module can register to emit Notifications. It should publish a list of
13051 + * notifications that it can emit and their behavior, such as when they will get
13052 + * triggered, and what information will be provided to the observer. Then it
13053 + * should register itself as an observable module. See dwc_register_notifier().
13055 + * Any module can observe any observable, registered module, provided it has a
13056 + * handle to the other module and knows what notifications to observe. See
13057 + * dwc_add_observer().
13059 + * A function of type dwc_notifier_callback_t is called whenever a notification
13060 + * is triggered with one or more observers observing it. This function is
13061 + * called in it's own process so it may sleep or block if needed. It is
13062 + * guaranteed to be called sometime after the notification has occurred and will
13063 + * be called once per each time the notification is triggered. It will NOT be
13064 + * called in the same process context used to trigger the notification.
13066 + * @section Limitiations
13068 + * Keep in mind that Notifications that can be triggered in rapid sucession may
13069 + * schedule too many processes too handle. Be aware of this limitation when
13070 + * designing to use notifications, and only add notifications for appropriate
13071 + * observable information.
13073 + * Also Notification callbacks are not synchronous. If you need to synchronize
13074 + * the behavior between module/observer you must use other means. And perhaps
13075 + * that will mean Notifications are not the proper solution.
13078 +struct dwc_notifier;
13079 +typedef struct dwc_notifier dwc_notifier_t;
13081 +/** The callback function must be of this type.
13083 + * @param object This is the object that is being observed.
13084 + * @param notification This is the notification that was triggered.
13085 + * @param observer This is the observer
13086 + * @param notification_data This is notification-specific data that the notifier
13087 + * has included in this notification. The value of this should be published in
13088 + * the documentation of the observable module with the notifications.
13089 + * @param user_data This is any custom data that the observer provided when
13090 + * adding itself as an observer to the notification. */
13091 +typedef void (*dwc_notifier_callback_t)(void *object, char *notification, void *observer,
13092 + void *notification_data, void *user_data);
13094 +/** Brings up the notification manager. */
13095 +extern int dwc_alloc_notification_manager(void *mem_ctx, void *wkq_ctx);
13096 +/** Brings down the notification manager. */
13097 +extern void dwc_free_notification_manager(void);
13099 +/** This function registers an observable module. A dwc_notifier_t object is
13100 + * returned to the observable module. This is an opaque object that is used by
13101 + * the observable module to trigger notifications. This object should only be
13102 + * accessible to functions that are authorized to trigger notifications for this
13103 + * module. Observers do not need this object. */
13104 +extern dwc_notifier_t *dwc_register_notifier(void *mem_ctx, void *object);
13106 +/** This function unregisters an observable module. All observers have to be
13107 + * removed prior to unregistration. */
13108 +extern void dwc_unregister_notifier(dwc_notifier_t *notifier);
13110 +/** Add a module as an observer to the observable module. The observable module
13111 + * needs to have previously registered with the notification manager.
13113 + * @param observer The observer module
13114 + * @param object The module to observe
13115 + * @param notification The notification to observe
13116 + * @param callback The callback function to call
13117 + * @param user_data Any additional user data to pass into the callback function */
13118 +extern int dwc_add_observer(void *observer, void *object, char *notification,
13119 + dwc_notifier_callback_t callback, void *user_data);
13121 +/** Removes the specified observer from all notifications that it is currently
13123 +extern int dwc_remove_observer(void *observer);
13125 +/** This function triggers a Notification. It should be called by the
13126 + * observable module, or any module or library which the observable module
13127 + * allows to trigger notification on it's behalf. Such as the dwc_cc_t.
13129 + * dwc_notify is a non-blocking function. Callbacks are scheduled called in
13130 + * their own process context for each trigger. Callbacks can be blocking.
13131 + * dwc_notify can be called from interrupt context if needed.
13134 +void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data);
13136 +#ifdef __cplusplus
13140 +#endif /* __DWC_NOTIFIER_H__ */
13142 +++ b/drivers/usb/host/dwc_common_port/dwc_os.h
13144 +/* =========================================================================
13145 + * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_os.h $
13146 + * $Revision: #14 $
13147 + * $Date: 2010/11/04 $
13148 + * $Change: 1621695 $
13150 + * Synopsys Portability Library Software and documentation
13151 + * (hereinafter, "Software") is an Unsupported proprietary work of
13152 + * Synopsys, Inc. unless otherwise expressly agreed to in writing
13153 + * between Synopsys and you.
13155 + * The Software IS NOT an item of Licensed Software or Licensed Product
13156 + * under any End User Software License Agreement or Agreement for
13157 + * Licensed Product with Synopsys or any supplement thereto. You are
13158 + * permitted to use and redistribute this Software in source and binary
13159 + * forms, with or without modification, provided that redistributions
13160 + * of source code must retain this notice. You may not view, use,
13161 + * disclose, copy or distribute this file or any information contained
13162 + * herein except pursuant to this license grant from Synopsys. If you
13163 + * do not agree with this notice, including the disclaimer below, then
13164 + * you are not authorized to use the Software.
13166 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
13167 + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
13168 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
13169 + * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
13170 + * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
13171 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
13172 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
13173 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
13174 + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
13175 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
13176 + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
13178 + * ========================================================================= */
13179 +#ifndef _DWC_OS_H_
13180 +#define _DWC_OS_H_
13182 +#ifdef __cplusplus
13188 + * DWC portability library, low level os-wrapper functions
13192 +/* These basic types need to be defined by some OS header file or custom header
13193 + * file for your specific target architecture.
13195 + * uint8_t, int8_t, uint16_t, int16_t, uint32_t, int32_t, uint64_t, int64_t
13197 + * Any custom or alternate header file must be added and enabled here.
13201 +# include <linux/types.h>
13202 +# ifdef CONFIG_DEBUG_MUTEXES
13203 +# include <linux/mutex.h>
13205 +# include <linux/spinlock.h>
13206 +# include <linux/errno.h>
13207 +# include <stdarg.h>
13210 +#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
13211 +# include <os_dep.h>
13215 +/** @name Primitive Types and Values */
13217 +/** We define a boolean type for consistency. Can be either YES or NO */
13218 +typedef uint8_t dwc_bool_t;
13224 +/** @name Error Codes */
13225 +#define DWC_E_INVALID EINVAL
13226 +#define DWC_E_NO_MEMORY ENOMEM
13227 +#define DWC_E_NO_DEVICE ENODEV
13228 +#define DWC_E_NOT_SUPPORTED EOPNOTSUPP
13229 +#define DWC_E_TIMEOUT ETIMEDOUT
13230 +#define DWC_E_BUSY EBUSY
13231 +#define DWC_E_AGAIN EAGAIN
13232 +#define DWC_E_RESTART ERESTART
13233 +#define DWC_E_ABORT ECONNABORTED
13234 +#define DWC_E_SHUTDOWN ESHUTDOWN
13235 +#define DWC_E_NO_DATA ENODATA
13236 +#define DWC_E_DISCONNECT ECONNRESET
13237 +#define DWC_E_UNKNOWN EINVAL
13238 +#define DWC_E_NO_STREAM_RES ENOSR
13239 +#define DWC_E_COMMUNICATION ECOMM
13240 +#define DWC_E_OVERFLOW EOVERFLOW
13241 +#define DWC_E_PROTOCOL EPROTO
13242 +#define DWC_E_IN_PROGRESS EINPROGRESS
13243 +#define DWC_E_PIPE EPIPE
13244 +#define DWC_E_IO EIO
13245 +#define DWC_E_NO_SPACE ENOSPC
13249 +/** @name Error Codes */
13250 +#define DWC_E_INVALID 1001
13251 +#define DWC_E_NO_MEMORY 1002
13252 +#define DWC_E_NO_DEVICE 1003
13253 +#define DWC_E_NOT_SUPPORTED 1004
13254 +#define DWC_E_TIMEOUT 1005
13255 +#define DWC_E_BUSY 1006
13256 +#define DWC_E_AGAIN 1007
13257 +#define DWC_E_RESTART 1008
13258 +#define DWC_E_ABORT 1009
13259 +#define DWC_E_SHUTDOWN 1010
13260 +#define DWC_E_NO_DATA 1011
13261 +#define DWC_E_DISCONNECT 2000
13262 +#define DWC_E_UNKNOWN 3000
13263 +#define DWC_E_NO_STREAM_RES 4001
13264 +#define DWC_E_COMMUNICATION 4002
13265 +#define DWC_E_OVERFLOW 4003
13266 +#define DWC_E_PROTOCOL 4004
13267 +#define DWC_E_IN_PROGRESS 4005
13268 +#define DWC_E_PIPE 4006
13269 +#define DWC_E_IO 4007
13270 +#define DWC_E_NO_SPACE 4008
13275 +/** @name Tracing/Logging Functions
13277 + * These function provide the capability to add tracing, debugging, and error
13278 + * messages, as well exceptions as assertions. The WUDEV uses these
13279 + * extensively. These could be logged to the main console, the serial port, an
13280 + * internal buffer, etc. These functions could also be no-op if they are too
13281 + * expensive on your system. By default undefining the DEBUG macro already
13282 + * no-ops some of these functions. */
13284 +/** Returns non-zero if in interrupt context. */
13285 +extern dwc_bool_t DWC_IN_IRQ(void);
13286 +#define dwc_in_irq DWC_IN_IRQ
13288 +/** Returns "IRQ" if DWC_IN_IRQ is true. */
13289 +static inline char *dwc_irq(void) {
13290 + return DWC_IN_IRQ() ? "IRQ" : "";
13293 +/** Returns non-zero if in bottom-half context. */
13294 +extern dwc_bool_t DWC_IN_BH(void);
13295 +#define dwc_in_bh DWC_IN_BH
13297 +/** Returns "BH" if DWC_IN_BH is true. */
13298 +static inline char *dwc_bh(void) {
13299 + return DWC_IN_BH() ? "BH" : "";
13303 + * A vprintf() clone. Just call vprintf if you've got it.
13305 +extern void DWC_VPRINTF(char *format, va_list args);
13306 +#define dwc_vprintf DWC_VPRINTF
13309 + * A vsnprintf() clone. Just call vprintf if you've got it.
13311 +extern int DWC_VSNPRINTF(char *str, int size, char *format, va_list args);
13312 +#define dwc_vsnprintf DWC_VSNPRINTF
13315 + * printf() clone. Just call printf if you've go it.
13317 +extern void DWC_PRINTF(char *format, ...)
13318 +/* This provides compiler level static checking of the parameters if you're
13321 + __attribute__ ((format(printf, 1, 2)));
13325 +#define dwc_printf DWC_PRINTF
13328 + * sprintf() clone. Just call sprintf if you've got it.
13330 +extern int DWC_SPRINTF(char *string, char *format, ...)
13332 + __attribute__ ((format(printf, 2, 3)));
13336 +#define dwc_sprintf DWC_SPRINTF
13339 + * snprintf() clone. Just call snprintf if you've got it.
13341 +extern int DWC_SNPRINTF(char *string, int size, char *format, ...)
13343 + __attribute__ ((format(printf, 3, 4)));
13347 +#define dwc_snprintf DWC_SNPRINTF
13350 + * Prints a WARNING message. On systems that don't differentiate between
13351 + * warnings and regular log messages, just print it. Indicates that something
13352 + * may be wrong with the driver. Works like printf().
13354 + * Use the DWC_WARN macro to call this function.
13356 +extern void __DWC_WARN(char *format, ...)
13358 + __attribute__ ((format(printf, 1, 2)));
13364 + * Prints an error message. On systems that don't differentiate between errors
13365 + * and regular log messages, just print it. Indicates that something went wrong
13366 + * with the driver. Works like printf().
13368 + * Use the DWC_ERROR macro to call this function.
13370 +extern void __DWC_ERROR(char *format, ...)
13372 + __attribute__ ((format(printf, 1, 2)));
13378 + * Prints an exception error message and takes some user-defined action such as
13379 + * print out a backtrace or trigger a breakpoint. Indicates that something went
13380 + * abnormally wrong with the driver such as programmer error, or other
13381 + * exceptional condition. It should not be ignored so even on systems without
13382 + * printing capability, some action should be taken to notify the developer of
13383 + * it. Works like printf().
13385 +extern void DWC_EXCEPTION(char *format, ...)
13387 + __attribute__ ((format(printf, 1, 2)));
13391 +#define dwc_exception DWC_EXCEPTION
13393 +#ifndef DWC_OTG_DEBUG_LEV
13394 +#define DWC_OTG_DEBUG_LEV 0
13399 + * Prints out a debug message. Used for logging/trace messages.
13401 + * Use the DWC_DEBUG macro to call this function
13403 +extern void __DWC_DEBUG(char *format, ...)
13405 + __attribute__ ((format(printf, 1, 2)));
13410 +#define __DWC_DEBUG printk
13414 + * Prints out a Debug message.
13416 +#define DWC_DEBUG(_format, _args...) __DWC_DEBUG("DEBUG:%s:%s: " _format "\n", \
13417 + __func__, dwc_irq(), ## _args)
13418 +#define dwc_debug DWC_DEBUG
13420 + * Prints out a Debug message if enabled at compile time.
13422 +#if DWC_OTG_DEBUG_LEV > 0
13423 +#define DWC_DEBUGC(_format, _args...) DWC_DEBUG(_format, ##_args )
13425 +#define DWC_DEBUGC(_format, _args...)
13427 +#define dwc_debugc DWC_DEBUGC
13429 + * Prints out an informative message.
13431 +#define DWC_INFO(_format, _args...) DWC_PRINTF("INFO:%s: " _format "\n", \
13432 + dwc_irq(), ## _args)
13433 +#define dwc_info DWC_INFO
13435 + * Prints out an informative message if enabled at compile time.
13437 +#if DWC_OTG_DEBUG_LEV > 1
13438 +#define DWC_INFOC(_format, _args...) DWC_INFO(_format, ##_args )
13440 +#define DWC_INFOC(_format, _args...)
13442 +#define dwc_infoc DWC_INFOC
13444 + * Prints out a warning message.
13446 +#define DWC_WARN(_format, _args...) __DWC_WARN("WARN:%s:%s:%d: " _format "\n", \
13447 + dwc_irq(), __func__, __LINE__, ## _args)
13448 +#define dwc_warn DWC_WARN
13450 + * Prints out an error message.
13452 +#define DWC_ERROR(_format, _args...) __DWC_ERROR("ERROR:%s:%s:%d: " _format "\n", \
13453 + dwc_irq(), __func__, __LINE__, ## _args)
13454 +#define dwc_error DWC_ERROR
13456 +#define DWC_PROTO_ERROR(_format, _args...) __DWC_WARN("ERROR:%s:%s:%d: " _format "\n", \
13457 + dwc_irq(), __func__, __LINE__, ## _args)
13458 +#define dwc_proto_error DWC_PROTO_ERROR
13461 +/** Prints out a exception error message if the _expr expression fails. Disabled
13462 + * if DEBUG is not enabled. */
13463 +#define DWC_ASSERT(_expr, _format, _args...) do { \
13464 + if (!(_expr)) { DWC_EXCEPTION("%s:%s:%d: " _format "\n", dwc_irq(), \
13465 + __FILE__, __LINE__, ## _args); } \
13468 +#define DWC_ASSERT(_x...)
13470 +#define dwc_assert DWC_ASSERT
13473 +/** @name Byte Ordering
13474 + * The following functions are for conversions between processor's byte ordering
13475 + * and specific ordering you want.
13478 +/** Converts 32 bit data in CPU byte ordering to little endian. */
13479 +extern uint32_t DWC_CPU_TO_LE32(uint32_t *p);
13480 +#define dwc_cpu_to_le32 DWC_CPU_TO_LE32
13482 +/** Converts 32 bit data in CPU byte orderint to big endian. */
13483 +extern uint32_t DWC_CPU_TO_BE32(uint32_t *p);
13484 +#define dwc_cpu_to_be32 DWC_CPU_TO_BE32
13486 +/** Converts 32 bit little endian data to CPU byte ordering. */
13487 +extern uint32_t DWC_LE32_TO_CPU(uint32_t *p);
13488 +#define dwc_le32_to_cpu DWC_LE32_TO_CPU
13490 +/** Converts 32 bit big endian data to CPU byte ordering. */
13491 +extern uint32_t DWC_BE32_TO_CPU(uint32_t *p);
13492 +#define dwc_be32_to_cpu DWC_BE32_TO_CPU
13494 +/** Converts 16 bit data in CPU byte ordering to little endian. */
13495 +extern uint16_t DWC_CPU_TO_LE16(uint16_t *p);
13496 +#define dwc_cpu_to_le16 DWC_CPU_TO_LE16
13498 +/** Converts 16 bit data in CPU byte orderint to big endian. */
13499 +extern uint16_t DWC_CPU_TO_BE16(uint16_t *p);
13500 +#define dwc_cpu_to_be16 DWC_CPU_TO_BE16
13502 +/** Converts 16 bit little endian data to CPU byte ordering. */
13503 +extern uint16_t DWC_LE16_TO_CPU(uint16_t *p);
13504 +#define dwc_le16_to_cpu DWC_LE16_TO_CPU
13506 +/** Converts 16 bit bi endian data to CPU byte ordering. */
13507 +extern uint16_t DWC_BE16_TO_CPU(uint16_t *p);
13508 +#define dwc_be16_to_cpu DWC_BE16_TO_CPU
13511 +/** @name Register Read/Write
13513 + * The following six functions should be implemented to read/write registers of
13514 + * 32-bit and 64-bit sizes. All modules use this to read/write register values.
13515 + * The reg value is a pointer to the register calculated from the void *base
13516 + * variable passed into the driver when it is started. */
13519 +/* Linux doesn't need any extra parameters for register read/write, so we
13520 + * just throw away the IO context parameter.
13522 +/** Reads the content of a 32-bit register. */
13523 +extern uint32_t DWC_READ_REG32(uint32_t volatile *reg);
13524 +#define dwc_read_reg32(_ctx_,_reg_) DWC_READ_REG32(_reg_)
13526 +/** Reads the content of a 64-bit register. */
13527 +extern uint64_t DWC_READ_REG64(uint64_t volatile *reg);
13528 +#define dwc_read_reg64(_ctx_,_reg_) DWC_READ_REG64(_reg_)
13530 +/** Writes to a 32-bit register. */
13531 +extern void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value);
13532 +#define dwc_write_reg32(_ctx_,_reg_,_val_) DWC_WRITE_REG32(_reg_, _val_)
13534 +/** Writes to a 64-bit register. */
13535 +extern void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value);
13536 +#define dwc_write_reg64(_ctx_,_reg_,_val_) DWC_WRITE_REG64(_reg_, _val_)
13539 + * Modify bit values in a register. Using the
13540 + * algorithm: (reg_contents & ~clear_mask) | set_mask.
13542 +extern void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask);
13543 +#define dwc_modify_reg32(_ctx_,_reg_,_cmsk_,_smsk_) DWC_MODIFY_REG32(_reg_,_cmsk_,_smsk_)
13544 +extern void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask);
13545 +#define dwc_modify_reg64(_ctx_,_reg_,_cmsk_,_smsk_) DWC_MODIFY_REG64(_reg_,_cmsk_,_smsk_)
13547 +#endif /* DWC_LINUX */
13549 +#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
13550 +typedef struct dwc_ioctx {
13551 + struct device *dev;
13552 + bus_space_tag_t iot;
13553 + bus_space_handle_t ioh;
13556 +/** BSD needs two extra parameters for register read/write, so we pass
13557 + * them in using the IO context parameter.
13559 +/** Reads the content of a 32-bit register. */
13560 +extern uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg);
13561 +#define dwc_read_reg32 DWC_READ_REG32
13563 +/** Reads the content of a 64-bit register. */
13564 +extern uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg);
13565 +#define dwc_read_reg64 DWC_READ_REG64
13567 +/** Writes to a 32-bit register. */
13568 +extern void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value);
13569 +#define dwc_write_reg32 DWC_WRITE_REG32
13571 +/** Writes to a 64-bit register. */
13572 +extern void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value);
13573 +#define dwc_write_reg64 DWC_WRITE_REG64
13576 + * Modify bit values in a register. Using the
13577 + * algorithm: (reg_contents & ~clear_mask) | set_mask.
13579 +extern void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask);
13580 +#define dwc_modify_reg32 DWC_MODIFY_REG32
13581 +extern void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask);
13582 +#define dwc_modify_reg64 DWC_MODIFY_REG64
13584 +#endif /* DWC_FREEBSD || DWC_NETBSD */
13588 +/** @name Some convenience MACROS used internally. Define DWC_DEBUG_REGS to log the
13589 + * register writes. */
13593 +# ifdef DWC_DEBUG_REGS
13595 +#define dwc_define_read_write_reg_n(_reg,_container_type) \
13596 +static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \
13597 + return DWC_READ_REG32(&container->regs->_reg[num]); \
13599 +static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \
13600 + DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, \
13601 + &(((uint32_t*)container->regs->_reg)[num]), data); \
13602 + DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \
13605 +#define dwc_define_read_write_reg(_reg,_container_type) \
13606 +static inline uint32_t dwc_read_##_reg(_container_type *container) { \
13607 + return DWC_READ_REG32(&container->regs->_reg); \
13609 +static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \
13610 + DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \
13611 + DWC_WRITE_REG32(&container->regs->_reg, data); \
13614 +# else /* DWC_DEBUG_REGS */
13616 +#define dwc_define_read_write_reg_n(_reg,_container_type) \
13617 +static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \
13618 + return DWC_READ_REG32(&container->regs->_reg[num]); \
13620 +static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \
13621 + DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \
13624 +#define dwc_define_read_write_reg(_reg,_container_type) \
13625 +static inline uint32_t dwc_read_##_reg(_container_type *container) { \
13626 + return DWC_READ_REG32(&container->regs->_reg); \
13628 +static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \
13629 + DWC_WRITE_REG32(&container->regs->_reg, data); \
13632 +# endif /* DWC_DEBUG_REGS */
13634 +#endif /* DWC_LINUX */
13636 +#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
13638 +# ifdef DWC_DEBUG_REGS
13640 +#define dwc_define_read_write_reg_n(_reg,_container_type) \
13641 +static inline uint32_t dwc_read_##_reg##_n(void *io_ctx, _container_type *container, int num) { \
13642 + return DWC_READ_REG32(io_ctx, &container->regs->_reg[num]); \
13644 +static inline void dwc_write_##_reg##_n(void *io_ctx, _container_type *container, int num, uint32_t data) { \
13645 + DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, \
13646 + &(((uint32_t*)container->regs->_reg)[num]), data); \
13647 + DWC_WRITE_REG32(io_ctx, &(((uint32_t*)container->regs->_reg)[num]), data); \
13650 +#define dwc_define_read_write_reg(_reg,_container_type) \
13651 +static inline uint32_t dwc_read_##_reg(void *io_ctx, _container_type *container) { \
13652 + return DWC_READ_REG32(io_ctx, &container->regs->_reg); \
13654 +static inline void dwc_write_##_reg(void *io_ctx, _container_type *container, uint32_t data) { \
13655 + DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \
13656 + DWC_WRITE_REG32(io_ctx, &container->regs->_reg, data); \
13659 +# else /* DWC_DEBUG_REGS */
13661 +#define dwc_define_read_write_reg_n(_reg,_container_type) \
13662 +static inline uint32_t dwc_read_##_reg##_n(void *io_ctx, _container_type *container, int num) { \
13663 + return DWC_READ_REG32(io_ctx, &container->regs->_reg[num]); \
13665 +static inline void dwc_write_##_reg##_n(void *io_ctx, _container_type *container, int num, uint32_t data) { \
13666 + DWC_WRITE_REG32(io_ctx, &(((uint32_t*)container->regs->_reg)[num]), data); \
13669 +#define dwc_define_read_write_reg(_reg,_container_type) \
13670 +static inline uint32_t dwc_read_##_reg(void *io_ctx, _container_type *container) { \
13671 + return DWC_READ_REG32(io_ctx, &container->regs->_reg); \
13673 +static inline void dwc_write_##_reg(void *io_ctx, _container_type *container, uint32_t data) { \
13674 + DWC_WRITE_REG32(io_ctx, &container->regs->_reg, data); \
13677 +# endif /* DWC_DEBUG_REGS */
13679 +#endif /* DWC_FREEBSD || DWC_NETBSD */
13684 +#ifdef DWC_CRYPTOLIB
13685 +/** @name Crypto Functions
13687 + * These are the low-level cryptographic functions used by the driver. */
13689 +/** Perform AES CBC */
13690 +extern int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out);
13691 +#define dwc_aes_cbc DWC_AES_CBC
13693 +/** Fill the provided buffer with random bytes. These should be cryptographic grade random numbers. */
13694 +extern void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length);
13695 +#define dwc_random_bytes DWC_RANDOM_BYTES
13697 +/** Perform the SHA-256 hash function */
13698 +extern int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out);
13699 +#define dwc_sha256 DWC_SHA256
13701 +/** Calculated the HMAC-SHA256 */
13702 +extern int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t *out);
13703 +#define dwc_hmac_sha256 DWC_HMAC_SHA256
13705 +#endif /* DWC_CRYPTOLIB */
13708 +/** @name Memory Allocation
13710 + * These function provide access to memory allocation. There are only 2 DMA
13711 + * functions and 3 Regular memory functions that need to be implemented. None
13712 + * of the memory debugging routines need to be implemented. The allocation
13713 + * routines all ZERO the contents of the memory.
13715 + * Defining DWC_DEBUG_MEMORY turns on memory debugging and statistic gathering.
13716 + * This checks for memory leaks, keeping track of alloc/free pairs. It also
13717 + * keeps track of how much memory the driver is using at any given time. */
13719 +#define DWC_PAGE_SIZE 4096
13720 +#define DWC_PAGE_OFFSET(addr) (((uint32_t)addr) & 0xfff)
13721 +#define DWC_PAGE_ALIGNED(addr) ((((uint32_t)addr) & 0xfff) == 0)
13723 +#define DWC_INVALID_DMA_ADDR 0x0
13726 +/** Type for a DMA address */
13727 +typedef dma_addr_t dwc_dma_t;
13730 +#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
13731 +typedef bus_addr_t dwc_dma_t;
13734 +#ifdef DWC_FREEBSD
13735 +typedef struct dwc_dmactx {
13736 + struct device *dev;
13737 + bus_dma_tag_t dma_tag;
13738 + bus_dmamap_t dma_map;
13739 + bus_addr_t dma_paddr;
13745 +typedef struct dwc_dmactx {
13746 + struct device *dev;
13747 + bus_dma_tag_t dma_tag;
13748 + bus_dmamap_t dma_map;
13749 + bus_dma_segment_t segs[1];
13751 + bus_addr_t dma_paddr;
13756 +/* @todo these functions will be added in the future */
13759 + * Creates a DMA pool from which you can allocate DMA buffers. Buffers
13760 + * allocated from this pool will be guaranteed to meet the size, alignment, and
13761 + * boundary requirements specified.
13763 + * @param[in] size Specifies the size of the buffers that will be allocated from
13765 + * @param[in] align Specifies the byte alignment requirements of the buffers
13766 + * allocated from this pool. Must be a power of 2.
13767 + * @param[in] boundary Specifies the N-byte boundary that buffers allocated from
13768 + * this pool must not cross.
13770 + * @returns A pointer to an internal opaque structure which is not to be
13771 + * accessed outside of these library functions. Use this handle to specify
13772 + * which pools to allocate/free DMA buffers from and also to destroy the pool,
13773 + * when you are done with it.
13775 +extern dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size, uint32_t align, uint32_t boundary);
13778 + * Destroy a DMA pool. All buffers allocated from that pool must be freed first.
13780 +extern void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool);
13783 + * Allocate a buffer from the specified DMA pool and zeros its contents.
13785 +extern void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr);
13788 + * Free a previously allocated buffer from the DMA pool.
13790 +extern void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr);
13793 +/** Allocates a DMA capable buffer and zeroes its contents. */
13794 +extern void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr);
13796 +/** Allocates a DMA capable buffer and zeroes its contents in atomic contest */
13797 +extern void *__DWC_DMA_ALLOC_ATOMIC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr);
13799 +/** Frees a previously allocated buffer. */
13800 +extern void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr);
13802 +/** Allocates a block of memory and zeroes its contents. */
13803 +extern void *__DWC_ALLOC(void *mem_ctx, uint32_t size);
13805 +/** Allocates a block of memory and zeroes its contents, in an atomic manner
13806 + * which can be used inside interrupt context. The size should be sufficiently
13807 + * small, a few KB at most, such that failures are not likely to occur. Can just call
13808 + * __DWC_ALLOC if it is atomic. */
13809 +extern void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size);
13811 +/** Frees a previously allocated buffer. */
13812 +extern void __DWC_FREE(void *mem_ctx, void *addr);
13814 +#ifndef DWC_DEBUG_MEMORY
13816 +#define DWC_ALLOC(_size_) __DWC_ALLOC(NULL, _size_)
13817 +#define DWC_ALLOC_ATOMIC(_size_) __DWC_ALLOC_ATOMIC(NULL, _size_)
13818 +#define DWC_FREE(_addr_) __DWC_FREE(NULL, _addr_)
13821 +#define DWC_DMA_ALLOC(_dev, _size_, _dma_) __DWC_DMA_ALLOC(_dev, _size_, _dma_)
13822 +#define DWC_DMA_ALLOC_ATOMIC(_dev, _size_, _dma_) __DWC_DMA_ALLOC_ATOMIC(_dev, _size_, _dma_)
13823 +#define DWC_DMA_FREE(_dev, _size_,_virt_, _dma_) __DWC_DMA_FREE(_dev, _size_, _virt_, _dma_)
13826 +# if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
13827 +#define DWC_DMA_ALLOC __DWC_DMA_ALLOC
13828 +#define DWC_DMA_FREE __DWC_DMA_FREE
13830 +extern void *dwc_dma_alloc_atomic_debug(uint32_t size, dwc_dma_t *dma_addr, char const *func, int line);
13832 +#else /* DWC_DEBUG_MEMORY */
13834 +extern void *dwc_alloc_debug(void *mem_ctx, uint32_t size, char const *func, int line);
13835 +extern void *dwc_alloc_atomic_debug(void *mem_ctx, uint32_t size, char const *func, int line);
13836 +extern void dwc_free_debug(void *mem_ctx, void *addr, char const *func, int line);
13837 +extern void *dwc_dma_alloc_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,
13838 + char const *func, int line);
13839 +extern void *dwc_dma_alloc_atomic_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,
13840 + char const *func, int line);
13841 +extern void dwc_dma_free_debug(void *dma_ctx, uint32_t size, void *virt_addr,
13842 + dwc_dma_t dma_addr, char const *func, int line);
13844 +extern int dwc_memory_debug_start(void *mem_ctx);
13845 +extern void dwc_memory_debug_stop(void);
13846 +extern void dwc_memory_debug_report(void);
13848 +#define DWC_ALLOC(_size_) dwc_alloc_debug(NULL, _size_, __func__, __LINE__)
13849 +#define DWC_ALLOC_ATOMIC(_size_) dwc_alloc_atomic_debug(NULL, _size_, \
13850 + __func__, __LINE__)
13851 +#define DWC_FREE(_addr_) dwc_free_debug(NULL, _addr_, __func__, __LINE__)
13854 +#define DWC_DMA_ALLOC(_dev, _size_, _dma_) \
13855 + dwc_dma_alloc_debug(_dev, _size_, _dma_, __func__, __LINE__)
13856 +#define DWC_DMA_ALLOC_ATOMIC(_dev, _size_, _dma_) \
13857 + dwc_dma_alloc_atomic_debug(_dev, _size_, _dma_, __func__, __LINE__)
13858 +#define DWC_DMA_FREE(_dev, _size_, _virt_, _dma_) \
13859 + dwc_dma_free_debug(_dev, _size_, _virt_, _dma_, __func__, __LINE__)
13862 +# if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
13863 +#define DWC_DMA_ALLOC(_ctx_,_size_,_dma_) dwc_dma_alloc_debug(_ctx_, _size_, \
13864 + _dma_, __func__, __LINE__)
13865 +#define DWC_DMA_FREE(_ctx_,_size_,_virt_,_dma_) dwc_dma_free_debug(_ctx_, _size_, \
13866 + _virt_, _dma_, __func__, __LINE__)
13869 +#endif /* DWC_DEBUG_MEMORY */
13871 +#define dwc_alloc(_ctx_,_size_) DWC_ALLOC(_size_)
13872 +#define dwc_alloc_atomic(_ctx_,_size_) DWC_ALLOC_ATOMIC(_size_)
13873 +#define dwc_free(_ctx_,_addr_) DWC_FREE(_addr_)
13876 +/* Linux doesn't need any extra parameters for DMA buffer allocation, so we
13877 + * just throw away the DMA context parameter.
13879 +#define dwc_dma_alloc(_ctx_,_size_,_dma_) DWC_DMA_ALLOC(_size_, _dma_)
13880 +#define dwc_dma_alloc_atomic(_ctx_,_size_,_dma_) DWC_DMA_ALLOC_ATOMIC(_size_, _dma_)
13881 +#define dwc_dma_free(_ctx_,_size_,_virt_,_dma_) DWC_DMA_FREE(_size_, _virt_, _dma_)
13884 +#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
13885 +/** BSD needs several extra parameters for DMA buffer allocation, so we pass
13886 + * them in using the DMA context parameter.
13888 +#define dwc_dma_alloc DWC_DMA_ALLOC
13889 +#define dwc_dma_free DWC_DMA_FREE
13893 +/** @name Memory and String Processing */
13895 +/** memset() clone */
13896 +extern void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size);
13897 +#define dwc_memset DWC_MEMSET
13899 +/** memcpy() clone */
13900 +extern void *DWC_MEMCPY(void *dest, void const *src, uint32_t size);
13901 +#define dwc_memcpy DWC_MEMCPY
13903 +/** memmove() clone */
13904 +extern void *DWC_MEMMOVE(void *dest, void *src, uint32_t size);
13905 +#define dwc_memmove DWC_MEMMOVE
13907 +/** memcmp() clone */
13908 +extern int DWC_MEMCMP(void *m1, void *m2, uint32_t size);
13909 +#define dwc_memcmp DWC_MEMCMP
13911 +/** strcmp() clone */
13912 +extern int DWC_STRCMP(void *s1, void *s2);
13913 +#define dwc_strcmp DWC_STRCMP
13915 +/** strncmp() clone */
13916 +extern int DWC_STRNCMP(void *s1, void *s2, uint32_t size);
13917 +#define dwc_strncmp DWC_STRNCMP
13919 +/** strlen() clone, for NULL terminated ASCII strings */
13920 +extern int DWC_STRLEN(char const *str);
13921 +#define dwc_strlen DWC_STRLEN
13923 +/** strcpy() clone, for NULL terminated ASCII strings */
13924 +extern char *DWC_STRCPY(char *to, const char *from);
13925 +#define dwc_strcpy DWC_STRCPY
13927 +/** strdup() clone. If you wish to use memory allocation debugging, this
13928 + * implementation of strdup should use the DWC_* memory routines instead of
13929 + * calling a predefined strdup. Otherwise the memory allocated by this routine
13930 + * will not be seen by the debugging routines. */
13931 +extern char *DWC_STRDUP(char const *str);
13932 +#define dwc_strdup(_ctx_,_str_) DWC_STRDUP(_str_)
13934 +/** NOT an atoi() clone. Read the description carefully. Returns an integer
13935 + * converted from the string str in base 10 unless the string begins with a "0x"
13936 + * in which case it is base 16. String must be a NULL terminated sequence of
13937 + * ASCII characters and may optionally begin with whitespace, a + or -, and a
13938 + * "0x" prefix if base 16. The remaining characters must be valid digits for
13939 + * the number and end with a NULL character. If any invalid characters are
13940 + * encountered or it returns with a negative error code and the results of the
13941 + * conversion are undefined. On sucess it returns 0. Overflow conditions are
13942 + * undefined. An example implementation using atoi() can be referenced from the
13943 + * Linux implementation. */
13944 +extern int DWC_ATOI(const char *str, int32_t *value);
13945 +#define dwc_atoi DWC_ATOI
13947 +/** Same as above but for unsigned. */
13948 +extern int DWC_ATOUI(const char *str, uint32_t *value);
13949 +#define dwc_atoui DWC_ATOUI
13952 +/** This routine returns a UTF16LE unicode encoded string from a UTF8 string. */
13953 +extern int DWC_UTF8_TO_UTF16LE(uint8_t const *utf8string, uint16_t *utf16string, unsigned len);
13954 +#define dwc_utf8_to_utf16le DWC_UTF8_TO_UTF16LE
13958 +/** @name Wait queues
13960 + * Wait queues provide a means of synchronizing between threads or processes. A
13961 + * process can block on a waitq if some condition is not true, waiting for it to
13962 + * become true. When the waitq is triggered all waiting process will get
13963 + * unblocked and the condition will be check again. Waitqs should be triggered
13964 + * every time a condition can potentially change.*/
13967 +/** Type for a waitq */
13968 +typedef struct dwc_waitq dwc_waitq_t;
13970 +/** The type of waitq condition callback function. This is called every time
13971 + * condition is evaluated. */
13972 +typedef int (*dwc_waitq_condition_t)(void *data);
13974 +/** Allocate a waitq */
13975 +extern dwc_waitq_t *DWC_WAITQ_ALLOC(void);
13976 +#define dwc_waitq_alloc(_ctx_) DWC_WAITQ_ALLOC()
13978 +/** Free a waitq */
13979 +extern void DWC_WAITQ_FREE(dwc_waitq_t *wq);
13980 +#define dwc_waitq_free DWC_WAITQ_FREE
13982 +/** Check the condition and if it is false, block on the waitq. When unblocked, check the
13983 + * condition again. The function returns when the condition becomes true. The return value
13984 + * is 0 on condition true, DWC_WAITQ_ABORTED on abort or killed, or DWC_WAITQ_UNKNOWN on error. */
13985 +extern int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data);
13986 +#define dwc_waitq_wait DWC_WAITQ_WAIT
13988 +/** Check the condition and if it is false, block on the waitq. When unblocked,
13989 + * check the condition again. The function returns when the condition become
13990 + * true or the timeout has passed. The return value is 0 on condition true or
13991 + * DWC_TIMED_OUT on timeout, or DWC_WAITQ_ABORTED, or DWC_WAITQ_UNKNOWN on
13993 +extern int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
13994 + void *data, int32_t msecs);
13995 +#define dwc_waitq_wait_timeout DWC_WAITQ_WAIT_TIMEOUT
13997 +/** Trigger a waitq, unblocking all processes. This should be called whenever a condition
13998 + * has potentially changed. */
13999 +extern void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq);
14000 +#define dwc_waitq_trigger DWC_WAITQ_TRIGGER
14002 +/** Unblock all processes waiting on the waitq with an ABORTED result. */
14003 +extern void DWC_WAITQ_ABORT(dwc_waitq_t *wq);
14004 +#define dwc_waitq_abort DWC_WAITQ_ABORT
14009 + * A thread must be explicitly stopped. It must check DWC_THREAD_SHOULD_STOP
14010 + * whenever it is woken up, and then return. The DWC_THREAD_STOP function
14011 + * returns the value from the thread.
14014 +struct dwc_thread;
14016 +/** Type for a thread */
14017 +typedef struct dwc_thread dwc_thread_t;
14019 +/** The thread function */
14020 +typedef int (*dwc_thread_function_t)(void *data);
14022 +/** Create a thread and start it running the thread_function. Returns a handle
14023 + * to the thread */
14024 +extern dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data);
14025 +#define dwc_thread_run(_ctx_,_func_,_name_,_data_) DWC_THREAD_RUN(_func_, _name_, _data_)
14027 +/** Stops a thread. Return the value returned by the thread. Or will return
14028 + * DWC_ABORT if the thread never started. */
14029 +extern int DWC_THREAD_STOP(dwc_thread_t *thread);
14030 +#define dwc_thread_stop DWC_THREAD_STOP
14032 +/** Signifies to the thread that it must stop. */
14034 +/* Linux doesn't need any parameters for kthread_should_stop() */
14035 +extern dwc_bool_t DWC_THREAD_SHOULD_STOP(void);
14036 +#define dwc_thread_should_stop(_thrd_) DWC_THREAD_SHOULD_STOP()
14038 +/* No thread_exit function in Linux */
14039 +#define dwc_thread_exit(_thrd_)
14042 +#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
14043 +/** BSD needs the thread pointer for kthread_suspend_check() */
14044 +extern dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread);
14045 +#define dwc_thread_should_stop DWC_THREAD_SHOULD_STOP
14047 +/** The thread must call this to exit. */
14048 +extern void DWC_THREAD_EXIT(dwc_thread_t *thread);
14049 +#define dwc_thread_exit DWC_THREAD_EXIT
14053 +/** @name Work queues
14055 + * Workqs are used to queue a callback function to be called at some later time,
14056 + * in another thread. */
14059 +/** Type for a workq */
14060 +typedef struct dwc_workq dwc_workq_t;
14062 +/** The type of the callback function to be called. */
14063 +typedef void (*dwc_work_callback_t)(void *data);
14065 +/** Allocate a workq */
14066 +extern dwc_workq_t *DWC_WORKQ_ALLOC(char *name);
14067 +#define dwc_workq_alloc(_ctx_,_name_) DWC_WORKQ_ALLOC(_name_)
14069 +/** Free a workq. All work must be completed before being freed. */
14070 +extern void DWC_WORKQ_FREE(dwc_workq_t *workq);
14071 +#define dwc_workq_free DWC_WORKQ_FREE
14073 +/** Schedule a callback on the workq, passing in data. The function will be
14074 + * scheduled at some later time. */
14075 +extern void DWC_WORKQ_SCHEDULE(dwc_workq_t *workq, dwc_work_callback_t cb,
14076 + void *data, char *format, ...)
14078 + __attribute__ ((format(printf, 4, 5)));
14082 +#define dwc_workq_schedule DWC_WORKQ_SCHEDULE
14084 +/** Schedule a callback on the workq, that will be called until at least
14085 + * given number miliseconds have passed. */
14086 +extern void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *workq, dwc_work_callback_t cb,
14087 + void *data, uint32_t time, char *format, ...)
14089 + __attribute__ ((format(printf, 5, 6)));
14093 +#define dwc_workq_schedule_delayed DWC_WORKQ_SCHEDULE_DELAYED
14095 +/** The number of processes in the workq */
14096 +extern int DWC_WORKQ_PENDING(dwc_workq_t *workq);
14097 +#define dwc_workq_pending DWC_WORKQ_PENDING
14099 +/** Blocks until all the work in the workq is complete or timed out. Returns <
14100 + * 0 on timeout. */
14101 +extern int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout);
14102 +#define dwc_workq_wait_work_done DWC_WORKQ_WAIT_WORK_DONE
14105 +/** @name Tasklets
14108 +struct dwc_tasklet;
14110 +/** Type for a tasklet */
14111 +typedef struct dwc_tasklet dwc_tasklet_t;
14113 +/** The type of the callback function to be called */
14114 +typedef void (*dwc_tasklet_callback_t)(void *data);
14116 +/** Allocates a tasklet */
14117 +extern dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data);
14118 +#define dwc_task_alloc(_ctx_,_name_,_cb_,_data_) DWC_TASK_ALLOC(_name_, _cb_, _data_)
14120 +/** Frees a tasklet */
14121 +extern void DWC_TASK_FREE(dwc_tasklet_t *task);
14122 +#define dwc_task_free DWC_TASK_FREE
14124 +/** Schedules a tasklet to run */
14125 +extern void DWC_TASK_SCHEDULE(dwc_tasklet_t *task);
14126 +#define dwc_task_schedule DWC_TASK_SCHEDULE
14128 +extern void DWC_TASK_HI_SCHEDULE(dwc_tasklet_t *task);
14129 +#define dwc_task_hi_schedule DWC_TASK_HI_SCHEDULE
14133 + * Callbacks must be small and atomic.
14137 +/** Type for a timer */
14138 +typedef struct dwc_timer dwc_timer_t;
14140 +/** The type of the callback function to be called */
14141 +typedef void (*dwc_timer_callback_t)(void *data);
14143 +/** Allocates a timer */
14144 +extern dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data);
14145 +#define dwc_timer_alloc(_ctx_,_name_,_cb_,_data_) DWC_TIMER_ALLOC(_name_,_cb_,_data_)
14147 +/** Frees a timer */
14148 +extern void DWC_TIMER_FREE(dwc_timer_t *timer);
14149 +#define dwc_timer_free DWC_TIMER_FREE
14151 +/** Schedules the timer to run at time ms from now. And will repeat at every
14152 + * repeat_interval msec therafter
14154 + * Modifies a timer that is still awaiting execution to a new expiration time.
14155 + * The mod_time is added to the old time. */
14156 +extern void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time);
14157 +#define dwc_timer_schedule DWC_TIMER_SCHEDULE
14159 +/** Disables the timer from execution. */
14160 +extern void DWC_TIMER_CANCEL(dwc_timer_t *timer);
14161 +#define dwc_timer_cancel DWC_TIMER_CANCEL
14164 +/** @name Spinlocks
14166 + * These locks are used when the work between the lock/unlock is atomic and
14167 + * short. Interrupts are also disabled during the lock/unlock and thus they are
14168 + * suitable to lock between interrupt/non-interrupt context. They also lock
14169 + * between processes if you have multiple CPUs or Preemption. If you don't have
14170 + * multiple CPUS or Preemption, then the you can simply implement the
14171 + * DWC_SPINLOCK and DWC_SPINUNLOCK to disable and enable interrupts. Because
14172 + * the work between the lock/unlock is atomic, the process context will never
14173 + * change, and so you never have to lock between processes. */
14175 +struct dwc_spinlock;
14177 +/** Type for a spinlock */
14178 +typedef struct dwc_spinlock dwc_spinlock_t;
14180 +/** Type for the 'flags' argument to spinlock funtions */
14181 +typedef unsigned long dwc_irqflags_t;
14183 +/** Returns an initialized lock variable. This function should allocate and
14184 + * initialize the OS-specific data structure used for locking. This data
14185 + * structure is to be used for the DWC_LOCK and DWC_UNLOCK functions and should
14186 + * be freed by the DWC_FREE_LOCK when it is no longer used.
14188 + * For Linux Spinlock Debugging make it macro because the debugging routines use
14189 + * the symbol name to determine recursive locking. Using a wrapper function
14190 + * makes it falsely think recursive locking occurs. */
14191 +#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK)
14192 +#define DWC_SPINLOCK_ALLOC_LINUX_DEBUG(lock) ({ \
14193 + lock = DWC_ALLOC(sizeof(spinlock_t)); \
14195 + spin_lock_init((spinlock_t *)lock); \
14199 +extern dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void);
14200 +#define dwc_spinlock_alloc(_ctx_) DWC_SPINLOCK_ALLOC()
14203 +/** Frees an initialized lock variable. */
14204 +extern void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock);
14205 +#define dwc_spinlock_free(_ctx_,_lock_) DWC_SPINLOCK_FREE(_lock_)
14207 +/** Disables interrupts and blocks until it acquires the lock.
14209 + * @param lock Pointer to the spinlock.
14210 + * @param flags Unsigned long for irq flags storage.
14212 +extern void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags);
14213 +#define dwc_spinlock_irqsave DWC_SPINLOCK_IRQSAVE
14215 +/** Re-enables the interrupt and releases the lock.
14217 + * @param lock Pointer to the spinlock.
14218 + * @param flags Unsigned long for irq flags storage. Must be the same as was
14219 + * passed into DWC_LOCK.
14221 +extern void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags);
14222 +#define dwc_spinunlock_irqrestore DWC_SPINUNLOCK_IRQRESTORE
14224 +/** Blocks until it acquires the lock.
14226 + * @param lock Pointer to the spinlock.
14228 +extern void DWC_SPINLOCK(dwc_spinlock_t *lock);
14229 +#define dwc_spinlock DWC_SPINLOCK
14231 +/** Releases the lock.
14233 + * @param lock Pointer to the spinlock.
14235 +extern void DWC_SPINUNLOCK(dwc_spinlock_t *lock);
14236 +#define dwc_spinunlock DWC_SPINUNLOCK
14241 + * Unlike spinlocks Mutexes lock only between processes and the work between the
14242 + * lock/unlock CAN block, therefore it CANNOT be called from interrupt context.
14247 +/** Type for a mutex */
14248 +typedef struct dwc_mutex dwc_mutex_t;
14250 +/* For Linux Mutex Debugging make it inline because the debugging routines use
14251 + * the symbol to determine recursive locking. This makes it falsely think
14252 + * recursive locking occurs. */
14253 +#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)
14254 +#define DWC_MUTEX_ALLOC_LINUX_DEBUG(__mutexp) ({ \
14255 + __mutexp = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex)); \
14256 + mutex_init((struct mutex *)__mutexp); \
14260 +/** Allocate a mutex */
14261 +extern dwc_mutex_t *DWC_MUTEX_ALLOC(void);
14262 +#define dwc_mutex_alloc(_ctx_) DWC_MUTEX_ALLOC()
14264 +/* For memory leak debugging when using Linux Mutex Debugging */
14265 +#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)
14266 +#define DWC_MUTEX_FREE(__mutexp) do { \
14267 + mutex_destroy((struct mutex *)__mutexp); \
14268 + DWC_FREE(__mutexp); \
14271 +/** Free a mutex */
14272 +extern void DWC_MUTEX_FREE(dwc_mutex_t *mutex);
14273 +#define dwc_mutex_free(_ctx_,_mutex_) DWC_MUTEX_FREE(_mutex_)
14276 +/** Lock a mutex */
14277 +extern void DWC_MUTEX_LOCK(dwc_mutex_t *mutex);
14278 +#define dwc_mutex_lock DWC_MUTEX_LOCK
14280 +/** Non-blocking lock returns 1 on successful lock. */
14281 +extern int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex);
14282 +#define dwc_mutex_trylock DWC_MUTEX_TRYLOCK
14284 +/** Unlock a mutex */
14285 +extern void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex);
14286 +#define dwc_mutex_unlock DWC_MUTEX_UNLOCK
14291 +/** Microsecond delay.
14293 + * @param usecs Microseconds to delay.
14295 +extern void DWC_UDELAY(uint32_t usecs);
14296 +#define dwc_udelay DWC_UDELAY
14298 +/** Millisecond delay.
14300 + * @param msecs Milliseconds to delay.
14302 +extern void DWC_MDELAY(uint32_t msecs);
14303 +#define dwc_mdelay DWC_MDELAY
14305 +/** Non-busy waiting.
14306 + * Sleeps for specified number of milliseconds.
14308 + * @param msecs Milliseconds to sleep.
14310 +extern void DWC_MSLEEP(uint32_t msecs);
14311 +#define dwc_msleep DWC_MSLEEP
14314 + * Returns number of milliseconds since boot.
14316 +extern uint32_t DWC_TIME(void);
14317 +#define dwc_time DWC_TIME
14322 +/* @mainpage DWC Portability and Common Library
14324 + * This is the documentation for the DWC Portability and Common Library.
14326 + * @section intro Introduction
14328 + * The DWC Portability library consists of wrapper calls and data structures to
14329 + * all low-level functions which are typically provided by the OS. The WUDEV
14330 + * driver uses only these functions. In order to port the WUDEV driver, only
14331 + * the functions in this library need to be re-implemented, with the same
14332 + * behavior as documented here.
14334 + * The Common library consists of higher level functions, which rely only on
14335 + * calling the functions from the DWC Portability library. These common
14336 + * routines are shared across modules. Some of the common libraries need to be
14337 + * used directly by the driver programmer when porting WUDEV. Such as the
14338 + * parameter and notification libraries.
14340 + * @section low Portability Library OS Wrapper Functions
14342 + * Any function starting with DWC and in all CAPS is a low-level OS-wrapper that
14343 + * needs to be implemented when porting, for example DWC_MUTEX_ALLOC(). All of
14344 + * these functions are included in the dwc_os.h file.
14346 + * There are many functions here covering a wide array of OS services. Please
14347 + * see dwc_os.h for details, and implementation notes for each function.
14349 + * @section common Common Library Functions
14351 + * Any function starting with dwc and in all lowercase is a common library
14352 + * routine. These functions have a portable implementation and do not need to
14353 + * be reimplemented when porting. The common routines can be used by any
14354 + * driver, and some must be used by the end user to control the drivers. For
14355 + * example, you must use the Parameter common library in order to set the
14356 + * parameters in the WUDEV module.
14358 + * The common libraries consist of the following:
14360 + * - Connection Contexts - Used internally and can be used by end-user. See dwc_cc.h
14361 + * - Parameters - Used internally and can be used by end-user. See dwc_params.h
14362 + * - Notifications - Used internally and can be used by end-user. See dwc_notifier.h
14363 + * - Lists - Used internally and can be used by end-user. See dwc_list.h
14364 + * - Memory Debugging - Used internally and can be used by end-user. See dwc_os.h
14365 + * - Modpow - Used internally only. See dwc_modpow.h
14366 + * - DH - Used internally only. See dwc_dh.h
14367 + * - Crypto - Used internally only. See dwc_crypto.h
14370 + * @section prereq Prerequistes For dwc_os.h
14371 + * @subsection types Data Types
14373 + * The dwc_os.h file assumes that several low-level data types are pre defined for the
14374 + * compilation environment. These data types are:
14376 + * - uint8_t - unsigned 8-bit data type
14377 + * - int8_t - signed 8-bit data type
14378 + * - uint16_t - unsigned 16-bit data type
14379 + * - int16_t - signed 16-bit data type
14380 + * - uint32_t - unsigned 32-bit data type
14381 + * - int32_t - signed 32-bit data type
14382 + * - uint64_t - unsigned 64-bit data type
14383 + * - int64_t - signed 64-bit data type
14385 + * Ensure that these are defined before using dwc_os.h. The easiest way to do
14386 + * that is to modify the top of the file to include the appropriate header.
14387 + * This is already done for the Linux environment. If the DWC_LINUX macro is
14388 + * defined, the correct header will be added. A standard header <stdint.h> is
14389 + * also used for environments where standard C headers are available.
14391 + * @subsection stdarg Variable Arguments
14393 + * Variable arguments are provided by a standard C header <stdarg.h>. it is
14394 + * available in Both the Linux and ANSI C enviornment. An equivalent must be
14395 + * provided in your enviornment in order to use dwc_os.h with the debug and
14396 + * tracing message functionality.
14398 + * @subsection thread Threading
14400 + * WUDEV Core must be run on an operating system that provides for multiple
14401 + * threads/processes. Threading can be implemented in many ways, even in
14402 + * embedded systems without an operating system. At the bare minimum, the
14403 + * system should be able to start any number of processes at any time to handle
14404 + * special work. It need not be a pre-emptive system. Process context can
14405 + * change upon a call to a blocking function. The hardware interrupt context
14406 + * that calls the module's ISR() function must be differentiable from process
14407 + * context, even if your processes are impemented via a hardware interrupt.
14408 + * Further locking mechanism between process must exist (or be implemented), and
14409 + * process context must have a way to disable interrupts for a period of time to
14410 + * lock them out. If all of this exists, the functions in dwc_os.h related to
14411 + * threading should be able to be implemented with the defined behavior.
14415 +#ifdef __cplusplus
14419 +#endif /* _DWC_OS_H_ */
14421 +++ b/drivers/usb/host/dwc_common_port/usb.h
14424 + * Copyright (c) 1998 The NetBSD Foundation, Inc.
14425 + * All rights reserved.
14427 + * This code is derived from software contributed to The NetBSD Foundation
14428 + * by Lennart Augustsson (lennart@augustsson.net) at
14429 + * Carlstedt Research & Technology.
14431 + * Redistribution and use in source and binary forms, with or without
14432 + * modification, are permitted provided that the following conditions
14434 + * 1. Redistributions of source code must retain the above copyright
14435 + * notice, this list of conditions and the following disclaimer.
14436 + * 2. Redistributions in binary form must reproduce the above copyright
14437 + * notice, this list of conditions and the following disclaimer in the
14438 + * documentation and/or other materials provided with the distribution.
14439 + * 3. All advertising materials mentioning features or use of this software
14440 + * must display the following acknowledgement:
14441 + * This product includes software developed by the NetBSD
14442 + * Foundation, Inc. and its contributors.
14443 + * 4. Neither the name of The NetBSD Foundation nor the names of its
14444 + * contributors may be used to endorse or promote products derived
14445 + * from this software without specific prior written permission.
14447 + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
14448 + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
14449 + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
14450 + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
14451 + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
14452 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
14453 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
14454 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
14455 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
14456 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
14457 + * POSSIBILITY OF SUCH DAMAGE.
14460 +/* Modified by Synopsys, Inc, 12/12/2007 */
14466 +#ifdef __cplusplus
14471 + * The USB records contain some unaligned little-endian word
14472 + * components. The U[SG]ETW macros take care of both the alignment
14473 + * and endian problem and should always be used to access non-byte
14476 +typedef u_int8_t uByte;
14477 +typedef u_int8_t uWord[2];
14478 +typedef u_int8_t uDWord[4];
14480 +#define USETW2(w,h,l) ((w)[0] = (u_int8_t)(l), (w)[1] = (u_int8_t)(h))
14481 +#define UCONSTW(x) { (x) & 0xff, ((x) >> 8) & 0xff }
14482 +#define UCONSTDW(x) { (x) & 0xff, ((x) >> 8) & 0xff, \
14483 + ((x) >> 16) & 0xff, ((x) >> 24) & 0xff }
14486 +#define UGETW(w) ((w)[0] | ((w)[1] << 8))
14487 +#define USETW(w,v) ((w)[0] = (u_int8_t)(v), (w)[1] = (u_int8_t)((v) >> 8))
14488 +#define UGETDW(w) ((w)[0] | ((w)[1] << 8) | ((w)[2] << 16) | ((w)[3] << 24))
14489 +#define USETDW(w,v) ((w)[0] = (u_int8_t)(v), \
14490 + (w)[1] = (u_int8_t)((v) >> 8), \
14491 + (w)[2] = (u_int8_t)((v) >> 16), \
14492 + (w)[3] = (u_int8_t)((v) >> 24))
14495 + * On little-endian machines that can handle unanliged accesses
14496 + * (e.g. i386) these macros can be replaced by the following.
14498 +#define UGETW(w) (*(u_int16_t *)(w))
14499 +#define USETW(w,v) (*(u_int16_t *)(w) = (v))
14500 +#define UGETDW(w) (*(u_int32_t *)(w))
14501 +#define USETDW(w,v) (*(u_int32_t *)(w) = (v))
14505 + * Macros for accessing UAS IU fields, which are big-endian
14507 +#define IUSETW2(w,h,l) ((w)[0] = (u_int8_t)(h), (w)[1] = (u_int8_t)(l))
14508 +#define IUCONSTW(x) { ((x) >> 8) & 0xff, (x) & 0xff }
14509 +#define IUCONSTDW(x) { ((x) >> 24) & 0xff, ((x) >> 16) & 0xff, \
14510 + ((x) >> 8) & 0xff, (x) & 0xff }
14511 +#define IUGETW(w) (((w)[0] << 8) | (w)[1])
14512 +#define IUSETW(w,v) ((w)[0] = (u_int8_t)((v) >> 8), (w)[1] = (u_int8_t)(v))
14513 +#define IUGETDW(w) (((w)[0] << 24) | ((w)[1] << 16) | ((w)[2] << 8) | (w)[3])
14514 +#define IUSETDW(w,v) ((w)[0] = (u_int8_t)((v) >> 24), \
14515 + (w)[1] = (u_int8_t)((v) >> 16), \
14516 + (w)[2] = (u_int8_t)((v) >> 8), \
14517 + (w)[3] = (u_int8_t)(v))
14519 +#define UPACKED __attribute__((__packed__))
14522 + uByte bmRequestType;
14527 +} UPACKED usb_device_request_t;
14529 +#define UT_GET_DIR(a) ((a) & 0x80)
14530 +#define UT_WRITE 0x00
14531 +#define UT_READ 0x80
14533 +#define UT_GET_TYPE(a) ((a) & 0x60)
14534 +#define UT_STANDARD 0x00
14535 +#define UT_CLASS 0x20
14536 +#define UT_VENDOR 0x40
14538 +#define UT_GET_RECIPIENT(a) ((a) & 0x1f)
14539 +#define UT_DEVICE 0x00
14540 +#define UT_INTERFACE 0x01
14541 +#define UT_ENDPOINT 0x02
14542 +#define UT_OTHER 0x03
14544 +#define UT_READ_DEVICE (UT_READ | UT_STANDARD | UT_DEVICE)
14545 +#define UT_READ_INTERFACE (UT_READ | UT_STANDARD | UT_INTERFACE)
14546 +#define UT_READ_ENDPOINT (UT_READ | UT_STANDARD | UT_ENDPOINT)
14547 +#define UT_WRITE_DEVICE (UT_WRITE | UT_STANDARD | UT_DEVICE)
14548 +#define UT_WRITE_INTERFACE (UT_WRITE | UT_STANDARD | UT_INTERFACE)
14549 +#define UT_WRITE_ENDPOINT (UT_WRITE | UT_STANDARD | UT_ENDPOINT)
14550 +#define UT_READ_CLASS_DEVICE (UT_READ | UT_CLASS | UT_DEVICE)
14551 +#define UT_READ_CLASS_INTERFACE (UT_READ | UT_CLASS | UT_INTERFACE)
14552 +#define UT_READ_CLASS_OTHER (UT_READ | UT_CLASS | UT_OTHER)
14553 +#define UT_READ_CLASS_ENDPOINT (UT_READ | UT_CLASS | UT_ENDPOINT)
14554 +#define UT_WRITE_CLASS_DEVICE (UT_WRITE | UT_CLASS | UT_DEVICE)
14555 +#define UT_WRITE_CLASS_INTERFACE (UT_WRITE | UT_CLASS | UT_INTERFACE)
14556 +#define UT_WRITE_CLASS_OTHER (UT_WRITE | UT_CLASS | UT_OTHER)
14557 +#define UT_WRITE_CLASS_ENDPOINT (UT_WRITE | UT_CLASS | UT_ENDPOINT)
14558 +#define UT_READ_VENDOR_DEVICE (UT_READ | UT_VENDOR | UT_DEVICE)
14559 +#define UT_READ_VENDOR_INTERFACE (UT_READ | UT_VENDOR | UT_INTERFACE)
14560 +#define UT_READ_VENDOR_OTHER (UT_READ | UT_VENDOR | UT_OTHER)
14561 +#define UT_READ_VENDOR_ENDPOINT (UT_READ | UT_VENDOR | UT_ENDPOINT)
14562 +#define UT_WRITE_VENDOR_DEVICE (UT_WRITE | UT_VENDOR | UT_DEVICE)
14563 +#define UT_WRITE_VENDOR_INTERFACE (UT_WRITE | UT_VENDOR | UT_INTERFACE)
14564 +#define UT_WRITE_VENDOR_OTHER (UT_WRITE | UT_VENDOR | UT_OTHER)
14565 +#define UT_WRITE_VENDOR_ENDPOINT (UT_WRITE | UT_VENDOR | UT_ENDPOINT)
14568 +#define UR_GET_STATUS 0x00
14569 +#define USTAT_STANDARD_STATUS 0x00
14570 +#define WUSTAT_WUSB_FEATURE 0x01
14571 +#define WUSTAT_CHANNEL_INFO 0x02
14572 +#define WUSTAT_RECEIVED_DATA 0x03
14573 +#define WUSTAT_MAS_AVAILABILITY 0x04
14574 +#define WUSTAT_CURRENT_TRANSMIT_POWER 0x05
14575 +#define UR_CLEAR_FEATURE 0x01
14576 +#define UR_SET_FEATURE 0x03
14577 +#define UR_SET_AND_TEST_FEATURE 0x0c
14578 +#define UR_SET_ADDRESS 0x05
14579 +#define UR_GET_DESCRIPTOR 0x06
14580 +#define UDESC_DEVICE 0x01
14581 +#define UDESC_CONFIG 0x02
14582 +#define UDESC_STRING 0x03
14583 +#define UDESC_INTERFACE 0x04
14584 +#define UDESC_ENDPOINT 0x05
14585 +#define UDESC_SS_USB_COMPANION 0x30
14586 +#define UDESC_DEVICE_QUALIFIER 0x06
14587 +#define UDESC_OTHER_SPEED_CONFIGURATION 0x07
14588 +#define UDESC_INTERFACE_POWER 0x08
14589 +#define UDESC_OTG 0x09
14590 +#define WUDESC_SECURITY 0x0c
14591 +#define WUDESC_KEY 0x0d
14592 +#define WUD_GET_KEY_INDEX(_wValue_) ((_wValue_) & 0xf)
14593 +#define WUD_GET_KEY_TYPE(_wValue_) (((_wValue_) & 0x30) >> 4)
14594 +#define WUD_KEY_TYPE_ASSOC 0x01
14595 +#define WUD_KEY_TYPE_GTK 0x02
14596 +#define WUD_GET_KEY_ORIGIN(_wValue_) (((_wValue_) & 0x40) >> 6)
14597 +#define WUD_KEY_ORIGIN_HOST 0x00
14598 +#define WUD_KEY_ORIGIN_DEVICE 0x01
14599 +#define WUDESC_ENCRYPTION_TYPE 0x0e
14600 +#define WUDESC_BOS 0x0f
14601 +#define WUDESC_DEVICE_CAPABILITY 0x10
14602 +#define WUDESC_WIRELESS_ENDPOINT_COMPANION 0x11
14603 +#define UDESC_BOS 0x0f
14604 +#define UDESC_DEVICE_CAPABILITY 0x10
14605 +#define UDESC_CS_DEVICE 0x21 /* class specific */
14606 +#define UDESC_CS_CONFIG 0x22
14607 +#define UDESC_CS_STRING 0x23
14608 +#define UDESC_CS_INTERFACE 0x24
14609 +#define UDESC_CS_ENDPOINT 0x25
14610 +#define UDESC_HUB 0x29
14611 +#define UR_SET_DESCRIPTOR 0x07
14612 +#define UR_GET_CONFIG 0x08
14613 +#define UR_SET_CONFIG 0x09
14614 +#define UR_GET_INTERFACE 0x0a
14615 +#define UR_SET_INTERFACE 0x0b
14616 +#define UR_SYNCH_FRAME 0x0c
14617 +#define WUR_SET_ENCRYPTION 0x0d
14618 +#define WUR_GET_ENCRYPTION 0x0e
14619 +#define WUR_SET_HANDSHAKE 0x0f
14620 +#define WUR_GET_HANDSHAKE 0x10
14621 +#define WUR_SET_CONNECTION 0x11
14622 +#define WUR_SET_SECURITY_DATA 0x12
14623 +#define WUR_GET_SECURITY_DATA 0x13
14624 +#define WUR_SET_WUSB_DATA 0x14
14625 +#define WUDATA_DRPIE_INFO 0x01
14626 +#define WUDATA_TRANSMIT_DATA 0x02
14627 +#define WUDATA_TRANSMIT_PARAMS 0x03
14628 +#define WUDATA_RECEIVE_PARAMS 0x04
14629 +#define WUDATA_TRANSMIT_POWER 0x05
14630 +#define WUR_LOOPBACK_DATA_WRITE 0x15
14631 +#define WUR_LOOPBACK_DATA_READ 0x16
14632 +#define WUR_SET_INTERFACE_DS 0x17
14634 +/* Feature numbers */
14635 +#define UF_ENDPOINT_HALT 0
14636 +#define UF_DEVICE_REMOTE_WAKEUP 1
14637 +#define UF_TEST_MODE 2
14638 +#define UF_DEVICE_B_HNP_ENABLE 3
14639 +#define UF_DEVICE_A_HNP_SUPPORT 4
14640 +#define UF_DEVICE_A_ALT_HNP_SUPPORT 5
14641 +#define WUF_WUSB 3
14642 +#define WUF_TX_DRPIE 0x0
14643 +#define WUF_DEV_XMIT_PACKET 0x1
14644 +#define WUF_COUNT_PACKETS 0x2
14645 +#define WUF_CAPTURE_PACKETS 0x3
14646 +#define UF_FUNCTION_SUSPEND 0
14647 +#define UF_U1_ENABLE 48
14648 +#define UF_U2_ENABLE 49
14649 +#define UF_LTM_ENABLE 50
14651 +/* Class requests from the USB 2.0 hub spec, table 11-15 */
14652 +#define UCR_CLEAR_HUB_FEATURE (0x2000 | UR_CLEAR_FEATURE)
14653 +#define UCR_CLEAR_PORT_FEATURE (0x2300 | UR_CLEAR_FEATURE)
14654 +#define UCR_GET_HUB_DESCRIPTOR (0xa000 | UR_GET_DESCRIPTOR)
14655 +#define UCR_GET_HUB_STATUS (0xa000 | UR_GET_STATUS)
14656 +#define UCR_GET_PORT_STATUS (0xa300 | UR_GET_STATUS)
14657 +#define UCR_SET_HUB_FEATURE (0x2000 | UR_SET_FEATURE)
14658 +#define UCR_SET_PORT_FEATURE (0x2300 | UR_SET_FEATURE)
14659 +#define UCR_SET_AND_TEST_PORT_FEATURE (0xa300 | UR_SET_AND_TEST_FEATURE)
14662 +#include <pshpack1.h>
14667 + uByte bDescriptorType;
14668 + uByte bDescriptorSubtype;
14669 +} UPACKED usb_descriptor_t;
14673 + uByte bDescriptorType;
14674 +} UPACKED usb_descriptor_header_t;
14678 + uByte bDescriptorType;
14680 +#define UD_USB_2_0 0x0200
14681 +#define UD_IS_USB2(d) (UGETW((d)->bcdUSB) >= UD_USB_2_0)
14682 + uByte bDeviceClass;
14683 + uByte bDeviceSubClass;
14684 + uByte bDeviceProtocol;
14685 + uByte bMaxPacketSize;
14686 + /* The fields below are not part of the initial descriptor. */
14690 + uByte iManufacturer;
14692 + uByte iSerialNumber;
14693 + uByte bNumConfigurations;
14694 +} UPACKED usb_device_descriptor_t;
14695 +#define USB_DEVICE_DESCRIPTOR_SIZE 18
14699 + uByte bDescriptorType;
14700 + uWord wTotalLength;
14701 + uByte bNumInterface;
14702 + uByte bConfigurationValue;
14703 + uByte iConfiguration;
14704 +#define UC_ATT_ONE (1 << 7) /* must be set */
14705 +#define UC_ATT_SELFPOWER (1 << 6) /* self powered */
14706 +#define UC_ATT_WAKEUP (1 << 5) /* can wakeup */
14707 +#define UC_ATT_BATTERY (1 << 4) /* battery powered */
14708 + uByte bmAttributes;
14709 +#define UC_BUS_POWERED 0x80
14710 +#define UC_SELF_POWERED 0x40
14711 +#define UC_REMOTE_WAKEUP 0x20
14712 + uByte bMaxPower; /* max current in 2 mA units */
14713 +#define UC_POWER_FACTOR 2
14714 +} UPACKED usb_config_descriptor_t;
14715 +#define USB_CONFIG_DESCRIPTOR_SIZE 9
14719 + uByte bDescriptorType;
14720 + uByte bInterfaceNumber;
14721 + uByte bAlternateSetting;
14722 + uByte bNumEndpoints;
14723 + uByte bInterfaceClass;
14724 + uByte bInterfaceSubClass;
14725 + uByte bInterfaceProtocol;
14726 + uByte iInterface;
14727 +} UPACKED usb_interface_descriptor_t;
14728 +#define USB_INTERFACE_DESCRIPTOR_SIZE 9
14732 + uByte bDescriptorType;
14733 + uByte bEndpointAddress;
14734 +#define UE_GET_DIR(a) ((a) & 0x80)
14735 +#define UE_SET_DIR(a,d) ((a) | (((d)&1) << 7))
14736 +#define UE_DIR_IN 0x80
14737 +#define UE_DIR_OUT 0x00
14738 +#define UE_ADDR 0x0f
14739 +#define UE_GET_ADDR(a) ((a) & UE_ADDR)
14740 + uByte bmAttributes;
14741 +#define UE_XFERTYPE 0x03
14742 +#define UE_CONTROL 0x00
14743 +#define UE_ISOCHRONOUS 0x01
14744 +#define UE_BULK 0x02
14745 +#define UE_INTERRUPT 0x03
14746 +#define UE_GET_XFERTYPE(a) ((a) & UE_XFERTYPE)
14747 +#define UE_ISO_TYPE 0x0c
14748 +#define UE_ISO_ASYNC 0x04
14749 +#define UE_ISO_ADAPT 0x08
14750 +#define UE_ISO_SYNC 0x0c
14751 +#define UE_GET_ISO_TYPE(a) ((a) & UE_ISO_TYPE)
14752 + uWord wMaxPacketSize;
14754 +} UPACKED usb_endpoint_descriptor_t;
14755 +#define USB_ENDPOINT_DESCRIPTOR_SIZE 7
14757 +typedef struct ss_endpoint_companion_descriptor {
14759 + uByte bDescriptorType;
14761 +#define USSE_GET_MAX_STREAMS(a) ((a) & 0x1f)
14762 +#define USSE_SET_MAX_STREAMS(a, b) ((a) | ((b) & 0x1f))
14763 +#define USSE_GET_MAX_PACKET_NUM(a) ((a) & 0x03)
14764 +#define USSE_SET_MAX_PACKET_NUM(a, b) ((a) | ((b) & 0x03))
14765 + uByte bmAttributes;
14766 + uWord wBytesPerInterval;
14767 +} UPACKED ss_endpoint_companion_descriptor_t;
14768 +#define USB_SS_ENDPOINT_COMPANION_DESCRIPTOR_SIZE 6
14772 + uByte bDescriptorType;
14773 + uWord bString[127];
14774 +} UPACKED usb_string_descriptor_t;
14775 +#define USB_MAX_STRING_LEN 128
14776 +#define USB_LANGUAGE_TABLE 0 /* # of the string language id table */
14778 +/* Hub specific request */
14779 +#define UR_GET_BUS_STATE 0x02
14780 +#define UR_CLEAR_TT_BUFFER 0x08
14781 +#define UR_RESET_TT 0x09
14782 +#define UR_GET_TT_STATE 0x0a
14783 +#define UR_STOP_TT 0x0b
14785 +/* Hub features */
14786 +#define UHF_C_HUB_LOCAL_POWER 0
14787 +#define UHF_C_HUB_OVER_CURRENT 1
14788 +#define UHF_PORT_CONNECTION 0
14789 +#define UHF_PORT_ENABLE 1
14790 +#define UHF_PORT_SUSPEND 2
14791 +#define UHF_PORT_OVER_CURRENT 3
14792 +#define UHF_PORT_RESET 4
14793 +#define UHF_PORT_L1 5
14794 +#define UHF_PORT_POWER 8
14795 +#define UHF_PORT_LOW_SPEED 9
14796 +#define UHF_PORT_HIGH_SPEED 10
14797 +#define UHF_C_PORT_CONNECTION 16
14798 +#define UHF_C_PORT_ENABLE 17
14799 +#define UHF_C_PORT_SUSPEND 18
14800 +#define UHF_C_PORT_OVER_CURRENT 19
14801 +#define UHF_C_PORT_RESET 20
14802 +#define UHF_C_PORT_L1 23
14803 +#define UHF_PORT_TEST 21
14804 +#define UHF_PORT_INDICATOR 22
14807 + uByte bDescLength;
14808 + uByte bDescriptorType;
14810 + uWord wHubCharacteristics;
14811 +#define UHD_PWR 0x0003
14812 +#define UHD_PWR_GANGED 0x0000
14813 +#define UHD_PWR_INDIVIDUAL 0x0001
14814 +#define UHD_PWR_NO_SWITCH 0x0002
14815 +#define UHD_COMPOUND 0x0004
14816 +#define UHD_OC 0x0018
14817 +#define UHD_OC_GLOBAL 0x0000
14818 +#define UHD_OC_INDIVIDUAL 0x0008
14819 +#define UHD_OC_NONE 0x0010
14820 +#define UHD_TT_THINK 0x0060
14821 +#define UHD_TT_THINK_8 0x0000
14822 +#define UHD_TT_THINK_16 0x0020
14823 +#define UHD_TT_THINK_24 0x0040
14824 +#define UHD_TT_THINK_32 0x0060
14825 +#define UHD_PORT_IND 0x0080
14826 + uByte bPwrOn2PwrGood; /* delay in 2 ms units */
14827 +#define UHD_PWRON_FACTOR 2
14828 + uByte bHubContrCurrent;
14829 + uByte DeviceRemovable[32]; /* max 255 ports */
14830 +#define UHD_NOT_REMOV(desc, i) \
14831 + (((desc)->DeviceRemovable[(i)/8] >> ((i) % 8)) & 1)
14832 + /* deprecated */ uByte PortPowerCtrlMask[1];
14833 +} UPACKED usb_hub_descriptor_t;
14834 +#define USB_HUB_DESCRIPTOR_SIZE 9 /* includes deprecated PortPowerCtrlMask */
14838 + uByte bDescriptorType;
14840 + uByte bDeviceClass;
14841 + uByte bDeviceSubClass;
14842 + uByte bDeviceProtocol;
14843 + uByte bMaxPacketSize0;
14844 + uByte bNumConfigurations;
14846 +} UPACKED usb_device_qualifier_t;
14847 +#define USB_DEVICE_QUALIFIER_SIZE 10
14851 + uByte bDescriptorType;
14852 + uByte bmAttributes;
14853 +#define UOTG_SRP 0x01
14854 +#define UOTG_HNP 0x02
14855 +} UPACKED usb_otg_descriptor_t;
14857 +/* OTG feature selectors */
14858 +#define UOTG_B_HNP_ENABLE 3
14859 +#define UOTG_A_HNP_SUPPORT 4
14860 +#define UOTG_A_ALT_HNP_SUPPORT 5
14864 +/* Device status flags */
14865 +#define UDS_SELF_POWERED 0x0001
14866 +#define UDS_REMOTE_WAKEUP 0x0002
14867 +/* Endpoint status flags */
14868 +#define UES_HALT 0x0001
14869 +} UPACKED usb_status_t;
14872 + uWord wHubStatus;
14873 +#define UHS_LOCAL_POWER 0x0001
14874 +#define UHS_OVER_CURRENT 0x0002
14875 + uWord wHubChange;
14876 +} UPACKED usb_hub_status_t;
14879 + uWord wPortStatus;
14880 +#define UPS_CURRENT_CONNECT_STATUS 0x0001
14881 +#define UPS_PORT_ENABLED 0x0002
14882 +#define UPS_SUSPEND 0x0004
14883 +#define UPS_OVERCURRENT_INDICATOR 0x0008
14884 +#define UPS_RESET 0x0010
14885 +#define UPS_PORT_POWER 0x0100
14886 +#define UPS_LOW_SPEED 0x0200
14887 +#define UPS_HIGH_SPEED 0x0400
14888 +#define UPS_PORT_TEST 0x0800
14889 +#define UPS_PORT_INDICATOR 0x1000
14890 + uWord wPortChange;
14891 +#define UPS_C_CONNECT_STATUS 0x0001
14892 +#define UPS_C_PORT_ENABLED 0x0002
14893 +#define UPS_C_SUSPEND 0x0004
14894 +#define UPS_C_OVERCURRENT_INDICATOR 0x0008
14895 +#define UPS_C_PORT_RESET 0x0010
14896 +} UPACKED usb_port_status_t;
14899 +#include <poppack.h>
14902 +/* Device class codes */
14903 +#define UDCLASS_IN_INTERFACE 0x00
14904 +#define UDCLASS_COMM 0x02
14905 +#define UDCLASS_HUB 0x09
14906 +#define UDSUBCLASS_HUB 0x00
14907 +#define UDPROTO_FSHUB 0x00
14908 +#define UDPROTO_HSHUBSTT 0x01
14909 +#define UDPROTO_HSHUBMTT 0x02
14910 +#define UDCLASS_DIAGNOSTIC 0xdc
14911 +#define UDCLASS_WIRELESS 0xe0
14912 +#define UDSUBCLASS_RF 0x01
14913 +#define UDPROTO_BLUETOOTH 0x01
14914 +#define UDCLASS_VENDOR 0xff
14916 +/* Interface class codes */
14917 +#define UICLASS_UNSPEC 0x00
14919 +#define UICLASS_AUDIO 0x01
14920 +#define UISUBCLASS_AUDIOCONTROL 1
14921 +#define UISUBCLASS_AUDIOSTREAM 2
14922 +#define UISUBCLASS_MIDISTREAM 3
14924 +#define UICLASS_CDC 0x02 /* communication */
14925 +#define UISUBCLASS_DIRECT_LINE_CONTROL_MODEL 1
14926 +#define UISUBCLASS_ABSTRACT_CONTROL_MODEL 2
14927 +#define UISUBCLASS_TELEPHONE_CONTROL_MODEL 3
14928 +#define UISUBCLASS_MULTICHANNEL_CONTROL_MODEL 4
14929 +#define UISUBCLASS_CAPI_CONTROLMODEL 5
14930 +#define UISUBCLASS_ETHERNET_NETWORKING_CONTROL_MODEL 6
14931 +#define UISUBCLASS_ATM_NETWORKING_CONTROL_MODEL 7
14932 +#define UIPROTO_CDC_AT 1
14934 +#define UICLASS_HID 0x03
14935 +#define UISUBCLASS_BOOT 1
14936 +#define UIPROTO_BOOT_KEYBOARD 1
14938 +#define UICLASS_PHYSICAL 0x05
14940 +#define UICLASS_IMAGE 0x06
14942 +#define UICLASS_PRINTER 0x07
14943 +#define UISUBCLASS_PRINTER 1
14944 +#define UIPROTO_PRINTER_UNI 1
14945 +#define UIPROTO_PRINTER_BI 2
14946 +#define UIPROTO_PRINTER_1284 3
14948 +#define UICLASS_MASS 0x08
14949 +#define UISUBCLASS_RBC 1
14950 +#define UISUBCLASS_SFF8020I 2
14951 +#define UISUBCLASS_QIC157 3
14952 +#define UISUBCLASS_UFI 4
14953 +#define UISUBCLASS_SFF8070I 5
14954 +#define UISUBCLASS_SCSI 6
14955 +#define UIPROTO_MASS_CBI_I 0
14956 +#define UIPROTO_MASS_CBI 1
14957 +#define UIPROTO_MASS_BBB_OLD 2 /* Not in the spec anymore */
14958 +#define UIPROTO_MASS_BBB 80 /* 'P' for the Iomega Zip drive */
14960 +#define UICLASS_HUB 0x09
14961 +#define UISUBCLASS_HUB 0
14962 +#define UIPROTO_FSHUB 0
14963 +#define UIPROTO_HSHUBSTT 0 /* Yes, same as previous */
14964 +#define UIPROTO_HSHUBMTT 1
14966 +#define UICLASS_CDC_DATA 0x0a
14967 +#define UISUBCLASS_DATA 0
14968 +#define UIPROTO_DATA_ISDNBRI 0x30 /* Physical iface */
14969 +#define UIPROTO_DATA_HDLC 0x31 /* HDLC */
14970 +#define UIPROTO_DATA_TRANSPARENT 0x32 /* Transparent */
14971 +#define UIPROTO_DATA_Q921M 0x50 /* Management for Q921 */
14972 +#define UIPROTO_DATA_Q921 0x51 /* Data for Q921 */
14973 +#define UIPROTO_DATA_Q921TM 0x52 /* TEI multiplexer for Q921 */
14974 +#define UIPROTO_DATA_V42BIS 0x90 /* Data compression */
14975 +#define UIPROTO_DATA_Q931 0x91 /* Euro-ISDN */
14976 +#define UIPROTO_DATA_V120 0x92 /* V.24 rate adaption */
14977 +#define UIPROTO_DATA_CAPI 0x93 /* CAPI 2.0 commands */
14978 +#define UIPROTO_DATA_HOST_BASED 0xfd /* Host based driver */
14979 +#define UIPROTO_DATA_PUF 0xfe /* see Prot. Unit Func. Desc.*/
14980 +#define UIPROTO_DATA_VENDOR 0xff /* Vendor specific */
14982 +#define UICLASS_SMARTCARD 0x0b
14984 +/*#define UICLASS_FIRM_UPD 0x0c*/
14986 +#define UICLASS_SECURITY 0x0d
14988 +#define UICLASS_DIAGNOSTIC 0xdc
14990 +#define UICLASS_WIRELESS 0xe0
14991 +#define UISUBCLASS_RF 0x01
14992 +#define UIPROTO_BLUETOOTH 0x01
14994 +#define UICLASS_APPL_SPEC 0xfe
14995 +#define UISUBCLASS_FIRMWARE_DOWNLOAD 1
14996 +#define UISUBCLASS_IRDA 2
14997 +#define UIPROTO_IRDA 0
14999 +#define UICLASS_VENDOR 0xff
15001 +#define USB_HUB_MAX_DEPTH 5
15004 + * Minimum time a device needs to be powered down to go through
15005 + * a power cycle. XXX Are these time in the spec?
15007 +#define USB_POWER_DOWN_TIME 200 /* ms */
15008 +#define USB_PORT_POWER_DOWN_TIME 100 /* ms */
15011 +/* These are the values from the spec. */
15012 +#define USB_PORT_RESET_DELAY 10 /* ms */
15013 +#define USB_PORT_ROOT_RESET_DELAY 50 /* ms */
15014 +#define USB_PORT_RESET_RECOVERY 10 /* ms */
15015 +#define USB_PORT_POWERUP_DELAY 100 /* ms */
15016 +#define USB_SET_ADDRESS_SETTLE 2 /* ms */
15017 +#define USB_RESUME_DELAY (20*5) /* ms */
15018 +#define USB_RESUME_WAIT 10 /* ms */
15019 +#define USB_RESUME_RECOVERY 10 /* ms */
15020 +#define USB_EXTRA_POWER_UP_TIME 0 /* ms */
15022 +/* Allow for marginal (i.e. non-conforming) devices. */
15023 +#define USB_PORT_RESET_DELAY 50 /* ms */
15024 +#define USB_PORT_ROOT_RESET_DELAY 250 /* ms */
15025 +#define USB_PORT_RESET_RECOVERY 250 /* ms */
15026 +#define USB_PORT_POWERUP_DELAY 300 /* ms */
15027 +#define USB_SET_ADDRESS_SETTLE 10 /* ms */
15028 +#define USB_RESUME_DELAY (50*5) /* ms */
15029 +#define USB_RESUME_WAIT 50 /* ms */
15030 +#define USB_RESUME_RECOVERY 50 /* ms */
15031 +#define USB_EXTRA_POWER_UP_TIME 20 /* ms */
15034 +#define USB_MIN_POWER 100 /* mA */
15035 +#define USB_MAX_POWER 500 /* mA */
15037 +#define USB_BUS_RESET_DELAY 100 /* ms XXX?*/
15039 +#define USB_UNCONFIG_NO 0
15040 +#define USB_UNCONFIG_INDEX (-1)
15042 +/*** ioctl() related stuff ***/
15044 +struct usb_ctl_request {
15046 + usb_device_request_t ucr_request;
15049 +#define USBD_SHORT_XFER_OK 0x04 /* allow short reads */
15050 + int ucr_actlen; /* actual length transferred */
15053 +struct usb_alt_interface {
15054 + int uai_config_index;
15055 + int uai_interface_index;
15059 +#define USB_CURRENT_CONFIG_INDEX (-1)
15060 +#define USB_CURRENT_ALT_INDEX (-1)
15062 +struct usb_config_desc {
15063 + int ucd_config_index;
15064 + usb_config_descriptor_t ucd_desc;
15067 +struct usb_interface_desc {
15068 + int uid_config_index;
15069 + int uid_interface_index;
15070 + int uid_alt_index;
15071 + usb_interface_descriptor_t uid_desc;
15074 +struct usb_endpoint_desc {
15075 + int ued_config_index;
15076 + int ued_interface_index;
15077 + int ued_alt_index;
15078 + int ued_endpoint_index;
15079 + usb_endpoint_descriptor_t ued_desc;
15082 +struct usb_full_desc {
15083 + int ufd_config_index;
15085 + u_char *ufd_data;
15088 +struct usb_string_desc {
15089 + int usd_string_index;
15090 + int usd_language_id;
15091 + usb_string_descriptor_t usd_desc;
15094 +struct usb_ctl_report_desc {
15096 + u_char ucrd_data[1024]; /* filled data size will vary */
15099 +typedef struct { u_int32_t cookie; } usb_event_cookie_t;
15101 +#define USB_MAX_DEVNAMES 4
15102 +#define USB_MAX_DEVNAMELEN 16
15103 +struct usb_device_info {
15104 + u_int8_t udi_bus;
15105 + u_int8_t udi_addr; /* device address */
15106 + usb_event_cookie_t udi_cookie;
15107 + char udi_product[USB_MAX_STRING_LEN];
15108 + char udi_vendor[USB_MAX_STRING_LEN];
15109 + char udi_release[8];
15110 + u_int16_t udi_productNo;
15111 + u_int16_t udi_vendorNo;
15112 + u_int16_t udi_releaseNo;
15113 + u_int8_t udi_class;
15114 + u_int8_t udi_subclass;
15115 + u_int8_t udi_protocol;
15116 + u_int8_t udi_config;
15117 + u_int8_t udi_speed;
15118 +#define USB_SPEED_UNKNOWN 0
15119 +#define USB_SPEED_LOW 1
15120 +#define USB_SPEED_FULL 2
15121 +#define USB_SPEED_HIGH 3
15122 +#define USB_SPEED_VARIABLE 4
15123 +#define USB_SPEED_SUPER 5
15124 + int udi_power; /* power consumption in mA, 0 if selfpowered */
15126 + char udi_devnames[USB_MAX_DEVNAMES][USB_MAX_DEVNAMELEN];
15127 + u_int8_t udi_ports[16];/* hub only: addresses of devices on ports */
15128 +#define USB_PORT_ENABLED 0xff
15129 +#define USB_PORT_SUSPENDED 0xfe
15130 +#define USB_PORT_POWERED 0xfd
15131 +#define USB_PORT_DISABLED 0xfc
15134 +struct usb_ctl_report {
15136 + u_char ucr_data[1024]; /* filled data size will vary */
15139 +struct usb_device_stats {
15140 + u_long uds_requests[4]; /* indexed by transfer type UE_* */
15143 +#define WUSB_MIN_IE 0x80
15144 +#define WUSB_WCTA_IE 0x80
15145 +#define WUSB_WCONNECTACK_IE 0x81
15146 +#define WUSB_WHOSTINFO_IE 0x82
15147 +#define WUHI_GET_CA(_bmAttributes_) ((_bmAttributes_) & 0x3)
15148 +#define WUHI_CA_RECONN 0x00
15149 +#define WUHI_CA_LIMITED 0x01
15150 +#define WUHI_CA_ALL 0x03
15151 +#define WUHI_GET_MLSI(_bmAttributes_) (((_bmAttributes_) & 0x38) >> 3)
15152 +#define WUSB_WCHCHANGEANNOUNCE_IE 0x83
15153 +#define WUSB_WDEV_DISCONNECT_IE 0x84
15154 +#define WUSB_WHOST_DISCONNECT_IE 0x85
15155 +#define WUSB_WRELEASE_CHANNEL_IE 0x86
15156 +#define WUSB_WWORK_IE 0x87
15157 +#define WUSB_WCHANNEL_STOP_IE 0x88
15158 +#define WUSB_WDEV_KEEPALIVE_IE 0x89
15159 +#define WUSB_WISOCH_DISCARD_IE 0x8A
15160 +#define WUSB_WRESETDEVICE_IE 0x8B
15161 +#define WUSB_WXMIT_PACKET_ADJUST_IE 0x8C
15162 +#define WUSB_MAX_IE 0x8C
15164 +/* Device Notification Types */
15166 +#define WUSB_DN_MIN 0x01
15167 +#define WUSB_DN_CONNECT 0x01
15168 +# define WUSB_DA_OLDCONN 0x00
15169 +# define WUSB_DA_NEWCONN 0x01
15170 +# define WUSB_DA_SELF_BEACON 0x02
15171 +# define WUSB_DA_DIR_BEACON 0x04
15172 +# define WUSB_DA_NO_BEACON 0x06
15173 +#define WUSB_DN_DISCONNECT 0x02
15174 +#define WUSB_DN_EPRDY 0x03
15175 +#define WUSB_DN_MASAVAILCHANGED 0x04
15176 +#define WUSB_DN_REMOTEWAKEUP 0x05
15177 +#define WUSB_DN_SLEEP 0x06
15178 +#define WUSB_DN_ALIVE 0x07
15179 +#define WUSB_DN_MAX 0x07
15182 +#include <pshpack1.h>
15185 +/* WUSB Handshake Data. Used during the SET/GET HANDSHAKE requests */
15186 +typedef struct wusb_hndshk_data {
15187 + uByte bMessageNumber;
15194 +} UPACKED wusb_hndshk_data_t;
15195 +#define WUSB_HANDSHAKE_LEN_FOR_MIC 38
15197 +/* WUSB Connection Context */
15198 +typedef struct wusb_conn_context {
15202 +} UPACKED wusb_conn_context_t;
15204 +/* WUSB Security Descriptor */
15205 +typedef struct wusb_security_desc {
15207 + uByte bDescriptorType;
15208 + uWord wTotalLength;
15209 + uByte bNumEncryptionTypes;
15210 +} UPACKED wusb_security_desc_t;
15212 +/* WUSB Encryption Type Descriptor */
15213 +typedef struct wusb_encrypt_type_desc {
15215 + uByte bDescriptorType;
15217 + uByte bEncryptionType;
15218 +#define WUETD_UNSECURE 0
15219 +#define WUETD_WIRED 1
15220 +#define WUETD_CCM_1 2
15221 +#define WUETD_RSA_1 3
15223 + uByte bEncryptionValue;
15224 + uByte bAuthKeyIndex;
15225 +} UPACKED wusb_encrypt_type_desc_t;
15227 +/* WUSB Key Descriptor */
15228 +typedef struct wusb_key_desc {
15230 + uByte bDescriptorType;
15233 + uByte KeyData[1]; /* variable length */
15234 +} UPACKED wusb_key_desc_t;
15236 +/* WUSB BOS Descriptor (Binary device Object Store) */
15237 +typedef struct wusb_bos_desc {
15239 + uByte bDescriptorType;
15240 + uWord wTotalLength;
15241 + uByte bNumDeviceCaps;
15242 +} UPACKED wusb_bos_desc_t;
15244 +#define USB_DEVICE_CAPABILITY_20_EXTENSION 0x02
15245 +typedef struct usb_dev_cap_20_ext_desc {
15247 + uByte bDescriptorType;
15248 + uByte bDevCapabilityType;
15249 +#define USB_20_EXT_LPM 0x02
15250 + uDWord bmAttributes;
15251 +} UPACKED usb_dev_cap_20_ext_desc_t;
15253 +#define USB_DEVICE_CAPABILITY_SS_USB 0x03
15254 +typedef struct usb_dev_cap_ss_usb {
15256 + uByte bDescriptorType;
15257 + uByte bDevCapabilityType;
15258 +#define USB_DC_SS_USB_LTM_CAPABLE 0x02
15259 + uByte bmAttributes;
15260 +#define USB_DC_SS_USB_SPEED_SUPPORT_LOW 0x01
15261 +#define USB_DC_SS_USB_SPEED_SUPPORT_FULL 0x02
15262 +#define USB_DC_SS_USB_SPEED_SUPPORT_HIGH 0x04
15263 +#define USB_DC_SS_USB_SPEED_SUPPORT_SS 0x08
15264 + uWord wSpeedsSupported;
15265 + uByte bFunctionalitySupport;
15266 + uByte bU1DevExitLat;
15267 + uWord wU2DevExitLat;
15268 +} UPACKED usb_dev_cap_ss_usb_t;
15270 +#define USB_DEVICE_CAPABILITY_CONTAINER_ID 0x04
15271 +typedef struct usb_dev_cap_container_id {
15273 + uByte bDescriptorType;
15274 + uByte bDevCapabilityType;
15276 + uByte containerID[16];
15277 +} UPACKED usb_dev_cap_container_id_t;
15279 +/* Device Capability Type Codes */
15280 +#define WUSB_DEVICE_CAPABILITY_WIRELESS_USB 0x01
15282 +/* Device Capability Descriptor */
15283 +typedef struct wusb_dev_cap_desc {
15285 + uByte bDescriptorType;
15286 + uByte bDevCapabilityType;
15287 + uByte caps[1]; /* Variable length */
15288 +} UPACKED wusb_dev_cap_desc_t;
15290 +/* Device Capability Descriptor */
15291 +typedef struct wusb_dev_cap_uwb_desc {
15293 + uByte bDescriptorType;
15294 + uByte bDevCapabilityType;
15295 + uByte bmAttributes;
15296 + uWord wPHYRates; /* Bitmap */
15297 + uByte bmTFITXPowerInfo;
15298 + uByte bmFFITXPowerInfo;
15299 + uWord bmBandGroup;
15301 +} UPACKED wusb_dev_cap_uwb_desc_t;
15303 +/* Wireless USB Endpoint Companion Descriptor */
15304 +typedef struct wusb_endpoint_companion_desc {
15306 + uByte bDescriptorType;
15308 + uByte bMaxSequence;
15309 + uWord wMaxStreamDelay;
15310 + uWord wOverTheAirPacketSize;
15311 + uByte bOverTheAirInterval;
15312 + uByte bmCompAttributes;
15313 +} UPACKED wusb_endpoint_companion_desc_t;
15315 +/* Wireless USB Numeric Association M1 Data Structure */
15316 +typedef struct wusb_m1_data {
15319 + uByte deviceFriendlyNameLength;
15320 + uByte sha_256_m3[32];
15321 + uByte deviceFriendlyName[256];
15322 +} UPACKED wusb_m1_data_t;
15324 +typedef struct wusb_m2_data {
15327 + uByte hostFriendlyNameLength;
15329 + uByte hostFriendlyName[256];
15330 +} UPACKED wusb_m2_data_t;
15332 +typedef struct wusb_m3_data {
15335 +} UPACKED wusb_m3_data_t;
15337 +typedef struct wusb_m4_data {
15338 + uDWord _attributeTypeIdAndLength_1;
15339 + uWord associationTypeId;
15341 + uDWord _attributeTypeIdAndLength_2;
15342 + uWord associationSubTypeId;
15344 + uDWord _attributeTypeIdAndLength_3;
15347 + uDWord _attributeTypeIdAndLength_4;
15348 + uDWord associationStatus;
15350 + uDWord _attributeTypeIdAndLength_5;
15353 + uDWord _attributeTypeIdAndLength_6;
15356 + uDWord _attributeTypeIdAndLength_7;
15357 + uByte bandGroups[2];
15358 +} UPACKED wusb_m4_data_t;
15361 +#include <poppack.h>
15364 +#ifdef __cplusplus
15368 +#endif /* _USB_H_ */
15370 +++ b/drivers/usb/host/dwc_otg/Makefile
15373 +# Makefile for DWC_otg Highspeed USB controller driver
15376 +ifneq ($(KERNELRELEASE),)
15378 +# Use the BUS_INTERFACE variable to compile the software for either
15379 +# PCI(PCI_INTERFACE) or LM(LM_INTERFACE) bus.
15380 +ifeq ($(BUS_INTERFACE),)
15381 +# BUS_INTERFACE = -DPCI_INTERFACE
15382 +# BUS_INTERFACE = -DLM_INTERFACE
15383 + BUS_INTERFACE = -DPLATFORM_INTERFACE
15386 +#ccflags-y += -DDEBUG
15387 +#ccflags-y += -DDWC_OTG_DEBUGLEV=1 # reduce common debug msgs
15389 +# Use one of the following flags to compile the software in host-only or
15390 +# device-only mode.
15391 +#ccflags-y += -DDWC_HOST_ONLY
15392 +#ccflags-y += -DDWC_DEVICE_ONLY
15394 +ccflags-y += -Dlinux -DDWC_HS_ELECT_TST
15395 +#ccflags-y += -DDWC_EN_ISOC
15396 +ccflags-y += -I$(srctree)/drivers/usb/host/dwc_common_port
15397 +#ccflags-y += -I$(PORTLIB)
15398 +ccflags-y += -DDWC_LINUX
15399 +ccflags-y += $(CFI)
15400 +ccflags-y += $(BUS_INTERFACE)
15401 +#ccflags-y += -DDWC_DEV_SRPCAP
15403 +obj-$(CONFIG_USB_DWCOTG) += dwc_otg.o
15405 +dwc_otg-objs := dwc_otg_driver.o dwc_otg_attr.o
15406 +dwc_otg-objs += dwc_otg_cil.o dwc_otg_cil_intr.o
15407 +dwc_otg-objs += dwc_otg_pcd_linux.o dwc_otg_pcd.o dwc_otg_pcd_intr.o
15408 +dwc_otg-objs += dwc_otg_hcd.o dwc_otg_hcd_linux.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o dwc_otg_hcd_ddma.o
15409 +dwc_otg-objs += dwc_otg_adp.o
15410 +dwc_otg-objs += dwc_otg_fiq_fsm.o
15411 +ifneq ($(CONFIG_ARM64),y)
15412 +dwc_otg-objs += dwc_otg_fiq_stub.o
15416 +dwc_otg-objs += dwc_otg_cfi.o
15419 +kernrelwd := $(subst ., ,$(KERNELRELEASE))
15420 +kernrel3 := $(word 1,$(kernrelwd)).$(word 2,$(kernrelwd)).$(word 3,$(kernrelwd))
15422 +ifneq ($(kernrel3),2.6.20)
15423 +ccflags-y += $(CPPFLAGS)
15428 +PWD := $(shell pwd)
15429 +PORTLIB := $(PWD)/../dwc_common_port
15433 +DOXYGEN := $(DOXYGEN)
15436 + $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
15439 + $(MAKE) -C$(KDIR) M=$(PORTLIB) modules_install
15440 + $(MAKE) -C$(KDIR) M=$(PWD) modules_install
15443 + $(MAKE) -C$(KDIR) M=$(PORTLIB) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
15444 + cp $(PORTLIB)/Module.symvers $(PWD)/
15446 +docs: $(wildcard *.[hc]) doc/doxygen.cfg
15447 + $(DOXYGEN) doc/doxygen.cfg
15449 +tags: $(wildcard *.[hc])
15450 + $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)
15454 + rm -rf *.o *.ko .*cmd *.mod.c .tmp_versions Module.symvers
15458 +++ b/drivers/usb/host/dwc_otg/doc/doxygen.cfg
15460 +# Doxyfile 1.3.9.1
15462 +#---------------------------------------------------------------------------
15463 +# Project related configuration options
15464 +#---------------------------------------------------------------------------
15465 +PROJECT_NAME = "DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver"
15466 +PROJECT_NUMBER = v3.00a
15467 +OUTPUT_DIRECTORY = ./doc/
15468 +CREATE_SUBDIRS = NO
15469 +OUTPUT_LANGUAGE = English
15470 +BRIEF_MEMBER_DESC = YES
15471 +REPEAT_BRIEF = YES
15472 +ABBREVIATE_BRIEF = "The $name class" \
15473 + "The $name widget" \
15474 + "The $name file" \
15483 +ALWAYS_DETAILED_SEC = NO
15484 +INLINE_INHERITED_MEMB = NO
15485 +FULL_PATH_NAMES = NO
15487 +STRIP_FROM_INC_PATH =
15489 +JAVADOC_AUTOBRIEF = YES
15490 +MULTILINE_CPP_IS_BRIEF = NO
15491 +INHERIT_DOCS = YES
15492 +DISTRIBUTE_GROUP_DOC = NO
15495 +OPTIMIZE_OUTPUT_FOR_C = YES
15496 +OPTIMIZE_OUTPUT_JAVA = NO
15498 +#---------------------------------------------------------------------------
15499 +# Build related configuration options
15500 +#---------------------------------------------------------------------------
15502 +EXTRACT_PRIVATE = YES
15503 +EXTRACT_STATIC = YES
15504 +EXTRACT_LOCAL_CLASSES = YES
15505 +EXTRACT_LOCAL_METHODS = NO
15506 +HIDE_UNDOC_MEMBERS = NO
15507 +HIDE_UNDOC_CLASSES = NO
15508 +HIDE_FRIEND_COMPOUNDS = NO
15509 +HIDE_IN_BODY_DOCS = NO
15510 +INTERNAL_DOCS = NO
15511 +CASE_SENSE_NAMES = NO
15512 +HIDE_SCOPE_NAMES = NO
15513 +SHOW_INCLUDE_FILES = YES
15515 +SORT_MEMBER_DOCS = NO
15516 +SORT_BRIEF_DOCS = NO
15517 +SORT_BY_SCOPE_NAME = NO
15518 +GENERATE_TODOLIST = YES
15519 +GENERATE_TESTLIST = YES
15520 +GENERATE_BUGLIST = YES
15521 +GENERATE_DEPRECATEDLIST= YES
15522 +ENABLED_SECTIONS =
15523 +MAX_INITIALIZER_LINES = 30
15524 +SHOW_USED_FILES = YES
15525 +SHOW_DIRECTORIES = YES
15526 +#---------------------------------------------------------------------------
15527 +# configuration options related to warning and progress messages
15528 +#---------------------------------------------------------------------------
15531 +WARN_IF_UNDOCUMENTED = NO
15532 +WARN_IF_DOC_ERROR = YES
15533 +WARN_FORMAT = "$file:$line: $text"
15535 +#---------------------------------------------------------------------------
15536 +# configuration options related to the input files
15537 +#---------------------------------------------------------------------------
15539 +FILE_PATTERNS = *.c \
15544 +EXCLUDE = ./test/ \
15545 + ./dwc_otg/.AppleDouble/
15546 +EXCLUDE_SYMLINKS = YES
15547 +EXCLUDE_PATTERNS = *.mod.*
15549 +EXAMPLE_PATTERNS = *
15550 +EXAMPLE_RECURSIVE = NO
15554 +FILTER_SOURCE_FILES = NO
15555 +#---------------------------------------------------------------------------
15556 +# configuration options related to source browsing
15557 +#---------------------------------------------------------------------------
15558 +SOURCE_BROWSER = YES
15559 +INLINE_SOURCES = NO
15560 +STRIP_CODE_COMMENTS = YES
15561 +REFERENCED_BY_RELATION = NO
15562 +REFERENCES_RELATION = NO
15563 +VERBATIM_HEADERS = NO
15564 +#---------------------------------------------------------------------------
15565 +# configuration options related to the alphabetical class index
15566 +#---------------------------------------------------------------------------
15567 +ALPHABETICAL_INDEX = NO
15568 +COLS_IN_ALPHA_INDEX = 5
15570 +#---------------------------------------------------------------------------
15571 +# configuration options related to the HTML output
15572 +#---------------------------------------------------------------------------
15573 +GENERATE_HTML = YES
15574 +HTML_OUTPUT = html
15575 +HTML_FILE_EXTENSION = .html
15579 +HTML_ALIGN_MEMBERS = YES
15580 +GENERATE_HTMLHELP = NO
15586 +DISABLE_INDEX = NO
15587 +ENUM_VALUES_PER_LINE = 4
15588 +GENERATE_TREEVIEW = YES
15589 +TREEVIEW_WIDTH = 250
15590 +#---------------------------------------------------------------------------
15591 +# configuration options related to the LaTeX output
15592 +#---------------------------------------------------------------------------
15593 +GENERATE_LATEX = NO
15594 +LATEX_OUTPUT = latex
15595 +LATEX_CMD_NAME = latex
15596 +MAKEINDEX_CMD_NAME = makeindex
15597 +COMPACT_LATEX = NO
15598 +PAPER_TYPE = a4wide
15601 +PDF_HYPERLINKS = NO
15603 +LATEX_BATCHMODE = NO
15604 +LATEX_HIDE_INDICES = NO
15605 +#---------------------------------------------------------------------------
15606 +# configuration options related to the RTF output
15607 +#---------------------------------------------------------------------------
15611 +RTF_HYPERLINKS = NO
15612 +RTF_STYLESHEET_FILE =
15613 +RTF_EXTENSIONS_FILE =
15614 +#---------------------------------------------------------------------------
15615 +# configuration options related to the man page output
15616 +#---------------------------------------------------------------------------
15619 +MAN_EXTENSION = .3
15621 +#---------------------------------------------------------------------------
15622 +# configuration options related to the XML output
15623 +#---------------------------------------------------------------------------
15628 +XML_PROGRAMLISTING = YES
15629 +#---------------------------------------------------------------------------
15630 +# configuration options for the AutoGen Definitions output
15631 +#---------------------------------------------------------------------------
15632 +GENERATE_AUTOGEN_DEF = NO
15633 +#---------------------------------------------------------------------------
15634 +# configuration options related to the Perl module output
15635 +#---------------------------------------------------------------------------
15636 +GENERATE_PERLMOD = NO
15637 +PERLMOD_LATEX = NO
15638 +PERLMOD_PRETTY = YES
15639 +PERLMOD_MAKEVAR_PREFIX =
15640 +#---------------------------------------------------------------------------
15641 +# Configuration options related to the preprocessor
15642 +#---------------------------------------------------------------------------
15643 +ENABLE_PREPROCESSING = YES
15644 +MACRO_EXPANSION = YES
15645 +EXPAND_ONLY_PREDEF = YES
15646 +SEARCH_INCLUDES = YES
15648 +INCLUDE_FILE_PATTERNS =
15649 +PREDEFINED = DEVICE_ATTR DWC_EN_ISOC
15650 +EXPAND_AS_DEFINED = DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW DWC_OTG_DEVICE_ATTR_BITFIELD_STORE DWC_OTG_DEVICE_ATTR_BITFIELD_RW DWC_OTG_DEVICE_ATTR_BITFIELD_RO DWC_OTG_DEVICE_ATTR_REG_SHOW DWC_OTG_DEVICE_ATTR_REG_STORE DWC_OTG_DEVICE_ATTR_REG32_RW DWC_OTG_DEVICE_ATTR_REG32_RO DWC_EN_ISOC
15651 +SKIP_FUNCTION_MACROS = NO
15652 +#---------------------------------------------------------------------------
15653 +# Configuration::additions related to external references
15654 +#---------------------------------------------------------------------------
15656 +GENERATE_TAGFILE =
15658 +EXTERNAL_GROUPS = YES
15659 +PERL_PATH = /usr/bin/perl
15660 +#---------------------------------------------------------------------------
15661 +# Configuration options related to the dot tool
15662 +#---------------------------------------------------------------------------
15663 +CLASS_DIAGRAMS = YES
15664 +HIDE_UNDOC_RELATIONS = YES
15667 +COLLABORATION_GRAPH = YES
15669 +TEMPLATE_RELATIONS = NO
15670 +INCLUDE_GRAPH = YES
15671 +INCLUDED_BY_GRAPH = YES
15673 +GRAPHICAL_HIERARCHY = YES
15674 +DOT_IMAGE_FORMAT = png
15677 +MAX_DOT_GRAPH_DEPTH = 1000
15678 +GENERATE_LEGEND = YES
15680 +#---------------------------------------------------------------------------
15681 +# Configuration::additions related to the search engine
15682 +#---------------------------------------------------------------------------
15685 +++ b/drivers/usb/host/dwc_otg/dummy_audio.c
15688 + * zero.c -- Gadget Zero, for USB development
15690 + * Copyright (C) 2003-2004 David Brownell
15691 + * All rights reserved.
15693 + * Redistribution and use in source and binary forms, with or without
15694 + * modification, are permitted provided that the following conditions
15696 + * 1. Redistributions of source code must retain the above copyright
15697 + * notice, this list of conditions, and the following disclaimer,
15698 + * without modification.
15699 + * 2. Redistributions in binary form must reproduce the above copyright
15700 + * notice, this list of conditions and the following disclaimer in the
15701 + * documentation and/or other materials provided with the distribution.
15702 + * 3. The names of the above-listed copyright holders may not be used
15703 + * to endorse or promote products derived from this software without
15704 + * specific prior written permission.
15706 + * ALTERNATIVELY, this software may be distributed under the terms of the
15707 + * GNU General Public License ("GPL") as published by the Free Software
15708 + * Foundation, either version 2 of that License or (at your option) any
15711 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
15712 + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
15713 + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
15714 + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
15715 + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
15716 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
15717 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
15718 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
15719 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
15720 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
15721 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
15726 + * Gadget Zero only needs two bulk endpoints, and is an example of how you
15727 + * can write a hardware-agnostic gadget driver running inside a USB device.
15729 + * Hardware details are visible (see CONFIG_USB_ZERO_* below) but don't
15730 + * affect most of the driver.
15732 + * Use it with the Linux host/master side "usbtest" driver to get a basic
15733 + * functional test of your device-side usb stack, or with "usb-skeleton".
15735 + * It supports two similar configurations. One sinks whatever the usb host
15736 + * writes, and in return sources zeroes. The other loops whatever the host
15737 + * writes back, so the host can read it. Module options include:
15739 + * buflen=N default N=4096, buffer size used
15740 + * qlen=N default N=32, how many buffers in the loopback queue
15741 + * loopdefault default false, list loopback config first
15743 + * Many drivers will only have one configuration, letting them be much
15744 + * simpler if they also don't support high speed operation (like this
15748 +#include <linux/config.h>
15749 +#include <linux/module.h>
15750 +#include <linux/kernel.h>
15751 +#include <linux/delay.h>
15752 +#include <linux/ioport.h>
15753 +#include <linux/sched.h>
15754 +#include <linux/slab.h>
15755 +#include <linux/smp_lock.h>
15756 +#include <linux/errno.h>
15757 +#include <linux/init.h>
15758 +#include <linux/timer.h>
15759 +#include <linux/list.h>
15760 +#include <linux/interrupt.h>
15761 +#include <linux/uts.h>
15762 +#include <linux/version.h>
15763 +#include <linux/device.h>
15764 +#include <linux/moduleparam.h>
15765 +#include <linux/proc_fs.h>
15767 +#include <asm/byteorder.h>
15768 +#include <asm/io.h>
15769 +#include <asm/irq.h>
15770 +#include <asm/system.h>
15771 +#include <asm/unaligned.h>
15773 +# include <linux/usb/ch9.h>
15775 +#include <linux/usb_gadget.h>
15778 +/*-------------------------------------------------------------------------*/
15779 +/*-------------------------------------------------------------------------*/
15782 +static int utf8_to_utf16le(const char *s, u16 *cp, unsigned len)
15788 + /* this insists on correct encodings, though not minimal ones.
15789 + * BUT it currently rejects legit 4-byte UTF-8 code points,
15790 + * which need surrogate pairs. (Unicode 3.1 can use them.)
15792 + while (len != 0 && (c = (u8) *s++) != 0) {
15793 + if (unlikely(c & 0x80)) {
15794 + // 2-byte sequence:
15795 + // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
15796 + if ((c & 0xe0) == 0xc0) {
15797 + uchar = (c & 0x1f) << 6;
15800 + if ((c & 0xc0) != 0xc0)
15805 + // 3-byte sequence (most CJKV characters):
15806 + // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
15807 + } else if ((c & 0xf0) == 0xe0) {
15808 + uchar = (c & 0x0f) << 12;
15811 + if ((c & 0xc0) != 0xc0)
15817 + if ((c & 0xc0) != 0xc0)
15822 + /* no bogus surrogates */
15823 + if (0xd800 <= uchar && uchar <= 0xdfff)
15826 + // 4-byte sequence (surrogate pairs, currently rare):
15827 + // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
15828 + // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
15829 + // (uuuuu = wwww + 1)
15830 + // FIXME accept the surrogate code points (only)
15836 + put_unaligned (cpu_to_le16 (uchar), cp++);
15847 + * usb_gadget_get_string - fill out a string descriptor
15848 + * @table: of c strings encoded using UTF-8
15849 + * @id: string id, from low byte of wValue in get string descriptor
15850 + * @buf: at least 256 bytes
15852 + * Finds the UTF-8 string matching the ID, and converts it into a
15853 + * string descriptor in utf16-le.
15854 + * Returns length of descriptor (always even) or negative errno
15856 + * If your driver needs stings in multiple languages, you'll probably
15857 + * "switch (wIndex) { ... }" in your ep0 string descriptor logic,
15858 + * using this routine after choosing which set of UTF-8 strings to use.
15859 + * Note that US-ASCII is a strict subset of UTF-8; any string bytes with
15860 + * the eighth bit set will be multibyte UTF-8 characters, not ISO-8859/1
15861 + * characters (which are also widely used in C strings).
15864 +usb_gadget_get_string (struct usb_gadget_strings *table, int id, u8 *buf)
15866 + struct usb_string *s;
15869 + /* descriptor 0 has the language id */
15872 + buf [1] = USB_DT_STRING;
15873 + buf [2] = (u8) table->language;
15874 + buf [3] = (u8) (table->language >> 8);
15877 + for (s = table->strings; s && s->s; s++)
15881 + /* unrecognized: stall. */
15885 + /* string descriptors have length, tag, then UTF16-LE text */
15886 + len = min ((size_t) 126, strlen (s->s));
15887 + memset (buf + 2, 0, 2 * len); /* zero all the bytes */
15888 + len = utf8_to_utf16le(s->s, (u16 *)&buf[2], len);
15891 + buf [0] = (len + 1) * 2;
15892 + buf [1] = USB_DT_STRING;
15897 +/*-------------------------------------------------------------------------*/
15898 +/*-------------------------------------------------------------------------*/
15902 + * usb_descriptor_fillbuf - fill buffer with descriptors
15903 + * @buf: Buffer to be filled
15904 + * @buflen: Size of buf
15905 + * @src: Array of descriptor pointers, terminated by null pointer.
15907 + * Copies descriptors into the buffer, returning the length or a
15908 + * negative error code if they can't all be copied. Useful when
15909 + * assembling descriptors for an associated set of interfaces used
15910 + * as part of configuring a composite device; or in other cases where
15911 + * sets of descriptors need to be marshaled.
15914 +usb_descriptor_fillbuf(void *buf, unsigned buflen,
15915 + const struct usb_descriptor_header **src)
15922 + /* fill buffer from src[] until null descriptor ptr */
15923 + for (; 0 != *src; src++) {
15924 + unsigned len = (*src)->bLength;
15926 + if (len > buflen)
15928 + memcpy(dest, *src, len);
15932 + return dest - (u8 *)buf;
15937 + * usb_gadget_config_buf - builts a complete configuration descriptor
15938 + * @config: Header for the descriptor, including characteristics such
15939 + * as power requirements and number of interfaces.
15940 + * @desc: Null-terminated vector of pointers to the descriptors (interface,
15941 + * endpoint, etc) defining all functions in this device configuration.
15942 + * @buf: Buffer for the resulting configuration descriptor.
15943 + * @length: Length of buffer. If this is not big enough to hold the
15944 + * entire configuration descriptor, an error code will be returned.
15946 + * This copies descriptors into the response buffer, building a descriptor
15947 + * for that configuration. It returns the buffer length or a negative
15948 + * status code. The config.wTotalLength field is set to match the length
15949 + * of the result, but other descriptor fields (including power usage and
15950 + * interface count) must be set by the caller.
15952 + * Gadget drivers could use this when constructing a config descriptor
15953 + * in response to USB_REQ_GET_DESCRIPTOR. They will need to patch the
15954 + * resulting bDescriptorType value if USB_DT_OTHER_SPEED_CONFIG is needed.
15956 +int usb_gadget_config_buf(
15957 + const struct usb_config_descriptor *config,
15960 + const struct usb_descriptor_header **desc
15963 + struct usb_config_descriptor *cp = buf;
15966 + /* config descriptor first */
15967 + if (length < USB_DT_CONFIG_SIZE || !desc)
15971 + /* then interface/endpoint/class/vendor/... */
15972 + len = usb_descriptor_fillbuf(USB_DT_CONFIG_SIZE + (u8*)buf,
15973 + length - USB_DT_CONFIG_SIZE, desc);
15976 + len += USB_DT_CONFIG_SIZE;
15977 + if (len > 0xffff)
15980 + /* patch up the config descriptor */
15981 + cp->bLength = USB_DT_CONFIG_SIZE;
15982 + cp->bDescriptorType = USB_DT_CONFIG;
15983 + cp->wTotalLength = cpu_to_le16(len);
15984 + cp->bmAttributes |= USB_CONFIG_ATT_ONE;
15988 +/*-------------------------------------------------------------------------*/
15989 +/*-------------------------------------------------------------------------*/
15992 +#define RBUF_LEN (1024*1024)
15993 +static int rbuf_start;
15994 +static int rbuf_len;
15995 +static __u8 rbuf[RBUF_LEN];
15997 +/*-------------------------------------------------------------------------*/
15999 +#define DRIVER_VERSION "St Patrick's Day 2004"
16001 +static const char shortname [] = "zero";
16002 +static const char longname [] = "YAMAHA YST-MS35D USB Speaker ";
16004 +static const char source_sink [] = "source and sink data";
16005 +static const char loopback [] = "loop input to output";
16007 +/*-------------------------------------------------------------------------*/
16010 + * driver assumes self-powered hardware, and
16011 + * has no way for users to trigger remote wakeup.
16013 + * this version autoconfigures as much as possible,
16014 + * which is reasonable for most "bulk-only" drivers.
16016 +static const char *EP_IN_NAME; /* source */
16017 +static const char *EP_OUT_NAME; /* sink */
16019 +/*-------------------------------------------------------------------------*/
16021 +/* big enough to hold our biggest descriptor */
16022 +#define USB_BUFSIZ 512
16026 + struct usb_gadget *gadget;
16027 + struct usb_request *req; /* for control responses */
16029 + /* when configured, we have one of two configs:
16030 + * - source data (in to host) and sink it (out from host)
16031 + * - or loop it back (out from host back in to host)
16034 + struct usb_ep *in_ep, *out_ep;
16036 + /* autoresume timer */
16037 + struct timer_list resume;
16040 +#define xprintk(d,level,fmt,args...) \
16041 + dev_printk(level , &(d)->gadget->dev , fmt , ## args)
16044 +#define DBG(dev,fmt,args...) \
16045 + xprintk(dev , KERN_DEBUG , fmt , ## args)
16047 +#define DBG(dev,fmt,args...) \
16049 +#endif /* DEBUG */
16054 +#define VDBG(dev,fmt,args...) \
16056 +#endif /* VERBOSE */
16058 +#define ERROR(dev,fmt,args...) \
16059 + xprintk(dev , KERN_ERR , fmt , ## args)
16060 +#define WARN(dev,fmt,args...) \
16061 + xprintk(dev , KERN_WARNING , fmt , ## args)
16062 +#define INFO(dev,fmt,args...) \
16063 + xprintk(dev , KERN_INFO , fmt , ## args)
16065 +/*-------------------------------------------------------------------------*/
16067 +static unsigned buflen = 4096;
16068 +static unsigned qlen = 32;
16069 +static unsigned pattern = 0;
16071 +module_param (buflen, uint, S_IRUGO|S_IWUSR);
16072 +module_param (qlen, uint, S_IRUGO|S_IWUSR);
16073 +module_param (pattern, uint, S_IRUGO|S_IWUSR);
16076 + * if it's nonzero, autoresume says how many seconds to wait
16077 + * before trying to wake up the host after suspend.
16079 +static unsigned autoresume = 0;
16080 +module_param (autoresume, uint, 0);
16083 + * Normally the "loopback" configuration is second (index 1) so
16084 + * it's not the default. Here's where to change that order, to
16085 + * work better with hosts where config changes are problematic.
16086 + * Or controllers (like superh) that only support one config.
16088 +static int loopdefault = 0;
16090 +module_param (loopdefault, bool, S_IRUGO|S_IWUSR);
16092 +/*-------------------------------------------------------------------------*/
16094 +/* Thanks to NetChip Technologies for donating this product ID.
16096 + * DO NOT REUSE THESE IDs with a protocol-incompatible driver!! Ever!!
16097 + * Instead: allocate your own, using normal USB-IF procedures.
16099 +#ifndef CONFIG_USB_ZERO_HNPTEST
16100 +#define DRIVER_VENDOR_NUM 0x0525 /* NetChip */
16101 +#define DRIVER_PRODUCT_NUM 0xa4a0 /* Linux-USB "Gadget Zero" */
16103 +#define DRIVER_VENDOR_NUM 0x1a0a /* OTG test device IDs */
16104 +#define DRIVER_PRODUCT_NUM 0xbadd
16107 +/*-------------------------------------------------------------------------*/
16110 + * DESCRIPTORS ... most are static, but strings and (full)
16111 + * configuration descriptors are built on demand.
16115 +#define STRING_MANUFACTURER 25
16116 +#define STRING_PRODUCT 42
16117 +#define STRING_SERIAL 101
16119 +#define STRING_MANUFACTURER 1
16120 +#define STRING_PRODUCT 2
16121 +#define STRING_SERIAL 3
16123 +#define STRING_SOURCE_SINK 250
16124 +#define STRING_LOOPBACK 251
16127 + * This device advertises two configurations; these numbers work
16128 + * on a pxa250 as well as more flexible hardware.
16130 +#define CONFIG_SOURCE_SINK 3
16131 +#define CONFIG_LOOPBACK 2
16134 +static struct usb_device_descriptor
16136 + .bLength = sizeof device_desc,
16137 + .bDescriptorType = USB_DT_DEVICE,
16139 + .bcdUSB = __constant_cpu_to_le16 (0x0200),
16140 + .bDeviceClass = USB_CLASS_VENDOR_SPEC,
16142 + .idVendor = __constant_cpu_to_le16 (DRIVER_VENDOR_NUM),
16143 + .idProduct = __constant_cpu_to_le16 (DRIVER_PRODUCT_NUM),
16144 + .iManufacturer = STRING_MANUFACTURER,
16145 + .iProduct = STRING_PRODUCT,
16146 + .iSerialNumber = STRING_SERIAL,
16147 + .bNumConfigurations = 2,
16150 +static struct usb_device_descriptor
16152 + .bLength = sizeof device_desc,
16153 + .bDescriptorType = USB_DT_DEVICE,
16154 + .bcdUSB = __constant_cpu_to_le16 (0x0100),
16155 + .bDeviceClass = USB_CLASS_PER_INTERFACE,
16156 + .bDeviceSubClass = 0,
16157 + .bDeviceProtocol = 0,
16158 + .bMaxPacketSize0 = 64,
16159 + .bcdDevice = __constant_cpu_to_le16 (0x0100),
16160 + .idVendor = __constant_cpu_to_le16 (0x0499),
16161 + .idProduct = __constant_cpu_to_le16 (0x3002),
16162 + .iManufacturer = STRING_MANUFACTURER,
16163 + .iProduct = STRING_PRODUCT,
16164 + .iSerialNumber = STRING_SERIAL,
16165 + .bNumConfigurations = 1,
16168 +static struct usb_config_descriptor
16170 + .bLength = sizeof z_config,
16171 + .bDescriptorType = USB_DT_CONFIG,
16173 + /* compute wTotalLength on the fly */
16174 + .bNumInterfaces = 2,
16175 + .bConfigurationValue = 1,
16176 + .iConfiguration = 0,
16177 + .bmAttributes = 0x40,
16178 + .bMaxPower = 0, /* self-powered */
16182 +static struct usb_otg_descriptor
16183 +otg_descriptor = {
16184 + .bLength = sizeof otg_descriptor,
16185 + .bDescriptorType = USB_DT_OTG,
16187 + .bmAttributes = USB_OTG_SRP,
16190 +/* one interface in each configuration */
16191 +#ifdef CONFIG_USB_GADGET_DUALSPEED
16194 + * usb 2.0 devices need to expose both high speed and full speed
16195 + * descriptors, unless they only run at full speed.
16197 + * that means alternate endpoint descriptors (bigger packets)
16198 + * and a "device qualifier" ... plus more construction options
16199 + * for the config descriptor.
16202 +static struct usb_qualifier_descriptor
16204 + .bLength = sizeof dev_qualifier,
16205 + .bDescriptorType = USB_DT_DEVICE_QUALIFIER,
16207 + .bcdUSB = __constant_cpu_to_le16 (0x0200),
16208 + .bDeviceClass = USB_CLASS_VENDOR_SPEC,
16210 + .bNumConfigurations = 2,
16214 +struct usb_cs_as_general_descriptor {
16216 + __u8 bDescriptorType;
16218 + __u8 bDescriptorSubType;
16219 + __u8 bTerminalLink;
16221 + __u16 wFormatTag;
16222 +} __attribute__ ((packed));
16224 +struct usb_cs_as_format_descriptor {
16226 + __u8 bDescriptorType;
16228 + __u8 bDescriptorSubType;
16229 + __u8 bFormatType;
16230 + __u8 bNrChannels;
16231 + __u8 bSubframeSize;
16232 + __u8 bBitResolution;
16233 + __u8 bSamfreqType;
16234 + __u8 tLowerSamFreq[3];
16235 + __u8 tUpperSamFreq[3];
16236 +} __attribute__ ((packed));
16238 +static const struct usb_interface_descriptor
16239 +z_audio_control_if_desc = {
16240 + .bLength = sizeof z_audio_control_if_desc,
16241 + .bDescriptorType = USB_DT_INTERFACE,
16242 + .bInterfaceNumber = 0,
16243 + .bAlternateSetting = 0,
16244 + .bNumEndpoints = 0,
16245 + .bInterfaceClass = USB_CLASS_AUDIO,
16246 + .bInterfaceSubClass = 0x1,
16247 + .bInterfaceProtocol = 0,
16251 +static const struct usb_interface_descriptor
16252 +z_audio_if_desc = {
16253 + .bLength = sizeof z_audio_if_desc,
16254 + .bDescriptorType = USB_DT_INTERFACE,
16255 + .bInterfaceNumber = 1,
16256 + .bAlternateSetting = 0,
16257 + .bNumEndpoints = 0,
16258 + .bInterfaceClass = USB_CLASS_AUDIO,
16259 + .bInterfaceSubClass = 0x2,
16260 + .bInterfaceProtocol = 0,
16264 +static const struct usb_interface_descriptor
16265 +z_audio_if_desc2 = {
16266 + .bLength = sizeof z_audio_if_desc,
16267 + .bDescriptorType = USB_DT_INTERFACE,
16268 + .bInterfaceNumber = 1,
16269 + .bAlternateSetting = 1,
16270 + .bNumEndpoints = 1,
16271 + .bInterfaceClass = USB_CLASS_AUDIO,
16272 + .bInterfaceSubClass = 0x2,
16273 + .bInterfaceProtocol = 0,
16277 +static const struct usb_cs_as_general_descriptor
16278 +z_audio_cs_as_if_desc = {
16280 + .bDescriptorType = 0x24,
16282 + .bDescriptorSubType = 0x01,
16283 + .bTerminalLink = 0x01,
16285 + .wFormatTag = __constant_cpu_to_le16 (0x0001)
16289 +static const struct usb_cs_as_format_descriptor
16290 +z_audio_cs_as_format_desc = {
16292 + .bDescriptorType = 0x24,
16294 + .bDescriptorSubType = 2,
16295 + .bFormatType = 1,
16296 + .bNrChannels = 1,
16297 + .bSubframeSize = 1,
16298 + .bBitResolution = 8,
16299 + .bSamfreqType = 0,
16300 + .tLowerSamFreq = {0x7e, 0x13, 0x00},
16301 + .tUpperSamFreq = {0xe2, 0xd6, 0x00},
16304 +static const struct usb_endpoint_descriptor
16307 + .bDescriptorType = 0x05,
16308 + .bEndpointAddress = 0x04,
16309 + .bmAttributes = 0x09,
16310 + .wMaxPacketSize = 0x0038,
16311 + .bInterval = 0x01,
16312 + .bRefresh = 0x00,
16313 + .bSynchAddress = 0x00,
16316 +static char z_iso_ep2[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
16319 +static char z_ac_interface_header_desc[] =
16320 +{ 0x09, 0x24, 0x01, 0x00, 0x01, 0x2b, 0x00, 0x01, 0x01 };
16323 +static char z_0[] = {0x0c, 0x24, 0x02, 0x01, 0x01, 0x01, 0x00, 0x02,
16324 + 0x03, 0x00, 0x00, 0x00};
16326 +static char z_1[] = {0x0d, 0x24, 0x06, 0x02, 0x01, 0x02, 0x15, 0x00,
16327 + 0x02, 0x00, 0x02, 0x00, 0x00};
16329 +static char z_2[] = {0x09, 0x24, 0x03, 0x03, 0x01, 0x03, 0x00, 0x02,
16332 +static char za_0[] = {0x09, 0x04, 0x01, 0x02, 0x01, 0x01, 0x02, 0x00,
16335 +static char za_1[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
16337 +static char za_2[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x01, 0x08, 0x00,
16338 + 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
16340 +static char za_3[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
16343 +static char za_4[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
16345 +static char za_5[] = {0x09, 0x04, 0x01, 0x03, 0x01, 0x01, 0x02, 0x00,
16348 +static char za_6[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
16350 +static char za_7[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x02, 0x10, 0x00,
16351 + 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
16353 +static char za_8[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
16356 +static char za_9[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
16358 +static char za_10[] = {0x09, 0x04, 0x01, 0x04, 0x01, 0x01, 0x02, 0x00,
16361 +static char za_11[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
16363 +static char za_12[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x02, 0x10, 0x00,
16364 + 0x73, 0x13, 0x00, 0xe2, 0xd6, 0x00};
16366 +static char za_13[] = {0x09, 0x05, 0x04, 0x09, 0xe0, 0x00, 0x01, 0x00,
16369 +static char za_14[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
16371 +static char za_15[] = {0x09, 0x04, 0x01, 0x05, 0x01, 0x01, 0x02, 0x00,
16374 +static char za_16[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
16376 +static char za_17[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x03, 0x14, 0x00,
16377 + 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
16379 +static char za_18[] = {0x09, 0x05, 0x04, 0x09, 0xa8, 0x00, 0x01, 0x00,
16382 +static char za_19[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
16384 +static char za_20[] = {0x09, 0x04, 0x01, 0x06, 0x01, 0x01, 0x02, 0x00,
16387 +static char za_21[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
16389 +static char za_22[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x03, 0x14, 0x00,
16390 + 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
16392 +static char za_23[] = {0x09, 0x05, 0x04, 0x09, 0x50, 0x01, 0x01, 0x00,
16395 +static char za_24[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
16399 +static const struct usb_descriptor_header *z_function [] = {
16400 + (struct usb_descriptor_header *) &z_audio_control_if_desc,
16401 + (struct usb_descriptor_header *) &z_ac_interface_header_desc,
16402 + (struct usb_descriptor_header *) &z_0,
16403 + (struct usb_descriptor_header *) &z_1,
16404 + (struct usb_descriptor_header *) &z_2,
16405 + (struct usb_descriptor_header *) &z_audio_if_desc,
16406 + (struct usb_descriptor_header *) &z_audio_if_desc2,
16407 + (struct usb_descriptor_header *) &z_audio_cs_as_if_desc,
16408 + (struct usb_descriptor_header *) &z_audio_cs_as_format_desc,
16409 + (struct usb_descriptor_header *) &z_iso_ep,
16410 + (struct usb_descriptor_header *) &z_iso_ep2,
16411 + (struct usb_descriptor_header *) &za_0,
16412 + (struct usb_descriptor_header *) &za_1,
16413 + (struct usb_descriptor_header *) &za_2,
16414 + (struct usb_descriptor_header *) &za_3,
16415 + (struct usb_descriptor_header *) &za_4,
16416 + (struct usb_descriptor_header *) &za_5,
16417 + (struct usb_descriptor_header *) &za_6,
16418 + (struct usb_descriptor_header *) &za_7,
16419 + (struct usb_descriptor_header *) &za_8,
16420 + (struct usb_descriptor_header *) &za_9,
16421 + (struct usb_descriptor_header *) &za_10,
16422 + (struct usb_descriptor_header *) &za_11,
16423 + (struct usb_descriptor_header *) &za_12,
16424 + (struct usb_descriptor_header *) &za_13,
16425 + (struct usb_descriptor_header *) &za_14,
16426 + (struct usb_descriptor_header *) &za_15,
16427 + (struct usb_descriptor_header *) &za_16,
16428 + (struct usb_descriptor_header *) &za_17,
16429 + (struct usb_descriptor_header *) &za_18,
16430 + (struct usb_descriptor_header *) &za_19,
16431 + (struct usb_descriptor_header *) &za_20,
16432 + (struct usb_descriptor_header *) &za_21,
16433 + (struct usb_descriptor_header *) &za_22,
16434 + (struct usb_descriptor_header *) &za_23,
16435 + (struct usb_descriptor_header *) &za_24,
16439 +/* maxpacket and other transfer characteristics vary by speed. */
16440 +#define ep_desc(g,hs,fs) (((g)->speed==USB_SPEED_HIGH)?(hs):(fs))
16444 +/* if there's no high speed support, maxpacket doesn't change. */
16445 +#define ep_desc(g,hs,fs) fs
16447 +#endif /* !CONFIG_USB_GADGET_DUALSPEED */
16449 +static char manufacturer [40];
16450 +//static char serial [40];
16451 +static char serial [] = "Ser 00 em";
16453 +/* static strings, in UTF-8 */
16454 +static struct usb_string strings [] = {
16455 + { STRING_MANUFACTURER, manufacturer, },
16456 + { STRING_PRODUCT, longname, },
16457 + { STRING_SERIAL, serial, },
16458 + { STRING_LOOPBACK, loopback, },
16459 + { STRING_SOURCE_SINK, source_sink, },
16460 + { } /* end of list */
16463 +static struct usb_gadget_strings stringtab = {
16464 + .language = 0x0409, /* en-us */
16465 + .strings = strings,
16469 + * config descriptors are also handcrafted. these must agree with code
16470 + * that sets configurations, and with code managing interfaces and their
16471 + * altsettings. other complexity may come from:
16473 + * - high speed support, including "other speed config" rules
16474 + * - multiple configurations
16475 + * - interfaces with alternate settings
16476 + * - embedded class or vendor-specific descriptors
16478 + * this handles high speed, and has a second config that could as easily
16479 + * have been an alternate interface setting (on most hardware).
16481 + * NOTE: to demonstrate (and test) more USB capabilities, this driver
16482 + * should include an altsetting to test interrupt transfers, including
16483 + * high bandwidth modes at high speed. (Maybe work like Intel's test
16487 +config_buf (struct usb_gadget *gadget, u8 *buf, u8 type, unsigned index)
16490 + const struct usb_descriptor_header **function;
16492 + function = z_function;
16493 + len = usb_gadget_config_buf (&z_config, buf, USB_BUFSIZ, function);
16496 + ((struct usb_config_descriptor *) buf)->bDescriptorType = type;
16500 +/*-------------------------------------------------------------------------*/
16502 +static struct usb_request *
16503 +alloc_ep_req (struct usb_ep *ep, unsigned length)
16505 + struct usb_request *req;
16507 + req = usb_ep_alloc_request (ep, GFP_ATOMIC);
16509 + req->length = length;
16510 + req->buf = usb_ep_alloc_buffer (ep, length,
16511 + &req->dma, GFP_ATOMIC);
16513 + usb_ep_free_request (ep, req);
16520 +static void free_ep_req (struct usb_ep *ep, struct usb_request *req)
16523 + usb_ep_free_buffer (ep, req->buf, req->dma, req->length);
16524 + usb_ep_free_request (ep, req);
16527 +/*-------------------------------------------------------------------------*/
16529 +/* optionally require specific source/sink data patterns */
16533 + struct zero_dev *dev,
16534 + struct usb_ep *ep,
16535 + struct usb_request *req
16539 + u8 *buf = req->buf;
16541 + for (i = 0; i < req->actual; i++, buf++) {
16542 + switch (pattern) {
16543 + /* all-zeroes has no synchronization issues */
16548 + /* mod63 stays in sync with short-terminated transfers,
16549 + * or otherwise when host and gadget agree on how large
16550 + * each usb transfer request should be. resync is done
16551 + * with set_interface or set_config.
16554 + if (*buf == (u8)(i % 63))
16558 + ERROR (dev, "bad OUT byte, buf [%d] = %d\n", i, *buf);
16559 + usb_ep_set_halt (ep);
16565 +/*-------------------------------------------------------------------------*/
16567 +static void zero_reset_config (struct zero_dev *dev)
16569 + if (dev->config == 0)
16572 + DBG (dev, "reset config\n");
16574 + /* just disable endpoints, forcing completion of pending i/o.
16575 + * all our completion handlers free their requests in this case.
16577 + if (dev->in_ep) {
16578 + usb_ep_disable (dev->in_ep);
16579 + dev->in_ep = NULL;
16581 + if (dev->out_ep) {
16582 + usb_ep_disable (dev->out_ep);
16583 + dev->out_ep = NULL;
16586 + del_timer (&dev->resume);
16589 +#define _write(f, buf, sz) (f->f_op->write(f, buf, sz, &f->f_pos))
16592 +zero_isoc_complete (struct usb_ep *ep, struct usb_request *req)
16594 + struct zero_dev *dev = ep->driver_data;
16595 + int status = req->status;
16598 + switch (status) {
16600 + case 0: /* normal completion? */
16601 + //printk ("\nzero ---------------> isoc normal completion %d bytes\n", req->actual);
16602 + for (i=0, j=rbuf_start; i<req->actual; i++) {
16603 + //printk ("%02x ", ((__u8*)req->buf)[i]);
16604 + rbuf[j] = ((__u8*)req->buf)[i];
16606 + if (j >= RBUF_LEN) j=0;
16609 + //printk ("\n\n");
16611 + if (rbuf_len < RBUF_LEN) {
16612 + rbuf_len += req->actual;
16613 + if (rbuf_len > RBUF_LEN) {
16614 + rbuf_len = RBUF_LEN;
16620 + /* this endpoint is normally active while we're configured */
16621 + case -ECONNABORTED: /* hardware forced ep reset */
16622 + case -ECONNRESET: /* request dequeued */
16623 + case -ESHUTDOWN: /* disconnect from host */
16624 + VDBG (dev, "%s gone (%d), %d/%d\n", ep->name, status,
16625 + req->actual, req->length);
16626 + if (ep == dev->out_ep)
16627 + check_read_data (dev, ep, req);
16628 + free_ep_req (ep, req);
16631 + case -EOVERFLOW: /* buffer overrun on read means that
16632 + * we didn't provide a big enough
16637 + DBG (dev, "%s complete --> %d, %d/%d\n", ep->name,
16638 + status, req->actual, req->length);
16640 + case -EREMOTEIO: /* short read */
16644 + status = usb_ep_queue (ep, req, GFP_ATOMIC);
16646 + ERROR (dev, "kill %s: resubmit %d bytes --> %d\n",
16647 + ep->name, req->length, status);
16648 + usb_ep_set_halt (ep);
16649 + /* FIXME recover later ... somehow */
16653 +static struct usb_request *
16654 +zero_start_isoc_ep (struct usb_ep *ep, int gfp_flags)
16656 + struct usb_request *req;
16659 + req = alloc_ep_req (ep, 512);
16663 + req->complete = zero_isoc_complete;
16665 + status = usb_ep_queue (ep, req, gfp_flags);
16667 + struct zero_dev *dev = ep->driver_data;
16669 + ERROR (dev, "start %s --> %d\n", ep->name, status);
16670 + free_ep_req (ep, req);
16677 +/* change our operational config. this code must agree with the code
16678 + * that returns config descriptors, and altsetting code.
16680 + * it's also responsible for power management interactions. some
16681 + * configurations might not work with our current power sources.
16683 + * note that some device controller hardware will constrain what this
16684 + * code can do, perhaps by disallowing more than one configuration or
16685 + * by limiting configuration choices (like the pxa2xx).
16688 +zero_set_config (struct zero_dev *dev, unsigned number, int gfp_flags)
16691 + struct usb_gadget *gadget = dev->gadget;
16692 + const struct usb_endpoint_descriptor *d;
16693 + struct usb_ep *ep;
16695 + if (number == dev->config)
16698 + zero_reset_config (dev);
16700 + gadget_for_each_ep (ep, gadget) {
16702 + if (strcmp (ep->name, "ep4") == 0) {
16704 + d = (struct usb_endpoint_descripter *)&za_23; // isoc ep desc for audio i/f alt setting 6
16705 + result = usb_ep_enable (ep, d);
16707 + if (result == 0) {
16708 + ep->driver_data = dev;
16711 + if (zero_start_isoc_ep (ep, gfp_flags) != 0) {
16717 + usb_ep_disable (ep);
16724 + dev->config = number;
16728 +/*-------------------------------------------------------------------------*/
16730 +static void zero_setup_complete (struct usb_ep *ep, struct usb_request *req)
16732 + if (req->status || req->actual != req->length)
16733 + DBG ((struct zero_dev *) ep->driver_data,
16734 + "setup complete --> %d, %d/%d\n",
16735 + req->status, req->actual, req->length);
16739 + * The setup() callback implements all the ep0 functionality that's
16740 + * not handled lower down, in hardware or the hardware driver (like
16741 + * device and endpoint feature flags, and their status). It's all
16742 + * housekeeping for the gadget function we're implementing. Most of
16743 + * the work is in config-specific setup.
16746 +zero_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
16748 + struct zero_dev *dev = get_gadget_data (gadget);
16749 + struct usb_request *req = dev->req;
16750 + int value = -EOPNOTSUPP;
16752 + /* usually this stores reply data in the pre-allocated ep0 buffer,
16753 + * but config change events will reconfigure hardware.
16756 + switch (ctrl->bRequest) {
16758 + case USB_REQ_GET_DESCRIPTOR:
16760 + switch (ctrl->wValue >> 8) {
16762 + case USB_DT_DEVICE:
16763 + value = min (ctrl->wLength, (u16) sizeof device_desc);
16764 + memcpy (req->buf, &device_desc, value);
16766 +#ifdef CONFIG_USB_GADGET_DUALSPEED
16767 + case USB_DT_DEVICE_QUALIFIER:
16768 + if (!gadget->is_dualspeed)
16770 + value = min (ctrl->wLength, (u16) sizeof dev_qualifier);
16771 + memcpy (req->buf, &dev_qualifier, value);
16774 + case USB_DT_OTHER_SPEED_CONFIG:
16775 + if (!gadget->is_dualspeed)
16778 +#endif /* CONFIG_USB_GADGET_DUALSPEED */
16779 + case USB_DT_CONFIG:
16780 + value = config_buf (gadget, req->buf,
16781 + ctrl->wValue >> 8,
16782 + ctrl->wValue & 0xff);
16784 + value = min (ctrl->wLength, (u16) value);
16787 + case USB_DT_STRING:
16788 + /* wIndex == language code.
16789 + * this driver only handles one language, you can
16790 + * add string tables for other languages, using
16791 + * any UTF-8 characters
16793 + value = usb_gadget_get_string (&stringtab,
16794 + ctrl->wValue & 0xff, req->buf);
16795 + if (value >= 0) {
16796 + value = min (ctrl->wLength, (u16) value);
16802 + /* currently two configs, two speeds */
16803 + case USB_REQ_SET_CONFIGURATION:
16804 + if (ctrl->bRequestType != 0)
16807 + spin_lock (&dev->lock);
16808 + value = zero_set_config (dev, ctrl->wValue, GFP_ATOMIC);
16809 + spin_unlock (&dev->lock);
16811 + case USB_REQ_GET_CONFIGURATION:
16812 + if (ctrl->bRequestType != USB_DIR_IN)
16814 + *(u8 *)req->buf = dev->config;
16815 + value = min (ctrl->wLength, (u16) 1);
16818 + /* until we add altsetting support, or other interfaces,
16819 + * only 0/0 are possible. pxa2xx only supports 0/0 (poorly)
16820 + * and already killed pending endpoint I/O.
16822 + case USB_REQ_SET_INTERFACE:
16824 + if (ctrl->bRequestType != USB_RECIP_INTERFACE)
16826 + spin_lock (&dev->lock);
16827 + if (dev->config) {
16828 + u8 config = dev->config;
16830 + /* resets interface configuration, forgets about
16831 + * previous transaction state (queued bufs, etc)
16832 + * and re-inits endpoint state (toggle etc)
16833 + * no response queued, just zero status == success.
16834 + * if we had more than one interface we couldn't
16835 + * use this "reset the config" shortcut.
16837 + zero_reset_config (dev);
16838 + zero_set_config (dev, config, GFP_ATOMIC);
16841 + spin_unlock (&dev->lock);
16843 + case USB_REQ_GET_INTERFACE:
16844 + if ((ctrl->bRequestType == 0x21) && (ctrl->wIndex == 0x02)) {
16845 + value = ctrl->wLength;
16849 + if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE))
16851 + if (!dev->config)
16853 + if (ctrl->wIndex != 0) {
16857 + *(u8 *)req->buf = 0;
16858 + value = min (ctrl->wLength, (u16) 1);
16863 + * These are the same vendor-specific requests supported by
16864 + * Intel's USB 2.0 compliance test devices. We exceed that
16865 + * device spec by allowing multiple-packet requests.
16867 + case 0x5b: /* control WRITE test -- fill the buffer */
16868 + if (ctrl->bRequestType != (USB_DIR_OUT|USB_TYPE_VENDOR))
16870 + if (ctrl->wValue || ctrl->wIndex)
16872 + /* just read that many bytes into the buffer */
16873 + if (ctrl->wLength > USB_BUFSIZ)
16875 + value = ctrl->wLength;
16877 + case 0x5c: /* control READ test -- return the buffer */
16878 + if (ctrl->bRequestType != (USB_DIR_IN|USB_TYPE_VENDOR))
16880 + if (ctrl->wValue || ctrl->wIndex)
16882 + /* expect those bytes are still in the buffer; send back */
16883 + if (ctrl->wLength > USB_BUFSIZ
16884 + || ctrl->wLength != req->length)
16886 + value = ctrl->wLength;
16889 + case 0x01: // SET_CUR
16894 + value = ctrl->wLength;
16897 + switch (ctrl->wValue) {
16900 + ((u8*)req->buf)[0] = 0x00;
16901 + ((u8*)req->buf)[1] = 0xe3;
16905 + ((u8*)req->buf)[0] = 0x00;
16908 + //((u8*)req->buf)[0] = 0x81;
16909 + //((u8*)req->buf)[1] = 0x81;
16910 + value = ctrl->wLength;
16913 + switch (ctrl->wValue) {
16916 + ((u8*)req->buf)[0] = 0x00;
16917 + ((u8*)req->buf)[1] = 0xc3;
16921 + ((u8*)req->buf)[0] = 0x00;
16924 + //((u8*)req->buf)[0] = 0x82;
16925 + //((u8*)req->buf)[1] = 0x82;
16926 + value = ctrl->wLength;
16929 + switch (ctrl->wValue) {
16932 + ((u8*)req->buf)[0] = 0x00;
16933 + ((u8*)req->buf)[1] = 0x00;
16936 + ((u8*)req->buf)[0] = 0x60;
16939 + ((u8*)req->buf)[0] = 0x18;
16942 + //((u8*)req->buf)[0] = 0x83;
16943 + //((u8*)req->buf)[1] = 0x83;
16944 + value = ctrl->wLength;
16947 + switch (ctrl->wValue) {
16950 + ((u8*)req->buf)[0] = 0x00;
16951 + ((u8*)req->buf)[1] = 0x01;
16955 + ((u8*)req->buf)[0] = 0x08;
16958 + //((u8*)req->buf)[0] = 0x84;
16959 + //((u8*)req->buf)[1] = 0x84;
16960 + value = ctrl->wLength;
16963 + ((u8*)req->buf)[0] = 0x85;
16964 + ((u8*)req->buf)[1] = 0x85;
16965 + value = ctrl->wLength;
16971 + printk("unknown control req%02x.%02x v%04x i%04x l%d\n",
16972 + ctrl->bRequestType, ctrl->bRequest,
16973 + ctrl->wValue, ctrl->wIndex, ctrl->wLength);
16976 + /* respond with data transfer before status phase? */
16977 + if (value >= 0) {
16978 + req->length = value;
16979 + req->zero = value < ctrl->wLength
16980 + && (value % gadget->ep0->maxpacket) == 0;
16981 + value = usb_ep_queue (gadget->ep0, req, GFP_ATOMIC);
16983 + DBG (dev, "ep_queue < 0 --> %d\n", value);
16985 + zero_setup_complete (gadget->ep0, req);
16989 + /* device either stalls (value < 0) or reports success */
16994 +zero_disconnect (struct usb_gadget *gadget)
16996 + struct zero_dev *dev = get_gadget_data (gadget);
16997 + unsigned long flags;
16999 + spin_lock_irqsave (&dev->lock, flags);
17000 + zero_reset_config (dev);
17002 + /* a more significant application might have some non-usb
17003 + * activities to quiesce here, saving resources like power
17004 + * or pushing the notification up a network stack.
17006 + spin_unlock_irqrestore (&dev->lock, flags);
17008 + /* next we may get setup() calls to enumerate new connections;
17009 + * or an unbind() during shutdown (including removing module).
17014 +zero_autoresume (unsigned long _dev)
17016 + struct zero_dev *dev = (struct zero_dev *) _dev;
17019 + /* normally the host would be woken up for something
17020 + * more significant than just a timer firing...
17022 + if (dev->gadget->speed != USB_SPEED_UNKNOWN) {
17023 + status = usb_gadget_wakeup (dev->gadget);
17024 + DBG (dev, "wakeup --> %d\n", status);
17028 +/*-------------------------------------------------------------------------*/
17031 +zero_unbind (struct usb_gadget *gadget)
17033 + struct zero_dev *dev = get_gadget_data (gadget);
17035 + DBG (dev, "unbind\n");
17037 + /* we've already been disconnected ... no i/o is active */
17039 + free_ep_req (gadget->ep0, dev->req);
17040 + del_timer_sync (&dev->resume);
17042 + set_gadget_data (gadget, NULL);
17046 +zero_bind (struct usb_gadget *gadget)
17048 + struct zero_dev *dev;
17049 + //struct usb_ep *ep;
17051 + printk("binding\n");
17053 + * DRIVER POLICY CHOICE: you may want to do this differently.
17054 + * One thing to avoid is reusing a bcdDevice revision code
17055 + * with different host-visible configurations or behavior
17056 + * restrictions -- using ep1in/ep2out vs ep1out/ep3in, etc
17058 + //device_desc.bcdDevice = __constant_cpu_to_le16 (0x0201);
17061 + /* ok, we made sense of the hardware ... */
17062 + dev = kzalloc (sizeof *dev, SLAB_KERNEL);
17065 + spin_lock_init (&dev->lock);
17066 + dev->gadget = gadget;
17067 + set_gadget_data (gadget, dev);
17069 + /* preallocate control response and buffer */
17070 + dev->req = usb_ep_alloc_request (gadget->ep0, GFP_KERNEL);
17073 + dev->req->buf = usb_ep_alloc_buffer (gadget->ep0, USB_BUFSIZ,
17074 + &dev->req->dma, GFP_KERNEL);
17075 + if (!dev->req->buf)
17078 + dev->req->complete = zero_setup_complete;
17080 + device_desc.bMaxPacketSize0 = gadget->ep0->maxpacket;
17082 +#ifdef CONFIG_USB_GADGET_DUALSPEED
17083 + /* assume ep0 uses the same value for both speeds ... */
17084 + dev_qualifier.bMaxPacketSize0 = device_desc.bMaxPacketSize0;
17086 + /* and that all endpoints are dual-speed */
17087 + //hs_source_desc.bEndpointAddress = fs_source_desc.bEndpointAddress;
17088 + //hs_sink_desc.bEndpointAddress = fs_sink_desc.bEndpointAddress;
17091 + usb_gadget_set_selfpowered (gadget);
17093 + init_timer (&dev->resume);
17094 + dev->resume.function = zero_autoresume;
17095 + dev->resume.data = (unsigned long) dev;
17097 + gadget->ep0->driver_data = dev;
17099 + INFO (dev, "%s, version: " DRIVER_VERSION "\n", longname);
17100 + INFO (dev, "using %s, OUT %s IN %s\n", gadget->name,
17101 + EP_OUT_NAME, EP_IN_NAME);
17103 + snprintf (manufacturer, sizeof manufacturer,
17104 + UTS_SYSNAME " " UTS_RELEASE " with %s",
17110 + zero_unbind (gadget);
17114 +/*-------------------------------------------------------------------------*/
17117 +zero_suspend (struct usb_gadget *gadget)
17119 + struct zero_dev *dev = get_gadget_data (gadget);
17121 + if (gadget->speed == USB_SPEED_UNKNOWN)
17124 + if (autoresume) {
17125 + mod_timer (&dev->resume, jiffies + (HZ * autoresume));
17126 + DBG (dev, "suspend, wakeup in %d seconds\n", autoresume);
17128 + DBG (dev, "suspend\n");
17132 +zero_resume (struct usb_gadget *gadget)
17134 + struct zero_dev *dev = get_gadget_data (gadget);
17136 + DBG (dev, "resume\n");
17137 + del_timer (&dev->resume);
17141 +/*-------------------------------------------------------------------------*/
17143 +static struct usb_gadget_driver zero_driver = {
17144 +#ifdef CONFIG_USB_GADGET_DUALSPEED
17145 + .speed = USB_SPEED_HIGH,
17147 + .speed = USB_SPEED_FULL,
17149 + .function = (char *) longname,
17150 + .bind = zero_bind,
17151 + .unbind = zero_unbind,
17153 + .setup = zero_setup,
17154 + .disconnect = zero_disconnect,
17156 + .suspend = zero_suspend,
17157 + .resume = zero_resume,
17160 + .name = (char *) shortname,
17161 + // .shutdown = ...
17162 + // .suspend = ...
17167 +MODULE_AUTHOR ("David Brownell");
17168 +MODULE_LICENSE ("Dual BSD/GPL");
17170 +static struct proc_dir_entry *pdir, *pfile;
17172 +static int isoc_read_data (char *page, char **start,
17173 + off_t off, int count,
17174 + int *eof, void *data)
17177 + static int c = 0;
17178 + static int done = 0;
17179 + static int s = 0;
17182 + printk ("\ncount: %d\n", count);
17183 + printk ("rbuf_start: %d\n", rbuf_start);
17184 + printk ("rbuf_len: %d\n", rbuf_len);
17185 + printk ("off: %d\n", off);
17186 + printk ("start: %p\n\n", *start);
17196 + if (rbuf_len == RBUF_LEN)
17201 + for (i=0; i<count && c<rbuf_len; i++, c++) {
17202 + page[i] = rbuf[(c+s) % RBUF_LEN];
17206 + if (c >= rbuf_len) {
17215 +static int __init init (void)
17220 + pdir = proc_mkdir("isoc_test", NULL);
17221 + if(pdir == NULL) {
17222 + retval = -ENOMEM;
17223 + printk("Error creating dir\n");
17226 + pdir->owner = THIS_MODULE;
17228 + pfile = create_proc_read_entry("isoc_data",
17232 + if (pfile == NULL) {
17233 + retval = -ENOMEM;
17234 + printk("Error creating file\n");
17237 + pfile->owner = THIS_MODULE;
17239 + return usb_gadget_register_driver (&zero_driver);
17242 + remove_proc_entry("isoc_data", NULL);
17246 +module_init (init);
17248 +static void __exit cleanup (void)
17251 + usb_gadget_unregister_driver (&zero_driver);
17253 + remove_proc_entry("isoc_data", pdir);
17254 + remove_proc_entry("isoc_test", NULL);
17256 +module_exit (cleanup);
17258 +++ b/drivers/usb/host/dwc_otg/dwc_cfi_common.h
17260 +/* ==========================================================================
17261 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
17262 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
17263 + * otherwise expressly agreed to in writing between Synopsys and you.
17265 + * The Software IS NOT an item of Licensed Software or Licensed Product under
17266 + * any End User Software License Agreement or Agreement for Licensed Product
17267 + * with Synopsys or any supplement thereto. You are permitted to use and
17268 + * redistribute this Software in source and binary forms, with or without
17269 + * modification, provided that redistributions of source code must retain this
17270 + * notice. You may not view, use, disclose, copy or distribute this file or
17271 + * any information contained herein except pursuant to this license grant from
17272 + * Synopsys. If you do not agree with this notice, including the disclaimer
17273 + * below, then you are not authorized to use the Software.
17275 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
17276 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17277 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17278 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
17279 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
17280 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
17281 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
17282 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
17283 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
17284 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
17286 + * ========================================================================== */
17288 +#if !defined(__DWC_CFI_COMMON_H__)
17289 +#define __DWC_CFI_COMMON_H__
17291 +//#include <linux/types.h>
17296 + * This file contains the CFI specific common constants, interfaces
17297 + * (functions and macros) and structures for Linux. No PCD specific
17298 + * data structure or definition is to be included in this file.
17302 +/** This is a request for all Core Features */
17303 +#define VEN_CORE_GET_FEATURES 0xB1
17305 +/** This is a request to get the value of a specific Core Feature */
17306 +#define VEN_CORE_GET_FEATURE 0xB2
17308 +/** This command allows the host to set the value of a specific Core Feature */
17309 +#define VEN_CORE_SET_FEATURE 0xB3
17311 +/** This command allows the host to set the default values of
17312 + * either all or any specific Core Feature
17314 +#define VEN_CORE_RESET_FEATURES 0xB4
17316 +/** This command forces the PCD to write the deferred values of a Core Features */
17317 +#define VEN_CORE_ACTIVATE_FEATURES 0xB5
17319 +/** This request reads a DWORD value from a register at the specified offset */
17320 +#define VEN_CORE_READ_REGISTER 0xB6
17322 +/** This request writes a DWORD value into a register at the specified offset */
17323 +#define VEN_CORE_WRITE_REGISTER 0xB7
17325 +/** This structure is the header of the Core Features dataset returned to
17328 +struct cfi_all_features_header {
17329 +/** The features header structure length is */
17330 +#define CFI_ALL_FEATURES_HDR_LEN 8
17332 + * The total length of the features dataset returned to the Host
17334 + uint16_t wTotalLen;
17337 + * CFI version number inBinary-Coded Decimal (i.e., 1.00 is 100H).
17338 + * This field identifies the version of the CFI Specification with which
17339 + * the device is compliant.
17341 + uint16_t wVersion;
17343 + /** The ID of the Core */
17344 + uint16_t wCoreID;
17345 +#define CFI_CORE_ID_UDC 1
17346 +#define CFI_CORE_ID_OTG 2
17347 +#define CFI_CORE_ID_WUDEV 3
17349 + /** Number of features returned by VEN_CORE_GET_FEATURES request */
17350 + uint16_t wNumFeatures;
17353 +typedef struct cfi_all_features_header cfi_all_features_header_t;
17355 +/** This structure is a header of the Core Feature descriptor dataset returned to
17356 + * the Host after the VEN_CORE_GET_FEATURES request
17358 +struct cfi_feature_desc_header {
17359 +#define CFI_FEATURE_DESC_HDR_LEN 8
17361 + /** The feature ID */
17362 + uint16_t wFeatureID;
17364 + /** Length of this feature descriptor in bytes - including the
17365 + * length of the feature name string
17367 + uint16_t wLength;
17369 + /** The data length of this feature in bytes */
17370 + uint16_t wDataLength;
17373 + * Attributes of this features
17374 + * D0: Access rights
17378 + uint8_t bmAttributes;
17379 +#define CFI_FEATURE_ATTR_RO 1
17380 +#define CFI_FEATURE_ATTR_RW 0
17382 + /** Length of the feature name in bytes */
17383 + uint8_t bNameLen;
17385 + /** The feature name buffer */
17389 +typedef struct cfi_feature_desc_header cfi_feature_desc_header_t;
17392 + * This structure describes a NULL terminated string referenced by its id field.
17393 + * It is very similar to usb_string structure but has the id field type set to 16-bit.
17395 +struct cfi_string {
17397 + const uint8_t *s;
17399 +typedef struct cfi_string cfi_string_t;
17403 +++ b/drivers/usb/host/dwc_otg/dwc_otg_adp.c
17405 +/* ==========================================================================
17406 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.c $
17407 + * $Revision: #12 $
17408 + * $Date: 2011/10/26 $
17409 + * $Change: 1873028 $
17411 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
17412 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
17413 + * otherwise expressly agreed to in writing between Synopsys and you.
17415 + * The Software IS NOT an item of Licensed Software or Licensed Product under
17416 + * any End User Software License Agreement or Agreement for Licensed Product
17417 + * with Synopsys or any supplement thereto. You are permitted to use and
17418 + * redistribute this Software in source and binary forms, with or without
17419 + * modification, provided that redistributions of source code must retain this
17420 + * notice. You may not view, use, disclose, copy or distribute this file or
17421 + * any information contained herein except pursuant to this license grant from
17422 + * Synopsys. If you do not agree with this notice, including the disclaimer
17423 + * below, then you are not authorized to use the Software.
17425 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
17426 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17427 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17428 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
17429 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
17430 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
17431 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
17432 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
17433 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
17434 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
17436 + * ========================================================================== */
17438 +#include "dwc_os.h"
17439 +#include "dwc_otg_regs.h"
17440 +#include "dwc_otg_cil.h"
17441 +#include "dwc_otg_adp.h"
17445 + * This file contains the most of the Attach Detect Protocol implementation for
17446 + * the driver to support OTG Rev2.0.
17450 +void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value)
17452 + adpctl_data_t adpctl;
17454 + adpctl.d32 = value;
17455 + adpctl.b.ar = 0x2;
17457 + DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32);
17459 + while (adpctl.b.ar) {
17460 + adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl);
17466 + * Function is called to read ADP registers
17468 +uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if)
17470 + adpctl_data_t adpctl;
17473 + adpctl.b.ar = 0x1;
17475 + DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32);
17477 + while (adpctl.b.ar) {
17478 + adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl);
17481 + return adpctl.d32;
17485 + * Function is called to read ADPCTL register and filter Write-clear bits
17487 +uint32_t dwc_otg_adp_read_reg_filter(dwc_otg_core_if_t * core_if)
17489 + adpctl_data_t adpctl;
17491 + adpctl.d32 = dwc_otg_adp_read_reg(core_if);
17492 + adpctl.b.adp_tmout_int = 0;
17493 + adpctl.b.adp_prb_int = 0;
17494 + adpctl.b.adp_tmout_int = 0;
17496 + return adpctl.d32;
17500 + * Function is called to write ADP registers
17502 +void dwc_otg_adp_modify_reg(dwc_otg_core_if_t * core_if, uint32_t clr,
17505 + dwc_otg_adp_write_reg(core_if,
17506 + (dwc_otg_adp_read_reg(core_if) & (~clr)) | set);
17509 +static void adp_sense_timeout(void *ptr)
17511 + dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
17512 + core_if->adp.sense_timer_started = 0;
17513 + DWC_PRINTF("ADP SENSE TIMEOUT\n");
17514 + if (core_if->adp_enable) {
17515 + dwc_otg_adp_sense_stop(core_if);
17516 + dwc_otg_adp_probe_start(core_if);
17521 + * This function is called when the ADP vbus timer expires. Timeout is 1.1s.
17523 +static void adp_vbuson_timeout(void *ptr)
17525 + gpwrdn_data_t gpwrdn;
17526 + dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
17527 + hprt0_data_t hprt0 = {.d32 = 0 };
17528 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
17529 + DWC_PRINTF("%s: 1.1 seconds expire after turning on VBUS\n",__FUNCTION__);
17531 + core_if->adp.vbuson_timer_started = 0;
17532 + /* Turn off vbus */
17533 + hprt0.b.prtpwr = 1;
17534 + DWC_MODIFY_REG32(core_if->host_if->hprt0, hprt0.d32, 0);
17537 + /* Power off the core */
17538 + if (core_if->power_down == 2) {
17539 + /* Enable Wakeup Logic */
17540 +// gpwrdn.b.wkupactiv = 1;
17541 + gpwrdn.b.pmuactv = 0;
17542 + gpwrdn.b.pwrdnrstn = 1;
17543 + gpwrdn.b.pwrdnclmp = 1;
17544 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
17547 + /* Suspend the Phy Clock */
17548 + pcgcctl.b.stoppclk = 1;
17549 + DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
17551 + /* Switch on VDD */
17552 +// gpwrdn.b.wkupactiv = 1;
17553 + gpwrdn.b.pmuactv = 1;
17554 + gpwrdn.b.pwrdnrstn = 1;
17555 + gpwrdn.b.pwrdnclmp = 1;
17556 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
17559 + /* Enable Power Down Logic */
17560 + gpwrdn.b.pmuintsel = 1;
17561 + gpwrdn.b.pmuactv = 1;
17562 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
17565 + /* Power off the core */
17566 + if (core_if->power_down == 2) {
17568 + gpwrdn.b.pwrdnswtch = 1;
17569 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn,
17573 + /* Unmask SRP detected interrupt from Power Down Logic */
17575 + gpwrdn.b.srp_det_msk = 1;
17576 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
17578 + dwc_otg_adp_probe_start(core_if);
17579 + dwc_otg_dump_global_registers(core_if);
17580 + dwc_otg_dump_host_registers(core_if);
17586 + * Start the ADP Initial Probe timer to detect if Port Connected interrupt is
17587 + * not asserted within 1.1 seconds.
17589 + * @param core_if the pointer to core_if strucure.
17591 +void dwc_otg_adp_vbuson_timer_start(dwc_otg_core_if_t * core_if)
17593 + core_if->adp.vbuson_timer_started = 1;
17594 + if (core_if->adp.vbuson_timer)
17596 + DWC_PRINTF("SCHEDULING VBUSON TIMER\n");
17597 + /* 1.1 secs + 60ms necessary for cil_hcd_start*/
17598 + DWC_TIMER_SCHEDULE(core_if->adp.vbuson_timer, 1160);
17600 + DWC_WARN("VBUSON_TIMER = %p\n",core_if->adp.vbuson_timer);
17606 + * Masks all DWC OTG core interrupts
17609 +static void mask_all_interrupts(dwc_otg_core_if_t * core_if)
17612 + gahbcfg_data_t ahbcfg = {.d32 = 0 };
17614 + /* Mask Host Interrupts */
17616 + /* Clear and disable HCINTs */
17617 + for (i = 0; i < core_if->core_params->host_channels; i++) {
17618 + DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk, 0);
17619 + DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcint, 0xFFFFFFFF);
17623 + /* Clear and disable HAINT */
17624 + DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk, 0x0000);
17625 + DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haint, 0xFFFFFFFF);
17627 + /* Mask Device Interrupts */
17628 + if (!core_if->multiproc_int_enable) {
17629 + /* Clear and disable IN Endpoint interrupts */
17630 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, 0);
17631 + for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
17632 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->
17633 + diepint, 0xFFFFFFFF);
17636 + /* Clear and disable OUT Endpoint interrupts */
17637 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, 0);
17638 + for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
17639 + DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
17640 + doepint, 0xFFFFFFFF);
17643 + /* Clear and disable DAINT */
17644 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daint,
17646 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, 0);
17648 + for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
17649 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
17650 + diepeachintmsk[i], 0);
17651 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->
17652 + diepint, 0xFFFFFFFF);
17655 + for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
17656 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
17657 + doepeachintmsk[i], 0);
17658 + DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
17659 + doepint, 0xFFFFFFFF);
17662 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachintmsk,
17664 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachint,
17669 + /* Disable interrupts */
17670 + ahbcfg.b.glblintrmsk = 1;
17671 + DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
17673 + /* Disable all interrupts. */
17674 + DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0);
17676 + /* Clear any pending interrupts */
17677 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
17679 + /* Clear any pending OTG Interrupts */
17680 + DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, 0xFFFFFFFF);
17684 + * Unmask Port Connection Detected interrupt
17687 +static void unmask_conn_det_intr(dwc_otg_core_if_t * core_if)
17689 + gintmsk_data_t gintmsk = {.d32 = 0,.b.portintr = 1 };
17691 + DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
17696 + * Starts the ADP Probing
17698 + * @param core_if the pointer to core_if structure.
17700 +uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if)
17703 + adpctl_data_t adpctl = {.d32 = 0};
17704 + gpwrdn_data_t gpwrdn;
17706 + adpctl_data_t adpctl_int = {.d32 = 0, .b.adp_prb_int = 1,
17707 + .b.adp_sns_int = 1, b.adp_tmout_int};
17709 + dwc_otg_disable_global_interrupts(core_if);
17710 + DWC_PRINTF("ADP Probe Start\n");
17711 + core_if->adp.probe_enabled = 1;
17713 + adpctl.b.adpres = 1;
17714 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
17716 + while (adpctl.b.adpres) {
17717 + adpctl.d32 = dwc_otg_adp_read_reg(core_if);
17721 + gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
17723 + /* In Host mode unmask SRP detected interrupt */
17725 + gpwrdn.b.sts_chngint_msk = 1;
17726 + if (!gpwrdn.b.idsts) {
17727 + gpwrdn.b.srp_det_msk = 1;
17729 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
17731 + adpctl.b.adp_tmout_int_msk = 1;
17732 + adpctl.b.adp_prb_int_msk = 1;
17733 + adpctl.b.prb_dschg = 1;
17734 + adpctl.b.prb_delta = 1;
17735 + adpctl.b.prb_per = 1;
17736 + adpctl.b.adpen = 1;
17737 + adpctl.b.enaprb = 1;
17739 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
17740 + DWC_PRINTF("ADP Probe Finish\n");
17745 + * Starts the ADP Sense timer to detect if ADP Sense interrupt is not asserted
17746 + * within 3 seconds.
17748 + * @param core_if the pointer to core_if strucure.
17750 +void dwc_otg_adp_sense_timer_start(dwc_otg_core_if_t * core_if)
17752 + core_if->adp.sense_timer_started = 1;
17753 + DWC_TIMER_SCHEDULE(core_if->adp.sense_timer, 3000 /* 3 secs */ );
17757 + * Starts the ADP Sense
17759 + * @param core_if the pointer to core_if strucure.
17761 +uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if)
17763 + adpctl_data_t adpctl;
17765 + DWC_PRINTF("ADP Sense Start\n");
17767 + /* Unmask ADP sense interrupt and mask all other from the core */
17768 + adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
17769 + adpctl.b.adp_sns_int_msk = 1;
17770 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
17771 + dwc_otg_disable_global_interrupts(core_if); // vahrama
17773 + /* Set ADP reset bit*/
17774 + adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
17775 + adpctl.b.adpres = 1;
17776 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
17778 + while (adpctl.b.adpres) {
17779 + adpctl.d32 = dwc_otg_adp_read_reg(core_if);
17782 + adpctl.b.adpres = 0;
17783 + adpctl.b.adpen = 1;
17784 + adpctl.b.enasns = 1;
17785 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
17787 + dwc_otg_adp_sense_timer_start(core_if);
17793 + * Stops the ADP Probing
17795 + * @param core_if the pointer to core_if strucure.
17797 +uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if)
17800 + adpctl_data_t adpctl;
17801 + DWC_PRINTF("Stop ADP probe\n");
17802 + core_if->adp.probe_enabled = 0;
17803 + core_if->adp.probe_counter = 0;
17804 + adpctl.d32 = dwc_otg_adp_read_reg(core_if);
17806 + adpctl.b.adpen = 0;
17807 + adpctl.b.adp_prb_int = 1;
17808 + adpctl.b.adp_tmout_int = 1;
17809 + adpctl.b.adp_sns_int = 1;
17810 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
17816 + * Stops the ADP Sensing
17818 + * @param core_if the pointer to core_if strucure.
17820 +uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if)
17822 + adpctl_data_t adpctl;
17824 + core_if->adp.sense_enabled = 0;
17826 + adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
17827 + adpctl.b.enasns = 0;
17828 + adpctl.b.adp_sns_int = 1;
17829 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
17835 + * Called to turn on the VBUS after initial ADP probe in host mode.
17836 + * If port power was already enabled in cil_hcd_start function then
17837 + * only schedule a timer.
17839 + * @param core_if the pointer to core_if structure.
17841 +void dwc_otg_adp_turnon_vbus(dwc_otg_core_if_t * core_if)
17843 + hprt0_data_t hprt0 = {.d32 = 0 };
17844 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
17845 + DWC_PRINTF("Turn on VBUS for 1.1s, port power is %d\n", hprt0.b.prtpwr);
17847 + if (hprt0.b.prtpwr == 0) {
17848 + hprt0.b.prtpwr = 1;
17849 + //DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
17852 + dwc_otg_adp_vbuson_timer_start(core_if);
17856 + * Called right after driver is loaded
17857 + * to perform initial actions for ADP
17859 + * @param core_if the pointer to core_if structure.
17860 + * @param is_host - flag for current mode of operation either from GINTSTS or GPWRDN
17862 +void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host)
17864 + gpwrdn_data_t gpwrdn;
17866 + DWC_PRINTF("ADP Initial Start\n");
17867 + core_if->adp.adp_started = 1;
17869 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
17870 + dwc_otg_disable_global_interrupts(core_if);
17872 + DWC_PRINTF("HOST MODE\n");
17873 + /* Enable Power Down Logic Interrupt*/
17875 + gpwrdn.b.pmuintsel = 1;
17876 + gpwrdn.b.pmuactv = 1;
17877 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
17878 + /* Initialize first ADP probe to obtain Ramp Time value */
17879 + core_if->adp.initial_probe = 1;
17880 + dwc_otg_adp_probe_start(core_if);
17882 + gotgctl_data_t gotgctl;
17883 + gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
17884 + DWC_PRINTF("DEVICE MODE\n");
17885 + if (gotgctl.b.bsesvld == 0) {
17886 + /* Enable Power Down Logic Interrupt*/
17888 + DWC_PRINTF("VBUS is not valid - start ADP probe\n");
17889 + gpwrdn.b.pmuintsel = 1;
17890 + gpwrdn.b.pmuactv = 1;
17891 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
17892 + core_if->adp.initial_probe = 1;
17893 + dwc_otg_adp_probe_start(core_if);
17895 + DWC_PRINTF("VBUS is valid - initialize core as a Device\n");
17896 + core_if->op_state = B_PERIPHERAL;
17897 + dwc_otg_core_init(core_if);
17898 + dwc_otg_enable_global_interrupts(core_if);
17899 + cil_pcd_start(core_if);
17900 + dwc_otg_dump_global_registers(core_if);
17901 + dwc_otg_dump_dev_registers(core_if);
17906 +void dwc_otg_adp_init(dwc_otg_core_if_t * core_if)
17908 + core_if->adp.adp_started = 0;
17909 + core_if->adp.initial_probe = 0;
17910 + core_if->adp.probe_timer_values[0] = -1;
17911 + core_if->adp.probe_timer_values[1] = -1;
17912 + core_if->adp.probe_enabled = 0;
17913 + core_if->adp.sense_enabled = 0;
17914 + core_if->adp.sense_timer_started = 0;
17915 + core_if->adp.vbuson_timer_started = 0;
17916 + core_if->adp.probe_counter = 0;
17917 + core_if->adp.gpwrdn = 0;
17918 + core_if->adp.attached = DWC_OTG_ADP_UNKOWN;
17919 + /* Initialize timers */
17920 + core_if->adp.sense_timer =
17921 + DWC_TIMER_ALLOC("ADP SENSE TIMER", adp_sense_timeout, core_if);
17922 + core_if->adp.vbuson_timer =
17923 + DWC_TIMER_ALLOC("ADP VBUS ON TIMER", adp_vbuson_timeout, core_if);
17924 + if (!core_if->adp.sense_timer || !core_if->adp.vbuson_timer)
17926 + DWC_ERROR("Could not allocate memory for ADP timers\n");
17930 +void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if)
17932 + gpwrdn_data_t gpwrdn = { .d32 = 0 };
17933 + gpwrdn.b.pmuintsel = 1;
17934 + gpwrdn.b.pmuactv = 1;
17935 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
17937 + if (core_if->adp.probe_enabled)
17938 + dwc_otg_adp_probe_stop(core_if);
17939 + if (core_if->adp.sense_enabled)
17940 + dwc_otg_adp_sense_stop(core_if);
17941 + if (core_if->adp.sense_timer_started)
17942 + DWC_TIMER_CANCEL(core_if->adp.sense_timer);
17943 + if (core_if->adp.vbuson_timer_started)
17944 + DWC_TIMER_CANCEL(core_if->adp.vbuson_timer);
17945 + DWC_TIMER_FREE(core_if->adp.sense_timer);
17946 + DWC_TIMER_FREE(core_if->adp.vbuson_timer);
17949 +/////////////////////////////////////////////////////////////////////
17950 +////////////// ADP Interrupt Handlers ///////////////////////////////
17951 +/////////////////////////////////////////////////////////////////////
17953 + * This function sets Ramp Timer values
17955 +static uint32_t set_timer_value(dwc_otg_core_if_t * core_if, uint32_t val)
17957 + if (core_if->adp.probe_timer_values[0] == -1) {
17958 + core_if->adp.probe_timer_values[0] = val;
17959 + core_if->adp.probe_timer_values[1] = -1;
17962 + core_if->adp.probe_timer_values[1] =
17963 + core_if->adp.probe_timer_values[0];
17964 + core_if->adp.probe_timer_values[0] = val;
17970 + * This function compares Ramp Timer values
17972 +static uint32_t compare_timer_values(dwc_otg_core_if_t * core_if)
17975 + if (core_if->adp.probe_timer_values[0]>=core_if->adp.probe_timer_values[1])
17976 + diff = core_if->adp.probe_timer_values[0]-core_if->adp.probe_timer_values[1];
17978 + diff = core_if->adp.probe_timer_values[1]-core_if->adp.probe_timer_values[0];
17987 + * This function handles ADP Probe Interrupts
17989 +static int32_t dwc_otg_adp_handle_prb_intr(dwc_otg_core_if_t * core_if,
17992 + adpctl_data_t adpctl = {.d32 = 0 };
17993 + gpwrdn_data_t gpwrdn, temp;
17994 + adpctl.d32 = val;
17996 + temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
17997 + core_if->adp.probe_counter++;
17998 + core_if->adp.gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
17999 + if (adpctl.b.rtim == 0 && !temp.b.idsts){
18000 + DWC_PRINTF("RTIM value is 0\n");
18003 + if (set_timer_value(core_if, adpctl.b.rtim) &&
18004 + core_if->adp.initial_probe) {
18005 + core_if->adp.initial_probe = 0;
18006 + dwc_otg_adp_probe_stop(core_if);
18008 + gpwrdn.b.pmuactv = 1;
18009 + gpwrdn.b.pmuintsel = 1;
18010 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
18011 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
18013 + /* check which value is for device mode and which for Host mode */
18014 + if (!temp.b.idsts) { /* considered host mode value is 0 */
18016 + * Turn on VBUS after initial ADP probe.
18018 + core_if->op_state = A_HOST;
18019 + dwc_otg_enable_global_interrupts(core_if);
18020 + DWC_SPINUNLOCK(core_if->lock);
18021 + cil_hcd_start(core_if);
18022 + dwc_otg_adp_turnon_vbus(core_if);
18023 + DWC_SPINLOCK(core_if->lock);
18026 + * Initiate SRP after initial ADP probe.
18028 + dwc_otg_enable_global_interrupts(core_if);
18029 + dwc_otg_initiate_srp(core_if);
18031 + } else if (core_if->adp.probe_counter > 2){
18032 + gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
18033 + if (compare_timer_values(core_if)) {
18034 + DWC_PRINTF("Difference in timer values !!! \n");
18035 +// core_if->adp.attached = DWC_OTG_ADP_ATTACHED;
18036 + dwc_otg_adp_probe_stop(core_if);
18038 + /* Power on the core */
18039 + if (core_if->power_down == 2) {
18040 + gpwrdn.b.pwrdnswtch = 1;
18041 + DWC_MODIFY_REG32(&core_if->core_global_regs->
18042 + gpwrdn, 0, gpwrdn.d32);
18045 + /* check which value is for device mode and which for Host mode */
18046 + if (!temp.b.idsts) { /* considered host mode value is 0 */
18047 + /* Disable Interrupt from Power Down Logic */
18049 + gpwrdn.b.pmuintsel = 1;
18050 + gpwrdn.b.pmuactv = 1;
18051 + DWC_MODIFY_REG32(&core_if->core_global_regs->
18052 + gpwrdn, gpwrdn.d32, 0);
18055 + * Initialize the Core for Host mode.
18057 + core_if->op_state = A_HOST;
18058 + dwc_otg_core_init(core_if);
18059 + dwc_otg_enable_global_interrupts(core_if);
18060 + cil_hcd_start(core_if);
18062 + gotgctl_data_t gotgctl;
18063 + /* Mask SRP detected interrupt from Power Down Logic */
18065 + gpwrdn.b.srp_det_msk = 1;
18066 + DWC_MODIFY_REG32(&core_if->core_global_regs->
18067 + gpwrdn, gpwrdn.d32, 0);
18069 + /* Disable Power Down Logic */
18071 + gpwrdn.b.pmuintsel = 1;
18072 + gpwrdn.b.pmuactv = 1;
18073 + DWC_MODIFY_REG32(&core_if->core_global_regs->
18074 + gpwrdn, gpwrdn.d32, 0);
18077 + * Initialize the Core for Device mode.
18079 + core_if->op_state = B_PERIPHERAL;
18080 + dwc_otg_core_init(core_if);
18081 + dwc_otg_enable_global_interrupts(core_if);
18082 + cil_pcd_start(core_if);
18084 + gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
18085 + if (!gotgctl.b.bsesvld) {
18086 + dwc_otg_initiate_srp(core_if);
18090 + if (core_if->power_down == 2) {
18091 + if (gpwrdn.b.bsessvld) {
18092 + /* Mask SRP detected interrupt from Power Down Logic */
18094 + gpwrdn.b.srp_det_msk = 1;
18095 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
18097 + /* Disable Power Down Logic */
18099 + gpwrdn.b.pmuactv = 1;
18100 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
18103 + * Initialize the Core for Device mode.
18105 + core_if->op_state = B_PERIPHERAL;
18106 + dwc_otg_core_init(core_if);
18107 + dwc_otg_enable_global_interrupts(core_if);
18108 + cil_pcd_start(core_if);
18113 + /* Clear interrupt */
18114 + adpctl.d32 = dwc_otg_adp_read_reg(core_if);
18115 + adpctl.b.adp_prb_int = 1;
18116 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
18122 + * This function hadles ADP Sense Interrupt
18124 +static int32_t dwc_otg_adp_handle_sns_intr(dwc_otg_core_if_t * core_if)
18126 + adpctl_data_t adpctl;
18127 + /* Stop ADP Sense timer */
18128 + DWC_TIMER_CANCEL(core_if->adp.sense_timer);
18130 + /* Restart ADP Sense timer */
18131 + dwc_otg_adp_sense_timer_start(core_if);
18133 + /* Clear interrupt */
18134 + adpctl.d32 = dwc_otg_adp_read_reg(core_if);
18135 + adpctl.b.adp_sns_int = 1;
18136 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
18142 + * This function handles ADP Probe Interrupts
18144 +static int32_t dwc_otg_adp_handle_prb_tmout_intr(dwc_otg_core_if_t * core_if,
18147 + adpctl_data_t adpctl = {.d32 = 0 };
18148 + adpctl.d32 = val;
18149 + set_timer_value(core_if, adpctl.b.rtim);
18151 + /* Clear interrupt */
18152 + adpctl.d32 = dwc_otg_adp_read_reg(core_if);
18153 + adpctl.b.adp_tmout_int = 1;
18154 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
18160 + * ADP Interrupt handler.
18163 +int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if)
18166 + adpctl_data_t adpctl = {.d32 = 0};
18168 + adpctl.d32 = dwc_otg_adp_read_reg(core_if);
18169 + DWC_PRINTF("ADPCTL = %08x\n",adpctl.d32);
18171 + if (adpctl.b.adp_sns_int & adpctl.b.adp_sns_int_msk) {
18172 + DWC_PRINTF("ADP Sense interrupt\n");
18173 + retval |= dwc_otg_adp_handle_sns_intr(core_if);
18175 + if (adpctl.b.adp_tmout_int & adpctl.b.adp_tmout_int_msk) {
18176 + DWC_PRINTF("ADP timeout interrupt\n");
18177 + retval |= dwc_otg_adp_handle_prb_tmout_intr(core_if, adpctl.d32);
18179 + if (adpctl.b.adp_prb_int & adpctl.b.adp_prb_int_msk) {
18180 + DWC_PRINTF("ADP Probe interrupt\n");
18181 + adpctl.b.adp_prb_int = 1;
18182 + retval |= dwc_otg_adp_handle_prb_intr(core_if, adpctl.d32);
18185 +// dwc_otg_adp_modify_reg(core_if, adpctl.d32, 0);
18186 + //dwc_otg_adp_write_reg(core_if, adpctl.d32);
18187 + DWC_PRINTF("RETURN FROM ADP ISR\n");
18194 + * @param core_if Programming view of DWC_otg controller.
18196 +int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if)
18199 +#ifndef DWC_HOST_ONLY
18200 + hprt0_data_t hprt0;
18201 + gpwrdn_data_t gpwrdn;
18202 + DWC_DEBUGPL(DBG_ANY, "++ Power Down Logic Session Request Interrupt++\n");
18204 + gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
18205 + /* check which value is for device mode and which for Host mode */
18206 + if (!gpwrdn.b.idsts) { /* considered host mode value is 0 */
18207 + DWC_PRINTF("SRP: Host mode\n");
18209 + if (core_if->adp_enable) {
18210 + dwc_otg_adp_probe_stop(core_if);
18212 + /* Power on the core */
18213 + if (core_if->power_down == 2) {
18214 + gpwrdn.b.pwrdnswtch = 1;
18215 + DWC_MODIFY_REG32(&core_if->core_global_regs->
18216 + gpwrdn, 0, gpwrdn.d32);
18219 + core_if->op_state = A_HOST;
18220 + dwc_otg_core_init(core_if);
18221 + dwc_otg_enable_global_interrupts(core_if);
18222 + cil_hcd_start(core_if);
18225 + /* Turn on the port power bit. */
18226 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
18227 + hprt0.b.prtpwr = 1;
18228 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
18230 + /* Start the Connection timer. So a message can be displayed
18231 + * if connect does not occur within 10 seconds. */
18232 + cil_hcd_session_start(core_if);
18234 + DWC_PRINTF("SRP: Device mode %s\n", __FUNCTION__);
18235 + if (core_if->adp_enable) {
18236 + dwc_otg_adp_probe_stop(core_if);
18238 + /* Power on the core */
18239 + if (core_if->power_down == 2) {
18240 + gpwrdn.b.pwrdnswtch = 1;
18241 + DWC_MODIFY_REG32(&core_if->core_global_regs->
18242 + gpwrdn, 0, gpwrdn.d32);
18246 + gpwrdn.b.pmuactv = 0;
18247 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
18250 + core_if->op_state = B_PERIPHERAL;
18251 + dwc_otg_core_init(core_if);
18252 + dwc_otg_enable_global_interrupts(core_if);
18253 + cil_pcd_start(core_if);
18260 +++ b/drivers/usb/host/dwc_otg/dwc_otg_adp.h
18262 +/* ==========================================================================
18263 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.h $
18264 + * $Revision: #7 $
18265 + * $Date: 2011/10/24 $
18266 + * $Change: 1871159 $
18268 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
18269 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
18270 + * otherwise expressly agreed to in writing between Synopsys and you.
18272 + * The Software IS NOT an item of Licensed Software or Licensed Product under
18273 + * any End User Software License Agreement or Agreement for Licensed Product
18274 + * with Synopsys or any supplement thereto. You are permitted to use and
18275 + * redistribute this Software in source and binary forms, with or without
18276 + * modification, provided that redistributions of source code must retain this
18277 + * notice. You may not view, use, disclose, copy or distribute this file or
18278 + * any information contained herein except pursuant to this license grant from
18279 + * Synopsys. If you do not agree with this notice, including the disclaimer
18280 + * below, then you are not authorized to use the Software.
18282 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
18283 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18284 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18285 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
18286 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18287 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
18288 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
18289 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
18290 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
18291 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
18293 + * ========================================================================== */
18295 +#ifndef __DWC_OTG_ADP_H__
18296 +#define __DWC_OTG_ADP_H__
18301 + * This file contains the Attach Detect Protocol interfaces and defines
18302 + * (functions) and structures for Linux.
18306 +#define DWC_OTG_ADP_UNATTACHED 0
18307 +#define DWC_OTG_ADP_ATTACHED 1
18308 +#define DWC_OTG_ADP_UNKOWN 2
18310 +typedef struct dwc_otg_adp {
18311 + uint32_t adp_started;
18312 + uint32_t initial_probe;
18313 + int32_t probe_timer_values[2];
18314 + uint32_t probe_enabled;
18315 + uint32_t sense_enabled;
18316 + dwc_timer_t *sense_timer;
18317 + uint32_t sense_timer_started;
18318 + dwc_timer_t *vbuson_timer;
18319 + uint32_t vbuson_timer_started;
18320 + uint32_t attached;
18321 + uint32_t probe_counter;
18326 + * Attach Detect Protocol functions
18329 +extern void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value);
18330 +extern uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if);
18331 +extern uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if);
18332 +extern uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if);
18333 +extern uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if);
18334 +extern uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if);
18335 +extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);
18336 +extern void dwc_otg_adp_init(dwc_otg_core_if_t * core_if);
18337 +extern void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if);
18338 +extern int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if);
18339 +extern int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if);
18341 +#endif //__DWC_OTG_ADP_H__
18343 +++ b/drivers/usb/host/dwc_otg/dwc_otg_attr.c
18345 +/* ==========================================================================
18346 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.c $
18347 + * $Revision: #44 $
18348 + * $Date: 2010/11/29 $
18349 + * $Change: 1636033 $
18351 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
18352 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
18353 + * otherwise expressly agreed to in writing between Synopsys and you.
18355 + * The Software IS NOT an item of Licensed Software or Licensed Product under
18356 + * any End User Software License Agreement or Agreement for Licensed Product
18357 + * with Synopsys or any supplement thereto. You are permitted to use and
18358 + * redistribute this Software in source and binary forms, with or without
18359 + * modification, provided that redistributions of source code must retain this
18360 + * notice. You may not view, use, disclose, copy or distribute this file or
18361 + * any information contained herein except pursuant to this license grant from
18362 + * Synopsys. If you do not agree with this notice, including the disclaimer
18363 + * below, then you are not authorized to use the Software.
18365 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
18366 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18367 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18368 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
18369 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18370 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
18371 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
18372 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
18373 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
18374 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
18376 + * ========================================================================== */
18380 + * The diagnostic interface will provide access to the controller for
18381 + * bringing up the hardware and testing. The Linux driver attributes
18382 + * feature will be used to provide the Linux Diagnostic
18383 + * Interface. These attributes are accessed through sysfs.
18386 +/** @page "Linux Module Attributes"
18388 + * The Linux module attributes feature is used to provide the Linux
18389 + * Diagnostic Interface. These attributes are accessed through sysfs.
18390 + * The diagnostic interface will provide access to the controller for
18391 + * bringing up the hardware and testing.
18393 + The following table shows the attributes.
18396 + <td><b> Name</b></td>
18397 + <td><b> Description</b></td>
18398 + <td><b> Access</b></td>
18403 + <td> Returns the current mode: 0 for device mode, 1 for host mode</td>
18408 + <td> hnpcapable </td>
18409 + <td> Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register.
18410 + Read returns the current value.</td>
18411 + <td> Read/Write</td>
18415 + <td> srpcapable </td>
18416 + <td> Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register.
18417 + Read returns the current value.</td>
18418 + <td> Read/Write</td>
18422 + <td> hsic_connect </td>
18423 + <td> Gets or sets the "HSIC-Connect" bit in the GLPMCFG Register.
18424 + Read returns the current value.</td>
18425 + <td> Read/Write</td>
18429 + <td> inv_sel_hsic </td>
18430 + <td> Gets or sets the "Invert Select HSIC" bit in the GLPMFG Register.
18431 + Read returns the current value.</td>
18432 + <td> Read/Write</td>
18437 + <td> Initiates the Host Negotiation Protocol. Read returns the status.</td>
18438 + <td> Read/Write</td>
18443 + <td> Initiates the Session Request Protocol. Read returns the status.</td>
18444 + <td> Read/Write</td>
18448 + <td> buspower </td>
18449 + <td> Gets or sets the Power State of the bus (0 - Off or 1 - On)</td>
18450 + <td> Read/Write</td>
18454 + <td> bussuspend </td>
18455 + <td> Suspends the USB bus.</td>
18456 + <td> Read/Write</td>
18460 + <td> busconnected </td>
18461 + <td> Gets the connection status of the bus</td>
18466 + <td> gotgctl </td>
18467 + <td> Gets or sets the Core Control Status Register.</td>
18468 + <td> Read/Write</td>
18472 + <td> gusbcfg </td>
18473 + <td> Gets or sets the Core USB Configuration Register</td>
18474 + <td> Read/Write</td>
18478 + <td> grxfsiz </td>
18479 + <td> Gets or sets the Receive FIFO Size Register</td>
18480 + <td> Read/Write</td>
18484 + <td> gnptxfsiz </td>
18485 + <td> Gets or sets the non-periodic Transmit Size Register</td>
18486 + <td> Read/Write</td>
18490 + <td> gpvndctl </td>
18491 + <td> Gets or sets the PHY Vendor Control Register</td>
18492 + <td> Read/Write</td>
18497 + <td> Gets the value in the lower 16-bits of the General Purpose IO Register
18498 + or sets the upper 16 bits.</td>
18499 + <td> Read/Write</td>
18504 + <td> Gets or sets the value of the User ID Register</td>
18505 + <td> Read/Write</td>
18509 + <td> gsnpsid </td>
18510 + <td> Gets the value of the Synopsys ID Regester</td>
18515 + <td> devspeed </td>
18516 + <td> Gets or sets the device speed setting in the DCFG register</td>
18517 + <td> Read/Write</td>
18521 + <td> enumspeed </td>
18522 + <td> Gets the device enumeration Speed.</td>
18527 + <td> hptxfsiz </td>
18528 + <td> Gets the value of the Host Periodic Transmit FIFO</td>
18534 + <td> Gets or sets the value in the Host Port Control and Status Register</td>
18535 + <td> Read/Write</td>
18539 + <td> regoffset </td>
18540 + <td> Sets the register offset for the next Register Access</td>
18541 + <td> Read/Write</td>
18545 + <td> regvalue </td>
18546 + <td> Gets or sets the value of the register at the offset in the regoffset attribute.</td>
18547 + <td> Read/Write</td>
18551 + <td> remote_wakeup </td>
18552 + <td> On read, shows the status of Remote Wakeup. On write, initiates a remote
18553 + wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote
18554 + Wakeup signalling bit in the Device Control Register is set for 1
18555 + milli-second.</td>
18556 + <td> Read/Write</td>
18560 + <td> rem_wakeup_pwrdn </td>
18561 + <td> On read, shows the status core - hibernated or not. On write, initiates
18562 + a remote wakeup of the device from Hibernation. </td>
18563 + <td> Read/Write</td>
18567 + <td> mode_ch_tim_en </td>
18568 + <td> This bit is used to enable or disable the host core to wait for 200 PHY
18569 + clock cycles at the end of Resume to change the opmode signal to the PHY to 00
18570 + after Suspend or LPM. </td>
18571 + <td> Read/Write</td>
18575 + <td> fr_interval </td>
18576 + <td> On read, shows the value of HFIR Frame Interval. On write, dynamically
18577 + reload HFIR register during runtime. The application can write a value to this
18578 + register only after the Port Enable bit of the Host Port Control and Status
18579 + register (HPRT.PrtEnaPort) has been set </td>
18580 + <td> Read/Write</td>
18584 + <td> disconnect_us </td>
18585 + <td> On read, shows the status of disconnect_device_us. On write, sets disconnect_us
18586 + which causes soft disconnect for 100us. Applicable only for device mode of operation.</td>
18587 + <td> Read/Write</td>
18591 + <td> regdump </td>
18592 + <td> Dumps the contents of core registers.</td>
18597 + <td> spramdump </td>
18598 + <td> Dumps the contents of core registers.</td>
18603 + <td> hcddump </td>
18604 + <td> Dumps the current HCD state.</td>
18609 + <td> hcd_frrem </td>
18610 + <td> Shows the average value of the Frame Remaining
18611 + field in the Host Frame Number/Frame Remaining register when an SOF interrupt
18612 + occurs. This can be used to determine the average interrupt latency. Also
18613 + shows the average Frame Remaining value for start_transfer and the "a" and
18614 + "b" sample points. The "a" and "b" sample points may be used during debugging
18615 + bto determine how long it takes to execute a section of the HCD code.</td>
18620 + <td> rd_reg_test </td>
18621 + <td> Displays the time required to read the GNPTXFSIZ register many times
18622 + (the output shows the number of times the register is read).
18627 + <td> wr_reg_test </td>
18628 + <td> Displays the time required to write the GNPTXFSIZ register many times
18629 + (the output shows the number of times the register is written).
18634 + <td> lpm_response </td>
18635 + <td> Gets or sets lpm_response mode. Applicable only in device mode.
18640 + <td> sleep_status </td>
18641 + <td> Shows sleep status of device.
18648 + To get the current mode:
18649 + cat /sys/devices/lm0/mode
18651 + To power down the USB:
18652 + echo 0 > /sys/devices/lm0/buspower
18655 +#include "dwc_otg_os_dep.h"
18656 +#include "dwc_os.h"
18657 +#include "dwc_otg_driver.h"
18658 +#include "dwc_otg_attr.h"
18659 +#include "dwc_otg_core_if.h"
18660 +#include "dwc_otg_pcd_if.h"
18661 +#include "dwc_otg_hcd_if.h"
18664 + * MACROs for defining sysfs attribute
18666 +#ifdef LM_INTERFACE
18668 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
18669 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
18671 + struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
18672 + dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
18674 + val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
18675 + return sprintf (buf, "%s = 0x%x\n", _string_, val); \
18677 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
18678 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
18679 + const char *buf, size_t count) \
18681 + struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
18682 + dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
18683 + uint32_t set = simple_strtoul(buf, NULL, 16); \
18684 + dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
18688 +#elif defined(PCI_INTERFACE)
18690 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
18691 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
18693 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
18695 + val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
18696 + return sprintf (buf, "%s = 0x%x\n", _string_, val); \
18698 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
18699 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
18700 + const char *buf, size_t count) \
18702 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
18703 + uint32_t set = simple_strtoul(buf, NULL, 16); \
18704 + dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
18708 +#elif defined(PLATFORM_INTERFACE)
18710 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
18711 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
18713 + struct platform_device *platform_dev = \
18714 + container_of(_dev, struct platform_device, dev); \
18715 + dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
18717 + DWC_PRINTF("%s(%p) -> platform_dev %p, otg_dev %p\n", \
18718 + __func__, _dev, platform_dev, otg_dev); \
18719 + val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
18720 + return sprintf (buf, "%s = 0x%x\n", _string_, val); \
18722 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
18723 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
18724 + const char *buf, size_t count) \
18726 + struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \
18727 + dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
18728 + uint32_t set = simple_strtoul(buf, NULL, 16); \
18729 + dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
18735 + * MACROs for defining sysfs attribute for 32-bit registers
18737 +#ifdef LM_INTERFACE
18738 +#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
18739 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
18741 + struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
18742 + dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
18744 + val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
18745 + return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
18747 +#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
18748 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
18749 + const char *buf, size_t count) \
18751 + struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
18752 + dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
18753 + uint32_t val = simple_strtoul(buf, NULL, 16); \
18754 + dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
18757 +#elif defined(PCI_INTERFACE)
18758 +#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
18759 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
18761 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
18763 + val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
18764 + return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
18766 +#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
18767 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
18768 + const char *buf, size_t count) \
18770 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
18771 + uint32_t val = simple_strtoul(buf, NULL, 16); \
18772 + dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
18776 +#elif defined(PLATFORM_INTERFACE)
18777 +#include "dwc_otg_dbg.h"
18778 +#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
18779 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
18781 + struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \
18782 + dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
18784 + DWC_PRINTF("%s(%p) -> platform_dev %p, otg_dev %p\n", \
18785 + __func__, _dev, platform_dev, otg_dev); \
18786 + val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
18787 + return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
18789 +#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
18790 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
18791 + const char *buf, size_t count) \
18793 + struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \
18794 + dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
18795 + uint32_t val = simple_strtoul(buf, NULL, 16); \
18796 + dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
18802 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_string_) \
18803 +DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
18804 +DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
18805 +DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
18807 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_string_) \
18808 +DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
18809 +DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
18811 +#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \
18812 +DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
18813 +DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
18814 +DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
18816 +#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \
18817 +DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
18818 +DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
18820 +/** @name Functions for Show/Store of Attributes */
18824 + * Helper function returning the otg_device structure of the given device
18826 +static dwc_otg_device_t *dwc_otg_drvdev(struct device *_dev)
18828 + dwc_otg_device_t *otg_dev;
18829 + DWC_OTG_GETDRVDEV(otg_dev, _dev);
18834 + * Show the register offset of the Register Access.
18836 +static ssize_t regoffset_show(struct device *_dev,
18837 + struct device_attribute *attr, char *buf)
18839 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18840 + return snprintf(buf, sizeof("0xFFFFFFFF\n") + 1, "0x%08x\n",
18841 + otg_dev->os_dep.reg_offset);
18845 + * Set the register offset for the next Register Access Read/Write
18847 +static ssize_t regoffset_store(struct device *_dev,
18848 + struct device_attribute *attr,
18849 + const char *buf, size_t count)
18851 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18852 + uint32_t offset = simple_strtoul(buf, NULL, 16);
18853 +#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)
18854 + if (offset < SZ_256K) {
18855 +#elif defined(PCI_INTERFACE)
18856 + if (offset < 0x00040000) {
18858 + otg_dev->os_dep.reg_offset = offset;
18860 + dev_err(_dev, "invalid offset\n");
18866 +DEVICE_ATTR(regoffset, S_IRUGO | S_IWUSR, regoffset_show, regoffset_store);
18869 + * Show the value of the register at the offset in the reg_offset
18872 +static ssize_t regvalue_show(struct device *_dev,
18873 + struct device_attribute *attr, char *buf)
18875 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18877 + volatile uint32_t *addr;
18879 + if (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) {
18880 + /* Calculate the address */
18881 + addr = (uint32_t *) (otg_dev->os_dep.reg_offset +
18882 + (uint8_t *) otg_dev->os_dep.base);
18883 + val = DWC_READ_REG32(addr);
18884 + return snprintf(buf,
18885 + sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n") + 1,
18886 + "Reg@0x%06x = 0x%08x\n", otg_dev->os_dep.reg_offset,
18889 + dev_err(_dev, "Invalid offset (0x%0x)\n", otg_dev->os_dep.reg_offset);
18890 + return sprintf(buf, "invalid offset\n");
18895 + * Store the value in the register at the offset in the reg_offset
18899 +static ssize_t regvalue_store(struct device *_dev,
18900 + struct device_attribute *attr,
18901 + const char *buf, size_t count)
18903 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18904 + volatile uint32_t *addr;
18905 + uint32_t val = simple_strtoul(buf, NULL, 16);
18906 + //dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val);
18907 + if (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) {
18908 + /* Calculate the address */
18909 + addr = (uint32_t *) (otg_dev->os_dep.reg_offset +
18910 + (uint8_t *) otg_dev->os_dep.base);
18911 + DWC_WRITE_REG32(addr, val);
18913 + dev_err(_dev, "Invalid Register Offset (0x%08x)\n",
18914 + otg_dev->os_dep.reg_offset);
18919 +DEVICE_ATTR(regvalue, S_IRUGO | S_IWUSR, regvalue_show, regvalue_store);
18924 +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode, "Mode");
18925 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable, "HNPCapable");
18926 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable, "SRPCapable");
18927 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hsic_connect, "HSIC Connect");
18928 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(inv_sel_hsic, "Invert Select HSIC");
18930 +//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
18931 +//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
18932 +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected, "Bus Connected");
18934 +DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl, 0, "GOTGCTL");
18935 +DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,
18936 + &(otg_dev->core_if->core_global_regs->gusbcfg),
18938 +DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,
18939 + &(otg_dev->core_if->core_global_regs->grxfsiz),
18941 +DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,
18942 + &(otg_dev->core_if->core_global_regs->gnptxfsiz),
18944 +DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,
18945 + &(otg_dev->core_if->core_global_regs->gpvndctl),
18947 +DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,
18948 + &(otg_dev->core_if->core_global_regs->ggpio),
18950 +DWC_OTG_DEVICE_ATTR_REG32_RW(guid, &(otg_dev->core_if->core_global_regs->guid),
18952 +DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,
18953 + &(otg_dev->core_if->core_global_regs->gsnpsid),
18955 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed, "Device Speed");
18956 +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed, "Device Enumeration Speed");
18958 +DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,
18959 + &(otg_dev->core_if->core_global_regs->hptxfsiz),
18961 +DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0, otg_dev->core_if->host_if->hprt0, "HPRT0");
18964 + * @todo Add code to initiate the HNP.
18967 + * Show the HNP status bit
18969 +static ssize_t hnp_show(struct device *_dev,
18970 + struct device_attribute *attr, char *buf)
18972 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18973 + return sprintf(buf, "HstNegScs = 0x%x\n",
18974 + dwc_otg_get_hnpstatus(otg_dev->core_if));
18978 + * Set the HNP Request bit
18980 +static ssize_t hnp_store(struct device *_dev,
18981 + struct device_attribute *attr,
18982 + const char *buf, size_t count)
18984 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18985 + uint32_t in = simple_strtoul(buf, NULL, 16);
18986 + dwc_otg_set_hnpreq(otg_dev->core_if, in);
18990 +DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store);
18993 + * @todo Add code to initiate the SRP.
18996 + * Show the SRP status bit
18998 +static ssize_t srp_show(struct device *_dev,
18999 + struct device_attribute *attr, char *buf)
19001 +#ifndef DWC_HOST_ONLY
19002 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19003 + return sprintf(buf, "SesReqScs = 0x%x\n",
19004 + dwc_otg_get_srpstatus(otg_dev->core_if));
19006 + return sprintf(buf, "Host Only Mode!\n");
19011 + * Set the SRP Request bit
19013 +static ssize_t srp_store(struct device *_dev,
19014 + struct device_attribute *attr,
19015 + const char *buf, size_t count)
19017 +#ifndef DWC_HOST_ONLY
19018 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19019 + dwc_otg_pcd_initiate_srp(otg_dev->pcd);
19024 +DEVICE_ATTR(srp, 0644, srp_show, srp_store);
19027 + * @todo Need to do more for power on/off?
19030 + * Show the Bus Power status
19032 +static ssize_t buspower_show(struct device *_dev,
19033 + struct device_attribute *attr, char *buf)
19035 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19036 + return sprintf(buf, "Bus Power = 0x%x\n",
19037 + dwc_otg_get_prtpower(otg_dev->core_if));
19041 + * Set the Bus Power status
19043 +static ssize_t buspower_store(struct device *_dev,
19044 + struct device_attribute *attr,
19045 + const char *buf, size_t count)
19047 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19048 + uint32_t on = simple_strtoul(buf, NULL, 16);
19049 + dwc_otg_set_prtpower(otg_dev->core_if, on);
19053 +DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store);
19056 + * @todo Need to do more for suspend?
19059 + * Show the Bus Suspend status
19061 +static ssize_t bussuspend_show(struct device *_dev,
19062 + struct device_attribute *attr, char *buf)
19064 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19065 + return sprintf(buf, "Bus Suspend = 0x%x\n",
19066 + dwc_otg_get_prtsuspend(otg_dev->core_if));
19070 + * Set the Bus Suspend status
19072 +static ssize_t bussuspend_store(struct device *_dev,
19073 + struct device_attribute *attr,
19074 + const char *buf, size_t count)
19076 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19077 + uint32_t in = simple_strtoul(buf, NULL, 16);
19078 + dwc_otg_set_prtsuspend(otg_dev->core_if, in);
19082 +DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store);
19085 + * Show the Mode Change Ready Timer status
19087 +static ssize_t mode_ch_tim_en_show(struct device *_dev,
19088 + struct device_attribute *attr, char *buf)
19090 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19091 + return sprintf(buf, "Mode Change Ready Timer Enable = 0x%x\n",
19092 + dwc_otg_get_mode_ch_tim(otg_dev->core_if));
19096 + * Set the Mode Change Ready Timer status
19098 +static ssize_t mode_ch_tim_en_store(struct device *_dev,
19099 + struct device_attribute *attr,
19100 + const char *buf, size_t count)
19102 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19103 + uint32_t in = simple_strtoul(buf, NULL, 16);
19104 + dwc_otg_set_mode_ch_tim(otg_dev->core_if, in);
19108 +DEVICE_ATTR(mode_ch_tim_en, 0644, mode_ch_tim_en_show, mode_ch_tim_en_store);
19111 + * Show the value of HFIR Frame Interval bitfield
19113 +static ssize_t fr_interval_show(struct device *_dev,
19114 + struct device_attribute *attr, char *buf)
19116 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19117 + return sprintf(buf, "Frame Interval = 0x%x\n",
19118 + dwc_otg_get_fr_interval(otg_dev->core_if));
19122 + * Set the HFIR Frame Interval value
19124 +static ssize_t fr_interval_store(struct device *_dev,
19125 + struct device_attribute *attr,
19126 + const char *buf, size_t count)
19128 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19129 + uint32_t in = simple_strtoul(buf, NULL, 10);
19130 + dwc_otg_set_fr_interval(otg_dev->core_if, in);
19134 +DEVICE_ATTR(fr_interval, 0644, fr_interval_show, fr_interval_store);
19137 + * Show the status of Remote Wakeup.
19139 +static ssize_t remote_wakeup_show(struct device *_dev,
19140 + struct device_attribute *attr, char *buf)
19142 +#ifndef DWC_HOST_ONLY
19143 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19145 + return sprintf(buf,
19146 + "Remote Wakeup Sig = %d Enabled = %d LPM Remote Wakeup = %d\n",
19147 + dwc_otg_get_remotewakesig(otg_dev->core_if),
19148 + dwc_otg_pcd_get_rmwkup_enable(otg_dev->pcd),
19149 + dwc_otg_get_lpm_remotewakeenabled(otg_dev->core_if));
19151 + return sprintf(buf, "Host Only Mode!\n");
19152 +#endif /* DWC_HOST_ONLY */
19156 + * Initiate a remote wakeup of the host. The Device control register
19157 + * Remote Wakeup Signal bit is written if the PCD Remote wakeup enable
19161 +static ssize_t remote_wakeup_store(struct device *_dev,
19162 + struct device_attribute *attr,
19163 + const char *buf, size_t count)
19165 +#ifndef DWC_HOST_ONLY
19166 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19167 + uint32_t val = simple_strtoul(buf, NULL, 16);
19170 + dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1);
19172 + dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0);
19174 +#endif /* DWC_HOST_ONLY */
19178 +DEVICE_ATTR(remote_wakeup, S_IRUGO | S_IWUSR, remote_wakeup_show,
19179 + remote_wakeup_store);
19182 + * Show the whether core is hibernated or not.
19184 +static ssize_t rem_wakeup_pwrdn_show(struct device *_dev,
19185 + struct device_attribute *attr, char *buf)
19187 +#ifndef DWC_HOST_ONLY
19188 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19190 + if (dwc_otg_get_core_state(otg_dev->core_if)) {
19191 + DWC_PRINTF("Core is in hibernation\n");
19193 + DWC_PRINTF("Core is not in hibernation\n");
19195 +#endif /* DWC_HOST_ONLY */
19199 +extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
19200 + int rem_wakeup, int reset);
19203 + * Initiate a remote wakeup of the device to exit from hibernation.
19205 +static ssize_t rem_wakeup_pwrdn_store(struct device *_dev,
19206 + struct device_attribute *attr,
19207 + const char *buf, size_t count)
19209 +#ifndef DWC_HOST_ONLY
19210 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19211 + dwc_otg_device_hibernation_restore(otg_dev->core_if, 1, 0);
19216 +DEVICE_ATTR(rem_wakeup_pwrdn, S_IRUGO | S_IWUSR, rem_wakeup_pwrdn_show,
19217 + rem_wakeup_pwrdn_store);
19219 +static ssize_t disconnect_us(struct device *_dev,
19220 + struct device_attribute *attr,
19221 + const char *buf, size_t count)
19224 +#ifndef DWC_HOST_ONLY
19225 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19226 + uint32_t val = simple_strtoul(buf, NULL, 16);
19227 + DWC_PRINTF("The Passed value is %04x\n", val);
19229 + dwc_otg_pcd_disconnect_us(otg_dev->pcd, 50);
19231 +#endif /* DWC_HOST_ONLY */
19235 +DEVICE_ATTR(disconnect_us, S_IWUSR, 0, disconnect_us);
19238 + * Dump global registers and either host or device registers (depending on the
19239 + * current mode of the core).
19241 +static ssize_t regdump_show(struct device *_dev,
19242 + struct device_attribute *attr, char *buf)
19244 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19246 + dwc_otg_dump_global_registers(otg_dev->core_if);
19247 + if (dwc_otg_is_host_mode(otg_dev->core_if)) {
19248 + dwc_otg_dump_host_registers(otg_dev->core_if);
19250 + dwc_otg_dump_dev_registers(otg_dev->core_if);
19253 + return sprintf(buf, "Register Dump\n");
19256 +DEVICE_ATTR(regdump, S_IRUGO, regdump_show, 0);
19259 + * Dump global registers and either host or device registers (depending on the
19260 + * current mode of the core).
19262 +static ssize_t spramdump_show(struct device *_dev,
19263 + struct device_attribute *attr, char *buf)
19266 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19268 + dwc_otg_dump_spram(otg_dev->core_if);
19271 + return sprintf(buf, "SPRAM Dump\n");
19274 +DEVICE_ATTR(spramdump, S_IRUGO, spramdump_show, 0);
19277 + * Dump the current hcd state.
19279 +static ssize_t hcddump_show(struct device *_dev,
19280 + struct device_attribute *attr, char *buf)
19282 +#ifndef DWC_DEVICE_ONLY
19283 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19284 + dwc_otg_hcd_dump_state(otg_dev->hcd);
19285 +#endif /* DWC_DEVICE_ONLY */
19286 + return sprintf(buf, "HCD Dump\n");
19289 +DEVICE_ATTR(hcddump, S_IRUGO, hcddump_show, 0);
19292 + * Dump the average frame remaining at SOF. This can be used to
19293 + * determine average interrupt latency. Frame remaining is also shown for
19294 + * start transfer and two additional sample points.
19296 +static ssize_t hcd_frrem_show(struct device *_dev,
19297 + struct device_attribute *attr, char *buf)
19299 +#ifndef DWC_DEVICE_ONLY
19300 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19302 + dwc_otg_hcd_dump_frrem(otg_dev->hcd);
19303 +#endif /* DWC_DEVICE_ONLY */
19304 + return sprintf(buf, "HCD Dump Frame Remaining\n");
19307 +DEVICE_ATTR(hcd_frrem, S_IRUGO, hcd_frrem_show, 0);
19310 + * Displays the time required to read the GNPTXFSIZ register many times (the
19311 + * output shows the number of times the register is read).
19313 +#define RW_REG_COUNT 10000000
19314 +#define MSEC_PER_JIFFIE 1000/HZ
19315 +static ssize_t rd_reg_test_show(struct device *_dev,
19316 + struct device_attribute *attr, char *buf)
19318 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19321 + int start_jiffies;
19323 + printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
19324 + HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
19325 + start_jiffies = jiffies;
19326 + for (i = 0; i < RW_REG_COUNT; i++) {
19327 + dwc_otg_get_gnptxfsiz(otg_dev->core_if);
19329 + time = jiffies - start_jiffies;
19330 + return sprintf(buf,
19331 + "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
19332 + RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
19335 +DEVICE_ATTR(rd_reg_test, S_IRUGO, rd_reg_test_show, 0);
19338 + * Displays the time required to write the GNPTXFSIZ register many times (the
19339 + * output shows the number of times the register is written).
19341 +static ssize_t wr_reg_test_show(struct device *_dev,
19342 + struct device_attribute *attr, char *buf)
19344 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19345 + uint32_t reg_val;
19348 + int start_jiffies;
19350 + printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
19351 + HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
19352 + reg_val = dwc_otg_get_gnptxfsiz(otg_dev->core_if);
19353 + start_jiffies = jiffies;
19354 + for (i = 0; i < RW_REG_COUNT; i++) {
19355 + dwc_otg_set_gnptxfsiz(otg_dev->core_if, reg_val);
19357 + time = jiffies - start_jiffies;
19358 + return sprintf(buf,
19359 + "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
19360 + RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
19363 +DEVICE_ATTR(wr_reg_test, S_IRUGO, wr_reg_test_show, 0);
19365 +#ifdef CONFIG_USB_DWC_OTG_LPM
19368 +* Show the lpm_response attribute.
19370 +static ssize_t lpmresp_show(struct device *_dev,
19371 + struct device_attribute *attr, char *buf)
19373 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19375 + if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if))
19376 + return sprintf(buf, "** LPM is DISABLED **\n");
19378 + if (!dwc_otg_is_device_mode(otg_dev->core_if)) {
19379 + return sprintf(buf, "** Current mode is not device mode\n");
19381 + return sprintf(buf, "lpm_response = %d\n",
19382 + dwc_otg_get_lpmresponse(otg_dev->core_if));
19386 +* Store the lpm_response attribute.
19388 +static ssize_t lpmresp_store(struct device *_dev,
19389 + struct device_attribute *attr,
19390 + const char *buf, size_t count)
19392 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19393 + uint32_t val = simple_strtoul(buf, NULL, 16);
19395 + if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if)) {
19399 + if (!dwc_otg_is_device_mode(otg_dev->core_if)) {
19403 + dwc_otg_set_lpmresponse(otg_dev->core_if, val);
19407 +DEVICE_ATTR(lpm_response, S_IRUGO | S_IWUSR, lpmresp_show, lpmresp_store);
19410 +* Show the sleep_status attribute.
19412 +static ssize_t sleepstatus_show(struct device *_dev,
19413 + struct device_attribute *attr, char *buf)
19415 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19416 + return sprintf(buf, "Sleep Status = %d\n",
19417 + dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if));
19421 + * Store the sleep_status attribure.
19423 +static ssize_t sleepstatus_store(struct device *_dev,
19424 + struct device_attribute *attr,
19425 + const char *buf, size_t count)
19427 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19428 + dwc_otg_core_if_t *core_if = otg_dev->core_if;
19430 + if (dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if)) {
19431 + if (dwc_otg_is_host_mode(core_if)) {
19433 + DWC_PRINTF("Host initiated resume\n");
19434 + dwc_otg_set_prtresume(otg_dev->core_if, 1);
19441 +DEVICE_ATTR(sleep_status, S_IRUGO | S_IWUSR, sleepstatus_show,
19442 + sleepstatus_store);
19444 +#endif /* CONFIG_USB_DWC_OTG_LPM_ENABLE */
19449 + * Create the device files
19451 +void dwc_otg_attr_create(
19452 +#ifdef LM_INTERFACE
19453 + struct lm_device *dev
19454 +#elif defined(PCI_INTERFACE)
19455 + struct pci_dev *dev
19456 +#elif defined(PLATFORM_INTERFACE)
19457 + struct platform_device *dev
19463 + error = device_create_file(&dev->dev, &dev_attr_regoffset);
19464 + error = device_create_file(&dev->dev, &dev_attr_regvalue);
19465 + error = device_create_file(&dev->dev, &dev_attr_mode);
19466 + error = device_create_file(&dev->dev, &dev_attr_hnpcapable);
19467 + error = device_create_file(&dev->dev, &dev_attr_srpcapable);
19468 + error = device_create_file(&dev->dev, &dev_attr_hsic_connect);
19469 + error = device_create_file(&dev->dev, &dev_attr_inv_sel_hsic);
19470 + error = device_create_file(&dev->dev, &dev_attr_hnp);
19471 + error = device_create_file(&dev->dev, &dev_attr_srp);
19472 + error = device_create_file(&dev->dev, &dev_attr_buspower);
19473 + error = device_create_file(&dev->dev, &dev_attr_bussuspend);
19474 + error = device_create_file(&dev->dev, &dev_attr_mode_ch_tim_en);
19475 + error = device_create_file(&dev->dev, &dev_attr_fr_interval);
19476 + error = device_create_file(&dev->dev, &dev_attr_busconnected);
19477 + error = device_create_file(&dev->dev, &dev_attr_gotgctl);
19478 + error = device_create_file(&dev->dev, &dev_attr_gusbcfg);
19479 + error = device_create_file(&dev->dev, &dev_attr_grxfsiz);
19480 + error = device_create_file(&dev->dev, &dev_attr_gnptxfsiz);
19481 + error = device_create_file(&dev->dev, &dev_attr_gpvndctl);
19482 + error = device_create_file(&dev->dev, &dev_attr_ggpio);
19483 + error = device_create_file(&dev->dev, &dev_attr_guid);
19484 + error = device_create_file(&dev->dev, &dev_attr_gsnpsid);
19485 + error = device_create_file(&dev->dev, &dev_attr_devspeed);
19486 + error = device_create_file(&dev->dev, &dev_attr_enumspeed);
19487 + error = device_create_file(&dev->dev, &dev_attr_hptxfsiz);
19488 + error = device_create_file(&dev->dev, &dev_attr_hprt0);
19489 + error = device_create_file(&dev->dev, &dev_attr_remote_wakeup);
19490 + error = device_create_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn);
19491 + error = device_create_file(&dev->dev, &dev_attr_disconnect_us);
19492 + error = device_create_file(&dev->dev, &dev_attr_regdump);
19493 + error = device_create_file(&dev->dev, &dev_attr_spramdump);
19494 + error = device_create_file(&dev->dev, &dev_attr_hcddump);
19495 + error = device_create_file(&dev->dev, &dev_attr_hcd_frrem);
19496 + error = device_create_file(&dev->dev, &dev_attr_rd_reg_test);
19497 + error = device_create_file(&dev->dev, &dev_attr_wr_reg_test);
19498 +#ifdef CONFIG_USB_DWC_OTG_LPM
19499 + error = device_create_file(&dev->dev, &dev_attr_lpm_response);
19500 + error = device_create_file(&dev->dev, &dev_attr_sleep_status);
19505 + * Remove the device files
19507 +void dwc_otg_attr_remove(
19508 +#ifdef LM_INTERFACE
19509 + struct lm_device *dev
19510 +#elif defined(PCI_INTERFACE)
19511 + struct pci_dev *dev
19512 +#elif defined(PLATFORM_INTERFACE)
19513 + struct platform_device *dev
19517 + device_remove_file(&dev->dev, &dev_attr_regoffset);
19518 + device_remove_file(&dev->dev, &dev_attr_regvalue);
19519 + device_remove_file(&dev->dev, &dev_attr_mode);
19520 + device_remove_file(&dev->dev, &dev_attr_hnpcapable);
19521 + device_remove_file(&dev->dev, &dev_attr_srpcapable);
19522 + device_remove_file(&dev->dev, &dev_attr_hsic_connect);
19523 + device_remove_file(&dev->dev, &dev_attr_inv_sel_hsic);
19524 + device_remove_file(&dev->dev, &dev_attr_hnp);
19525 + device_remove_file(&dev->dev, &dev_attr_srp);
19526 + device_remove_file(&dev->dev, &dev_attr_buspower);
19527 + device_remove_file(&dev->dev, &dev_attr_bussuspend);
19528 + device_remove_file(&dev->dev, &dev_attr_mode_ch_tim_en);
19529 + device_remove_file(&dev->dev, &dev_attr_fr_interval);
19530 + device_remove_file(&dev->dev, &dev_attr_busconnected);
19531 + device_remove_file(&dev->dev, &dev_attr_gotgctl);
19532 + device_remove_file(&dev->dev, &dev_attr_gusbcfg);
19533 + device_remove_file(&dev->dev, &dev_attr_grxfsiz);
19534 + device_remove_file(&dev->dev, &dev_attr_gnptxfsiz);
19535 + device_remove_file(&dev->dev, &dev_attr_gpvndctl);
19536 + device_remove_file(&dev->dev, &dev_attr_ggpio);
19537 + device_remove_file(&dev->dev, &dev_attr_guid);
19538 + device_remove_file(&dev->dev, &dev_attr_gsnpsid);
19539 + device_remove_file(&dev->dev, &dev_attr_devspeed);
19540 + device_remove_file(&dev->dev, &dev_attr_enumspeed);
19541 + device_remove_file(&dev->dev, &dev_attr_hptxfsiz);
19542 + device_remove_file(&dev->dev, &dev_attr_hprt0);
19543 + device_remove_file(&dev->dev, &dev_attr_remote_wakeup);
19544 + device_remove_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn);
19545 + device_remove_file(&dev->dev, &dev_attr_disconnect_us);
19546 + device_remove_file(&dev->dev, &dev_attr_regdump);
19547 + device_remove_file(&dev->dev, &dev_attr_spramdump);
19548 + device_remove_file(&dev->dev, &dev_attr_hcddump);
19549 + device_remove_file(&dev->dev, &dev_attr_hcd_frrem);
19550 + device_remove_file(&dev->dev, &dev_attr_rd_reg_test);
19551 + device_remove_file(&dev->dev, &dev_attr_wr_reg_test);
19552 +#ifdef CONFIG_USB_DWC_OTG_LPM
19553 + device_remove_file(&dev->dev, &dev_attr_lpm_response);
19554 + device_remove_file(&dev->dev, &dev_attr_sleep_status);
19558 +++ b/drivers/usb/host/dwc_otg/dwc_otg_attr.h
19560 +/* ==========================================================================
19561 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $
19562 + * $Revision: #13 $
19563 + * $Date: 2010/06/21 $
19564 + * $Change: 1532021 $
19566 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
19567 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
19568 + * otherwise expressly agreed to in writing between Synopsys and you.
19570 + * The Software IS NOT an item of Licensed Software or Licensed Product under
19571 + * any End User Software License Agreement or Agreement for Licensed Product
19572 + * with Synopsys or any supplement thereto. You are permitted to use and
19573 + * redistribute this Software in source and binary forms, with or without
19574 + * modification, provided that redistributions of source code must retain this
19575 + * notice. You may not view, use, disclose, copy or distribute this file or
19576 + * any information contained herein except pursuant to this license grant from
19577 + * Synopsys. If you do not agree with this notice, including the disclaimer
19578 + * below, then you are not authorized to use the Software.
19580 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
19581 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19582 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19583 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
19584 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19585 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
19586 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
19587 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
19588 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
19589 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
19591 + * ========================================================================== */
19593 +#if !defined(__DWC_OTG_ATTR_H__)
19594 +#define __DWC_OTG_ATTR_H__
19597 + * This file contains the interface to the Linux device attributes.
19599 +extern struct device_attribute dev_attr_regoffset;
19600 +extern struct device_attribute dev_attr_regvalue;
19602 +extern struct device_attribute dev_attr_mode;
19603 +extern struct device_attribute dev_attr_hnpcapable;
19604 +extern struct device_attribute dev_attr_srpcapable;
19605 +extern struct device_attribute dev_attr_hnp;
19606 +extern struct device_attribute dev_attr_srp;
19607 +extern struct device_attribute dev_attr_buspower;
19608 +extern struct device_attribute dev_attr_bussuspend;
19609 +extern struct device_attribute dev_attr_mode_ch_tim_en;
19610 +extern struct device_attribute dev_attr_fr_interval;
19611 +extern struct device_attribute dev_attr_busconnected;
19612 +extern struct device_attribute dev_attr_gotgctl;
19613 +extern struct device_attribute dev_attr_gusbcfg;
19614 +extern struct device_attribute dev_attr_grxfsiz;
19615 +extern struct device_attribute dev_attr_gnptxfsiz;
19616 +extern struct device_attribute dev_attr_gpvndctl;
19617 +extern struct device_attribute dev_attr_ggpio;
19618 +extern struct device_attribute dev_attr_guid;
19619 +extern struct device_attribute dev_attr_gsnpsid;
19620 +extern struct device_attribute dev_attr_devspeed;
19621 +extern struct device_attribute dev_attr_enumspeed;
19622 +extern struct device_attribute dev_attr_hptxfsiz;
19623 +extern struct device_attribute dev_attr_hprt0;
19624 +#ifdef CONFIG_USB_DWC_OTG_LPM
19625 +extern struct device_attribute dev_attr_lpm_response;
19626 +extern struct device_attribute devi_attr_sleep_status;
19629 +void dwc_otg_attr_create(
19630 +#ifdef LM_INTERFACE
19631 + struct lm_device *dev
19632 +#elif defined(PCI_INTERFACE)
19633 + struct pci_dev *dev
19634 +#elif defined(PLATFORM_INTERFACE)
19635 + struct platform_device *dev
19639 +void dwc_otg_attr_remove(
19640 +#ifdef LM_INTERFACE
19641 + struct lm_device *dev
19642 +#elif defined(PCI_INTERFACE)
19643 + struct pci_dev *dev
19644 +#elif defined(PLATFORM_INTERFACE)
19645 + struct platform_device *dev
19650 +++ b/drivers/usb/host/dwc_otg/dwc_otg_cfi.c
19652 +/* ==========================================================================
19653 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
19654 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
19655 + * otherwise expressly agreed to in writing between Synopsys and you.
19657 + * The Software IS NOT an item of Licensed Software or Licensed Product under
19658 + * any End User Software License Agreement or Agreement for Licensed Product
19659 + * with Synopsys or any supplement thereto. You are permitted to use and
19660 + * redistribute this Software in source and binary forms, with or without
19661 + * modification, provided that redistributions of source code must retain this
19662 + * notice. You may not view, use, disclose, copy or distribute this file or
19663 + * any information contained herein except pursuant to this license grant from
19664 + * Synopsys. If you do not agree with this notice, including the disclaimer
19665 + * below, then you are not authorized to use the Software.
19667 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
19668 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19669 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19670 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
19671 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19672 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
19673 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
19674 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
19675 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
19676 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
19678 + * ========================================================================== */
19682 + * This file contains the most of the CFI(Core Feature Interface)
19683 + * implementation for the OTG.
19686 +#ifdef DWC_UTE_CFI
19688 +#include "dwc_otg_pcd.h"
19689 +#include "dwc_otg_cfi.h"
19691 +/** This definition should actually migrate to the Portability Library */
19692 +#define DWC_CONSTANT_CPU_TO_LE16(x) (x)
19694 +extern dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex);
19696 +static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen);
19697 +static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen,
19698 + struct dwc_otg_pcd *pcd,
19699 + struct cfi_usb_ctrlrequest *ctrl_req);
19700 +static int cfi_set_feature_value(struct dwc_otg_pcd *pcd);
19701 +static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
19702 + struct cfi_usb_ctrlrequest *req);
19703 +static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
19704 + struct cfi_usb_ctrlrequest *req);
19705 +static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
19706 + struct cfi_usb_ctrlrequest *req);
19707 +static int cfi_preproc_reset(struct dwc_otg_pcd *pcd,
19708 + struct cfi_usb_ctrlrequest *req);
19709 +static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep);
19711 +static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if);
19712 +static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue);
19713 +static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue);
19715 +static uint8_t resize_fifos(dwc_otg_core_if_t * core_if);
19717 +/** This is the header of the all features descriptor */
19718 +static cfi_all_features_header_t all_props_desc_header = {
19719 + .wVersion = DWC_CONSTANT_CPU_TO_LE16(0x100),
19720 + .wCoreID = DWC_CONSTANT_CPU_TO_LE16(CFI_CORE_ID_OTG),
19721 + .wNumFeatures = DWC_CONSTANT_CPU_TO_LE16(9),
19724 +/** This is an array of statically allocated feature descriptors */
19725 +static cfi_feature_desc_header_t prop_descs[] = {
19727 + /* FT_ID_DMA_MODE */
19729 + .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_MODE),
19730 + .bmAttributes = CFI_FEATURE_ATTR_RW,
19731 + .wDataLength = DWC_CONSTANT_CPU_TO_LE16(1),
19734 + /* FT_ID_DMA_BUFFER_SETUP */
19736 + .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFFER_SETUP),
19737 + .bmAttributes = CFI_FEATURE_ATTR_RW,
19738 + .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
19741 + /* FT_ID_DMA_BUFF_ALIGN */
19743 + .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFF_ALIGN),
19744 + .bmAttributes = CFI_FEATURE_ATTR_RW,
19745 + .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
19748 + /* FT_ID_DMA_CONCAT_SETUP */
19750 + .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CONCAT_SETUP),
19751 + .bmAttributes = CFI_FEATURE_ATTR_RW,
19752 + //.wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
19755 + /* FT_ID_DMA_CIRCULAR */
19757 + .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CIRCULAR),
19758 + .bmAttributes = CFI_FEATURE_ATTR_RW,
19759 + .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
19762 + /* FT_ID_THRESHOLD_SETUP */
19764 + .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_THRESHOLD_SETUP),
19765 + .bmAttributes = CFI_FEATURE_ATTR_RW,
19766 + .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
19769 + /* FT_ID_DFIFO_DEPTH */
19771 + .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DFIFO_DEPTH),
19772 + .bmAttributes = CFI_FEATURE_ATTR_RO,
19773 + .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
19776 + /* FT_ID_TX_FIFO_DEPTH */
19778 + .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_TX_FIFO_DEPTH),
19779 + .bmAttributes = CFI_FEATURE_ATTR_RW,
19780 + .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
19783 + /* FT_ID_RX_FIFO_DEPTH */
19785 + .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_RX_FIFO_DEPTH),
19786 + .bmAttributes = CFI_FEATURE_ATTR_RW,
19787 + .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
19791 +/** The table of feature names */
19792 +cfi_string_t prop_name_table[] = {
19793 + {FT_ID_DMA_MODE, "dma_mode"},
19794 + {FT_ID_DMA_BUFFER_SETUP, "buffer_setup"},
19795 + {FT_ID_DMA_BUFF_ALIGN, "buffer_align"},
19796 + {FT_ID_DMA_CONCAT_SETUP, "concat_setup"},
19797 + {FT_ID_DMA_CIRCULAR, "buffer_circular"},
19798 + {FT_ID_THRESHOLD_SETUP, "threshold_setup"},
19799 + {FT_ID_DFIFO_DEPTH, "dfifo_depth"},
19800 + {FT_ID_TX_FIFO_DEPTH, "txfifo_depth"},
19801 + {FT_ID_RX_FIFO_DEPTH, "rxfifo_depth"},
19805 +/************************************************************************/
19808 + * Returns the name of the feature by its ID
19809 + * or NULL if no featute ID matches.
19812 +const uint8_t *get_prop_name(uint16_t prop_id, int *len)
19814 + cfi_string_t *pstr;
19817 + for (pstr = prop_name_table; pstr && pstr->s; pstr++) {
19818 + if (pstr->id == prop_id) {
19819 + *len = DWC_STRLEN(pstr->s);
19827 + * This function handles all CFI specific control requests.
19829 + * Return a negative value to stall the DCE.
19831 +int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl)
19834 + dwc_otg_pcd_ep_t *ep = NULL;
19835 + cfiobject_t *cfi = pcd->cfi;
19836 + struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd);
19837 + uint16_t wLen = DWC_LE16_TO_CPU(&ctrl->wLength);
19838 + uint16_t wValue = DWC_LE16_TO_CPU(&ctrl->wValue);
19839 + uint16_t wIndex = DWC_LE16_TO_CPU(&ctrl->wIndex);
19840 + uint32_t regaddr = 0;
19841 + uint32_t regval = 0;
19843 + /* Save this Control Request in the CFI object.
19844 + * The data field will be assigned in the data stage completion CB function.
19846 + cfi->ctrl_req = *ctrl;
19847 + cfi->ctrl_req.data = NULL;
19849 + cfi->need_gadget_att = 0;
19850 + cfi->need_status_in_complete = 0;
19852 + switch (ctrl->bRequest) {
19853 + case VEN_CORE_GET_FEATURES:
19854 + retval = cfi_core_features_buf(cfi->buf_in.buf, CFI_IN_BUF_LEN);
19855 + if (retval >= 0) {
19856 + //dump_msg(cfi->buf_in.buf, retval);
19859 + retval = min((uint16_t) retval, wLen);
19860 + /* Transfer this buffer to the host through the EP0-IN EP */
19861 + ep->dwc_ep.dma_addr = cfi->buf_in.addr;
19862 + ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
19863 + ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
19864 + ep->dwc_ep.xfer_len = retval;
19865 + ep->dwc_ep.xfer_count = 0;
19866 + ep->dwc_ep.sent_zlp = 0;
19867 + ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
19869 + pcd->ep0_pending = 1;
19870 + dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
19875 + case VEN_CORE_GET_FEATURE:
19876 + CFI_INFO("VEN_CORE_GET_FEATURE\n");
19877 + retval = cfi_get_feature_value(cfi->buf_in.buf, CFI_IN_BUF_LEN,
19879 + if (retval >= 0) {
19882 + retval = min((uint16_t) retval, wLen);
19883 + /* Transfer this buffer to the host through the EP0-IN EP */
19884 + ep->dwc_ep.dma_addr = cfi->buf_in.addr;
19885 + ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
19886 + ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
19887 + ep->dwc_ep.xfer_len = retval;
19888 + ep->dwc_ep.xfer_count = 0;
19889 + ep->dwc_ep.sent_zlp = 0;
19890 + ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
19892 + pcd->ep0_pending = 1;
19893 + dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
19895 + CFI_INFO("VEN_CORE_GET_FEATURE=%d\n", retval);
19896 + dump_msg(cfi->buf_in.buf, retval);
19899 + case VEN_CORE_SET_FEATURE:
19900 + CFI_INFO("VEN_CORE_SET_FEATURE\n");
19901 + /* Set up an XFER to get the data stage of the control request,
19902 + * which is the new value of the feature to be modified.
19905 + ep->dwc_ep.is_in = 0;
19906 + ep->dwc_ep.dma_addr = cfi->buf_out.addr;
19907 + ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf;
19908 + ep->dwc_ep.xfer_buff = cfi->buf_out.buf;
19909 + ep->dwc_ep.xfer_len = wLen;
19910 + ep->dwc_ep.xfer_count = 0;
19911 + ep->dwc_ep.sent_zlp = 0;
19912 + ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
19914 + pcd->ep0_pending = 1;
19915 + /* Read the control write's data stage */
19916 + dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
19920 + case VEN_CORE_RESET_FEATURES:
19921 + CFI_INFO("VEN_CORE_RESET_FEATURES\n");
19922 + cfi->need_gadget_att = 1;
19923 + cfi->need_status_in_complete = 1;
19924 + retval = cfi_preproc_reset(pcd, ctrl);
19925 + CFI_INFO("VEN_CORE_RESET_FEATURES = (%d)\n", retval);
19928 + case VEN_CORE_ACTIVATE_FEATURES:
19929 + CFI_INFO("VEN_CORE_ACTIVATE_FEATURES\n");
19932 + case VEN_CORE_READ_REGISTER:
19933 + CFI_INFO("VEN_CORE_READ_REGISTER\n");
19934 + /* wValue optionally contains the HI WORD of the register offset and
19935 + * wIndex contains the LOW WORD of the register offset
19937 + if (wValue == 0) {
19938 + /* @TODO - MAS - fix the access to the base field */
19940 + //regaddr = (uint32_t) pcd->otg_dev->os_dep.base;
19941 + //GET_CORE_IF(pcd)->co
19942 + regaddr |= wIndex;
19944 + regaddr = (wValue << 16) | wIndex;
19947 + /* Read a 32-bit value of the memory at the regaddr */
19948 + regval = DWC_READ_REG32((uint32_t *) regaddr);
19951 + dwc_memcpy(cfi->buf_in.buf, ®val, sizeof(uint32_t));
19952 + ep->dwc_ep.is_in = 1;
19953 + ep->dwc_ep.dma_addr = cfi->buf_in.addr;
19954 + ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
19955 + ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
19956 + ep->dwc_ep.xfer_len = wLen;
19957 + ep->dwc_ep.xfer_count = 0;
19958 + ep->dwc_ep.sent_zlp = 0;
19959 + ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
19961 + pcd->ep0_pending = 1;
19962 + dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
19963 + cfi->need_gadget_att = 0;
19967 + case VEN_CORE_WRITE_REGISTER:
19968 + CFI_INFO("VEN_CORE_WRITE_REGISTER\n");
19969 + /* Set up an XFER to get the data stage of the control request,
19970 + * which is the new value of the register to be modified.
19973 + ep->dwc_ep.is_in = 0;
19974 + ep->dwc_ep.dma_addr = cfi->buf_out.addr;
19975 + ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf;
19976 + ep->dwc_ep.xfer_buff = cfi->buf_out.buf;
19977 + ep->dwc_ep.xfer_len = wLen;
19978 + ep->dwc_ep.xfer_count = 0;
19979 + ep->dwc_ep.sent_zlp = 0;
19980 + ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
19982 + pcd->ep0_pending = 1;
19983 + /* Read the control write's data stage */
19984 + dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
19989 + retval = -DWC_E_NOT_SUPPORTED;
19997 + * This function prepares the core features descriptors and copies its
19998 + * raw representation into the buffer <buf>.
20000 + * The buffer structure is as follows:
20001 + * all_features_header (8 bytes)
20002 + * features_#1 (8 bytes + feature name string length)
20003 + * features_#2 (8 bytes + feature name string length)
20005 + * features_#n - where n=the total count of feature descriptors
20007 +static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen)
20009 + cfi_feature_desc_header_t *prop_hdr = prop_descs;
20010 + cfi_feature_desc_header_t *prop;
20011 + cfi_all_features_header_t *all_props_hdr = &all_props_desc_header;
20012 + cfi_all_features_header_t *tmp;
20013 + uint8_t *tmpbuf = buf;
20014 + const uint8_t *pname = NULL;
20015 + int i, j, namelen = 0, totlen;
20017 + /* Prepare and copy the core features into the buffer */
20018 + CFI_INFO("%s:\n", __func__);
20020 + tmp = (cfi_all_features_header_t *) tmpbuf;
20021 + *tmp = *all_props_hdr;
20022 + tmpbuf += CFI_ALL_FEATURES_HDR_LEN;
20024 + j = sizeof(prop_descs) / sizeof(cfi_all_features_header_t);
20025 + for (i = 0; i < j; i++, prop_hdr++) {
20026 + pname = get_prop_name(prop_hdr->wFeatureID, &namelen);
20027 + prop = (cfi_feature_desc_header_t *) tmpbuf;
20028 + *prop = *prop_hdr;
20030 + prop->bNameLen = namelen;
20032 + DWC_CONSTANT_CPU_TO_LE16(CFI_FEATURE_DESC_HDR_LEN +
20035 + tmpbuf += CFI_FEATURE_DESC_HDR_LEN;
20036 + dwc_memcpy(tmpbuf, pname, namelen);
20037 + tmpbuf += namelen;
20040 + totlen = tmpbuf - buf;
20042 + if (totlen > 0) {
20043 + tmp = (cfi_all_features_header_t *) buf;
20044 + tmp->wTotalLen = DWC_CONSTANT_CPU_TO_LE16(totlen);
20051 + * This function releases all the dynamic memory in the CFI object.
20053 +static void cfi_release(cfiobject_t * cfiobj)
20056 + dwc_list_link_t *tmp;
20058 + CFI_INFO("%s\n", __func__);
20060 + if (cfiobj->buf_in.buf) {
20061 + DWC_DMA_FREE(CFI_IN_BUF_LEN, cfiobj->buf_in.buf,
20062 + cfiobj->buf_in.addr);
20063 + cfiobj->buf_in.buf = NULL;
20066 + if (cfiobj->buf_out.buf) {
20067 + DWC_DMA_FREE(CFI_OUT_BUF_LEN, cfiobj->buf_out.buf,
20068 + cfiobj->buf_out.addr);
20069 + cfiobj->buf_out.buf = NULL;
20072 + /* Free the Buffer Setup values for each EP */
20073 + //list_for_each_entry(cfiep, &cfiobj->active_eps, lh) {
20074 + DWC_LIST_FOREACH(tmp, &cfiobj->active_eps) {
20075 + cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
20076 + cfi_free_ep_bs_dyn_data(cfiep);
20081 + * This function frees the dynamically allocated EP buffer setup data.
20083 +static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep)
20085 + if (cfiep->bm_sg) {
20086 + DWC_FREE(cfiep->bm_sg);
20087 + cfiep->bm_sg = NULL;
20090 + if (cfiep->bm_align) {
20091 + DWC_FREE(cfiep->bm_align);
20092 + cfiep->bm_align = NULL;
20095 + if (cfiep->bm_concat) {
20096 + if (NULL != cfiep->bm_concat->wTxBytes) {
20097 + DWC_FREE(cfiep->bm_concat->wTxBytes);
20098 + cfiep->bm_concat->wTxBytes = NULL;
20100 + DWC_FREE(cfiep->bm_concat);
20101 + cfiep->bm_concat = NULL;
20106 + * This function initializes the default values of the features
20107 + * for a specific endpoint and should be called only once when
20108 + * the EP is enabled first time.
20110 +static int cfi_ep_init_defaults(struct dwc_otg_pcd *pcd, cfi_ep_t * cfiep)
20114 + cfiep->bm_sg = DWC_ALLOC(sizeof(ddma_sg_buffer_setup_t));
20115 + if (NULL == cfiep->bm_sg) {
20116 + CFI_INFO("Failed to allocate memory for SG feature value\n");
20117 + return -DWC_E_NO_MEMORY;
20119 + dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
20121 + /* For the Concatenation feature's default value we do not allocate
20122 + * memory for the wTxBytes field - it will be done in the set_feature_value
20123 + * request handler.
20125 + cfiep->bm_concat = DWC_ALLOC(sizeof(ddma_concat_buffer_setup_t));
20126 + if (NULL == cfiep->bm_concat) {
20128 + ("Failed to allocate memory for CONCATENATION feature value\n");
20129 + DWC_FREE(cfiep->bm_sg);
20130 + return -DWC_E_NO_MEMORY;
20132 + dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t));
20134 + cfiep->bm_align = DWC_ALLOC(sizeof(ddma_align_buffer_setup_t));
20135 + if (NULL == cfiep->bm_align) {
20137 + ("Failed to allocate memory for Alignment feature value\n");
20138 + DWC_FREE(cfiep->bm_sg);
20139 + DWC_FREE(cfiep->bm_concat);
20140 + return -DWC_E_NO_MEMORY;
20142 + dwc_memset(cfiep->bm_align, 0, sizeof(ddma_align_buffer_setup_t));
20148 + * The callback function that notifies the CFI on the activation of
20149 + * an endpoint in the PCD. The following steps are done in this function:
20151 + * Create a dynamically allocated cfi_ep_t object (a CFI wrapper to the PCD's
20152 + * active endpoint)
20153 + * Create MAX_DMA_DESCS_PER_EP count DMA Descriptors for the EP
20154 + * Set the Buffer Mode to standard
20155 + * Initialize the default values for all EP modes (SG, Circular, Concat, Align)
20156 + * Add the cfi_ep_t object to the list of active endpoints in the CFI object
20158 +static int cfi_ep_enable(struct cfiobject *cfi, struct dwc_otg_pcd *pcd,
20159 + struct dwc_otg_pcd_ep *ep)
20162 + int retval = -DWC_E_NOT_SUPPORTED;
20164 + CFI_INFO("%s: epname=%s; epnum=0x%02x\n", __func__,
20165 + "EP_" /*ep->ep.name */ , ep->desc->bEndpointAddress);
20166 + /* MAS - Check whether this endpoint already is in the list */
20167 + cfiep = get_cfi_ep_by_pcd_ep(cfi, ep);
20169 + if (NULL == cfiep) {
20170 + /* Allocate a cfi_ep_t object */
20171 + cfiep = DWC_ALLOC(sizeof(cfi_ep_t));
20172 + if (NULL == cfiep) {
20174 + ("Unable to allocate memory for <cfiep> in function %s\n",
20176 + return -DWC_E_NO_MEMORY;
20178 + dwc_memset(cfiep, 0, sizeof(cfi_ep_t));
20180 + /* Save the dwc_otg_pcd_ep pointer in the cfiep object */
20183 + /* Allocate the DMA Descriptors chain of MAX_DMA_DESCS_PER_EP count */
20184 + ep->dwc_ep.descs =
20185 + DWC_DMA_ALLOC(MAX_DMA_DESCS_PER_EP *
20186 + sizeof(dwc_otg_dma_desc_t),
20187 + &ep->dwc_ep.descs_dma_addr);
20189 + if (NULL == ep->dwc_ep.descs) {
20191 + return -DWC_E_NO_MEMORY;
20194 + DWC_LIST_INIT(&cfiep->lh);
20196 + /* Set the buffer mode to BM_STANDARD. It will be modified
20197 + * when building descriptors for a specific buffer mode */
20198 + ep->dwc_ep.buff_mode = BM_STANDARD;
20200 + /* Create and initialize the default values for this EP's Buffer modes */
20201 + if ((retval = cfi_ep_init_defaults(pcd, cfiep)) < 0)
20204 + /* Add the cfi_ep_t object to the CFI object's list of active endpoints */
20205 + DWC_LIST_INSERT_TAIL(&cfi->active_eps, &cfiep->lh);
20207 + } else { /* The sought EP already is in the list */
20208 + CFI_INFO("%s: The sought EP already is in the list\n",
20216 + * This function is called when the data stage of a 3-stage Control Write request
20220 +static int cfi_ctrl_write_complete(struct cfiobject *cfi,
20221 + struct dwc_otg_pcd *pcd)
20223 + uint32_t addr, reg_value;
20224 + uint16_t wIndex, wValue;
20225 + uint8_t bRequest;
20226 + uint8_t *buf = cfi->buf_out.buf;
20227 + //struct usb_ctrlrequest *ctrl_req = &cfi->ctrl_req_saved;
20228 + struct cfi_usb_ctrlrequest *ctrl_req = &cfi->ctrl_req;
20229 + int retval = -DWC_E_NOT_SUPPORTED;
20231 + CFI_INFO("%s\n", __func__);
20233 + bRequest = ctrl_req->bRequest;
20234 + wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex);
20235 + wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue);
20238 + * Save the pointer to the data stage in the ctrl_req's <data> field.
20239 + * The request should be already saved in the command stage by now.
20241 + ctrl_req->data = cfi->buf_out.buf;
20242 + cfi->need_status_in_complete = 0;
20243 + cfi->need_gadget_att = 0;
20245 + switch (bRequest) {
20246 + case VEN_CORE_WRITE_REGISTER:
20247 + /* The buffer contains raw data of the new value for the register */
20248 + reg_value = *((uint32_t *) buf);
20249 + if (wValue == 0) {
20251 + //addr = (uint32_t) pcd->otg_dev->os_dep.base;
20254 + addr = (wValue << 16) | wIndex;
20257 + //writel(reg_value, addr);
20260 + cfi->need_status_in_complete = 1;
20263 + case VEN_CORE_SET_FEATURE:
20264 + /* The buffer contains raw data of the new value of the feature */
20265 + retval = cfi_set_feature_value(pcd);
20269 + cfi->need_status_in_complete = 1;
20280 + * This function builds the DMA descriptors for the SG buffer mode.
20282 +static void cfi_build_sg_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
20283 + dwc_otg_pcd_request_t * req)
20285 + struct dwc_otg_pcd_ep *ep = cfiep->ep;
20286 + ddma_sg_buffer_setup_t *sgval = cfiep->bm_sg;
20287 + struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
20288 + struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs;
20289 + dma_addr_t buff_addr = req->dma;
20291 + uint32_t txsize, off;
20293 + txsize = sgval->wSize;
20294 + off = sgval->bOffset;
20296 +// CFI_INFO("%s: %s TXSIZE=0x%08x; OFFSET=0x%08x\n",
20297 +// __func__, cfiep->ep->ep.name, txsize, off);
20299 + for (i = 0; i < sgval->bCount; i++) {
20300 + desc->status.b.bs = BS_HOST_BUSY;
20301 + desc->buf = buff_addr;
20302 + desc->status.b.l = 0;
20303 + desc->status.b.ioc = 0;
20304 + desc->status.b.sp = 0;
20305 + desc->status.b.bytes = txsize;
20306 + desc->status.b.bs = BS_HOST_READY;
20308 + /* Set the next address of the buffer */
20309 + buff_addr += txsize + off;
20310 + desc_last = desc;
20314 + /* Set the last, ioc and sp bits on the Last DMA Descriptor */
20315 + desc_last->status.b.l = 1;
20316 + desc_last->status.b.ioc = 1;
20317 + desc_last->status.b.sp = ep->dwc_ep.sent_zlp;
20318 + /* Save the last DMA descriptor pointer */
20319 + cfiep->dma_desc_last = desc_last;
20320 + cfiep->desc_count = sgval->bCount;
20324 + * This function builds the DMA descriptors for the Concatenation buffer mode.
20326 +static void cfi_build_concat_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
20327 + dwc_otg_pcd_request_t * req)
20329 + struct dwc_otg_pcd_ep *ep = cfiep->ep;
20330 + ddma_concat_buffer_setup_t *concatval = cfiep->bm_concat;
20331 + struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
20332 + struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs;
20333 + dma_addr_t buff_addr = req->dma;
20335 + uint16_t *txsize;
20337 + txsize = concatval->wTxBytes;
20339 + for (i = 0; i < concatval->hdr.bDescCount; i++) {
20340 + desc->buf = buff_addr;
20341 + desc->status.b.bs = BS_HOST_BUSY;
20342 + desc->status.b.l = 0;
20343 + desc->status.b.ioc = 0;
20344 + desc->status.b.sp = 0;
20345 + desc->status.b.bytes = *txsize;
20346 + desc->status.b.bs = BS_HOST_READY;
20349 + /* Set the next address of the buffer */
20350 + buff_addr += UGETW(ep->desc->wMaxPacketSize);
20351 + desc_last = desc;
20355 + /* Set the last, ioc and sp bits on the Last DMA Descriptor */
20356 + desc_last->status.b.l = 1;
20357 + desc_last->status.b.ioc = 1;
20358 + desc_last->status.b.sp = ep->dwc_ep.sent_zlp;
20359 + cfiep->dma_desc_last = desc_last;
20360 + cfiep->desc_count = concatval->hdr.bDescCount;
20364 + * This function builds the DMA descriptors for the Circular buffer mode
20366 +static void cfi_build_circ_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
20367 + dwc_otg_pcd_request_t * req)
20369 + /* @todo: MAS - add implementation when this feature needs to be tested */
20373 + * This function builds the DMA descriptors for the Alignment buffer mode
20375 +static void cfi_build_align_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
20376 + dwc_otg_pcd_request_t * req)
20378 + struct dwc_otg_pcd_ep *ep = cfiep->ep;
20379 + ddma_align_buffer_setup_t *alignval = cfiep->bm_align;
20380 + struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
20381 + dma_addr_t buff_addr = req->dma;
20383 + desc->status.b.bs = BS_HOST_BUSY;
20384 + desc->status.b.l = 1;
20385 + desc->status.b.ioc = 1;
20386 + desc->status.b.sp = ep->dwc_ep.sent_zlp;
20387 + desc->status.b.bytes = req->length;
20388 + /* Adjust the buffer alignment */
20389 + desc->buf = (buff_addr + alignval->bAlign);
20390 + desc->status.b.bs = BS_HOST_READY;
20391 + cfiep->dma_desc_last = desc;
20392 + cfiep->desc_count = 1;
20396 + * This function builds the DMA descriptors chain for different modes of the
20397 + * buffer setup of an endpoint.
20399 +static void cfi_build_descriptors(struct cfiobject *cfi,
20400 + struct dwc_otg_pcd *pcd,
20401 + struct dwc_otg_pcd_ep *ep,
20402 + dwc_otg_pcd_request_t * req)
20406 + /* Get the cfiep by the dwc_otg_pcd_ep */
20407 + cfiep = get_cfi_ep_by_pcd_ep(cfi, ep);
20408 + if (NULL == cfiep) {
20409 + CFI_INFO("%s: Unable to find a matching active endpoint\n",
20414 + cfiep->xfer_len = req->length;
20416 + /* Iterate through all the DMA descriptors */
20417 + switch (cfiep->ep->dwc_ep.buff_mode) {
20419 + cfi_build_sg_descs(cfi, cfiep, req);
20423 + cfi_build_concat_descs(cfi, cfiep, req);
20426 + case BM_CIRCULAR:
20427 + cfi_build_circ_descs(cfi, cfiep, req);
20431 + cfi_build_align_descs(cfi, cfiep, req);
20440 + * Allocate DMA buffer for different Buffer modes.
20442 +static void *cfi_ep_alloc_buf(struct cfiobject *cfi, struct dwc_otg_pcd *pcd,
20443 + struct dwc_otg_pcd_ep *ep, dma_addr_t * dma,
20444 + unsigned size, gfp_t flags)
20446 + return DWC_DMA_ALLOC(size, dma);
20450 + * This function initializes the CFI object.
20452 +int init_cfi(cfiobject_t * cfiobj)
20454 + CFI_INFO("%s\n", __func__);
20456 + /* Allocate a buffer for IN XFERs */
20457 + cfiobj->buf_in.buf =
20458 + DWC_DMA_ALLOC(CFI_IN_BUF_LEN, &cfiobj->buf_in.addr);
20459 + if (NULL == cfiobj->buf_in.buf) {
20460 + CFI_INFO("Unable to allocate buffer for INs\n");
20461 + return -DWC_E_NO_MEMORY;
20464 + /* Allocate a buffer for OUT XFERs */
20465 + cfiobj->buf_out.buf =
20466 + DWC_DMA_ALLOC(CFI_OUT_BUF_LEN, &cfiobj->buf_out.addr);
20467 + if (NULL == cfiobj->buf_out.buf) {
20468 + CFI_INFO("Unable to allocate buffer for OUT\n");
20469 + return -DWC_E_NO_MEMORY;
20472 + /* Initialize the callback function pointers */
20473 + cfiobj->ops.release = cfi_release;
20474 + cfiobj->ops.ep_enable = cfi_ep_enable;
20475 + cfiobj->ops.ctrl_write_complete = cfi_ctrl_write_complete;
20476 + cfiobj->ops.build_descriptors = cfi_build_descriptors;
20477 + cfiobj->ops.ep_alloc_buf = cfi_ep_alloc_buf;
20479 + /* Initialize the list of active endpoints in the CFI object */
20480 + DWC_LIST_INIT(&cfiobj->active_eps);
20486 + * This function reads the required feature's current value into the buffer
20488 + * @retval: Returns negative as error, or the data length of the feature
20490 +static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen,
20491 + struct dwc_otg_pcd *pcd,
20492 + struct cfi_usb_ctrlrequest *ctrl_req)
20494 + int retval = -DWC_E_NOT_SUPPORTED;
20495 + struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd);
20496 + uint16_t dfifo, rxfifo, txfifo;
20498 + switch (ctrl_req->wIndex) {
20499 + /* Whether the DDMA is enabled or not */
20500 + case FT_ID_DMA_MODE:
20501 + *buf = (coreif->dma_enable && coreif->dma_desc_enable) ? 1 : 0;
20505 + case FT_ID_DMA_BUFFER_SETUP:
20506 + retval = cfi_ep_get_sg_val(buf, pcd, ctrl_req);
20509 + case FT_ID_DMA_BUFF_ALIGN:
20510 + retval = cfi_ep_get_align_val(buf, pcd, ctrl_req);
20513 + case FT_ID_DMA_CONCAT_SETUP:
20514 + retval = cfi_ep_get_concat_val(buf, pcd, ctrl_req);
20517 + case FT_ID_DMA_CIRCULAR:
20518 + CFI_INFO("GetFeature value (FT_ID_DMA_CIRCULAR)\n");
20521 + case FT_ID_THRESHOLD_SETUP:
20522 + CFI_INFO("GetFeature value (FT_ID_THRESHOLD_SETUP)\n");
20525 + case FT_ID_DFIFO_DEPTH:
20526 + dfifo = get_dfifo_size(coreif);
20527 + *((uint16_t *) buf) = dfifo;
20528 + retval = sizeof(uint16_t);
20531 + case FT_ID_TX_FIFO_DEPTH:
20532 + retval = get_txfifo_size(pcd, ctrl_req->wValue);
20533 + if (retval >= 0) {
20535 + *((uint16_t *) buf) = txfifo;
20536 + retval = sizeof(uint16_t);
20540 + case FT_ID_RX_FIFO_DEPTH:
20541 + retval = get_rxfifo_size(coreif, ctrl_req->wValue);
20542 + if (retval >= 0) {
20544 + *((uint16_t *) buf) = rxfifo;
20545 + retval = sizeof(uint16_t);
20554 + * This function resets the SG for the specified EP to its default value
20556 +static int cfi_reset_sg_val(cfi_ep_t * cfiep)
20558 + dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
20563 + * This function resets the Alignment for the specified EP to its default value
20565 +static int cfi_reset_align_val(cfi_ep_t * cfiep)
20567 + dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
20572 + * This function resets the Concatenation for the specified EP to its default value
20573 + * This function will also set the value of the wTxBytes field to NULL after
20574 + * freeing the memory previously allocated for this field.
20576 +static int cfi_reset_concat_val(cfi_ep_t * cfiep)
20578 + /* First we need to free the wTxBytes field */
20579 + if (cfiep->bm_concat->wTxBytes) {
20580 + DWC_FREE(cfiep->bm_concat->wTxBytes);
20581 + cfiep->bm_concat->wTxBytes = NULL;
20584 + dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t));
20589 + * This function resets all the buffer setups of the specified endpoint
20591 +static int cfi_ep_reset_all_setup_vals(cfi_ep_t * cfiep)
20593 + cfi_reset_sg_val(cfiep);
20594 + cfi_reset_align_val(cfiep);
20595 + cfi_reset_concat_val(cfiep);
20599 +static int cfi_handle_reset_fifo_val(struct dwc_otg_pcd *pcd, uint8_t ep_addr,
20600 + uint8_t rx_rst, uint8_t tx_rst)
20602 + int retval = -DWC_E_INVALID;
20603 + uint16_t tx_siz[15];
20604 + uint16_t rx_siz = 0;
20605 + dwc_otg_pcd_ep_t *ep = NULL;
20606 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
20607 + dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
20610 + rx_siz = params->dev_rx_fifo_size;
20611 + params->dev_rx_fifo_size = GET_CORE_IF(pcd)->init_rxfsiz;
20615 + if (ep_addr == 0) {
20618 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
20620 + core_if->core_params->dev_tx_fifo_size[i];
20621 + core_if->core_params->dev_tx_fifo_size[i] =
20622 + core_if->init_txfsiz[i];
20626 + ep = get_ep_by_addr(pcd, ep_addr);
20628 + if (NULL == ep) {
20630 + ("%s: Unable to get the endpoint addr=0x%02x\n",
20631 + __func__, ep_addr);
20632 + return -DWC_E_INVALID;
20636 + params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num -
20638 + params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] =
20639 + GET_CORE_IF(pcd)->init_txfsiz[ep->
20640 + dwc_ep.tx_fifo_num -
20645 + if (resize_fifos(GET_CORE_IF(pcd))) {
20649 + ("%s: Error resetting the feature Reset All(FIFO size)\n",
20652 + params->dev_rx_fifo_size = rx_siz;
20656 + if (ep_addr == 0) {
20658 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps;
20661 + core_params->dev_tx_fifo_size[i] =
20665 + params->dev_tx_fifo_size[ep->
20666 + dwc_ep.tx_fifo_num -
20670 + retval = -DWC_E_INVALID;
20675 +static int cfi_handle_reset_all(struct dwc_otg_pcd *pcd, uint8_t addr)
20679 + cfiobject_t *cfi = pcd->cfi;
20680 + dwc_list_link_t *tmp;
20682 + retval = cfi_handle_reset_fifo_val(pcd, addr, 1, 1);
20683 + if (retval < 0) {
20687 + /* If the EP address is known then reset the features for only that EP */
20689 + cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
20690 + if (NULL == cfiep) {
20691 + CFI_INFO("%s: Error getting the EP address 0x%02x\n",
20693 + return -DWC_E_INVALID;
20695 + retval = cfi_ep_reset_all_setup_vals(cfiep);
20696 + cfiep->ep->dwc_ep.buff_mode = BM_STANDARD;
20698 + /* Otherwise (wValue == 0), reset all features of all EP's */
20700 + /* Traverse all the active EP's and reset the feature(s) value(s) */
20701 + //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
20702 + DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
20703 + cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
20704 + retval = cfi_ep_reset_all_setup_vals(cfiep);
20705 + cfiep->ep->dwc_ep.buff_mode = BM_STANDARD;
20706 + if (retval < 0) {
20708 + ("%s: Error resetting the feature Reset All\n",
20717 +static int cfi_handle_reset_dma_buff_setup(struct dwc_otg_pcd *pcd,
20722 + cfiobject_t *cfi = pcd->cfi;
20723 + dwc_list_link_t *tmp;
20725 + /* If the EP address is known then reset the features for only that EP */
20727 + cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
20728 + if (NULL == cfiep) {
20729 + CFI_INFO("%s: Error getting the EP address 0x%02x\n",
20731 + return -DWC_E_INVALID;
20733 + retval = cfi_reset_sg_val(cfiep);
20735 + /* Otherwise (wValue == 0), reset all features of all EP's */
20737 + /* Traverse all the active EP's and reset the feature(s) value(s) */
20738 + //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
20739 + DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
20740 + cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
20741 + retval = cfi_reset_sg_val(cfiep);
20742 + if (retval < 0) {
20744 + ("%s: Error resetting the feature Buffer Setup\n",
20753 +static int cfi_handle_reset_concat_val(struct dwc_otg_pcd *pcd, uint8_t addr)
20757 + cfiobject_t *cfi = pcd->cfi;
20758 + dwc_list_link_t *tmp;
20760 + /* If the EP address is known then reset the features for only that EP */
20762 + cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
20763 + if (NULL == cfiep) {
20764 + CFI_INFO("%s: Error getting the EP address 0x%02x\n",
20766 + return -DWC_E_INVALID;
20768 + retval = cfi_reset_concat_val(cfiep);
20770 + /* Otherwise (wValue == 0), reset all features of all EP's */
20772 + /* Traverse all the active EP's and reset the feature(s) value(s) */
20773 + //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
20774 + DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
20775 + cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
20776 + retval = cfi_reset_concat_val(cfiep);
20777 + if (retval < 0) {
20779 + ("%s: Error resetting the feature Concatenation Value\n",
20788 +static int cfi_handle_reset_align_val(struct dwc_otg_pcd *pcd, uint8_t addr)
20792 + cfiobject_t *cfi = pcd->cfi;
20793 + dwc_list_link_t *tmp;
20795 + /* If the EP address is known then reset the features for only that EP */
20797 + cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
20798 + if (NULL == cfiep) {
20799 + CFI_INFO("%s: Error getting the EP address 0x%02x\n",
20801 + return -DWC_E_INVALID;
20803 + retval = cfi_reset_align_val(cfiep);
20805 + /* Otherwise (wValue == 0), reset all features of all EP's */
20807 + /* Traverse all the active EP's and reset the feature(s) value(s) */
20808 + //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
20809 + DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
20810 + cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
20811 + retval = cfi_reset_align_val(cfiep);
20812 + if (retval < 0) {
20814 + ("%s: Error resetting the feature Aliignment Value\n",
20824 +static int cfi_preproc_reset(struct dwc_otg_pcd *pcd,
20825 + struct cfi_usb_ctrlrequest *req)
20829 + switch (req->wIndex) {
20831 + /* Reset all features */
20832 + retval = cfi_handle_reset_all(pcd, req->wValue & 0xff);
20835 + case FT_ID_DMA_BUFFER_SETUP:
20836 + /* Reset the SG buffer setup */
20838 + cfi_handle_reset_dma_buff_setup(pcd, req->wValue & 0xff);
20841 + case FT_ID_DMA_CONCAT_SETUP:
20842 + /* Reset the Concatenation buffer setup */
20843 + retval = cfi_handle_reset_concat_val(pcd, req->wValue & 0xff);
20846 + case FT_ID_DMA_BUFF_ALIGN:
20847 + /* Reset the Alignment buffer setup */
20848 + retval = cfi_handle_reset_align_val(pcd, req->wValue & 0xff);
20851 + case FT_ID_TX_FIFO_DEPTH:
20853 + cfi_handle_reset_fifo_val(pcd, req->wValue & 0xff, 0, 1);
20854 + pcd->cfi->need_gadget_att = 0;
20857 + case FT_ID_RX_FIFO_DEPTH:
20858 + retval = cfi_handle_reset_fifo_val(pcd, 0, 1, 0);
20859 + pcd->cfi->need_gadget_att = 0;
20868 + * This function sets a new value for the SG buffer setup.
20870 +static int cfi_ep_set_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
20872 + uint8_t inaddr, outaddr;
20873 + cfi_ep_t *epin, *epout;
20874 + ddma_sg_buffer_setup_t *psgval;
20875 + uint32_t desccount, size;
20877 + CFI_INFO("%s\n", __func__);
20879 + psgval = (ddma_sg_buffer_setup_t *) buf;
20880 + desccount = (uint32_t) psgval->bCount;
20881 + size = (uint32_t) psgval->wSize;
20883 + /* Check the DMA descriptor count */
20884 + if ((desccount > MAX_DMA_DESCS_PER_EP) || (desccount == 0)) {
20886 + ("%s: The count of DMA Descriptors should be between 1 and %d\n",
20887 + __func__, MAX_DMA_DESCS_PER_EP);
20888 + return -DWC_E_INVALID;
20891 + /* Check the DMA descriptor count */
20895 + CFI_INFO("%s: The transfer size should be at least 1 byte\n",
20898 + return -DWC_E_INVALID;
20902 + inaddr = psgval->bInEndpointAddress;
20903 + outaddr = psgval->bOutEndpointAddress;
20905 + epin = get_cfi_ep_by_addr(pcd->cfi, inaddr);
20906 + epout = get_cfi_ep_by_addr(pcd->cfi, outaddr);
20908 + if (NULL == epin || NULL == epout) {
20910 + ("%s: Unable to get the endpoints inaddr=0x%02x outaddr=0x%02x\n",
20911 + __func__, inaddr, outaddr);
20912 + return -DWC_E_INVALID;
20915 + epin->ep->dwc_ep.buff_mode = BM_SG;
20916 + dwc_memcpy(epin->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t));
20918 + epout->ep->dwc_ep.buff_mode = BM_SG;
20919 + dwc_memcpy(epout->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t));
20925 + * This function sets a new value for the buffer Alignment setup.
20927 +static int cfi_ep_set_alignment_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
20931 + ddma_align_buffer_setup_t *palignval;
20933 + palignval = (ddma_align_buffer_setup_t *) buf;
20934 + addr = palignval->bEndpointAddress;
20936 + ep = get_cfi_ep_by_addr(pcd->cfi, addr);
20938 + if (NULL == ep) {
20939 + CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
20941 + return -DWC_E_INVALID;
20944 + ep->ep->dwc_ep.buff_mode = BM_ALIGN;
20945 + dwc_memcpy(ep->bm_align, palignval, sizeof(ddma_align_buffer_setup_t));
20951 + * This function sets a new value for the Concatenation buffer setup.
20953 +static int cfi_ep_set_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
20957 + struct _ddma_concat_buffer_setup_hdr *pConcatValHdr;
20959 + uint32_t desccount;
20963 + pConcatValHdr = (struct _ddma_concat_buffer_setup_hdr *)buf;
20964 + desccount = (uint32_t) pConcatValHdr->bDescCount;
20965 + pVals = (uint16_t *) (buf + BS_CONCAT_VAL_HDR_LEN);
20967 + /* Check the DMA descriptor count */
20968 + if (desccount > MAX_DMA_DESCS_PER_EP) {
20969 + CFI_INFO("%s: Maximum DMA Descriptor count should be %d\n",
20970 + __func__, MAX_DMA_DESCS_PER_EP);
20971 + return -DWC_E_INVALID;
20974 + addr = pConcatValHdr->bEndpointAddress;
20975 + ep = get_cfi_ep_by_addr(pcd->cfi, addr);
20976 + if (NULL == ep) {
20977 + CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
20979 + return -DWC_E_INVALID;
20982 + mps = UGETW(ep->ep->desc->wMaxPacketSize);
20985 + for (i = 0; i < desccount; i++) {
20986 + CFI_INFO("%s: wTxSize[%d]=0x%04x\n", __func__, i, pVals[i]);
20988 + CFI_INFO("%s: epname=%s; mps=%d\n", __func__, ep->ep->ep.name, mps);
20991 + /* Check the wTxSizes to be less than or equal to the mps */
20992 + for (i = 0; i < desccount; i++) {
20993 + if (pVals[i] > mps) {
20995 + ("%s: ERROR - the wTxSize[%d] should be <= MPS (wTxSize=%d)\n",
20996 + __func__, i, pVals[i]);
20997 + return -DWC_E_INVALID;
21001 + ep->ep->dwc_ep.buff_mode = BM_CONCAT;
21002 + dwc_memcpy(ep->bm_concat, pConcatValHdr, BS_CONCAT_VAL_HDR_LEN);
21004 + /* Free the previously allocated storage for the wTxBytes */
21005 + if (ep->bm_concat->wTxBytes) {
21006 + DWC_FREE(ep->bm_concat->wTxBytes);
21009 + /* Allocate a new storage for the wTxBytes field */
21010 + ep->bm_concat->wTxBytes =
21011 + DWC_ALLOC(sizeof(uint16_t) * pConcatValHdr->bDescCount);
21012 + if (NULL == ep->bm_concat->wTxBytes) {
21013 + CFI_INFO("%s: Unable to allocate memory\n", __func__);
21014 + return -DWC_E_NO_MEMORY;
21017 + /* Copy the new values into the wTxBytes filed */
21018 + dwc_memcpy(ep->bm_concat->wTxBytes, buf + BS_CONCAT_VAL_HDR_LEN,
21019 + sizeof(uint16_t) * pConcatValHdr->bDescCount);
21025 + * This function calculates the total of all FIFO sizes
21027 + * @param core_if Programming view of DWC_otg controller
21029 + * @return The total of data FIFO sizes.
21032 +static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if)
21034 + dwc_otg_core_params_t *params = core_if->core_params;
21035 + uint16_t dfifo_total = 0;
21038 + /* The shared RxFIFO size */
21040 + params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size;
21042 + /* Add up each TxFIFO size to the total */
21043 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
21044 + dfifo_total += params->dev_tx_fifo_size[i];
21047 + return dfifo_total;
21051 + * This function returns Rx FIFO size
21053 + * @param core_if Programming view of DWC_otg controller
21055 + * @return The total of data FIFO sizes.
21058 +static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue)
21060 + switch (wValue >> 8) {
21062 + return (core_if->pwron_rxfsiz <
21063 + 32768) ? core_if->pwron_rxfsiz : 32768;
21066 + return core_if->core_params->dev_rx_fifo_size;
21069 + return -DWC_E_INVALID;
21075 + * This function returns Tx FIFO size for IN EP
21077 + * @param core_if Programming view of DWC_otg controller
21079 + * @return The total of data FIFO sizes.
21082 +static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue)
21084 + dwc_otg_pcd_ep_t *ep;
21086 + ep = get_ep_by_addr(pcd, wValue & 0xff);
21088 + if (NULL == ep) {
21089 + CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
21090 + __func__, wValue & 0xff);
21091 + return -DWC_E_INVALID;
21094 + if (!ep->dwc_ep.is_in) {
21096 + ("%s: No Tx FIFO assingned to the Out endpoint addr=0x%02x\n",
21097 + __func__, wValue & 0xff);
21098 + return -DWC_E_INVALID;
21101 + switch (wValue >> 8) {
21103 + return (GET_CORE_IF(pcd)->pwron_txfsiz
21104 + [ep->dwc_ep.tx_fifo_num - 1] <
21105 + 768) ? GET_CORE_IF(pcd)->pwron_txfsiz[ep->
21106 + dwc_ep.tx_fifo_num
21110 + return GET_CORE_IF(pcd)->core_params->
21111 + dev_tx_fifo_size[ep->dwc_ep.num - 1];
21114 + return -DWC_E_INVALID;
21120 + * This function checks if the submitted combination of
21121 + * device mode FIFO sizes is possible or not.
21123 + * @param core_if Programming view of DWC_otg controller
21125 + * @return 1 if possible, 0 otherwise.
21128 +static uint8_t check_fifo_sizes(dwc_otg_core_if_t * core_if)
21130 + uint16_t dfifo_actual = 0;
21131 + dwc_otg_core_params_t *params = core_if->core_params;
21132 + uint16_t start_addr = 0;
21136 + params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size;
21138 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
21139 + dfifo_actual += params->dev_tx_fifo_size[i];
21142 + if (dfifo_actual > core_if->total_fifo_size) {
21146 + if (params->dev_rx_fifo_size > 32768 || params->dev_rx_fifo_size < 16)
21149 + if (params->dev_nperio_tx_fifo_size > 32768
21150 + || params->dev_nperio_tx_fifo_size < 16)
21153 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
21155 + if (params->dev_tx_fifo_size[i] > 768
21156 + || params->dev_tx_fifo_size[i] < 4)
21160 + if (params->dev_rx_fifo_size > core_if->pwron_rxfsiz)
21162 + start_addr = params->dev_rx_fifo_size;
21164 + if (params->dev_nperio_tx_fifo_size > core_if->pwron_gnptxfsiz)
21166 + start_addr += params->dev_nperio_tx_fifo_size;
21168 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
21170 + if (params->dev_tx_fifo_size[i] > core_if->pwron_txfsiz[i])
21172 + start_addr += params->dev_tx_fifo_size[i];
21179 + * This function resizes Device mode FIFOs
21181 + * @param core_if Programming view of DWC_otg controller
21183 + * @return 1 if successful, 0 otherwise
21186 +static uint8_t resize_fifos(dwc_otg_core_if_t * core_if)
21189 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
21190 + dwc_otg_core_params_t *params = core_if->core_params;
21191 + uint32_t rx_fifo_size;
21192 + fifosize_data_t nptxfifosize;
21193 + fifosize_data_t txfifosize[15];
21195 + uint32_t rx_fsz_bak;
21196 + uint32_t nptxfsz_bak;
21197 + uint32_t txfsz_bak[15];
21199 + uint16_t start_address;
21200 + uint8_t retval = 1;
21202 + if (!check_fifo_sizes(core_if)) {
21206 + /* Configure data FIFO sizes */
21207 + if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
21208 + rx_fsz_bak = DWC_READ_REG32(&global_regs->grxfsiz);
21209 + rx_fifo_size = params->dev_rx_fifo_size;
21210 + DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size);
21213 + * Tx FIFOs These FIFOs are numbered from 1 to 15.
21214 + * Indexes of the FIFO size module parameters in the
21215 + * dev_tx_fifo_size array and the FIFO size registers in
21216 + * the dtxfsiz array run from 0 to 14.
21219 + /* Non-periodic Tx FIFO */
21220 + nptxfsz_bak = DWC_READ_REG32(&global_regs->gnptxfsiz);
21221 + nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
21222 + start_address = params->dev_rx_fifo_size;
21223 + nptxfifosize.b.startaddr = start_address;
21225 + DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32);
21227 + start_address += nptxfifosize.b.depth;
21229 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
21230 + txfsz_bak[i] = DWC_READ_REG32(&global_regs->dtxfsiz[i]);
21232 + txfifosize[i].b.depth = params->dev_tx_fifo_size[i];
21233 + txfifosize[i].b.startaddr = start_address;
21234 + DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
21235 + txfifosize[i].d32);
21237 + start_address += txfifosize[i].b.depth;
21240 + /** Check if register values are set correctly */
21241 + if (rx_fifo_size != DWC_READ_REG32(&global_regs->grxfsiz)) {
21245 + if (nptxfifosize.d32 != DWC_READ_REG32(&global_regs->gnptxfsiz)) {
21249 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
21250 + if (txfifosize[i].d32 !=
21251 + DWC_READ_REG32(&global_regs->dtxfsiz[i])) {
21256 + /** If register values are not set correctly, reset old values */
21257 + if (retval == 0) {
21258 + DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fsz_bak);
21260 + /* Non-periodic Tx FIFO */
21261 + DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfsz_bak);
21263 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
21264 + DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
21272 + /* Flush the FIFOs */
21273 + dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */
21274 + dwc_otg_flush_rx_fifo(core_if);
21280 + * This function sets a new value for the buffer Alignment setup.
21282 +static int cfi_ep_set_tx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd)
21287 + uint16_t ep_addr;
21288 + dwc_otg_pcd_ep_t *ep;
21289 + dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
21290 + tx_fifo_size_setup_t *ptxfifoval;
21292 + ptxfifoval = (tx_fifo_size_setup_t *) buf;
21293 + ep_addr = ptxfifoval->bEndpointAddress;
21294 + size = ptxfifoval->wDepth;
21296 + ep = get_ep_by_addr(pcd, ep_addr);
21299 + ("%s: Set Tx FIFO size: endpoint addr=0x%02x, depth=%d, FIFO Num=%d\n",
21300 + __func__, ep_addr, size, ep->dwc_ep.tx_fifo_num);
21302 + if (NULL == ep) {
21303 + CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
21304 + __func__, ep_addr);
21305 + return -DWC_E_INVALID;
21308 + fsiz = params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1];
21309 + params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = size;
21311 + if (resize_fifos(GET_CORE_IF(pcd))) {
21315 + ("%s: Error setting the feature Tx FIFO Size for EP%d\n",
21316 + __func__, ep_addr);
21317 + params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = fsiz;
21318 + retval = -DWC_E_INVALID;
21325 + * This function sets a new value for the buffer Alignment setup.
21327 +static int cfi_set_rx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd)
21332 + dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
21333 + rx_fifo_size_setup_t *prxfifoval;
21335 + prxfifoval = (rx_fifo_size_setup_t *) buf;
21336 + size = prxfifoval->wDepth;
21338 + fsiz = params->dev_rx_fifo_size;
21339 + params->dev_rx_fifo_size = size;
21341 + if (resize_fifos(GET_CORE_IF(pcd))) {
21344 + CFI_INFO("%s: Error setting the feature Rx FIFO Size\n",
21346 + params->dev_rx_fifo_size = fsiz;
21347 + retval = -DWC_E_INVALID;
21354 + * This function reads the SG of an EP's buffer setup into the buffer buf
21356 +static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
21357 + struct cfi_usb_ctrlrequest *req)
21359 + int retval = -DWC_E_INVALID;
21363 + /* The Low Byte of the wValue contains a non-zero address of the endpoint */
21364 + addr = req->wValue & 0xFF;
21365 + if (addr == 0) /* The address should be non-zero */
21368 + ep = get_cfi_ep_by_addr(pcd->cfi, addr);
21369 + if (NULL == ep) {
21370 + CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
21375 + dwc_memcpy(buf, ep->bm_sg, BS_SG_VAL_DESC_LEN);
21376 + retval = BS_SG_VAL_DESC_LEN;
21381 + * This function reads the Concatenation value of an EP's buffer mode into
21384 +static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
21385 + struct cfi_usb_ctrlrequest *req)
21387 + int retval = -DWC_E_INVALID;
21390 + uint8_t desc_count;
21392 + /* The Low Byte of the wValue contains a non-zero address of the endpoint */
21393 + addr = req->wValue & 0xFF;
21394 + if (addr == 0) /* The address should be non-zero */
21397 + ep = get_cfi_ep_by_addr(pcd->cfi, addr);
21398 + if (NULL == ep) {
21399 + CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
21404 + /* Copy the header to the buffer */
21405 + dwc_memcpy(buf, ep->bm_concat, BS_CONCAT_VAL_HDR_LEN);
21406 + /* Advance the buffer pointer by the header size */
21407 + buf += BS_CONCAT_VAL_HDR_LEN;
21409 + desc_count = ep->bm_concat->hdr.bDescCount;
21410 + /* Copy alll the wTxBytes to the buffer */
21411 + dwc_memcpy(buf, ep->bm_concat->wTxBytes, sizeof(uid16_t) * desc_count);
21413 + retval = BS_CONCAT_VAL_HDR_LEN + sizeof(uid16_t) * desc_count;
21418 + * This function reads the buffer Alignment value of an EP's buffer mode into
21421 + * @return The total number of bytes copied to the buffer or negative error code.
21423 +static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
21424 + struct cfi_usb_ctrlrequest *req)
21426 + int retval = -DWC_E_INVALID;
21430 + /* The Low Byte of the wValue contains a non-zero address of the endpoint */
21431 + addr = req->wValue & 0xFF;
21432 + if (addr == 0) /* The address should be non-zero */
21435 + ep = get_cfi_ep_by_addr(pcd->cfi, addr);
21436 + if (NULL == ep) {
21437 + CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
21442 + dwc_memcpy(buf, ep->bm_align, BS_ALIGN_VAL_HDR_LEN);
21443 + retval = BS_ALIGN_VAL_HDR_LEN;
21449 + * This function sets a new value for the specified feature
21451 + * @param pcd A pointer to the PCD object
21453 + * @return 0 if successful, negative error code otherwise to stall the DCE.
21455 +static int cfi_set_feature_value(struct dwc_otg_pcd *pcd)
21457 + int retval = -DWC_E_NOT_SUPPORTED;
21458 + uint16_t wIndex, wValue;
21459 + uint8_t bRequest;
21460 + struct dwc_otg_core_if *coreif;
21461 + cfiobject_t *cfi = pcd->cfi;
21462 + struct cfi_usb_ctrlrequest *ctrl_req;
21464 + ctrl_req = &cfi->ctrl_req;
21466 + buf = pcd->cfi->ctrl_req.data;
21468 + coreif = GET_CORE_IF(pcd);
21469 + bRequest = ctrl_req->bRequest;
21470 + wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex);
21471 + wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue);
21473 + /* See which feature is to be modified */
21474 + switch (wIndex) {
21475 + case FT_ID_DMA_BUFFER_SETUP:
21476 + /* Modify the feature */
21477 + if ((retval = cfi_ep_set_sg_val(buf, pcd)) < 0)
21480 + /* And send this request to the gadget */
21481 + cfi->need_gadget_att = 1;
21484 + case FT_ID_DMA_BUFF_ALIGN:
21485 + if ((retval = cfi_ep_set_alignment_val(buf, pcd)) < 0)
21487 + cfi->need_gadget_att = 1;
21490 + case FT_ID_DMA_CONCAT_SETUP:
21491 + /* Modify the feature */
21492 + if ((retval = cfi_ep_set_concat_val(buf, pcd)) < 0)
21494 + cfi->need_gadget_att = 1;
21497 + case FT_ID_DMA_CIRCULAR:
21498 + CFI_INFO("FT_ID_DMA_CIRCULAR\n");
21501 + case FT_ID_THRESHOLD_SETUP:
21502 + CFI_INFO("FT_ID_THRESHOLD_SETUP\n");
21505 + case FT_ID_DFIFO_DEPTH:
21506 + CFI_INFO("FT_ID_DFIFO_DEPTH\n");
21509 + case FT_ID_TX_FIFO_DEPTH:
21510 + CFI_INFO("FT_ID_TX_FIFO_DEPTH\n");
21511 + if ((retval = cfi_ep_set_tx_fifo_val(buf, pcd)) < 0)
21513 + cfi->need_gadget_att = 0;
21516 + case FT_ID_RX_FIFO_DEPTH:
21517 + CFI_INFO("FT_ID_RX_FIFO_DEPTH\n");
21518 + if ((retval = cfi_set_rx_fifo_val(buf, pcd)) < 0)
21520 + cfi->need_gadget_att = 0;
21527 +#endif //DWC_UTE_CFI
21529 +++ b/drivers/usb/host/dwc_otg/dwc_otg_cfi.h
21531 +/* ==========================================================================
21532 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
21533 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
21534 + * otherwise expressly agreed to in writing between Synopsys and you.
21536 + * The Software IS NOT an item of Licensed Software or Licensed Product under
21537 + * any End User Software License Agreement or Agreement for Licensed Product
21538 + * with Synopsys or any supplement thereto. You are permitted to use and
21539 + * redistribute this Software in source and binary forms, with or without
21540 + * modification, provided that redistributions of source code must retain this
21541 + * notice. You may not view, use, disclose, copy or distribute this file or
21542 + * any information contained herein except pursuant to this license grant from
21543 + * Synopsys. If you do not agree with this notice, including the disclaimer
21544 + * below, then you are not authorized to use the Software.
21546 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
21547 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21548 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21549 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
21550 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21551 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21552 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
21553 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21554 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
21555 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
21557 + * ========================================================================== */
21559 +#if !defined(__DWC_OTG_CFI_H__)
21560 +#define __DWC_OTG_CFI_H__
21562 +#include "dwc_otg_pcd.h"
21563 +#include "dwc_cfi_common.h"
21567 + * This file contains the CFI related OTG PCD specific common constants,
21568 + * interfaces(functions and macros) and data structures.The CFI Protocol is an
21569 + * optional interface for internal testing purposes that a DUT may implement to
21570 + * support testing of configurable features.
21574 +struct dwc_otg_pcd;
21575 +struct dwc_otg_pcd_ep;
21577 +/** OTG CFI Features (properties) ID constants */
21578 +/** This is a request for all Core Features */
21579 +#define FT_ID_DMA_MODE 0x0001
21580 +#define FT_ID_DMA_BUFFER_SETUP 0x0002
21581 +#define FT_ID_DMA_BUFF_ALIGN 0x0003
21582 +#define FT_ID_DMA_CONCAT_SETUP 0x0004
21583 +#define FT_ID_DMA_CIRCULAR 0x0005
21584 +#define FT_ID_THRESHOLD_SETUP 0x0006
21585 +#define FT_ID_DFIFO_DEPTH 0x0007
21586 +#define FT_ID_TX_FIFO_DEPTH 0x0008
21587 +#define FT_ID_RX_FIFO_DEPTH 0x0009
21589 +/**********************************************************/
21590 +#define CFI_INFO_DEF
21592 +#ifdef CFI_INFO_DEF
21593 +#define CFI_INFO(fmt...) DWC_PRINTF("CFI: " fmt);
21595 +#define CFI_INFO(fmt...)
21598 +#define min(x,y) ({ \
21599 + x < y ? x : y; })
21601 +#define max(x,y) ({ \
21602 + x > y ? x : y; })
21605 + * Descriptor DMA SG Buffer setup structure (SG buffer). This structure is
21606 + * also used for setting up a buffer for Circular DDMA.
21608 +struct _ddma_sg_buffer_setup {
21609 +#define BS_SG_VAL_DESC_LEN 6
21610 + /* The OUT EP address */
21611 + uint8_t bOutEndpointAddress;
21612 + /* The IN EP address */
21613 + uint8_t bInEndpointAddress;
21614 + /* Number of bytes to put between transfer segments (must be DWORD boundaries) */
21616 + /* The number of transfer segments (a DMA descriptors per each segment) */
21618 + /* Size (in byte) of each transfer segment */
21620 +} __attribute__ ((packed));
21621 +typedef struct _ddma_sg_buffer_setup ddma_sg_buffer_setup_t;
21623 +/** Descriptor DMA Concatenation Buffer setup structure */
21624 +struct _ddma_concat_buffer_setup_hdr {
21625 +#define BS_CONCAT_VAL_HDR_LEN 4
21626 + /* The endpoint for which the buffer is to be set up */
21627 + uint8_t bEndpointAddress;
21628 + /* The count of descriptors to be used */
21629 + uint8_t bDescCount;
21630 + /* The total size of the transfer */
21632 +} __attribute__ ((packed));
21633 +typedef struct _ddma_concat_buffer_setup_hdr ddma_concat_buffer_setup_hdr_t;
21635 +/** Descriptor DMA Concatenation Buffer setup structure */
21636 +struct _ddma_concat_buffer_setup {
21637 + /* The SG header */
21638 + ddma_concat_buffer_setup_hdr_t hdr;
21640 + /* The XFER sizes pointer (allocated dynamically) */
21641 + uint16_t *wTxBytes;
21642 +} __attribute__ ((packed));
21643 +typedef struct _ddma_concat_buffer_setup ddma_concat_buffer_setup_t;
21645 +/** Descriptor DMA Alignment Buffer setup structure */
21646 +struct _ddma_align_buffer_setup {
21647 +#define BS_ALIGN_VAL_HDR_LEN 2
21648 + uint8_t bEndpointAddress;
21650 +} __attribute__ ((packed));
21651 +typedef struct _ddma_align_buffer_setup ddma_align_buffer_setup_t;
21653 +/** Transmit FIFO Size setup structure */
21654 +struct _tx_fifo_size_setup {
21655 + uint8_t bEndpointAddress;
21657 +} __attribute__ ((packed));
21658 +typedef struct _tx_fifo_size_setup tx_fifo_size_setup_t;
21660 +/** Transmit FIFO Size setup structure */
21661 +struct _rx_fifo_size_setup {
21663 +} __attribute__ ((packed));
21664 +typedef struct _rx_fifo_size_setup rx_fifo_size_setup_t;
21667 + * struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest
21668 + * This structure encapsulates the standard usb_ctrlrequest and adds a pointer
21669 + * to the data returned in the data stage of a 3-stage Control Write requests.
21671 +struct cfi_usb_ctrlrequest {
21672 + uint8_t bRequestType;
21673 + uint8_t bRequest;
21676 + uint16_t wLength;
21680 +/*---------------------------------------------------------------------------*/
21683 + * The CFI wrapper of the enabled and activated dwc_otg_pcd_ep structures.
21684 + * This structure is used to store the buffer setup data for any
21685 + * enabled endpoint in the PCD.
21688 + /* Entry for the list container */
21689 + dwc_list_link_t lh;
21690 + /* Pointer to the active PCD endpoint structure */
21691 + struct dwc_otg_pcd_ep *ep;
21692 + /* The last descriptor in the chain of DMA descriptors of the endpoint */
21693 + struct dwc_otg_dma_desc *dma_desc_last;
21694 + /* The SG feature value */
21695 + ddma_sg_buffer_setup_t *bm_sg;
21696 + /* The Circular feature value */
21697 + ddma_sg_buffer_setup_t *bm_circ;
21698 + /* The Concatenation feature value */
21699 + ddma_concat_buffer_setup_t *bm_concat;
21700 + /* The Alignment feature value */
21701 + ddma_align_buffer_setup_t *bm_align;
21702 + /* XFER length */
21703 + uint32_t xfer_len;
21705 + * Count of DMA descriptors currently used.
21706 + * The total should not exceed the MAX_DMA_DESCS_PER_EP value
21707 + * defined in the dwc_otg_cil.h
21709 + uint32_t desc_count;
21711 +typedef struct cfi_ep cfi_ep_t;
21713 +typedef struct cfi_dma_buff {
21714 +#define CFI_IN_BUF_LEN 1024
21715 +#define CFI_OUT_BUF_LEN 1024
21723 + * This is the interface for the CFI operations.
21725 + * @param ep_enable Called when any endpoint is enabled and activated.
21726 + * @param release Called when the CFI object is released and it needs to correctly
21727 + * deallocate the dynamic memory
21728 + * @param ctrl_write_complete Called when the data stage of the request is complete
21730 +typedef struct cfi_ops {
21731 + int (*ep_enable) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd,
21732 + struct dwc_otg_pcd_ep * ep);
21733 + void *(*ep_alloc_buf) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd,
21734 + struct dwc_otg_pcd_ep * ep, dma_addr_t * dma,
21735 + unsigned size, gfp_t flags);
21736 + void (*release) (struct cfiobject * cfi);
21737 + int (*ctrl_write_complete) (struct cfiobject * cfi,
21738 + struct dwc_otg_pcd * pcd);
21739 + void (*build_descriptors) (struct cfiobject * cfi,
21740 + struct dwc_otg_pcd * pcd,
21741 + struct dwc_otg_pcd_ep * ep,
21742 + dwc_otg_pcd_request_t * req);
21745 +struct cfiobject {
21747 + struct dwc_otg_pcd *pcd;
21748 + struct usb_gadget *gadget;
21750 + /* Buffers used to send/receive CFI-related request data */
21751 + cfi_dma_buff_t buf_in;
21752 + cfi_dma_buff_t buf_out;
21754 + /* CFI specific Control request wrapper */
21755 + struct cfi_usb_ctrlrequest ctrl_req;
21757 + /* The list of active EP's in the PCD of type cfi_ep_t */
21758 + dwc_list_link_t active_eps;
21760 + /* This flag shall control the propagation of a specific request
21761 + * to the gadget's processing routines.
21762 + * 0 - no gadget handling
21763 + * 1 - the gadget needs to know about this request (w/o completing a status
21764 + * phase - just return a 0 to the _setup callback)
21766 + uint8_t need_gadget_att;
21768 + /* Flag indicating whether the status IN phase needs to be
21769 + * completed by the PCD
21771 + uint8_t need_status_in_complete;
21773 +typedef struct cfiobject cfiobject_t;
21777 +#if defined(DUMP_MSG)
21778 +static inline void dump_msg(const u8 * buf, unsigned int length)
21780 + unsigned int start, num, i;
21781 + char line[52], *p;
21783 + if (length >= 512)
21787 + while (length > 0) {
21788 + num = min(length, 16u);
21790 + for (i = 0; i < num; ++i) {
21793 + DWC_SPRINTF(p, " %02x", buf[i]);
21797 + DWC_DEBUG("%6x: %s\n", start, line);
21804 +static inline void dump_msg(const u8 * buf, unsigned int length)
21810 + * This function returns a pointer to cfi_ep_t object with the addr address.
21812 +static inline struct cfi_ep *get_cfi_ep_by_addr(struct cfiobject *cfi,
21815 + struct cfi_ep *pcfiep;
21816 + dwc_list_link_t *tmp;
21818 + DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
21819 + pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
21821 + if (pcfiep->ep->desc->bEndpointAddress == addr) {
21830 + * This function returns a pointer to cfi_ep_t object that matches
21831 + * the dwc_otg_pcd_ep object.
21833 +static inline struct cfi_ep *get_cfi_ep_by_pcd_ep(struct cfiobject *cfi,
21834 + struct dwc_otg_pcd_ep *ep)
21836 + struct cfi_ep *pcfiep = NULL;
21837 + dwc_list_link_t *tmp;
21839 + DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
21840 + pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
21841 + if (pcfiep->ep == ep) {
21848 +int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl);
21850 +#endif /* (__DWC_OTG_CFI_H__) */
21852 +++ b/drivers/usb/host/dwc_otg/dwc_otg_cil.c
21854 +/* ==========================================================================
21855 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $
21856 + * $Revision: #191 $
21857 + * $Date: 2012/08/10 $
21858 + * $Change: 2047372 $
21860 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
21861 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
21862 + * otherwise expressly agreed to in writing between Synopsys and you.
21864 + * The Software IS NOT an item of Licensed Software or Licensed Product under
21865 + * any End User Software License Agreement or Agreement for Licensed Product
21866 + * with Synopsys or any supplement thereto. You are permitted to use and
21867 + * redistribute this Software in source and binary forms, with or without
21868 + * modification, provided that redistributions of source code must retain this
21869 + * notice. You may not view, use, disclose, copy or distribute this file or
21870 + * any information contained herein except pursuant to this license grant from
21871 + * Synopsys. If you do not agree with this notice, including the disclaimer
21872 + * below, then you are not authorized to use the Software.
21874 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
21875 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21876 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21877 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
21878 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21879 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21880 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
21881 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21882 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
21883 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
21885 + * ========================================================================== */
21889 + * The Core Interface Layer provides basic services for accessing and
21890 + * managing the DWC_otg hardware. These services are used by both the
21891 + * Host Controller Driver and the Peripheral Controller Driver.
21893 + * The CIL manages the memory map for the core so that the HCD and PCD
21894 + * don't have to do this separately. It also handles basic tasks like
21895 + * reading/writing the registers and data FIFOs in the controller.
21896 + * Some of the data access functions provide encapsulation of several
21897 + * operations required to perform a task, such as writing multiple
21898 + * registers to start a transfer. Finally, the CIL performs basic
21899 + * services that are not specific to either the host or device modes
21900 + * of operation. These services include management of the OTG Host
21901 + * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A
21902 + * Diagnostic API is also provided to allow testing of the controller
21905 + * The Core Interface Layer has the following requirements:
21906 + * - Provides basic controller operations.
21907 + * - Minimal use of OS services.
21908 + * - The OS services used will be abstracted by using inline functions
21913 +#include "dwc_os.h"
21914 +#include "dwc_otg_regs.h"
21915 +#include "dwc_otg_cil.h"
21917 +extern bool cil_force_host;
21919 +static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if);
21922 + * This function is called to initialize the DWC_otg CSR data
21923 + * structures. The register addresses in the device and host
21924 + * structures are initialized from the base address supplied by the
21925 + * caller. The calling function must make the OS calls to get the
21926 + * base address of the DWC_otg controller registers. The core_params
21927 + * argument holds the parameters that specify how the core should be
21930 + * @param reg_base_addr Base address of DWC_otg core registers
21933 +dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * reg_base_addr)
21935 + dwc_otg_core_if_t *core_if = 0;
21936 + dwc_otg_dev_if_t *dev_if = 0;
21937 + dwc_otg_host_if_t *host_if = 0;
21938 + uint8_t *reg_base = (uint8_t *) reg_base_addr;
21941 + DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, reg_base_addr);
21943 + core_if = DWC_ALLOC(sizeof(dwc_otg_core_if_t));
21945 + if (core_if == NULL) {
21946 + DWC_DEBUGPL(DBG_CIL,
21947 + "Allocation of dwc_otg_core_if_t failed\n");
21950 + core_if->core_global_regs = (dwc_otg_core_global_regs_t *) reg_base;
21953 + * Allocate the Device Mode structures.
21955 + dev_if = DWC_ALLOC(sizeof(dwc_otg_dev_if_t));
21957 + if (dev_if == NULL) {
21958 + DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n");
21959 + DWC_FREE(core_if);
21963 + dev_if->dev_global_regs =
21964 + (dwc_otg_device_global_regs_t *) (reg_base +
21965 + DWC_DEV_GLOBAL_REG_OFFSET);
21967 + for (i = 0; i < MAX_EPS_CHANNELS; i++) {
21968 + dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *)
21969 + (reg_base + DWC_DEV_IN_EP_REG_OFFSET +
21970 + (i * DWC_EP_REG_OFFSET));
21972 + dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *)
21973 + (reg_base + DWC_DEV_OUT_EP_REG_OFFSET +
21974 + (i * DWC_EP_REG_OFFSET));
21975 + DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n",
21976 + i, &dev_if->in_ep_regs[i]->diepctl);
21977 + DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n",
21978 + i, &dev_if->out_ep_regs[i]->doepctl);
21981 + dev_if->speed = 0; // unknown
21983 + core_if->dev_if = dev_if;
21986 + * Allocate the Host Mode structures.
21988 + host_if = DWC_ALLOC(sizeof(dwc_otg_host_if_t));
21990 + if (host_if == NULL) {
21991 + DWC_DEBUGPL(DBG_CIL,
21992 + "Allocation of dwc_otg_host_if_t failed\n");
21993 + DWC_FREE(dev_if);
21994 + DWC_FREE(core_if);
21998 + host_if->host_global_regs = (dwc_otg_host_global_regs_t *)
21999 + (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET);
22002 + (uint32_t *) (reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET);
22004 + for (i = 0; i < MAX_EPS_CHANNELS; i++) {
22005 + host_if->hc_regs[i] = (dwc_otg_hc_regs_t *)
22006 + (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET +
22007 + (i * DWC_OTG_CHAN_REGS_OFFSET));
22008 + DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n",
22009 + i, &host_if->hc_regs[i]->hcchar);
22012 + host_if->num_host_channels = MAX_EPS_CHANNELS;
22013 + core_if->host_if = host_if;
22015 + for (i = 0; i < MAX_EPS_CHANNELS; i++) {
22016 + core_if->data_fifo[i] =
22017 + (uint32_t *) (reg_base + DWC_OTG_DATA_FIFO_OFFSET +
22018 + (i * DWC_OTG_DATA_FIFO_SIZE));
22019 + DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08lx\n",
22020 + i, (unsigned long)core_if->data_fifo[i]);
22023 + core_if->pcgcctl = (uint32_t *) (reg_base + DWC_OTG_PCGCCTL_OFFSET);
22025 + /* Initiate lx_state to L3 disconnected state */
22026 + core_if->lx_state = DWC_OTG_L3;
22028 + * Store the contents of the hardware configuration registers here for
22029 + * easy access later.
22031 + core_if->hwcfg1.d32 =
22032 + DWC_READ_REG32(&core_if->core_global_regs->ghwcfg1);
22033 + core_if->hwcfg2.d32 =
22034 + DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);
22035 + core_if->hwcfg3.d32 =
22036 + DWC_READ_REG32(&core_if->core_global_regs->ghwcfg3);
22037 + core_if->hwcfg4.d32 =
22038 + DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4);
22040 + /* Force host mode to get HPTXFSIZ exact power on value */
22042 + gusbcfg_data_t gusbcfg = {.d32 = 0 };
22043 + gusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
22044 + gusbcfg.b.force_host_mode = 1;
22045 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
22047 + core_if->hptxfsiz.d32 =
22048 + DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
22049 + gusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
22050 + if (cil_force_host)
22051 + gusbcfg.b.force_host_mode = 1;
22053 + gusbcfg.b.force_host_mode = 0;
22054 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
22058 + DWC_DEBUGPL(DBG_CILV, "hwcfg1=%08x\n", core_if->hwcfg1.d32);
22059 + DWC_DEBUGPL(DBG_CILV, "hwcfg2=%08x\n", core_if->hwcfg2.d32);
22060 + DWC_DEBUGPL(DBG_CILV, "hwcfg3=%08x\n", core_if->hwcfg3.d32);
22061 + DWC_DEBUGPL(DBG_CILV, "hwcfg4=%08x\n", core_if->hwcfg4.d32);
22063 + core_if->hcfg.d32 =
22064 + DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
22065 + core_if->dcfg.d32 =
22066 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
22068 + DWC_DEBUGPL(DBG_CILV, "hcfg=%08x\n", core_if->hcfg.d32);
22069 + DWC_DEBUGPL(DBG_CILV, "dcfg=%08x\n", core_if->dcfg.d32);
22071 + DWC_DEBUGPL(DBG_CILV, "op_mode=%0x\n", core_if->hwcfg2.b.op_mode);
22072 + DWC_DEBUGPL(DBG_CILV, "arch=%0x\n", core_if->hwcfg2.b.architecture);
22073 + DWC_DEBUGPL(DBG_CILV, "num_dev_ep=%d\n", core_if->hwcfg2.b.num_dev_ep);
22074 + DWC_DEBUGPL(DBG_CILV, "num_host_chan=%d\n",
22075 + core_if->hwcfg2.b.num_host_chan);
22076 + DWC_DEBUGPL(DBG_CILV, "nonperio_tx_q_depth=0x%0x\n",
22077 + core_if->hwcfg2.b.nonperio_tx_q_depth);
22078 + DWC_DEBUGPL(DBG_CILV, "host_perio_tx_q_depth=0x%0x\n",
22079 + core_if->hwcfg2.b.host_perio_tx_q_depth);
22080 + DWC_DEBUGPL(DBG_CILV, "dev_token_q_depth=0x%0x\n",
22081 + core_if->hwcfg2.b.dev_token_q_depth);
22083 + DWC_DEBUGPL(DBG_CILV, "Total FIFO SZ=%d\n",
22084 + core_if->hwcfg3.b.dfifo_depth);
22085 + DWC_DEBUGPL(DBG_CILV, "xfer_size_cntr_width=%0x\n",
22086 + core_if->hwcfg3.b.xfer_size_cntr_width);
22089 + * Set the SRP sucess bit for FS-I2c
22091 + core_if->srp_success = 0;
22092 + core_if->srp_timer_started = 0;
22095 + * Create new workqueue and init works
22097 + core_if->wq_otg = DWC_WORKQ_ALLOC("dwc_otg");
22098 + if (core_if->wq_otg == 0) {
22099 + DWC_WARN("DWC_WORKQ_ALLOC failed\n");
22100 + DWC_FREE(host_if);
22101 + DWC_FREE(dev_if);
22102 + DWC_FREE(core_if);
22106 + core_if->snpsid = DWC_READ_REG32(&core_if->core_global_regs->gsnpsid);
22108 + DWC_PRINTF("Core Release: %x.%x%x%x\n",
22109 + (core_if->snpsid >> 12 & 0xF),
22110 + (core_if->snpsid >> 8 & 0xF),
22111 + (core_if->snpsid >> 4 & 0xF), (core_if->snpsid & 0xF));
22113 + core_if->wkp_timer = DWC_TIMER_ALLOC("Wake Up Timer",
22114 + w_wakeup_detected, core_if);
22115 + if (core_if->wkp_timer == 0) {
22116 + DWC_WARN("DWC_TIMER_ALLOC failed\n");
22117 + DWC_FREE(host_if);
22118 + DWC_FREE(dev_if);
22119 + DWC_WORKQ_FREE(core_if->wq_otg);
22120 + DWC_FREE(core_if);
22124 + if (dwc_otg_setup_params(core_if)) {
22125 + DWC_WARN("Error while setting core params\n");
22128 + core_if->hibernation_suspend = 0;
22130 + /** ADP initialization */
22131 + dwc_otg_adp_init(core_if);
22137 + * This function frees the structures allocated by dwc_otg_cil_init().
22139 + * @param core_if The core interface pointer returned from
22140 + * dwc_otg_cil_init().
22143 +void dwc_otg_cil_remove(dwc_otg_core_if_t * core_if)
22145 + dctl_data_t dctl = {.d32 = 0 };
22146 + DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if);
22148 + /* Disable all interrupts */
22149 + DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 1, 0);
22150 + DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0);
22152 + dctl.b.sftdiscon = 1;
22153 + if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
22154 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0,
22158 + if (core_if->wq_otg) {
22159 + DWC_WORKQ_WAIT_WORK_DONE(core_if->wq_otg, 500);
22160 + DWC_WORKQ_FREE(core_if->wq_otg);
22162 + if (core_if->dev_if) {
22163 + DWC_FREE(core_if->dev_if);
22165 + if (core_if->host_if) {
22166 + DWC_FREE(core_if->host_if);
22169 + /** Remove ADP Stuff */
22170 + dwc_otg_adp_remove(core_if);
22171 + if (core_if->core_params) {
22172 + DWC_FREE(core_if->core_params);
22174 + if (core_if->wkp_timer) {
22175 + DWC_TIMER_FREE(core_if->wkp_timer);
22177 + if (core_if->srp_timer) {
22178 + DWC_TIMER_FREE(core_if->srp_timer);
22180 + DWC_FREE(core_if);
22184 + * This function enables the controller's Global Interrupt in the AHB Config
22187 + * @param core_if Programming view of DWC_otg controller.
22189 +void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * core_if)
22191 + gahbcfg_data_t ahbcfg = {.d32 = 0 };
22192 + ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
22193 + DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32);
22197 + * This function disables the controller's Global Interrupt in the AHB Config
22200 + * @param core_if Programming view of DWC_otg controller.
22202 +void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * core_if)
22204 + gahbcfg_data_t ahbcfg = {.d32 = 0 };
22205 + ahbcfg.b.glblintrmsk = 1; /* Disable interrupts */
22206 + DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
22210 + * This function initializes the commmon interrupts, used in both
22211 + * device and host modes.
22213 + * @param core_if Programming view of the DWC_otg controller
22216 +static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t * core_if)
22218 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
22219 + gintmsk_data_t intr_mask = {.d32 = 0 };
22221 + /* Clear any pending OTG Interrupts */
22222 + DWC_WRITE_REG32(&global_regs->gotgint, 0xFFFFFFFF);
22224 + /* Clear any pending interrupts */
22225 + DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
22228 + * Enable the interrupts in the GINTMSK.
22230 + intr_mask.b.modemismatch = 1;
22231 + intr_mask.b.otgintr = 1;
22233 + if (!core_if->dma_enable) {
22234 + intr_mask.b.rxstsqlvl = 1;
22237 + intr_mask.b.conidstschng = 1;
22238 + intr_mask.b.wkupintr = 1;
22239 + intr_mask.b.disconnect = 0;
22240 + intr_mask.b.usbsuspend = 1;
22241 + intr_mask.b.sessreqintr = 1;
22242 +#ifdef CONFIG_USB_DWC_OTG_LPM
22243 + if (core_if->core_params->lpm_enable) {
22244 + intr_mask.b.lpmtranrcvd = 1;
22247 + DWC_WRITE_REG32(&global_regs->gintmsk, intr_mask.d32);
22251 + * The restore operation is modified to support Synopsys Emulated Powerdown and
22252 + * Hibernation. This function is for exiting from Device mode hibernation by
22253 + * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
22254 + * @param core_if Programming view of DWC_otg controller.
22255 + * @param rem_wakeup - indicates whether resume is initiated by Device or Host.
22256 + * @param reset - indicates whether resume is initiated by Reset.
22258 +int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
22259 + int rem_wakeup, int reset)
22261 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
22262 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
22263 + dctl_data_t dctl = {.d32 = 0 };
22265 + int timeout = 2000;
22267 + if (!core_if->hibernation_suspend) {
22268 + DWC_PRINTF("Already exited from Hibernation\n");
22272 + DWC_DEBUGPL(DBG_PCD, "%s called\n", __FUNCTION__);
22273 + /* Switch-on voltage to the core */
22274 + gpwrdn.b.pwrdnswtch = 1;
22275 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22280 + gpwrdn.b.pwrdnrstn = 1;
22281 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22284 + /* Assert Restore signal */
22286 + gpwrdn.b.restore = 1;
22287 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
22290 + /* Disable power clamps */
22292 + gpwrdn.b.pwrdnclmp = 1;
22293 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22295 + if (rem_wakeup) {
22299 + /* Deassert Reset core */
22301 + gpwrdn.b.pwrdnrstn = 1;
22302 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
22305 + /* Disable PMU interrupt */
22307 + gpwrdn.b.pmuintsel = 1;
22308 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22310 + /* Mask interrupts from gpwrdn */
22312 + gpwrdn.b.connect_det_msk = 1;
22313 + gpwrdn.b.srp_det_msk = 1;
22314 + gpwrdn.b.disconn_det_msk = 1;
22315 + gpwrdn.b.rst_det_msk = 1;
22316 + gpwrdn.b.lnstchng_msk = 1;
22317 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22319 + /* Indicates that we are going out from hibernation */
22320 + core_if->hibernation_suspend = 0;
22323 + * Set Restore Essential Regs bit in PCGCCTL register, restore_mode = 1
22324 + * indicates restore from remote_wakeup
22326 + restore_essential_regs(core_if, rem_wakeup, 0);
22329 + * Wait a little for seeing new value of variable hibernation_suspend if
22330 + * Restore done interrupt received before polling
22334 + if (core_if->hibernation_suspend == 0) {
22336 + * Wait For Restore_done Interrupt. This mechanism of polling the
22337 + * interrupt is introduced to avoid any possible race conditions
22340 + gintsts_data_t gintsts;
22342 + DWC_READ_REG32(&core_if->core_global_regs->gintsts);
22343 + if (gintsts.b.restoredone) {
22345 + gintsts.b.restoredone = 1;
22346 + DWC_WRITE_REG32(&core_if->core_global_regs->
22347 + gintsts, gintsts.d32);
22348 + DWC_PRINTF("Restore Done Interrupt seen\n");
22352 + } while (--timeout);
22354 + DWC_PRINTF("Restore Done interrupt wasn't generated here\n");
22357 + /* Clear all pending interupts */
22358 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
22360 + /* De-assert Restore */
22362 + gpwrdn.b.restore = 1;
22363 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22366 + if (!rem_wakeup) {
22368 + pcgcctl.b.rstpdwnmodule = 1;
22369 + DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
22372 + /* Restore GUSBCFG and DCFG */
22373 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
22374 + core_if->gr_backup->gusbcfg_local);
22375 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
22376 + core_if->dr_backup->dcfg);
22378 + /* De-assert Wakeup Logic */
22380 + gpwrdn.b.pmuactv = 1;
22381 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22384 + if (!rem_wakeup) {
22385 + /* Set Device programming done bit */
22386 + dctl.b.pwronprgdone = 1;
22387 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
22389 + /* Start Remote Wakeup Signaling */
22390 + dctl.d32 = core_if->dr_backup->dctl;
22391 + dctl.b.rmtwkupsig = 1;
22392 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
22396 + /* Clear all pending interupts */
22397 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
22399 + /* Restore global registers */
22400 + dwc_otg_restore_global_regs(core_if);
22401 + /* Restore device global registers */
22402 + dwc_otg_restore_dev_regs(core_if, rem_wakeup);
22404 + if (rem_wakeup) {
22407 + dctl.b.rmtwkupsig = 1;
22408 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
22411 + core_if->hibernation_suspend = 0;
22412 + /* The core will be in ON STATE */
22413 + core_if->lx_state = DWC_OTG_L0;
22414 + DWC_PRINTF("Hibernation recovery completes here\n");
22420 + * The restore operation is modified to support Synopsys Emulated Powerdown and
22421 + * Hibernation. This function is for exiting from Host mode hibernation by
22422 + * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
22423 + * @param core_if Programming view of DWC_otg controller.
22424 + * @param rem_wakeup - indicates whether resume is initiated by Device or Host.
22425 + * @param reset - indicates whether resume is initiated by Reset.
22427 +int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if,
22428 + int rem_wakeup, int reset)
22430 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
22431 + hprt0_data_t hprt0 = {.d32 = 0 };
22433 + int timeout = 2000;
22435 + DWC_DEBUGPL(DBG_HCD, "%s called\n", __FUNCTION__);
22436 + /* Switch-on voltage to the core */
22437 + gpwrdn.b.pwrdnswtch = 1;
22438 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22443 + gpwrdn.b.pwrdnrstn = 1;
22444 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22447 + /* Assert Restore signal */
22449 + gpwrdn.b.restore = 1;
22450 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
22453 + /* Disable power clamps */
22455 + gpwrdn.b.pwrdnclmp = 1;
22456 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22458 + if (!rem_wakeup) {
22462 + /* Deassert Reset core */
22464 + gpwrdn.b.pwrdnrstn = 1;
22465 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
22468 + /* Disable PMU interrupt */
22470 + gpwrdn.b.pmuintsel = 1;
22471 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22474 + gpwrdn.b.connect_det_msk = 1;
22475 + gpwrdn.b.srp_det_msk = 1;
22476 + gpwrdn.b.disconn_det_msk = 1;
22477 + gpwrdn.b.rst_det_msk = 1;
22478 + gpwrdn.b.lnstchng_msk = 1;
22479 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22481 + /* Indicates that we are going out from hibernation */
22482 + core_if->hibernation_suspend = 0;
22484 + /* Set Restore Essential Regs bit in PCGCCTL register */
22485 + restore_essential_regs(core_if, rem_wakeup, 1);
22487 + /* Wait a little for seeing new value of variable hibernation_suspend if
22488 + * Restore done interrupt received before polling */
22491 + if (core_if->hibernation_suspend == 0) {
22492 + /* Wait For Restore_done Interrupt. This mechanism of polling the
22493 + * interrupt is introduced to avoid any possible race conditions
22496 + gintsts_data_t gintsts;
22497 + gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
22498 + if (gintsts.b.restoredone) {
22500 + gintsts.b.restoredone = 1;
22501 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
22502 + DWC_DEBUGPL(DBG_HCD,"Restore Done Interrupt seen\n");
22506 + } while (--timeout);
22508 + DWC_WARN("Restore Done interrupt wasn't generated\n");
22512 + /* Set the flag's value to 0 again after receiving restore done interrupt */
22513 + core_if->hibernation_suspend = 0;
22515 + /* This step is not described in functional spec but if not wait for this
22516 + * delay, mismatch interrupts occurred because just after restore core is
22517 + * in Device mode(gintsts.curmode == 0) */
22520 + /* Clear all pending interrupts */
22521 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
22523 + /* De-assert Restore */
22525 + gpwrdn.b.restore = 1;
22526 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22529 + /* Restore GUSBCFG and HCFG */
22530 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
22531 + core_if->gr_backup->gusbcfg_local);
22532 + DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
22533 + core_if->hr_backup->hcfg_local);
22535 + /* De-assert Wakeup Logic */
22537 + gpwrdn.b.pmuactv = 1;
22538 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22541 + /* Start the Resume operation by programming HPRT0 */
22542 + hprt0.d32 = core_if->hr_backup->hprt0_local;
22543 + hprt0.b.prtpwr = 1;
22544 + hprt0.b.prtena = 0;
22545 + hprt0.b.prtsusp = 0;
22546 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
22548 + DWC_PRINTF("Resume Starts Now\n");
22549 + if (!reset) { // Indicates it is Resume Operation
22550 + hprt0.d32 = core_if->hr_backup->hprt0_local;
22551 + hprt0.b.prtres = 1;
22552 + hprt0.b.prtpwr = 1;
22553 + hprt0.b.prtena = 0;
22554 + hprt0.b.prtsusp = 0;
22555 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
22558 + hprt0.b.prtres = 0;
22559 + /* Wait for Resume time and then program HPRT again */
22561 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
22563 + } else { // Indicates it is Reset Operation
22564 + hprt0.d32 = core_if->hr_backup->hprt0_local;
22565 + hprt0.b.prtrst = 1;
22566 + hprt0.b.prtpwr = 1;
22567 + hprt0.b.prtena = 0;
22568 + hprt0.b.prtsusp = 0;
22569 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
22570 + /* Wait for Reset time and then program HPRT again */
22572 + hprt0.b.prtrst = 0;
22573 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
22575 + /* Clear all interrupt status */
22576 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
22577 + hprt0.b.prtconndet = 1;
22578 + hprt0.b.prtenchng = 1;
22579 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
22581 + /* Clear all pending interupts */
22582 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
22584 + /* Restore global registers */
22585 + dwc_otg_restore_global_regs(core_if);
22586 + /* Restore host global registers */
22587 + dwc_otg_restore_host_regs(core_if, reset);
22589 + /* The core will be in ON STATE */
22590 + core_if->lx_state = DWC_OTG_L0;
22591 + DWC_PRINTF("Hibernation recovery is complete here\n");
22595 +/** Saves some register values into system memory. */
22596 +int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if)
22598 + struct dwc_otg_global_regs_backup *gr;
22601 + gr = core_if->gr_backup;
22603 + gr = DWC_ALLOC(sizeof(*gr));
22605 + return -DWC_E_NO_MEMORY;
22607 + core_if->gr_backup = gr;
22610 + gr->gotgctl_local = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
22611 + gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
22612 + gr->gahbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg);
22613 + gr->gusbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
22614 + gr->grxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
22615 + gr->gnptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
22616 + gr->hptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
22617 +#ifdef CONFIG_USB_DWC_OTG_LPM
22618 + gr->glpmcfg_local = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
22620 + gr->gi2cctl_local = DWC_READ_REG32(&core_if->core_global_regs->gi2cctl);
22621 + gr->pcgcctl_local = DWC_READ_REG32(core_if->pcgcctl);
22622 + gr->gdfifocfg_local =
22623 + DWC_READ_REG32(&core_if->core_global_regs->gdfifocfg);
22624 + for (i = 0; i < MAX_EPS_CHANNELS; i++) {
22625 + gr->dtxfsiz_local[i] =
22626 + DWC_READ_REG32(&(core_if->core_global_regs->dtxfsiz[i]));
22629 + DWC_DEBUGPL(DBG_ANY, "===========Backing Global registers==========\n");
22630 + DWC_DEBUGPL(DBG_ANY, "Backed up gotgctl = %08x\n", gr->gotgctl_local);
22631 + DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk = %08x\n", gr->gintmsk_local);
22632 + DWC_DEBUGPL(DBG_ANY, "Backed up gahbcfg = %08x\n", gr->gahbcfg_local);
22633 + DWC_DEBUGPL(DBG_ANY, "Backed up gusbcfg = %08x\n", gr->gusbcfg_local);
22634 + DWC_DEBUGPL(DBG_ANY, "Backed up grxfsiz = %08x\n", gr->grxfsiz_local);
22635 + DWC_DEBUGPL(DBG_ANY, "Backed up gnptxfsiz = %08x\n",
22636 + gr->gnptxfsiz_local);
22637 + DWC_DEBUGPL(DBG_ANY, "Backed up hptxfsiz = %08x\n",
22638 + gr->hptxfsiz_local);
22639 +#ifdef CONFIG_USB_DWC_OTG_LPM
22640 + DWC_DEBUGPL(DBG_ANY, "Backed up glpmcfg = %08x\n", gr->glpmcfg_local);
22642 + DWC_DEBUGPL(DBG_ANY, "Backed up gi2cctl = %08x\n", gr->gi2cctl_local);
22643 + DWC_DEBUGPL(DBG_ANY, "Backed up pcgcctl = %08x\n", gr->pcgcctl_local);
22644 + DWC_DEBUGPL(DBG_ANY,"Backed up gdfifocfg = %08x\n",gr->gdfifocfg_local);
22649 +/** Saves GINTMSK register before setting the msk bits. */
22650 +int dwc_otg_save_gintmsk_reg(dwc_otg_core_if_t * core_if)
22652 + struct dwc_otg_global_regs_backup *gr;
22654 + gr = core_if->gr_backup;
22656 + gr = DWC_ALLOC(sizeof(*gr));
22658 + return -DWC_E_NO_MEMORY;
22660 + core_if->gr_backup = gr;
22663 + gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
22665 + DWC_DEBUGPL(DBG_ANY,"=============Backing GINTMSK registers============\n");
22666 + DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk = %08x\n", gr->gintmsk_local);
22671 +int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if)
22673 + struct dwc_otg_dev_regs_backup *dr;
22676 + dr = core_if->dr_backup;
22678 + dr = DWC_ALLOC(sizeof(*dr));
22680 + return -DWC_E_NO_MEMORY;
22682 + core_if->dr_backup = dr;
22685 + dr->dcfg = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
22686 + dr->dctl = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
22688 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
22690 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->diepmsk);
22692 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->doepmsk);
22694 + for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
22696 + DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl);
22697 + dr->dieptsiz[i] =
22698 + DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz);
22700 + DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma);
22703 + DWC_DEBUGPL(DBG_ANY,
22704 + "=============Backing Host registers==============\n");
22705 + DWC_DEBUGPL(DBG_ANY, "Backed up dcfg = %08x\n", dr->dcfg);
22706 + DWC_DEBUGPL(DBG_ANY, "Backed up dctl = %08x\n", dr->dctl);
22707 + DWC_DEBUGPL(DBG_ANY, "Backed up daintmsk = %08x\n",
22709 + DWC_DEBUGPL(DBG_ANY, "Backed up diepmsk = %08x\n", dr->diepmsk);
22710 + DWC_DEBUGPL(DBG_ANY, "Backed up doepmsk = %08x\n", dr->doepmsk);
22711 + for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
22712 + DWC_DEBUGPL(DBG_ANY, "Backed up diepctl[%d] = %08x\n", i,
22714 + DWC_DEBUGPL(DBG_ANY, "Backed up dieptsiz[%d] = %08x\n",
22715 + i, dr->dieptsiz[i]);
22716 + DWC_DEBUGPL(DBG_ANY, "Backed up diepdma[%d] = %08x\n", i,
22723 +int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if)
22725 + struct dwc_otg_host_regs_backup *hr;
22728 + hr = core_if->hr_backup;
22730 + hr = DWC_ALLOC(sizeof(*hr));
22732 + return -DWC_E_NO_MEMORY;
22734 + core_if->hr_backup = hr;
22738 + DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
22739 + hr->haintmsk_local =
22740 + DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk);
22741 + for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
22742 + hr->hcintmsk_local[i] =
22743 + DWC_READ_REG32(&core_if->host_if->hc_regs[i]->hcintmsk);
22745 + hr->hprt0_local = DWC_READ_REG32(core_if->host_if->hprt0);
22747 + DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
22749 + DWC_DEBUGPL(DBG_ANY,
22750 + "=============Backing Host registers===============\n");
22751 + DWC_DEBUGPL(DBG_ANY, "Backed up hcfg = %08x\n",
22753 + DWC_DEBUGPL(DBG_ANY, "Backed up haintmsk = %08x\n", hr->haintmsk_local);
22754 + for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
22755 + DWC_DEBUGPL(DBG_ANY, "Backed up hcintmsk[%02d]=%08x\n", i,
22756 + hr->hcintmsk_local[i]);
22758 + DWC_DEBUGPL(DBG_ANY, "Backed up hprt0 = %08x\n",
22759 + hr->hprt0_local);
22760 + DWC_DEBUGPL(DBG_ANY, "Backed up hfir = %08x\n",
22766 +int dwc_otg_restore_global_regs(dwc_otg_core_if_t *core_if)
22768 + struct dwc_otg_global_regs_backup *gr;
22771 + gr = core_if->gr_backup;
22773 + return -DWC_E_INVALID;
22776 + DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, gr->gotgctl_local);
22777 + DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gr->gintmsk_local);
22778 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gr->gusbcfg_local);
22779 + DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gr->gahbcfg_local);
22780 + DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, gr->grxfsiz_local);
22781 + DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz,
22782 + gr->gnptxfsiz_local);
22783 + DWC_WRITE_REG32(&core_if->core_global_regs->hptxfsiz,
22784 + gr->hptxfsiz_local);
22785 + DWC_WRITE_REG32(&core_if->core_global_regs->gdfifocfg,
22786 + gr->gdfifocfg_local);
22787 + for (i = 0; i < MAX_EPS_CHANNELS; i++) {
22788 + DWC_WRITE_REG32(&core_if->core_global_regs->dtxfsiz[i],
22789 + gr->dtxfsiz_local[i]);
22792 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
22793 + DWC_WRITE_REG32(core_if->host_if->hprt0, 0x0000100A);
22794 + DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg,
22795 + (gr->gahbcfg_local));
22799 +int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if, int rem_wakeup)
22801 + struct dwc_otg_dev_regs_backup *dr;
22804 + dr = core_if->dr_backup;
22807 + return -DWC_E_INVALID;
22810 + if (!rem_wakeup) {
22811 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
22815 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, dr->daintmsk);
22816 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, dr->diepmsk);
22817 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, dr->doepmsk);
22819 + for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
22820 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz, dr->dieptsiz[i]);
22821 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma, dr->diepdma[i]);
22822 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl, dr->diepctl[i]);
22828 +int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset)
22830 + struct dwc_otg_host_regs_backup *hr;
22832 + hr = core_if->hr_backup;
22835 + return -DWC_E_INVALID;
22838 + DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hr->hcfg_local);
22841 + // DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hr->hfir_local);
22844 + DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk,
22845 + hr->haintmsk_local);
22846 + for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
22847 + DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk,
22848 + hr->hcintmsk_local[i]);
22854 +int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if)
22856 + struct dwc_otg_global_regs_backup *gr;
22858 + gr = core_if->gr_backup;
22860 + /* Restore values for LPM and I2C */
22861 +#ifdef CONFIG_USB_DWC_OTG_LPM
22862 + DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, gr->glpmcfg_local);
22864 + DWC_WRITE_REG32(&core_if->core_global_regs->gi2cctl, gr->gi2cctl_local);
22869 +int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode, int is_host)
22871 + struct dwc_otg_global_regs_backup *gr;
22872 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
22873 + gahbcfg_data_t gahbcfg = {.d32 = 0 };
22874 + gusbcfg_data_t gusbcfg = {.d32 = 0 };
22875 + gintmsk_data_t gintmsk = {.d32 = 0 };
22877 + /* Restore LPM and I2C registers */
22878 + restore_lpm_i2c_regs(core_if);
22880 + /* Set PCGCCTL to 0 */
22881 + DWC_WRITE_REG32(core_if->pcgcctl, 0x00000000);
22883 + gr = core_if->gr_backup;
22884 + /* Load restore values for [31:14] bits */
22885 + DWC_WRITE_REG32(core_if->pcgcctl,
22886 + ((gr->pcgcctl_local & 0xffffc000) | 0x00020000));
22888 + /* Umnask global Interrupt in GAHBCFG and restore it */
22889 + gahbcfg.d32 = gr->gahbcfg_local;
22890 + gahbcfg.b.glblintrmsk = 1;
22891 + DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32);
22893 + /* Clear all pending interupts */
22894 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
22896 + /* Unmask restore done interrupt */
22897 + gintmsk.b.restoredone = 1;
22898 + DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
22900 + /* Restore GUSBCFG and HCFG/DCFG */
22901 + gusbcfg.d32 = core_if->gr_backup->gusbcfg_local;
22902 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
22905 + hcfg_data_t hcfg = {.d32 = 0 };
22906 + hcfg.d32 = core_if->hr_backup->hcfg_local;
22907 + DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
22910 + /* Load restore values for [31:14] bits */
22911 + pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
22912 + pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
22915 + pcgcctl.b.restoremode = 1;
22916 + DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
22919 + /* Load restore values for [31:14] bits and set EssRegRestored bit */
22920 + pcgcctl.d32 = gr->pcgcctl_local | 0xffffc000;
22921 + pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
22922 + pcgcctl.b.ess_reg_restored = 1;
22924 + pcgcctl.b.restoremode = 1;
22925 + DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
22927 + dcfg_data_t dcfg = {.d32 = 0 };
22928 + dcfg.d32 = core_if->dr_backup->dcfg;
22929 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
22931 + /* Load restore values for [31:14] bits */
22932 + pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
22933 + pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
22935 + pcgcctl.d32 |= 0x208;
22937 + DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
22940 + /* Load restore values for [31:14] bits */
22941 + pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
22942 + pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
22943 + pcgcctl.b.ess_reg_restored = 1;
22945 + pcgcctl.d32 |= 0x208;
22946 + DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
22953 + * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY
22956 +static void init_fslspclksel(dwc_otg_core_if_t * core_if)
22959 + hcfg_data_t hcfg;
22961 + if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
22962 + (core_if->hwcfg2.b.fs_phy_type == 1) &&
22963 + (core_if->core_params->ulpi_fs_ls)) ||
22964 + (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
22965 + /* Full speed PHY */
22966 + val = DWC_HCFG_48_MHZ;
22968 + /* High speed PHY running at full speed or high speed */
22969 + val = DWC_HCFG_30_60_MHZ;
22972 + DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val);
22973 + hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
22974 + hcfg.b.fslspclksel = val;
22975 + DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
22979 + * Initializes the DevSpd field of the DCFG register depending on the PHY type
22980 + * and the enumeration speed of the device.
22982 +static void init_devspd(dwc_otg_core_if_t * core_if)
22985 + dcfg_data_t dcfg;
22987 + if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
22988 + (core_if->hwcfg2.b.fs_phy_type == 1) &&
22989 + (core_if->core_params->ulpi_fs_ls)) ||
22990 + (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
22991 + /* Full speed PHY */
22993 + } else if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
22994 + /* High speed PHY running at full speed */
22997 + /* High speed PHY running at high speed */
23001 + DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
23003 + dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
23004 + dcfg.b.devspd = val;
23005 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
23009 + * This function calculates the number of IN EPS
23010 + * using GHWCFG1 and GHWCFG2 registers values
23012 + * @param core_if Programming view of the DWC_otg controller
23014 +static uint32_t calc_num_in_eps(dwc_otg_core_if_t * core_if)
23016 + uint32_t num_in_eps = 0;
23017 + uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
23018 + uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 3;
23019 + uint32_t num_tx_fifos = core_if->hwcfg4.b.num_in_eps;
23022 + for (i = 0; i < num_eps; ++i) {
23023 + if (!(hwcfg1 & 0x1))
23029 + if (core_if->hwcfg4.b.ded_fifo_en) {
23031 + (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps;
23034 + return num_in_eps;
23038 + * This function calculates the number of OUT EPS
23039 + * using GHWCFG1 and GHWCFG2 registers values
23041 + * @param core_if Programming view of the DWC_otg controller
23043 +static uint32_t calc_num_out_eps(dwc_otg_core_if_t * core_if)
23045 + uint32_t num_out_eps = 0;
23046 + uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
23047 + uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2;
23050 + for (i = 0; i < num_eps; ++i) {
23051 + if (!(hwcfg1 & 0x1))
23056 + return num_out_eps;
23060 + * This function initializes the DWC_otg controller registers and
23061 + * prepares the core for device mode or host mode operation.
23063 + * @param core_if Programming view of the DWC_otg controller
23066 +void dwc_otg_core_init(dwc_otg_core_if_t * core_if)
23069 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
23070 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
23071 + gahbcfg_data_t ahbcfg = {.d32 = 0 };
23072 + gusbcfg_data_t usbcfg = {.d32 = 0 };
23073 + gi2cctl_data_t i2cctl = {.d32 = 0 };
23075 + DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p) regs at %p\n",
23076 + core_if, global_regs);
23078 + /* Common Initialization */
23079 + usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
23081 + /* Program the ULPI External VBUS bit if needed */
23082 + usbcfg.b.ulpi_ext_vbus_drv =
23083 + (core_if->core_params->phy_ulpi_ext_vbus ==
23084 + DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0;
23086 + /* Set external TS Dline pulsing */
23087 + usbcfg.b.term_sel_dl_pulse =
23088 + (core_if->core_params->ts_dline == 1) ? 1 : 0;
23089 + DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
23091 + /* Reset the Controller */
23092 + dwc_otg_core_reset(core_if);
23094 + core_if->adp_enable = core_if->core_params->adp_supp_enable;
23095 + core_if->power_down = core_if->core_params->power_down;
23096 + core_if->otg_sts = 0;
23098 + /* Initialize parameters from Hardware configuration registers. */
23099 + dev_if->num_in_eps = calc_num_in_eps(core_if);
23100 + dev_if->num_out_eps = calc_num_out_eps(core_if);
23102 + DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n",
23103 + core_if->hwcfg4.b.num_dev_perio_in_ep);
23105 + for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
23106 + dev_if->perio_tx_fifo_size[i] =
23107 + DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
23108 + DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n",
23109 + i, dev_if->perio_tx_fifo_size[i]);
23112 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
23113 + dev_if->tx_fifo_size[i] =
23114 + DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
23115 + DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n",
23116 + i, dev_if->tx_fifo_size[i]);
23119 + core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth;
23120 + core_if->rx_fifo_size = DWC_READ_REG32(&global_regs->grxfsiz);
23121 + core_if->nperio_tx_fifo_size =
23122 + DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16;
23124 + DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size);
23125 + DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size);
23126 + DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n",
23127 + core_if->nperio_tx_fifo_size);
23129 + /* This programming sequence needs to happen in FS mode before any other
23130 + * programming occurs */
23131 + if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) &&
23132 + (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
23133 + /* If FS mode with FS PHY */
23135 + /* core_init() is now called on every switch so only call the
23136 + * following for the first time through. */
23137 + if (!core_if->phy_init_done) {
23138 + core_if->phy_init_done = 1;
23139 + DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n");
23140 + usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
23141 + usbcfg.b.physel = 1;
23142 + DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
23144 + /* Reset after a PHY select */
23145 + dwc_otg_core_reset(core_if);
23148 + /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
23149 + * do this on HNP Dev/Host mode switches (done in dev_init and
23151 + if (dwc_otg_is_host_mode(core_if)) {
23152 + init_fslspclksel(core_if);
23154 + init_devspd(core_if);
23157 + if (core_if->core_params->i2c_enable) {
23158 + DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
23159 + /* Program GUSBCFG.OtgUtmifsSel to I2C */
23160 + usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
23161 + usbcfg.b.otgutmifssel = 1;
23162 + DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
23164 + /* Program GI2CCTL.I2CEn */
23165 + i2cctl.d32 = DWC_READ_REG32(&global_regs->gi2cctl);
23166 + i2cctl.b.i2cdevaddr = 1;
23167 + i2cctl.b.i2cen = 0;
23168 + DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
23169 + i2cctl.b.i2cen = 1;
23170 + DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
23173 + } /* endif speed == DWC_SPEED_PARAM_FULL */
23175 + /* High speed PHY. */
23176 + if (!core_if->phy_init_done) {
23177 + core_if->phy_init_done = 1;
23178 + /* HS PHY parameters. These parameters are preserved
23179 + * during soft reset so only program the first time. Do
23180 + * a soft reset immediately after setting phyif. */
23182 + if (core_if->core_params->phy_type == 2) {
23183 + /* ULPI interface */
23184 + usbcfg.b.ulpi_utmi_sel = 1;
23185 + usbcfg.b.phyif = 0;
23186 + usbcfg.b.ddrsel =
23187 + core_if->core_params->phy_ulpi_ddr;
23188 + } else if (core_if->core_params->phy_type == 1) {
23189 + /* UTMI+ interface */
23190 + usbcfg.b.ulpi_utmi_sel = 0;
23191 + if (core_if->core_params->phy_utmi_width == 16) {
23192 + usbcfg.b.phyif = 1;
23195 + usbcfg.b.phyif = 0;
23198 + DWC_ERROR("FS PHY TYPE\n");
23200 + DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
23201 + /* Reset after setting the PHY parameters */
23202 + dwc_otg_core_reset(core_if);
23206 + if ((core_if->hwcfg2.b.hs_phy_type == 2) &&
23207 + (core_if->hwcfg2.b.fs_phy_type == 1) &&
23208 + (core_if->core_params->ulpi_fs_ls)) {
23209 + DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n");
23210 + usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
23211 + usbcfg.b.ulpi_fsls = 1;
23212 + usbcfg.b.ulpi_clk_sus_m = 1;
23213 + DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
23215 + usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
23216 + usbcfg.b.ulpi_fsls = 0;
23217 + usbcfg.b.ulpi_clk_sus_m = 0;
23218 + DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
23221 + /* Program the GAHBCFG Register. */
23222 + switch (core_if->hwcfg2.b.architecture) {
23224 + case DWC_SLAVE_ONLY_ARCH:
23225 + DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n");
23226 + ahbcfg.b.nptxfemplvl_txfemplvl =
23227 + DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
23228 + ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
23229 + core_if->dma_enable = 0;
23230 + core_if->dma_desc_enable = 0;
23233 + case DWC_EXT_DMA_ARCH:
23234 + DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n");
23236 + uint8_t brst_sz = core_if->core_params->dma_burst_size;
23237 + ahbcfg.b.hburstlen = 0;
23238 + while (brst_sz > 1) {
23239 + ahbcfg.b.hburstlen++;
23243 + core_if->dma_enable = (core_if->core_params->dma_enable != 0);
23244 + core_if->dma_desc_enable =
23245 + (core_if->core_params->dma_desc_enable != 0);
23248 + case DWC_INT_DMA_ARCH:
23249 + DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
23250 + /* Old value was DWC_GAHBCFG_INT_DMA_BURST_INCR - done for
23251 + Host mode ISOC in issue fix - vahrama */
23252 + /* Broadcom had altered to (1<<3)|(0<<0) - WRESP=1, max 4 beats */
23253 + ahbcfg.b.hburstlen = (1<<3)|(0<<0);//DWC_GAHBCFG_INT_DMA_BURST_INCR4;
23254 + core_if->dma_enable = (core_if->core_params->dma_enable != 0);
23255 + core_if->dma_desc_enable =
23256 + (core_if->core_params->dma_desc_enable != 0);
23260 + if (core_if->dma_enable) {
23261 + if (core_if->dma_desc_enable) {
23262 + DWC_PRINTF("Using Descriptor DMA mode\n");
23264 + DWC_PRINTF("Using Buffer DMA mode\n");
23268 + DWC_PRINTF("Using Slave mode\n");
23269 + core_if->dma_desc_enable = 0;
23272 + if (core_if->core_params->ahb_single) {
23273 + ahbcfg.b.ahbsingle = 1;
23276 + ahbcfg.b.dmaenable = core_if->dma_enable;
23277 + DWC_WRITE_REG32(&global_regs->gahbcfg, ahbcfg.d32);
23279 + core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en;
23281 + core_if->pti_enh_enable = core_if->core_params->pti_enable != 0;
23282 + core_if->multiproc_int_enable = core_if->core_params->mpi_enable;
23283 + DWC_PRINTF("Periodic Transfer Interrupt Enhancement - %s\n",
23284 + ((core_if->pti_enh_enable) ? "enabled" : "disabled"));
23285 + DWC_PRINTF("Multiprocessor Interrupt Enhancement - %s\n",
23286 + ((core_if->multiproc_int_enable) ? "enabled" : "disabled"));
23289 + * Program the GUSBCFG register.
23291 + usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
23293 + switch (core_if->hwcfg2.b.op_mode) {
23294 + case DWC_MODE_HNP_SRP_CAPABLE:
23295 + usbcfg.b.hnpcap = (core_if->core_params->otg_cap ==
23296 + DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
23297 + usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
23298 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
23301 + case DWC_MODE_SRP_ONLY_CAPABLE:
23302 + usbcfg.b.hnpcap = 0;
23303 + usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
23304 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
23307 + case DWC_MODE_NO_HNP_SRP_CAPABLE:
23308 + usbcfg.b.hnpcap = 0;
23309 + usbcfg.b.srpcap = 0;
23312 + case DWC_MODE_SRP_CAPABLE_DEVICE:
23313 + usbcfg.b.hnpcap = 0;
23314 + usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
23315 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
23318 + case DWC_MODE_NO_SRP_CAPABLE_DEVICE:
23319 + usbcfg.b.hnpcap = 0;
23320 + usbcfg.b.srpcap = 0;
23323 + case DWC_MODE_SRP_CAPABLE_HOST:
23324 + usbcfg.b.hnpcap = 0;
23325 + usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
23326 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
23329 + case DWC_MODE_NO_SRP_CAPABLE_HOST:
23330 + usbcfg.b.hnpcap = 0;
23331 + usbcfg.b.srpcap = 0;
23335 + DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
23337 +#ifdef CONFIG_USB_DWC_OTG_LPM
23338 + if (core_if->core_params->lpm_enable) {
23339 + glpmcfg_data_t lpmcfg = {.d32 = 0 };
23341 + /* To enable LPM support set lpm_cap_en bit */
23342 + lpmcfg.b.lpm_cap_en = 1;
23344 + /* Make AppL1Res ACK */
23345 + lpmcfg.b.appl_resp = 1;
23347 + /* Retry 3 times */
23348 + lpmcfg.b.retry_count = 3;
23350 + DWC_MODIFY_REG32(&core_if->core_global_regs->glpmcfg,
23355 + if (core_if->core_params->ic_usb_cap) {
23356 + gusbcfg_data_t gusbcfg = {.d32 = 0 };
23357 + gusbcfg.b.ic_usb_cap = 1;
23358 + DWC_MODIFY_REG32(&core_if->core_global_regs->gusbcfg,
23362 + gotgctl_data_t gotgctl = {.d32 = 0 };
23363 + gotgctl.b.otgver = core_if->core_params->otg_ver;
23364 + DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, 0,
23366 + /* Set OTG version supported */
23367 + core_if->otg_ver = core_if->core_params->otg_ver;
23368 + DWC_PRINTF("OTG VER PARAM: %d, OTG VER FLAG: %d\n",
23369 + core_if->core_params->otg_ver, core_if->otg_ver);
23373 + /* Enable common interrupts */
23374 + dwc_otg_enable_common_interrupts(core_if);
23376 + /* Do device or host intialization based on mode during PCD
23377 + * and HCD initialization */
23378 + if (dwc_otg_is_host_mode(core_if)) {
23379 + DWC_DEBUGPL(DBG_ANY, "Host Mode\n");
23380 + core_if->op_state = A_HOST;
23382 + DWC_DEBUGPL(DBG_ANY, "Device Mode\n");
23383 + core_if->op_state = B_PERIPHERAL;
23384 +#ifdef DWC_DEVICE_ONLY
23385 + dwc_otg_core_dev_init(core_if);
23391 + * This function enables the Device mode interrupts.
23393 + * @param core_if Programming view of DWC_otg controller
23395 +void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * core_if)
23397 + gintmsk_data_t intr_mask = {.d32 = 0 };
23398 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
23400 + DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
23402 + /* Disable all interrupts. */
23403 + DWC_WRITE_REG32(&global_regs->gintmsk, 0);
23405 + /* Clear any pending interrupts */
23406 + DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
23408 + /* Enable the common interrupts */
23409 + dwc_otg_enable_common_interrupts(core_if);
23411 + /* Enable interrupts */
23412 + intr_mask.b.usbreset = 1;
23413 + intr_mask.b.enumdone = 1;
23414 + /* Disable Disconnect interrupt in Device mode */
23415 + intr_mask.b.disconnect = 0;
23417 + if (!core_if->multiproc_int_enable) {
23418 + intr_mask.b.inepintr = 1;
23419 + intr_mask.b.outepintr = 1;
23422 + intr_mask.b.erlysuspend = 1;
23424 + if (core_if->en_multiple_tx_fifo == 0) {
23425 + intr_mask.b.epmismatch = 1;
23428 + //intr_mask.b.incomplisoout = 1;
23429 + intr_mask.b.incomplisoin = 1;
23431 +/* Enable the ignore frame number for ISOC xfers - MAS */
23432 +/* Disable to support high bandwith ISOC transfers - manukz */
23434 +#ifdef DWC_UTE_PER_IO
23435 + if (core_if->dma_enable) {
23436 + if (core_if->dma_desc_enable) {
23437 + dctl_data_t dctl1 = {.d32 = 0 };
23438 + dctl1.b.ifrmnum = 1;
23439 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
23440 + dctl, 0, dctl1.d32);
23441 + DWC_DEBUG("----Enabled Ignore frame number (0x%08x)",
23442 + DWC_READ_REG32(&core_if->dev_if->
23443 + dev_global_regs->dctl));
23448 +#ifdef DWC_EN_ISOC
23449 + if (core_if->dma_enable) {
23450 + if (core_if->dma_desc_enable == 0) {
23451 + if (core_if->pti_enh_enable) {
23452 + dctl_data_t dctl = {.d32 = 0 };
23453 + dctl.b.ifrmnum = 1;
23454 + DWC_MODIFY_REG32(&core_if->
23455 + dev_if->dev_global_regs->dctl,
23458 + intr_mask.b.incomplisoin = 1;
23459 + intr_mask.b.incomplisoout = 1;
23463 + intr_mask.b.incomplisoin = 1;
23464 + intr_mask.b.incomplisoout = 1;
23466 +#endif /* DWC_EN_ISOC */
23468 + /** @todo NGS: Should this be a module parameter? */
23469 +#ifdef USE_PERIODIC_EP
23470 + intr_mask.b.isooutdrop = 1;
23471 + intr_mask.b.eopframe = 1;
23472 + intr_mask.b.incomplisoin = 1;
23473 + intr_mask.b.incomplisoout = 1;
23476 + DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
23478 + DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__,
23479 + DWC_READ_REG32(&global_regs->gintmsk));
23483 + * This function initializes the DWC_otg controller registers for
23486 + * @param core_if Programming view of DWC_otg controller
23489 +void dwc_otg_core_dev_init(dwc_otg_core_if_t * core_if)
23492 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
23493 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
23494 + dwc_otg_core_params_t *params = core_if->core_params;
23495 + dcfg_data_t dcfg = {.d32 = 0 };
23496 + depctl_data_t diepctl = {.d32 = 0 };
23497 + grstctl_t resetctl = {.d32 = 0 };
23498 + uint32_t rx_fifo_size;
23499 + fifosize_data_t nptxfifosize;
23500 + fifosize_data_t txfifosize;
23501 + dthrctl_data_t dthrctl;
23502 + fifosize_data_t ptxfifosize;
23503 + uint16_t rxfsiz, nptxfsiz;
23504 + gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
23505 + hwcfg3_data_t hwcfg3 = {.d32 = 0 };
23507 + /* Restart the Phy Clock */
23508 + DWC_WRITE_REG32(core_if->pcgcctl, 0);
23510 + /* Device configuration register */
23511 + init_devspd(core_if);
23512 + dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
23513 + dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0;
23514 + dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80;
23515 + /* Enable Device OUT NAK in case of DDMA mode*/
23516 + if (core_if->core_params->dev_out_nak) {
23517 + dcfg.b.endevoutnak = 1;
23520 + if (core_if->core_params->cont_on_bna) {
23521 + dctl_data_t dctl = {.d32 = 0 };
23522 + dctl.b.encontonbna = 1;
23523 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
23527 + DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
23529 + /* Configure data FIFO sizes */
23530 + if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
23531 + DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
23532 + core_if->total_fifo_size);
23533 + DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
23534 + params->dev_rx_fifo_size);
23535 + DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
23536 + params->dev_nperio_tx_fifo_size);
23539 + DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
23540 + DWC_READ_REG32(&global_regs->grxfsiz));
23542 +#ifdef DWC_UTE_CFI
23543 + core_if->pwron_rxfsiz = DWC_READ_REG32(&global_regs->grxfsiz);
23544 + core_if->init_rxfsiz = params->dev_rx_fifo_size;
23546 + rx_fifo_size = params->dev_rx_fifo_size;
23547 + DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size);
23549 + DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
23550 + DWC_READ_REG32(&global_regs->grxfsiz));
23552 + /** Set Periodic Tx FIFO Mask all bits 0 */
23553 + core_if->p_tx_msk = 0;
23555 + /** Set Tx FIFO Mask all bits 0 */
23556 + core_if->tx_msk = 0;
23558 + if (core_if->en_multiple_tx_fifo == 0) {
23559 + /* Non-periodic Tx FIFO */
23560 + DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
23561 + DWC_READ_REG32(&global_regs->gnptxfsiz));
23563 + nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
23564 + nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
23566 + DWC_WRITE_REG32(&global_regs->gnptxfsiz,
23567 + nptxfifosize.d32);
23569 + DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
23570 + DWC_READ_REG32(&global_regs->gnptxfsiz));
23572 + /**@todo NGS: Fix Periodic FIFO Sizing! */
23574 + * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15.
23575 + * Indexes of the FIFO size module parameters in the
23576 + * dev_perio_tx_fifo_size array and the FIFO size registers in
23577 + * the dptxfsiz array run from 0 to 14.
23579 + /** @todo Finish debug of this */
23580 + ptxfifosize.b.startaddr =
23581 + nptxfifosize.b.startaddr + nptxfifosize.b.depth;
23582 + for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
23583 + ptxfifosize.b.depth =
23584 + params->dev_perio_tx_fifo_size[i];
23585 + DWC_DEBUGPL(DBG_CIL,
23586 + "initial dtxfsiz[%d]=%08x\n", i,
23587 + DWC_READ_REG32(&global_regs->dtxfsiz
23589 + DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
23590 + ptxfifosize.d32);
23591 + DWC_DEBUGPL(DBG_CIL, "new dtxfsiz[%d]=%08x\n",
23593 + DWC_READ_REG32(&global_regs->dtxfsiz
23595 + ptxfifosize.b.startaddr += ptxfifosize.b.depth;
23599 + * Tx FIFOs These FIFOs are numbered from 1 to 15.
23600 + * Indexes of the FIFO size module parameters in the
23601 + * dev_tx_fifo_size array and the FIFO size registers in
23602 + * the dtxfsiz array run from 0 to 14.
23605 + /* Non-periodic Tx FIFO */
23606 + DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
23607 + DWC_READ_REG32(&global_regs->gnptxfsiz));
23609 +#ifdef DWC_UTE_CFI
23610 + core_if->pwron_gnptxfsiz =
23611 + (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
23612 + core_if->init_gnptxfsiz =
23613 + params->dev_nperio_tx_fifo_size;
23615 + nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
23616 + nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
23618 + DWC_WRITE_REG32(&global_regs->gnptxfsiz,
23619 + nptxfifosize.d32);
23621 + DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
23622 + DWC_READ_REG32(&global_regs->gnptxfsiz));
23624 + txfifosize.b.startaddr =
23625 + nptxfifosize.b.startaddr + nptxfifosize.b.depth;
23627 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
23629 + txfifosize.b.depth =
23630 + params->dev_tx_fifo_size[i];
23632 + DWC_DEBUGPL(DBG_CIL,
23633 + "initial dtxfsiz[%d]=%08x\n",
23635 + DWC_READ_REG32(&global_regs->dtxfsiz
23638 +#ifdef DWC_UTE_CFI
23639 + core_if->pwron_txfsiz[i] =
23641 + (&global_regs->dtxfsiz[i]) >> 16);
23642 + core_if->init_txfsiz[i] =
23643 + params->dev_tx_fifo_size[i];
23645 + DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
23648 + DWC_DEBUGPL(DBG_CIL,
23649 + "new dtxfsiz[%d]=%08x\n",
23651 + DWC_READ_REG32(&global_regs->dtxfsiz
23654 + txfifosize.b.startaddr += txfifosize.b.depth;
23656 + if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
23657 + /* Calculating DFIFOCFG for Device mode to include RxFIFO and NPTXFIFO */
23658 + gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
23659 + hwcfg3.d32 = DWC_READ_REG32(&global_regs->ghwcfg3);
23660 + gdfifocfg.b.gdfifocfg = (DWC_READ_REG32(&global_regs->ghwcfg3) >> 16);
23661 + DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
23662 + rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff);
23663 + nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
23664 + gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz;
23665 + DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
23669 + /* Flush the FIFOs */
23670 + dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */
23671 + dwc_otg_flush_rx_fifo(core_if);
23673 + /* Flush the Learning Queue. */
23674 + resetctl.b.intknqflsh = 1;
23675 + DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
23677 + if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) {
23678 + core_if->start_predict = 0;
23679 + for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) {
23680 + core_if->nextep_seq[i] = 0xff; // 0xff - EP not active
23682 + core_if->nextep_seq[0] = 0;
23683 + core_if->first_in_nextep_seq = 0;
23684 + diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
23685 + diepctl.b.nextep = 0;
23686 + DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
23688 + /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */
23689 + dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
23690 + dcfg.b.epmscnt = 2;
23691 + DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
23693 + DWC_DEBUGPL(DBG_CILV,"%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
23694 + __func__, core_if->first_in_nextep_seq);
23695 + for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
23696 + DWC_DEBUGPL(DBG_CILV, "%2d ", core_if->nextep_seq[i]);
23698 + DWC_DEBUGPL(DBG_CILV,"\n");
23701 + /* Clear all pending Device Interrupts */
23702 + /** @todo - if the condition needed to be checked
23703 + * or in any case all pending interrutps should be cleared?
23705 + if (core_if->multiproc_int_enable) {
23706 + for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
23707 + DWC_WRITE_REG32(&dev_if->
23708 + dev_global_regs->diepeachintmsk[i], 0);
23712 + for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
23713 + DWC_WRITE_REG32(&dev_if->
23714 + dev_global_regs->doepeachintmsk[i], 0);
23717 + DWC_WRITE_REG32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF);
23718 + DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk, 0);
23720 + DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, 0);
23721 + DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, 0);
23722 + DWC_WRITE_REG32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF);
23723 + DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk, 0);
23726 + for (i = 0; i <= dev_if->num_in_eps; i++) {
23727 + depctl_data_t depctl;
23728 + depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
23729 + if (depctl.b.epena) {
23731 + depctl.b.epdis = 1;
23732 + depctl.b.snak = 1;
23737 + DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
23739 + DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, 0);
23740 + DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, 0);
23741 + DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepint, 0xFF);
23744 + for (i = 0; i <= dev_if->num_out_eps; i++) {
23745 + depctl_data_t depctl;
23746 + depctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
23747 + if (depctl.b.epena) {
23748 + dctl_data_t dctl = {.d32 = 0 };
23749 + gintmsk_data_t gintsts = {.d32 = 0 };
23750 + doepint_data_t doepint = {.d32 = 0 };
23751 + dctl.b.sgoutnak = 1;
23752 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
23755 + gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
23756 + } while (!gintsts.b.goutnakeff);
23758 + gintsts.b.goutnakeff = 1;
23759 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
23762 + depctl.b.epdis = 1;
23763 + depctl.b.snak = 1;
23764 + DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepctl, depctl.d32);
23767 + doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
23768 + out_ep_regs[i]->doepint);
23769 + } while (!doepint.b.epdisabled);
23771 + doepint.b.epdisabled = 1;
23772 + DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepint, doepint.d32);
23775 + dctl.b.cgoutnak = 1;
23776 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
23781 + DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32);
23783 + DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doeptsiz, 0);
23784 + DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepdma, 0);
23785 + DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepint, 0xFF);
23788 + if (core_if->en_multiple_tx_fifo && core_if->dma_enable) {
23789 + dev_if->non_iso_tx_thr_en = params->thr_ctl & 0x1;
23790 + dev_if->iso_tx_thr_en = (params->thr_ctl >> 1) & 0x1;
23791 + dev_if->rx_thr_en = (params->thr_ctl >> 2) & 0x1;
23793 + dev_if->rx_thr_length = params->rx_thr_length;
23794 + dev_if->tx_thr_length = params->tx_thr_length;
23796 + dev_if->setup_desc_index = 0;
23799 + dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en;
23800 + dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en;
23801 + dthrctl.b.tx_thr_len = dev_if->tx_thr_length;
23802 + dthrctl.b.rx_thr_en = dev_if->rx_thr_en;
23803 + dthrctl.b.rx_thr_len = dev_if->rx_thr_length;
23804 + dthrctl.b.ahb_thr_ratio = params->ahb_thr_ratio;
23806 + DWC_WRITE_REG32(&dev_if->dev_global_regs->dtknqr3_dthrctl,
23809 + DWC_DEBUGPL(DBG_CIL,
23810 + "Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n",
23811 + dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en,
23812 + dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len,
23813 + dthrctl.b.rx_thr_len);
23817 + dwc_otg_enable_device_interrupts(core_if);
23820 + diepmsk_data_t msk = {.d32 = 0 };
23821 + msk.b.txfifoundrn = 1;
23822 + if (core_if->multiproc_int_enable) {
23823 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->
23824 + diepeachintmsk[0], msk.d32, msk.d32);
23826 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk,
23827 + msk.d32, msk.d32);
23831 + if (core_if->multiproc_int_enable) {
23832 + /* Set NAK on Babble */
23833 + dctl_data_t dctl = {.d32 = 0 };
23834 + dctl.b.nakonbble = 1;
23835 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
23838 + if (core_if->snpsid >= OTG_CORE_REV_2_94a) {
23839 + dctl_data_t dctl = {.d32 = 0 };
23840 + dctl.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dctl);
23841 + dctl.b.sftdiscon = 0;
23842 + DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl, dctl.d32);
23847 + * This function enables the Host mode interrupts.
23849 + * @param core_if Programming view of DWC_otg controller
23851 +void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * core_if)
23853 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
23854 + gintmsk_data_t intr_mask = {.d32 = 0 };
23856 + DWC_DEBUGPL(DBG_CIL, "%s(%p)\n", __func__, core_if);
23858 + /* Disable all interrupts. */
23859 + DWC_WRITE_REG32(&global_regs->gintmsk, 0);
23861 + /* Clear any pending interrupts. */
23862 + DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
23864 + /* Enable the common interrupts */
23865 + dwc_otg_enable_common_interrupts(core_if);
23868 + * Enable host mode interrupts without disturbing common
23872 + intr_mask.b.disconnect = 1;
23873 + intr_mask.b.portintr = 1;
23874 + intr_mask.b.hcintr = 1;
23876 + DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
23880 + * This function disables the Host Mode interrupts.
23882 + * @param core_if Programming view of DWC_otg controller
23884 +void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * core_if)
23886 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
23887 + gintmsk_data_t intr_mask = {.d32 = 0 };
23889 + DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__);
23892 + * Disable host mode interrupts without disturbing common
23895 + intr_mask.b.sofintr = 1;
23896 + intr_mask.b.portintr = 1;
23897 + intr_mask.b.hcintr = 1;
23898 + intr_mask.b.ptxfempty = 1;
23899 + intr_mask.b.nptxfempty = 1;
23901 + DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, 0);
23905 + * This function initializes the DWC_otg controller registers for
23908 + * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
23909 + * request queues. Host channels are reset to ensure that they are ready for
23910 + * performing transfers.
23912 + * @param core_if Programming view of DWC_otg controller
23915 +void dwc_otg_core_host_init(dwc_otg_core_if_t * core_if)
23917 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
23918 + dwc_otg_host_if_t *host_if = core_if->host_if;
23919 + dwc_otg_core_params_t *params = core_if->core_params;
23920 + hprt0_data_t hprt0 = {.d32 = 0 };
23921 + fifosize_data_t nptxfifosize;
23922 + fifosize_data_t ptxfifosize;
23923 + uint16_t rxfsiz, nptxfsiz, hptxfsiz;
23924 + gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
23926 + hcchar_data_t hcchar;
23927 + hcfg_data_t hcfg;
23928 + hfir_data_t hfir;
23929 + dwc_otg_hc_regs_t *hc_regs;
23930 + int num_channels;
23931 + gotgctl_data_t gotgctl = {.d32 = 0 };
23933 + DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if);
23935 + /* Restart the Phy Clock */
23936 + DWC_WRITE_REG32(core_if->pcgcctl, 0);
23938 + /* Initialize Host Configuration Register */
23939 + init_fslspclksel(core_if);
23940 + if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
23941 + hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);
23942 + hcfg.b.fslssupp = 1;
23943 + DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);
23947 + /* This bit allows dynamic reloading of the HFIR register
23948 + * during runtime. This bit needs to be programmed during
23949 + * initial configuration and its value must not be changed
23950 + * during runtime.*/
23951 + if (core_if->core_params->reload_ctl == 1) {
23952 + hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);
23953 + hfir.b.hfirrldctrl = 1;
23954 + DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);
23957 + if (core_if->core_params->dma_desc_enable) {
23958 + uint8_t op_mode = core_if->hwcfg2.b.op_mode;
23960 + (core_if->hwcfg4.b.desc_dma
23961 + && (core_if->snpsid >= OTG_CORE_REV_2_90a)
23962 + && ((op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
23963 + || (op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
23965 + DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG)
23966 + || (op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)
23968 + DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST)))) {
23970 + DWC_ERROR("Host can't operate in Descriptor DMA mode.\n"
23971 + "Either core version is below 2.90a or "
23972 + "GHWCFG2, GHWCFG4 registers' values do not allow Descriptor DMA in host mode.\n"
23973 + "To run the driver in Buffer DMA host mode set dma_desc_enable "
23974 + "module parameter to 0.\n");
23977 + hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);
23978 + hcfg.b.descdma = 1;
23979 + DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);
23982 + /* Configure data FIFO sizes */
23983 + if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
23984 + DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
23985 + core_if->total_fifo_size);
23986 + DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
23987 + params->host_rx_fifo_size);
23988 + DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
23989 + params->host_nperio_tx_fifo_size);
23990 + DWC_DEBUGPL(DBG_CIL, "P Tx FIFO Size=%d\n",
23991 + params->host_perio_tx_fifo_size);
23994 + DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
23995 + DWC_READ_REG32(&global_regs->grxfsiz));
23996 + DWC_WRITE_REG32(&global_regs->grxfsiz,
23997 + params->host_rx_fifo_size);
23998 + DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
23999 + DWC_READ_REG32(&global_regs->grxfsiz));
24001 + /* Non-periodic Tx FIFO */
24002 + DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
24003 + DWC_READ_REG32(&global_regs->gnptxfsiz));
24004 + nptxfifosize.b.depth = params->host_nperio_tx_fifo_size;
24005 + nptxfifosize.b.startaddr = params->host_rx_fifo_size;
24006 + DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32);
24007 + DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
24008 + DWC_READ_REG32(&global_regs->gnptxfsiz));
24010 + /* Periodic Tx FIFO */
24011 + DWC_DEBUGPL(DBG_CIL, "initial hptxfsiz=%08x\n",
24012 + DWC_READ_REG32(&global_regs->hptxfsiz));
24013 + ptxfifosize.b.depth = params->host_perio_tx_fifo_size;
24014 + ptxfifosize.b.startaddr =
24015 + nptxfifosize.b.startaddr + nptxfifosize.b.depth;
24016 + DWC_WRITE_REG32(&global_regs->hptxfsiz, ptxfifosize.d32);
24017 + DWC_DEBUGPL(DBG_CIL, "new hptxfsiz=%08x\n",
24018 + DWC_READ_REG32(&global_regs->hptxfsiz));
24020 + if (core_if->en_multiple_tx_fifo
24021 + && core_if->snpsid <= OTG_CORE_REV_2_94a) {
24022 + /* Global DFIFOCFG calculation for Host mode - include RxFIFO, NPTXFIFO and HPTXFIFO */
24023 + gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
24024 + rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff);
24025 + nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
24026 + hptxfsiz = (DWC_READ_REG32(&global_regs->hptxfsiz) >> 16);
24027 + gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz + hptxfsiz;
24028 + DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
24032 + /* TODO - check this */
24033 + /* Clear Host Set HNP Enable in the OTG Control Register */
24034 + gotgctl.b.hstsethnpen = 1;
24035 + DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
24036 + /* Make sure the FIFOs are flushed. */
24037 + dwc_otg_flush_tx_fifo(core_if, 0x10 /* all TX FIFOs */ );
24038 + dwc_otg_flush_rx_fifo(core_if);
24040 + /* Clear Host Set HNP Enable in the OTG Control Register */
24041 + gotgctl.b.hstsethnpen = 1;
24042 + DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
24044 + if (!core_if->core_params->dma_desc_enable) {
24045 + /* Flush out any leftover queued requests. */
24046 + num_channels = core_if->core_params->host_channels;
24048 + for (i = 0; i < num_channels; i++) {
24049 + hc_regs = core_if->host_if->hc_regs[i];
24050 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
24051 + hcchar.b.chen = 0;
24052 + hcchar.b.chdis = 1;
24053 + hcchar.b.epdir = 0;
24054 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
24057 + /* Halt all channels to put them into a known state. */
24058 + for (i = 0; i < num_channels; i++) {
24060 + hc_regs = core_if->host_if->hc_regs[i];
24061 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
24062 + hcchar.b.chen = 1;
24063 + hcchar.b.chdis = 1;
24064 + hcchar.b.epdir = 0;
24065 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
24066 + DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d regs %p\n", __func__, i, hc_regs);
24068 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
24069 + if (++count > 1000) {
24071 + ("%s: Unable to clear halt on channel %d (timeout HCCHAR 0x%X @%p)\n",
24072 + __func__, i, hcchar.d32, &hc_regs->hcchar);
24076 + } while (hcchar.b.chen);
24080 + /* Turn on the vbus power. */
24081 + DWC_PRINTF("Init: Port Power? op_state=%d\n", core_if->op_state);
24082 + if (core_if->op_state == A_HOST) {
24083 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
24084 + DWC_PRINTF("Init: Power Port (%d)\n", hprt0.b.prtpwr);
24085 + if (hprt0.b.prtpwr == 0) {
24086 + hprt0.b.prtpwr = 1;
24087 + DWC_WRITE_REG32(host_if->hprt0, hprt0.d32);
24091 + dwc_otg_enable_host_interrupts(core_if);
24095 + * Prepares a host channel for transferring packets to/from a specific
24096 + * endpoint. The HCCHARn register is set up with the characteristics specified
24097 + * in _hc. Host channel interrupts that may need to be serviced while this
24098 + * transfer is in progress are enabled.
24100 + * @param core_if Programming view of DWC_otg controller
24101 + * @param hc Information needed to initialize the host channel
24103 +void dwc_otg_hc_init(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
24105 + hcintmsk_data_t hc_intr_mask;
24106 + hcchar_data_t hcchar;
24107 + hcsplt_data_t hcsplt;
24109 + uint8_t hc_num = hc->hc_num;
24110 + dwc_otg_host_if_t *host_if = core_if->host_if;
24111 + dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num];
24113 + /* Clear old interrupt conditions for this host channel. */
24114 + hc_intr_mask.d32 = 0xFFFFFFFF;
24115 + hc_intr_mask.b.reserved14_31 = 0;
24116 + DWC_WRITE_REG32(&hc_regs->hcint, hc_intr_mask.d32);
24118 + /* Enable channel interrupts required for this transfer. */
24119 + hc_intr_mask.d32 = 0;
24120 + hc_intr_mask.b.chhltd = 1;
24121 + if (core_if->dma_enable) {
24122 + /* For Descriptor DMA mode core halts the channel on AHB error. Interrupt is not required */
24123 + if (!core_if->dma_desc_enable)
24124 + hc_intr_mask.b.ahberr = 1;
24126 + if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
24127 + hc_intr_mask.b.xfercompl = 1;
24130 + if (hc->error_state && !hc->do_split &&
24131 + hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
24132 + hc_intr_mask.b.ack = 1;
24133 + if (hc->ep_is_in) {
24134 + hc_intr_mask.b.datatglerr = 1;
24135 + if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
24136 + hc_intr_mask.b.nak = 1;
24141 + switch (hc->ep_type) {
24142 + case DWC_OTG_EP_TYPE_CONTROL:
24143 + case DWC_OTG_EP_TYPE_BULK:
24144 + hc_intr_mask.b.xfercompl = 1;
24145 + hc_intr_mask.b.stall = 1;
24146 + hc_intr_mask.b.xacterr = 1;
24147 + hc_intr_mask.b.datatglerr = 1;
24148 + if (hc->ep_is_in) {
24149 + hc_intr_mask.b.bblerr = 1;
24151 + hc_intr_mask.b.nak = 1;
24152 + hc_intr_mask.b.nyet = 1;
24153 + if (hc->do_ping) {
24154 + hc_intr_mask.b.ack = 1;
24158 + if (hc->do_split) {
24159 + hc_intr_mask.b.nak = 1;
24160 + if (hc->complete_split) {
24161 + hc_intr_mask.b.nyet = 1;
24163 + hc_intr_mask.b.ack = 1;
24167 + if (hc->error_state) {
24168 + hc_intr_mask.b.ack = 1;
24171 + case DWC_OTG_EP_TYPE_INTR:
24172 + hc_intr_mask.b.xfercompl = 1;
24173 + hc_intr_mask.b.nak = 1;
24174 + hc_intr_mask.b.stall = 1;
24175 + hc_intr_mask.b.xacterr = 1;
24176 + hc_intr_mask.b.datatglerr = 1;
24177 + hc_intr_mask.b.frmovrun = 1;
24179 + if (hc->ep_is_in) {
24180 + hc_intr_mask.b.bblerr = 1;
24182 + if (hc->error_state) {
24183 + hc_intr_mask.b.ack = 1;
24185 + if (hc->do_split) {
24186 + if (hc->complete_split) {
24187 + hc_intr_mask.b.nyet = 1;
24189 + hc_intr_mask.b.ack = 1;
24193 + case DWC_OTG_EP_TYPE_ISOC:
24194 + hc_intr_mask.b.xfercompl = 1;
24195 + hc_intr_mask.b.frmovrun = 1;
24196 + hc_intr_mask.b.ack = 1;
24198 + if (hc->ep_is_in) {
24199 + hc_intr_mask.b.xacterr = 1;
24200 + hc_intr_mask.b.bblerr = 1;
24205 + DWC_WRITE_REG32(&hc_regs->hcintmsk, hc_intr_mask.d32);
24208 + * Program the HCCHARn register with the endpoint characteristics for
24209 + * the current transfer.
24212 + hcchar.b.devaddr = hc->dev_addr;
24213 + hcchar.b.epnum = hc->ep_num;
24214 + hcchar.b.epdir = hc->ep_is_in;
24215 + hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
24216 + hcchar.b.eptype = hc->ep_type;
24217 + hcchar.b.mps = hc->max_packet;
24219 + DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32);
24221 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d, Dev Addr %d, EP #%d\n",
24222 + __func__, hc->hc_num, hcchar.b.devaddr, hcchar.b.epnum);
24223 + DWC_DEBUGPL(DBG_HCDV, " Is In %d, Is Low Speed %d, EP Type %d, "
24224 + "Max Pkt %d, Multi Cnt %d\n",
24225 + hcchar.b.epdir, hcchar.b.lspddev, hcchar.b.eptype,
24226 + hcchar.b.mps, hcchar.b.multicnt);
24229 + * Program the HCSPLIT register for SPLITs
24232 + if (hc->do_split) {
24233 + DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n",
24235 + hc->complete_split ? "CSPLIT" : "SSPLIT");
24236 + hcsplt.b.compsplt = hc->complete_split;
24237 + hcsplt.b.xactpos = hc->xact_pos;
24238 + hcsplt.b.hubaddr = hc->hub_addr;
24239 + hcsplt.b.prtaddr = hc->port_addr;
24240 + DWC_DEBUGPL(DBG_HCDV, "\t comp split %d\n", hc->complete_split);
24241 + DWC_DEBUGPL(DBG_HCDV, "\t xact pos %d\n", hc->xact_pos);
24242 + DWC_DEBUGPL(DBG_HCDV, "\t hub addr %d\n", hc->hub_addr);
24243 + DWC_DEBUGPL(DBG_HCDV, "\t port addr %d\n", hc->port_addr);
24244 + DWC_DEBUGPL(DBG_HCDV, "\t is_in %d\n", hc->ep_is_in);
24245 + DWC_DEBUGPL(DBG_HCDV, "\t Max Pkt: %d\n", hcchar.b.mps);
24246 + DWC_DEBUGPL(DBG_HCDV, "\t xferlen: %d\n", hc->xfer_len);
24248 + DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32);
24253 + * Attempts to halt a host channel. This function should only be called in
24254 + * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under
24255 + * normal circumstances in DMA mode, the controller halts the channel when the
24256 + * transfer is complete or a condition occurs that requires application
24259 + * In slave mode, checks for a free request queue entry, then sets the Channel
24260 + * Enable and Channel Disable bits of the Host Channel Characteristics
24261 + * register of the specified channel to intiate the halt. If there is no free
24262 + * request queue entry, sets only the Channel Disable bit of the HCCHARn
24263 + * register to flush requests for this channel. In the latter case, sets a
24264 + * flag to indicate that the host channel needs to be halted when a request
24265 + * queue slot is open.
24267 + * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
24268 + * HCCHARn register. The controller ensures there is space in the request
24269 + * queue before submitting the halt request.
24271 + * Some time may elapse before the core flushes any posted requests for this
24272 + * host channel and halts. The Channel Halted interrupt handler completes the
24273 + * deactivation of the host channel.
24275 + * @param core_if Controller register interface.
24276 + * @param hc Host channel to halt.
24277 + * @param halt_status Reason for halting the channel.
24279 +void dwc_otg_hc_halt(dwc_otg_core_if_t * core_if,
24280 + dwc_hc_t * hc, dwc_otg_halt_status_e halt_status)
24282 + gnptxsts_data_t nptxsts;
24283 + hptxsts_data_t hptxsts;
24284 + hcchar_data_t hcchar;
24285 + dwc_otg_hc_regs_t *hc_regs;
24286 + dwc_otg_core_global_regs_t *global_regs;
24287 + dwc_otg_host_global_regs_t *host_global_regs;
24289 + hc_regs = core_if->host_if->hc_regs[hc->hc_num];
24290 + global_regs = core_if->core_global_regs;
24291 + host_global_regs = core_if->host_if->host_global_regs;
24293 + DWC_ASSERT(!(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS),
24294 + "halt_status = %d\n", halt_status);
24296 + if (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
24297 + halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
24299 + * Disable all channel interrupts except Ch Halted. The QTD
24300 + * and QH state associated with this transfer has been cleared
24301 + * (in the case of URB_DEQUEUE), so the channel needs to be
24302 + * shut down carefully to prevent crashes.
24304 + hcintmsk_data_t hcintmsk;
24305 + hcintmsk.d32 = 0;
24306 + hcintmsk.b.chhltd = 1;
24307 + DWC_WRITE_REG32(&hc_regs->hcintmsk, hcintmsk.d32);
24310 + * Make sure no other interrupts besides halt are currently
24311 + * pending. Handling another interrupt could cause a crash due
24312 + * to the QTD and QH state.
24314 + DWC_WRITE_REG32(&hc_regs->hcint, ~hcintmsk.d32);
24317 + * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
24318 + * even if the channel was already halted for some other
24321 + hc->halt_status = halt_status;
24323 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
24324 + if (hcchar.b.chen == 0) {
24326 + * The channel is either already halted or it hasn't
24327 + * started yet. In DMA mode, the transfer may halt if
24328 + * it finishes normally or a condition occurs that
24329 + * requires driver intervention. Don't want to halt
24330 + * the channel again. In either Slave or DMA mode,
24331 + * it's possible that the transfer has been assigned
24332 + * to a channel, but not started yet when an URB is
24333 + * dequeued. Don't want to halt a channel that hasn't
24339 + if (hc->halt_pending) {
24341 + * A halt has already been issued for this channel. This might
24342 + * happen when a transfer is aborted by a higher level in
24347 + ("*** %s: Channel %d, _hc->halt_pending already set ***\n",
24348 + __func__, hc->hc_num);
24354 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
24356 + /* No need to set the bit in DDMA for disabling the channel */
24357 + //TODO check it everywhere channel is disabled
24358 + if (!core_if->core_params->dma_desc_enable)
24359 + hcchar.b.chen = 1;
24360 + hcchar.b.chdis = 1;
24362 + if (!core_if->dma_enable) {
24363 + /* Check for space in the request queue to issue the halt. */
24364 + if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
24365 + hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
24366 + nptxsts.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
24367 + if (nptxsts.b.nptxqspcavail == 0) {
24368 + hcchar.b.chen = 0;
24372 + DWC_READ_REG32(&host_global_regs->hptxsts);
24373 + if ((hptxsts.b.ptxqspcavail == 0)
24374 + || (core_if->queuing_high_bandwidth)) {
24375 + hcchar.b.chen = 0;
24379 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
24381 + hc->halt_status = halt_status;
24383 + if (hcchar.b.chen) {
24384 + hc->halt_pending = 1;
24385 + hc->halt_on_queue = 0;
24387 + hc->halt_on_queue = 1;
24390 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
24391 + DWC_DEBUGPL(DBG_HCDV, " hcchar: 0x%08x\n", hcchar.d32);
24392 + DWC_DEBUGPL(DBG_HCDV, " halt_pending: %d\n", hc->halt_pending);
24393 + DWC_DEBUGPL(DBG_HCDV, " halt_on_queue: %d\n", hc->halt_on_queue);
24394 + DWC_DEBUGPL(DBG_HCDV, " halt_status: %d\n", hc->halt_status);
24400 + * Clears the transfer state for a host channel. This function is normally
24401 + * called after a transfer is done and the host channel is being released.
24403 + * @param core_if Programming view of DWC_otg controller.
24404 + * @param hc Identifies the host channel to clean up.
24406 +void dwc_otg_hc_cleanup(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
24408 + dwc_otg_hc_regs_t *hc_regs;
24410 + hc->xfer_started = 0;
24413 + * Clear channel interrupt enables and any unhandled channel interrupt
24416 + hc_regs = core_if->host_if->hc_regs[hc->hc_num];
24417 + DWC_WRITE_REG32(&hc_regs->hcintmsk, 0);
24418 + DWC_WRITE_REG32(&hc_regs->hcint, 0xFFFFFFFF);
24420 + DWC_TIMER_CANCEL(core_if->hc_xfer_timer[hc->hc_num]);
24425 + * Sets the channel property that indicates in which frame a periodic transfer
24426 + * should occur. This is always set to the _next_ frame. This function has no
24427 + * effect on non-periodic transfers.
24429 + * @param core_if Programming view of DWC_otg controller.
24430 + * @param hc Identifies the host channel to set up and its properties.
24431 + * @param hcchar Current value of the HCCHAR register for the specified host
24434 +static inline void hc_set_even_odd_frame(dwc_otg_core_if_t * core_if,
24435 + dwc_hc_t * hc, hcchar_data_t * hcchar)
24437 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
24438 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
24439 + hfnum_data_t hfnum;
24441 + DWC_READ_REG32(&core_if->host_if->host_global_regs->hfnum);
24443 + /* 1 if _next_ frame is odd, 0 if it's even */
24444 + hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
24446 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR && hc->do_split
24447 + && !hc->complete_split) {
24448 + switch (hfnum.b.frnum & 0x7) {
24450 + core_if->hfnum_7_samples++;
24451 + core_if->hfnum_7_frrem_accum += hfnum.b.frrem;
24454 + core_if->hfnum_0_samples++;
24455 + core_if->hfnum_0_frrem_accum += hfnum.b.frrem;
24458 + core_if->hfnum_other_samples++;
24459 + core_if->hfnum_other_frrem_accum +=
24469 +void hc_xfer_timeout(void *ptr)
24471 + hc_xfer_info_t *xfer_info = NULL;
24475 + xfer_info = (hc_xfer_info_t *) ptr;
24477 + if (!xfer_info->hc) {
24478 + DWC_ERROR("xfer_info->hc = %p\n", xfer_info->hc);
24482 + hc_num = xfer_info->hc->hc_num;
24483 + DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num);
24484 + DWC_WARN(" start_hcchar_val 0x%08x\n",
24485 + xfer_info->core_if->start_hcchar_val[hc_num]);
24489 +void ep_xfer_timeout(void *ptr)
24491 + ep_xfer_info_t *xfer_info = NULL;
24493 + dctl_data_t dctl = {.d32 = 0 };
24494 + gintsts_data_t gintsts = {.d32 = 0 };
24495 + gintmsk_data_t gintmsk = {.d32 = 0 };
24498 + xfer_info = (ep_xfer_info_t *) ptr;
24500 + if (!xfer_info->ep) {
24501 + DWC_ERROR("xfer_info->ep = %p\n", xfer_info->ep);
24505 + ep_num = xfer_info->ep->num;
24506 + DWC_WARN("%s: timeout on endpoit %d\n", __func__, ep_num);
24507 + /* Put the sate to 2 as it was time outed */
24508 + xfer_info->state = 2;
24511 + DWC_READ_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl);
24513 + DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintsts);
24515 + DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintmsk);
24517 + if (!gintmsk.b.goutnakeff) {
24519 + gintmsk.b.goutnakeff = 1;
24520 + DWC_WRITE_REG32(&xfer_info->core_if->core_global_regs->gintmsk,
24525 + if (!gintsts.b.goutnakeff) {
24526 + dctl.b.sgoutnak = 1;
24528 + DWC_WRITE_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl,
24533 +void set_pid_isoc(dwc_hc_t * hc)
24535 + /* Set up the initial PID for the transfer. */
24536 + if (hc->speed == DWC_OTG_EP_SPEED_HIGH) {
24537 + if (hc->ep_is_in) {
24538 + if (hc->multi_count == 1) {
24539 + hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
24540 + } else if (hc->multi_count == 2) {
24541 + hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
24543 + hc->data_pid_start = DWC_OTG_HC_PID_DATA2;
24546 + if (hc->multi_count == 1) {
24547 + hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
24549 + hc->data_pid_start = DWC_OTG_HC_PID_MDATA;
24553 + hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
24558 + * This function does the setup for a data transfer for a host channel and
24559 + * starts the transfer. May be called in either Slave mode or DMA mode. In
24560 + * Slave mode, the caller must ensure that there is sufficient space in the
24561 + * request queue and Tx Data FIFO.
24563 + * For an OUT transfer in Slave mode, it loads a data packet into the
24564 + * appropriate FIFO. If necessary, additional data packets will be loaded in
24567 + * For an IN transfer in Slave mode, a data packet is requested. The data
24568 + * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
24569 + * additional data packets are requested in the Host ISR.
24571 + * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
24572 + * register along with a packet count of 1 and the channel is enabled. This
24573 + * causes a single PING transaction to occur. Other fields in HCTSIZ are
24574 + * simply set to 0 since no data transfer occurs in this case.
24576 + * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
24577 + * all the information required to perform the subsequent data transfer. In
24578 + * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
24579 + * controller performs the entire PING protocol, then starts the data
24582 + * @param core_if Programming view of DWC_otg controller.
24583 + * @param hc Information needed to initialize the host channel. The xfer_len
24584 + * value may be reduced to accommodate the max widths of the XferSize and
24585 + * PktCnt fields in the HCTSIZn register. The multi_count value may be changed
24586 + * to reflect the final xfer_len value.
24588 +void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
24590 + hcchar_data_t hcchar;
24591 + hctsiz_data_t hctsiz;
24592 + uint16_t num_packets;
24593 + uint32_t max_hc_xfer_size = core_if->core_params->max_transfer_size;
24594 + uint16_t max_hc_pkt_count = core_if->core_params->max_packet_count;
24595 + dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
24599 + if (hc->do_ping) {
24600 + if (!core_if->dma_enable) {
24601 + dwc_otg_hc_do_ping(core_if, hc);
24602 + hc->xfer_started = 1;
24605 + hctsiz.b.dopng = 1;
24609 + if (hc->do_split) {
24612 + if (hc->complete_split && !hc->ep_is_in) {
24613 + /* For CSPLIT OUT Transfer, set the size to 0 so the
24614 + * core doesn't expect any data written to the FIFO */
24615 + hc->xfer_len = 0;
24616 + } else if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {
24617 + hc->xfer_len = hc->max_packet;
24618 + } else if (!hc->ep_is_in && (hc->xfer_len > 188)) {
24619 + hc->xfer_len = 188;
24622 + hctsiz.b.xfersize = hc->xfer_len;
24625 + * Ensure that the transfer length and packet count will fit
24626 + * in the widths allocated for them in the HCTSIZn register.
24628 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
24629 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
24631 + * Make sure the transfer size is no larger than one
24632 + * (micro)frame's worth of data. (A check was done
24633 + * when the periodic transfer was accepted to ensure
24634 + * that a (micro)frame's worth of data can be
24635 + * programmed into a channel.)
24637 + uint32_t max_periodic_len =
24638 + hc->multi_count * hc->max_packet;
24639 + if (hc->xfer_len > max_periodic_len) {
24640 + hc->xfer_len = max_periodic_len;
24643 + } else if (hc->xfer_len > max_hc_xfer_size) {
24644 + /* Make sure that xfer_len is a multiple of max packet size. */
24645 + hc->xfer_len = max_hc_xfer_size - hc->max_packet + 1;
24648 + if (hc->xfer_len > 0) {
24650 + (hc->xfer_len + hc->max_packet -
24651 + 1) / hc->max_packet;
24652 + if (num_packets > max_hc_pkt_count) {
24653 + num_packets = max_hc_pkt_count;
24654 + hc->xfer_len = num_packets * hc->max_packet;
24657 + /* Need 1 packet for transfer length of 0. */
24661 + if (hc->ep_is_in) {
24662 + /* Always program an integral # of max packets for IN transfers. */
24663 + hc->xfer_len = num_packets * hc->max_packet;
24666 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
24667 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
24669 + * Make sure that the multi_count field matches the
24670 + * actual transfer length.
24672 + hc->multi_count = num_packets;
24675 + if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
24676 + set_pid_isoc(hc);
24678 + hctsiz.b.xfersize = hc->xfer_len;
24681 + hc->start_pkt_count = num_packets;
24682 + hctsiz.b.pktcnt = num_packets;
24683 + hctsiz.b.pid = hc->data_pid_start;
24684 + DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
24686 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
24687 + DWC_DEBUGPL(DBG_HCDV, " Xfer Size: %d\n", hctsiz.b.xfersize);
24688 + DWC_DEBUGPL(DBG_HCDV, " Num Pkts: %d\n", hctsiz.b.pktcnt);
24689 + DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid);
24691 + if (core_if->dma_enable) {
24692 + dwc_dma_t dma_addr;
24693 + if (hc->align_buff) {
24694 + dma_addr = hc->align_buff;
24696 + dma_addr = ((unsigned long)hc->xfer_buff & 0xffffffff);
24698 + DWC_WRITE_REG32(&hc_regs->hcdma, dma_addr);
24701 + /* Start the split */
24702 + if (hc->do_split) {
24703 + hcsplt_data_t hcsplt;
24704 + hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
24705 + hcsplt.b.spltena = 1;
24706 + DWC_WRITE_REG32(&hc_regs->hcsplt, hcsplt.d32);
24709 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
24710 + hcchar.b.multicnt = hc->multi_count;
24711 + hc_set_even_odd_frame(core_if, hc, &hcchar);
24713 + core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
24714 + if (hcchar.b.chdis) {
24715 + DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
24716 + __func__, hc->hc_num, hcchar.d32);
24720 + /* Set host channel enable after all other setup is complete. */
24721 + hcchar.b.chen = 1;
24722 + hcchar.b.chdis = 0;
24723 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
24725 + hc->xfer_started = 1;
24728 + if (!core_if->dma_enable && !hc->ep_is_in && hc->xfer_len > 0) {
24729 + /* Load OUT packet into the appropriate Tx FIFO. */
24730 + dwc_otg_hc_write_packet(core_if, hc);
24733 + if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
24734 + DWC_DEBUGPL(DBG_HCDV, "transfer %d from core_if %p\n",
24735 + hc->hc_num, core_if);//GRAYG
24736 + core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
24737 + core_if->hc_xfer_info[hc->hc_num].hc = hc;
24739 + /* Start a timer for this transfer. */
24740 + DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
24746 + * This function does the setup for a data transfer for a host channel
24747 + * and starts the transfer in Descriptor DMA mode.
24749 + * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
24750 + * Sets PID and NTD values. For periodic transfers
24751 + * initializes SCHED_INFO field with micro-frame bitmap.
24753 + * Initializes HCDMA register with descriptor list address and CTD value
24754 + * then starts the transfer via enabling the channel.
24756 + * @param core_if Programming view of DWC_otg controller.
24757 + * @param hc Information needed to initialize the host channel.
24759 +void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
24761 + dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
24762 + hcchar_data_t hcchar;
24763 + hctsiz_data_t hctsiz;
24764 + hcdma_data_t hcdma;
24769 + hctsiz.b_ddma.dopng = 1;
24771 + if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
24772 + set_pid_isoc(hc);
24774 + /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
24775 + hctsiz.b_ddma.pid = hc->data_pid_start;
24776 + hctsiz.b_ddma.ntd = hc->ntd - 1; /* 0 - 1 descriptor, 1 - 2 descriptors, etc. */
24777 + hctsiz.b_ddma.schinfo = hc->schinfo; /* Non-zero only for high-speed interrupt endpoints */
24779 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
24780 + DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid);
24781 + DWC_DEBUGPL(DBG_HCDV, " NTD: %d\n", hctsiz.b_ddma.ntd);
24783 + DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
24786 + hcdma.b.dma_addr = ((uint32_t) hc->desc_list_addr) >> 11;
24788 + /* Always start from first descriptor. */
24790 + DWC_WRITE_REG32(&hc_regs->hcdma, hcdma.d32);
24792 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
24793 + hcchar.b.multicnt = hc->multi_count;
24796 + core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
24797 + if (hcchar.b.chdis) {
24798 + DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
24799 + __func__, hc->hc_num, hcchar.d32);
24803 + /* Set host channel enable after all other setup is complete. */
24804 + hcchar.b.chen = 1;
24805 + hcchar.b.chdis = 0;
24807 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
24809 + hc->xfer_started = 1;
24813 + if ((hc->ep_type != DWC_OTG_EP_TYPE_INTR)
24814 + && (hc->ep_type != DWC_OTG_EP_TYPE_ISOC)) {
24815 + DWC_DEBUGPL(DBG_HCDV, "DMA transfer %d from core_if %p\n",
24816 + hc->hc_num, core_if);//GRAYG
24817 + core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
24818 + core_if->hc_xfer_info[hc->hc_num].hc = hc;
24819 + /* Start a timer for this transfer. */
24820 + DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
24827 + * This function continues a data transfer that was started by previous call
24828 + * to <code>dwc_otg_hc_start_transfer</code>. The caller must ensure there is
24829 + * sufficient space in the request queue and Tx Data FIFO. This function
24830 + * should only be called in Slave mode. In DMA mode, the controller acts
24831 + * autonomously to complete transfers programmed to a host channel.
24833 + * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
24834 + * if there is any data remaining to be queued. For an IN transfer, another
24835 + * data packet is always requested. For the SETUP phase of a control transfer,
24836 + * this function does nothing.
24838 + * @return 1 if a new request is queued, 0 if no more requests are required
24839 + * for this transfer.
24841 +int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
24843 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
24845 + if (hc->do_split) {
24846 + /* SPLITs always queue just once per channel */
24848 + } else if (hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
24849 + /* SETUPs are queued only once since they can't be NAKed. */
24851 + } else if (hc->ep_is_in) {
24853 + * Always queue another request for other IN transfers. If
24854 + * back-to-back INs are issued and NAKs are received for both,
24855 + * the driver may still be processing the first NAK when the
24856 + * second NAK is received. When the interrupt handler clears
24857 + * the NAK interrupt for the first NAK, the second NAK will
24858 + * not be seen. So we can't depend on the NAK interrupt
24859 + * handler to requeue a NAKed request. Instead, IN requests
24860 + * are issued each time this function is called. When the
24861 + * transfer completes, the extra requests for the channel will
24864 + hcchar_data_t hcchar;
24865 + dwc_otg_hc_regs_t *hc_regs =
24866 + core_if->host_if->hc_regs[hc->hc_num];
24868 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
24869 + hc_set_even_odd_frame(core_if, hc, &hcchar);
24870 + hcchar.b.chen = 1;
24871 + hcchar.b.chdis = 0;
24872 + DWC_DEBUGPL(DBG_HCDV, " IN xfer: hcchar = 0x%08x\n",
24874 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
24878 + /* OUT transfers. */
24879 + if (hc->xfer_count < hc->xfer_len) {
24880 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
24881 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
24882 + hcchar_data_t hcchar;
24883 + dwc_otg_hc_regs_t *hc_regs;
24884 + hc_regs = core_if->host_if->hc_regs[hc->hc_num];
24885 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
24886 + hc_set_even_odd_frame(core_if, hc, &hcchar);
24889 + /* Load OUT packet into the appropriate Tx FIFO. */
24890 + dwc_otg_hc_write_packet(core_if, hc);
24900 + * Starts a PING transfer. This function should only be called in Slave mode.
24901 + * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled.
24903 +void dwc_otg_hc_do_ping(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
24905 + hcchar_data_t hcchar;
24906 + hctsiz_data_t hctsiz;
24907 + dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
24909 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
24912 + hctsiz.b.dopng = 1;
24913 + hctsiz.b.pktcnt = 1;
24914 + DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
24916 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
24917 + hcchar.b.chen = 1;
24918 + hcchar.b.chdis = 0;
24919 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
24923 + * This function writes a packet into the Tx FIFO associated with the Host
24924 + * Channel. For a channel associated with a non-periodic EP, the non-periodic
24925 + * Tx FIFO is written. For a channel associated with a periodic EP, the
24926 + * periodic Tx FIFO is written. This function should only be called in Slave
24929 + * Upon return the xfer_buff and xfer_count fields in _hc are incremented by
24930 + * then number of bytes written to the Tx FIFO.
24932 +void dwc_otg_hc_write_packet(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
24935 + uint32_t remaining_count;
24936 + uint32_t byte_count;
24937 + uint32_t dword_count;
24939 + uint32_t *data_buff = (uint32_t *) (hc->xfer_buff);
24940 + uint32_t *data_fifo = core_if->data_fifo[hc->hc_num];
24942 + remaining_count = hc->xfer_len - hc->xfer_count;
24943 + if (remaining_count > hc->max_packet) {
24944 + byte_count = hc->max_packet;
24946 + byte_count = remaining_count;
24949 + dword_count = (byte_count + 3) / 4;
24951 + if ((((unsigned long)data_buff) & 0x3) == 0) {
24952 + /* xfer_buff is DWORD aligned. */
24953 + for (i = 0; i < dword_count; i++, data_buff++) {
24954 + DWC_WRITE_REG32(data_fifo, *data_buff);
24957 + /* xfer_buff is not DWORD aligned. */
24958 + for (i = 0; i < dword_count; i++, data_buff++) {
24961 + (data_buff[0] | data_buff[1] << 8 | data_buff[2] <<
24962 + 16 | data_buff[3] << 24);
24963 + DWC_WRITE_REG32(data_fifo, data);
24967 + hc->xfer_count += byte_count;
24968 + hc->xfer_buff += byte_count;
24972 + * Gets the current USB frame number. This is the frame number from the last
24975 +uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * core_if)
24977 + dsts_data_t dsts;
24978 + dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
24980 + /* read current frame/microframe number from DSTS register */
24981 + return dsts.b.soffn;
24985 + * Calculates and gets the frame Interval value of HFIR register according PHY
24986 + * type and speed.The application can modify a value of HFIR register only after
24987 + * the Port Enable bit of the Host Port Control and Status register
24988 + * (HPRT.PrtEnaPort) has been set.
24991 +uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if)
24993 + gusbcfg_data_t usbcfg;
24994 + hwcfg2_data_t hwcfg2;
24995 + hprt0_data_t hprt0;
24996 + int clock = 60; // default value
24997 + usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
24998 + hwcfg2.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);
24999 + hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
25000 + if (!usbcfg.b.physel && usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)
25002 + if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 3)
25004 + if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
25005 + !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)
25007 + if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
25008 + !usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)
25010 + if (usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
25011 + !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)
25013 + if (usbcfg.b.physel && !usbcfg.b.phyif && hwcfg2.b.fs_phy_type == 2)
25015 + if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 1)
25017 + if (hprt0.b.prtspd == 0)
25018 + /* High speed case */
25019 + return 125 * clock - 1;
25022 + return 1000 * clock - 1;
25026 + * This function reads a setup packet from the Rx FIFO into the destination
25027 + * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl)
25028 + * Interrupt routine when a SETUP packet has been received in Slave mode.
25030 + * @param core_if Programming view of DWC_otg controller.
25031 + * @param dest Destination buffer for packet data.
25033 +void dwc_otg_read_setup_packet(dwc_otg_core_if_t * core_if, uint32_t * dest)
25035 + device_grxsts_data_t status;
25036 + /* Get the 8 bytes of a setup transaction data */
25038 + /* Pop 2 DWORDS off the receive data FIFO into memory */
25039 + dest[0] = DWC_READ_REG32(core_if->data_fifo[0]);
25040 + dest[1] = DWC_READ_REG32(core_if->data_fifo[0]);
25041 + if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
25043 + DWC_READ_REG32(&core_if->core_global_regs->grxstsp);
25044 + DWC_DEBUGPL(DBG_ANY,
25045 + "EP:%d BCnt:%d " "pktsts:%x Frame:%d(0x%0x)\n",
25046 + status.b.epnum, status.b.bcnt, status.b.pktsts,
25047 + status.b.fn, status.b.fn);
25052 + * This function enables EP0 OUT to receive SETUP packets and configures EP0
25053 + * IN for transmitting packets. It is normally called when the
25054 + * "Enumeration Done" interrupt occurs.
25056 + * @param core_if Programming view of DWC_otg controller.
25057 + * @param ep The EP0 data.
25059 +void dwc_otg_ep0_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
25061 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
25062 + dsts_data_t dsts;
25063 + depctl_data_t diepctl;
25064 + depctl_data_t doepctl;
25065 + dctl_data_t dctl = {.d32 = 0 };
25067 + ep->stp_rollover = 0;
25068 + /* Read the Device Status and Endpoint 0 Control registers */
25069 + dsts.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dsts);
25070 + diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
25071 + doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl);
25073 + /* Set the MPS of the IN EP based on the enumeration speed */
25074 + switch (dsts.b.enumspd) {
25075 + case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
25076 + case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
25077 + case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
25078 + diepctl.b.mps = DWC_DEP0CTL_MPS_64;
25080 + case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
25081 + diepctl.b.mps = DWC_DEP0CTL_MPS_8;
25085 + DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
25087 + /* Enable OUT EP for receive */
25088 + if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
25089 + doepctl.b.epena = 1;
25090 + DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
25093 + DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
25094 + DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
25095 + DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
25096 + DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl));
25098 + dctl.b.cgnpinnak = 1;
25100 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
25101 + DWC_DEBUGPL(DBG_PCDV, "dctl=%0x\n",
25102 + DWC_READ_REG32(&dev_if->dev_global_regs->dctl));
25107 + * This function activates an EP. The Device EP control register for
25108 + * the EP is configured as defined in the ep structure. Note: This
25109 + * function is not used for EP0.
25111 + * @param core_if Programming view of DWC_otg controller.
25112 + * @param ep The EP to activate.
25114 +void dwc_otg_ep_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
25116 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
25117 + depctl_data_t depctl;
25118 + volatile uint32_t *addr;
25119 + daint_data_t daintmsk = {.d32 = 0 };
25120 + dcfg_data_t dcfg;
25123 + DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, ep->num,
25124 + (ep->is_in ? "IN" : "OUT"));
25126 +#ifdef DWC_UTE_PER_IO
25127 + ep->xiso_frame_num = 0xFFFFFFFF;
25128 + ep->xiso_active_xfers = 0;
25129 + ep->xiso_queued_xfers = 0;
25131 + /* Read DEPCTLn register */
25132 + if (ep->is_in == 1) {
25133 + addr = &dev_if->in_ep_regs[ep->num]->diepctl;
25134 + daintmsk.ep.in = 1 << ep->num;
25136 + addr = &dev_if->out_ep_regs[ep->num]->doepctl;
25137 + daintmsk.ep.out = 1 << ep->num;
25140 + /* If the EP is already active don't change the EP Control
25142 + depctl.d32 = DWC_READ_REG32(addr);
25143 + if (!depctl.b.usbactep) {
25144 + depctl.b.mps = ep->maxpacket;
25145 + depctl.b.eptype = ep->type;
25146 + depctl.b.txfnum = ep->tx_fifo_num;
25148 + if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
25149 + depctl.b.setd0pid = 1; // ???
25151 + depctl.b.setd0pid = 1;
25153 + depctl.b.usbactep = 1;
25155 + /* Update nextep_seq array and EPMSCNT in DCFG*/
25156 + if (!(depctl.b.eptype & 1) && (ep->is_in == 1)) { // NP IN EP
25157 + for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
25158 + if (core_if->nextep_seq[i] == core_if->first_in_nextep_seq)
25161 + core_if->nextep_seq[i] = ep->num;
25162 + core_if->nextep_seq[ep->num] = core_if->first_in_nextep_seq;
25163 + depctl.b.nextep = core_if->nextep_seq[ep->num];
25164 + dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
25165 + dcfg.b.epmscnt++;
25166 + DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
25168 + DWC_DEBUGPL(DBG_PCDV,
25169 + "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
25170 + __func__, core_if->first_in_nextep_seq);
25171 + for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
25172 + DWC_DEBUGPL(DBG_PCDV, "%2d\n",
25173 + core_if->nextep_seq[i]);
25179 + DWC_WRITE_REG32(addr, depctl.d32);
25180 + DWC_DEBUGPL(DBG_PCDV, "DEPCTL=%08x\n", DWC_READ_REG32(addr));
25183 + /* Enable the Interrupt for this EP */
25184 + if (core_if->multiproc_int_enable) {
25185 + if (ep->is_in == 1) {
25186 + diepmsk_data_t diepmsk = {.d32 = 0 };
25187 + diepmsk.b.xfercompl = 1;
25188 + diepmsk.b.timeout = 1;
25189 + diepmsk.b.epdisabled = 1;
25190 + diepmsk.b.ahberr = 1;
25191 + diepmsk.b.intknepmis = 1;
25192 + if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
25193 + diepmsk.b.intknepmis = 0;
25194 + diepmsk.b.txfifoundrn = 1; //?????
25195 + if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
25196 + diepmsk.b.nak = 1;
25202 + if (core_if->dma_desc_enable) {
25203 + diepmsk.b.bna = 1;
25207 + if (core_if->dma_enable) {
25208 + doepmsk.b.nak = 1;
25211 + DWC_WRITE_REG32(&dev_if->dev_global_regs->
25212 + diepeachintmsk[ep->num], diepmsk.d32);
25215 + doepmsk_data_t doepmsk = {.d32 = 0 };
25216 + doepmsk.b.xfercompl = 1;
25217 + doepmsk.b.ahberr = 1;
25218 + doepmsk.b.epdisabled = 1;
25219 + if (ep->type == DWC_OTG_EP_TYPE_ISOC)
25220 + doepmsk.b.outtknepdis = 1;
25224 + if (core_if->dma_desc_enable) {
25225 + doepmsk.b.bna = 1;
25229 + doepmsk.b.babble = 1;
25230 + doepmsk.b.nyet = 1;
25231 + doepmsk.b.nak = 1;
25233 + DWC_WRITE_REG32(&dev_if->dev_global_regs->
25234 + doepeachintmsk[ep->num], doepmsk.d32);
25236 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->deachintmsk,
25237 + 0, daintmsk.d32);
25239 + if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
25241 + diepmsk_data_t diepmsk = {.d32 = 0 };
25242 + diepmsk.b.nak = 1;
25243 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk, 0, diepmsk.d32);
25245 + doepmsk_data_t doepmsk = {.d32 = 0 };
25246 + doepmsk.b.outtknepdis = 1;
25247 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->doepmsk, 0, doepmsk.d32);
25250 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->daintmsk,
25251 + 0, daintmsk.d32);
25254 + DWC_DEBUGPL(DBG_PCDV, "DAINTMSK=%0x\n",
25255 + DWC_READ_REG32(&dev_if->dev_global_regs->daintmsk));
25257 + ep->stall_clear_flag = 0;
25263 + * This function deactivates an EP. This is done by clearing the USB Active
25264 + * EP bit in the Device EP control register. Note: This function is not used
25265 + * for EP0. EP0 cannot be deactivated.
25267 + * @param core_if Programming view of DWC_otg controller.
25268 + * @param ep The EP to deactivate.
25270 +void dwc_otg_ep_deactivate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
25272 + depctl_data_t depctl = {.d32 = 0 };
25273 + volatile uint32_t *addr;
25274 + daint_data_t daintmsk = {.d32 = 0 };
25275 + dcfg_data_t dcfg;
25278 +#ifdef DWC_UTE_PER_IO
25279 + ep->xiso_frame_num = 0xFFFFFFFF;
25280 + ep->xiso_active_xfers = 0;
25281 + ep->xiso_queued_xfers = 0;
25284 + /* Read DEPCTLn register */
25285 + if (ep->is_in == 1) {
25286 + addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
25287 + daintmsk.ep.in = 1 << ep->num;
25289 + addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
25290 + daintmsk.ep.out = 1 << ep->num;
25293 + depctl.d32 = DWC_READ_REG32(addr);
25295 + depctl.b.usbactep = 0;
25297 + /* Update nextep_seq array and EPMSCNT in DCFG*/
25298 + if (!(depctl.b.eptype & 1) && ep->is_in == 1) { // NP EP IN
25299 + for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
25300 + if (core_if->nextep_seq[i] == ep->num)
25303 + core_if->nextep_seq[i] = core_if->nextep_seq[ep->num];
25304 + if (core_if->first_in_nextep_seq == ep->num)
25305 + core_if->first_in_nextep_seq = i;
25306 + core_if->nextep_seq[ep->num] = 0xff;
25307 + depctl.b.nextep = 0;
25309 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
25310 + dcfg.b.epmscnt--;
25311 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
25314 + DWC_DEBUGPL(DBG_PCDV,
25315 + "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
25316 + __func__, core_if->first_in_nextep_seq);
25317 + for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
25318 + DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]);
25322 + if (ep->is_in == 1)
25323 + depctl.b.txfnum = 0;
25325 + if (core_if->dma_desc_enable)
25326 + depctl.b.epdis = 1;
25328 + DWC_WRITE_REG32(addr, depctl.d32);
25329 + depctl.d32 = DWC_READ_REG32(addr);
25330 + if (core_if->dma_enable && ep->type == DWC_OTG_EP_TYPE_ISOC
25331 + && depctl.b.epena) {
25332 + depctl_data_t depctl = {.d32 = 0};
25334 + diepint_data_t diepint = {.d32 = 0};
25336 + depctl.b.snak = 1;
25337 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
25338 + diepctl, depctl.d32);
25342 + DWC_READ_REG32(&core_if->
25343 + dev_if->in_ep_regs[ep->num]->
25345 + } while (!diepint.b.inepnakeff);
25346 + diepint.b.inepnakeff = 1;
25347 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
25348 + diepint, diepint.d32);
25350 + depctl.b.epdis = 1;
25351 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
25352 + diepctl, depctl.d32);
25356 + DWC_READ_REG32(&core_if->
25357 + dev_if->in_ep_regs[ep->num]->
25359 + } while (!diepint.b.epdisabled);
25360 + diepint.b.epdisabled = 1;
25361 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
25362 + diepint, diepint.d32);
25364 + dctl_data_t dctl = {.d32 = 0};
25365 + gintmsk_data_t gintsts = {.d32 = 0};
25366 + doepint_data_t doepint = {.d32 = 0};
25367 + dctl.b.sgoutnak = 1;
25368 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
25369 + dctl, 0, dctl.d32);
25372 + gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
25373 + } while (!gintsts.b.goutnakeff);
25375 + gintsts.b.goutnakeff = 1;
25376 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
25379 + depctl.b.epdis = 1;
25380 + depctl.b.snak = 1;
25381 + DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepctl, depctl.d32);
25385 + doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
25386 + out_ep_regs[ep->num]->doepint);
25387 + } while (!doepint.b.epdisabled);
25389 + doepint.b.epdisabled = 1;
25390 + DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepint, doepint.d32);
25393 + dctl.b.cgoutnak = 1;
25394 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
25398 + /* Disable the Interrupt for this EP */
25399 + if (core_if->multiproc_int_enable) {
25400 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->deachintmsk,
25401 + daintmsk.d32, 0);
25403 + if (ep->is_in == 1) {
25404 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
25405 + diepeachintmsk[ep->num], 0);
25407 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
25408 + doepeachintmsk[ep->num], 0);
25411 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->daintmsk,
25412 + daintmsk.d32, 0);
25418 + * This function initializes dma descriptor chain.
25420 + * @param core_if Programming view of DWC_otg controller.
25421 + * @param ep The EP to start the transfer on.
25423 +static void init_dma_desc_chain(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
25425 + dwc_otg_dev_dma_desc_t *dma_desc;
25427 + uint32_t xfer_est;
25429 + unsigned maxxfer_local, total_len;
25431 + if (!ep->is_in && ep->type == DWC_OTG_EP_TYPE_INTR &&
25432 + (ep->maxpacket%4)) {
25433 + maxxfer_local = ep->maxpacket;
25434 + total_len = ep->xfer_len;
25436 + maxxfer_local = ep->maxxfer;
25437 + total_len = ep->total_len;
25440 + ep->desc_cnt = (total_len / maxxfer_local) +
25441 + ((total_len % maxxfer_local) ? 1 : 0);
25443 + if (!ep->desc_cnt)
25444 + ep->desc_cnt = 1;
25446 + if (ep->desc_cnt > MAX_DMA_DESC_CNT)
25447 + ep->desc_cnt = MAX_DMA_DESC_CNT;
25449 + dma_desc = ep->desc_addr;
25450 + if (maxxfer_local == ep->maxpacket) {
25451 + if ((total_len % maxxfer_local) &&
25452 + (total_len/maxxfer_local < MAX_DMA_DESC_CNT)) {
25453 + xfer_est = (ep->desc_cnt - 1) * maxxfer_local +
25454 + (total_len % maxxfer_local);
25456 + xfer_est = ep->desc_cnt * maxxfer_local;
25458 + xfer_est = total_len;
25460 + for (i = 0; i < ep->desc_cnt; ++i) {
25461 + /** DMA Descriptor Setup */
25462 + if (xfer_est > maxxfer_local) {
25463 + dma_desc->status.b.bs = BS_HOST_BUSY;
25464 + dma_desc->status.b.l = 0;
25465 + dma_desc->status.b.ioc = 0;
25466 + dma_desc->status.b.sp = 0;
25467 + dma_desc->status.b.bytes = maxxfer_local;
25468 + dma_desc->buf = ep->dma_addr + offset;
25469 + dma_desc->status.b.sts = 0;
25470 + dma_desc->status.b.bs = BS_HOST_READY;
25472 + xfer_est -= maxxfer_local;
25473 + offset += maxxfer_local;
25475 + dma_desc->status.b.bs = BS_HOST_BUSY;
25476 + dma_desc->status.b.l = 1;
25477 + dma_desc->status.b.ioc = 1;
25479 + dma_desc->status.b.sp =
25481 + ep->maxpacket) ? 1 : ((ep->
25482 + sent_zlp) ? 1 : 0);
25483 + dma_desc->status.b.bytes = xfer_est;
25485 + if (maxxfer_local == ep->maxpacket)
25486 + dma_desc->status.b.bytes = xfer_est;
25488 + dma_desc->status.b.bytes =
25489 + xfer_est + ((4 - (xfer_est & 0x3)) & 0x3);
25492 + dma_desc->buf = ep->dma_addr + offset;
25493 + dma_desc->status.b.sts = 0;
25494 + dma_desc->status.b.bs = BS_HOST_READY;
25500 + * This function is called when to write ISOC data into appropriate dedicated
25503 +static int32_t write_isoc_tx_fifo(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep)
25505 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
25506 + dwc_otg_dev_in_ep_regs_t *ep_regs;
25507 + dtxfsts_data_t txstatus = {.d32 = 0 };
25508 + uint32_t len = 0;
25509 + int epnum = dwc_ep->num;
25512 + DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum);
25514 + ep_regs = core_if->dev_if->in_ep_regs[epnum];
25516 + len = dwc_ep->xfer_len - dwc_ep->xfer_count;
25518 + if (len > dwc_ep->maxpacket) {
25519 + len = dwc_ep->maxpacket;
25522 + dwords = (len + 3) / 4;
25524 + /* While there is space in the queue and space in the FIFO and
25525 + * More data to tranfer, Write packets to the Tx FIFO */
25526 + txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
25527 + DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
25529 + while (txstatus.b.txfspcavail > dwords &&
25530 + dwc_ep->xfer_count < dwc_ep->xfer_len && dwc_ep->xfer_len != 0) {
25531 + /* Write the FIFO */
25532 + dwc_otg_ep_write_packet(core_if, dwc_ep, 0);
25534 + len = dwc_ep->xfer_len - dwc_ep->xfer_count;
25535 + if (len > dwc_ep->maxpacket) {
25536 + len = dwc_ep->maxpacket;
25539 + dwords = (len + 3) / 4;
25541 + DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
25542 + DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum,
25546 + DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum,
25547 + DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts));
25552 + * This function does the setup for a data transfer for an EP and
25553 + * starts the transfer. For an IN transfer, the packets will be
25554 + * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
25555 + * the packets are unloaded from the Rx FIFO in the ISR. the ISR.
25557 + * @param core_if Programming view of DWC_otg controller.
25558 + * @param ep The EP to start the transfer on.
25561 +void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
25563 + depctl_data_t depctl;
25564 + deptsiz_data_t deptsiz;
25565 + gintmsk_data_t intr_mask = {.d32 = 0 };
25567 + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
25568 + DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
25569 + "xfer_buff=%p start_xfer_buff=%p, total_len = %d\n",
25570 + ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
25571 + ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff,
25573 + /* IN endpoint */
25574 + if (ep->is_in == 1) {
25575 + dwc_otg_dev_in_ep_regs_t *in_regs =
25576 + core_if->dev_if->in_ep_regs[ep->num];
25578 + gnptxsts_data_t gtxstatus;
25581 + DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
25583 + if (core_if->en_multiple_tx_fifo == 0
25584 + && gtxstatus.b.nptxqspcavail == 0 && !core_if->dma_enable) {
25586 + DWC_PRINTF("TX Queue Full (0x%0x)\n", gtxstatus.d32);
25591 + depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));
25592 + deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));
25594 + if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
25595 + ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
25596 + ep->maxxfer : (ep->total_len - ep->xfer_len);
25598 + ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len - ep->xfer_len)) ?
25599 + MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len);
25602 + /* Zero Length Packet? */
25603 + if ((ep->xfer_len - ep->xfer_count) == 0) {
25604 + deptsiz.b.xfersize = 0;
25605 + deptsiz.b.pktcnt = 1;
25607 + /* Program the transfer size and packet count
25608 + * as follows: xfersize = N * maxpacket +
25609 + * short_packet pktcnt = N + (short_packet
25612 + deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
25613 + deptsiz.b.pktcnt =
25614 + (ep->xfer_len - ep->xfer_count - 1 +
25615 + ep->maxpacket) / ep->maxpacket;
25616 + if (deptsiz.b.pktcnt > MAX_PKT_CNT) {
25617 + deptsiz.b.pktcnt = MAX_PKT_CNT;
25618 + deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
25620 + if (ep->type == DWC_OTG_EP_TYPE_ISOC)
25621 + deptsiz.b.mc = deptsiz.b.pktcnt;
25624 + /* Write the DMA register */
25625 + if (core_if->dma_enable) {
25626 + if (core_if->dma_desc_enable == 0) {
25627 + if (ep->type != DWC_OTG_EP_TYPE_ISOC)
25628 + deptsiz.b.mc = 1;
25629 + DWC_WRITE_REG32(&in_regs->dieptsiz,
25631 + DWC_WRITE_REG32(&(in_regs->diepdma),
25632 + (uint32_t) ep->dma_addr);
25634 +#ifdef DWC_UTE_CFI
25635 + /* The descriptor chain should be already initialized by now */
25636 + if (ep->buff_mode != BM_STANDARD) {
25637 + DWC_WRITE_REG32(&in_regs->diepdma,
25638 + ep->descs_dma_addr);
25641 + init_dma_desc_chain(core_if, ep);
25642 + /** DIEPDMAn Register write */
25643 + DWC_WRITE_REG32(&in_regs->diepdma,
25644 + ep->dma_desc_addr);
25645 +#ifdef DWC_UTE_CFI
25650 + DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
25651 + if (ep->type != DWC_OTG_EP_TYPE_ISOC) {
25653 + * Enable the Non-Periodic Tx FIFO empty interrupt,
25654 + * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
25655 + * the data will be written into the fifo by the ISR.
25657 + if (core_if->en_multiple_tx_fifo == 0) {
25658 + intr_mask.b.nptxfempty = 1;
25660 + (&core_if->core_global_regs->gintmsk,
25661 + intr_mask.d32, intr_mask.d32);
25663 + /* Enable the Tx FIFO Empty Interrupt for this EP */
25664 + if (ep->xfer_len > 0) {
25665 + uint32_t fifoemptymsk = 0;
25666 + fifoemptymsk = 1 << ep->num;
25668 + (&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
25669 + 0, fifoemptymsk);
25674 + write_isoc_tx_fifo(core_if, ep);
25677 + if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
25678 + depctl.b.nextep = core_if->nextep_seq[ep->num];
25680 + if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
25681 + dsts_data_t dsts = {.d32 = 0};
25682 + if (ep->bInterval == 1) {
25684 + DWC_READ_REG32(&core_if->dev_if->
25685 + dev_global_regs->dsts);
25686 + ep->frame_num = dsts.b.soffn + ep->bInterval;
25687 + if (ep->frame_num > 0x3FFF) {
25688 + ep->frm_overrun = 1;
25689 + ep->frame_num &= 0x3FFF;
25691 + ep->frm_overrun = 0;
25692 + if (ep->frame_num & 0x1) {
25693 + depctl.b.setd1pid = 1;
25695 + depctl.b.setd0pid = 1;
25699 + /* EP enable, IN data in FIFO */
25700 + depctl.b.cnak = 1;
25701 + depctl.b.epena = 1;
25702 + DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
25705 + /* OUT endpoint */
25706 + dwc_otg_dev_out_ep_regs_t *out_regs =
25707 + core_if->dev_if->out_ep_regs[ep->num];
25709 + depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));
25710 + deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));
25712 + if (!core_if->dma_desc_enable) {
25713 + if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
25714 + ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
25715 + ep->maxxfer : (ep->total_len - ep->xfer_len);
25717 + ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len
25718 + - ep->xfer_len)) ? MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len);
25721 + /* Program the transfer size and packet count as follows:
25724 + * xfersize = N * maxpacket
25726 + if ((ep->xfer_len - ep->xfer_count) == 0) {
25727 + /* Zero Length Packet */
25728 + deptsiz.b.xfersize = ep->maxpacket;
25729 + deptsiz.b.pktcnt = 1;
25731 + deptsiz.b.pktcnt =
25732 + (ep->xfer_len - ep->xfer_count +
25733 + (ep->maxpacket - 1)) / ep->maxpacket;
25734 + if (deptsiz.b.pktcnt > MAX_PKT_CNT) {
25735 + deptsiz.b.pktcnt = MAX_PKT_CNT;
25737 + if (!core_if->dma_desc_enable) {
25739 + deptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count;
25741 + deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
25744 + DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n",
25745 + ep->num, deptsiz.b.xfersize, deptsiz.b.pktcnt);
25747 + if (core_if->dma_enable) {
25748 + if (!core_if->dma_desc_enable) {
25749 + DWC_WRITE_REG32(&out_regs->doeptsiz,
25752 + DWC_WRITE_REG32(&(out_regs->doepdma),
25753 + (uint32_t) ep->dma_addr);
25755 +#ifdef DWC_UTE_CFI
25756 + /* The descriptor chain should be already initialized by now */
25757 + if (ep->buff_mode != BM_STANDARD) {
25758 + DWC_WRITE_REG32(&out_regs->doepdma,
25759 + ep->descs_dma_addr);
25762 + /** This is used for interrupt out transfers*/
25763 + if (!ep->xfer_len)
25764 + ep->xfer_len = ep->total_len;
25765 + init_dma_desc_chain(core_if, ep);
25767 + if (core_if->core_params->dev_out_nak) {
25768 + if (ep->type == DWC_OTG_EP_TYPE_BULK) {
25769 + deptsiz.b.pktcnt = (ep->total_len +
25770 + (ep->maxpacket - 1)) / ep->maxpacket;
25771 + deptsiz.b.xfersize = ep->total_len;
25772 + /* Remember initial value of doeptsiz */
25773 + core_if->start_doeptsiz_val[ep->num] = deptsiz.d32;
25774 + DWC_WRITE_REG32(&out_regs->doeptsiz,
25778 + /** DOEPDMAn Register write */
25779 + DWC_WRITE_REG32(&out_regs->doepdma,
25780 + ep->dma_desc_addr);
25781 +#ifdef DWC_UTE_CFI
25786 + DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
25789 + if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
25790 + dsts_data_t dsts = {.d32 = 0};
25791 + if (ep->bInterval == 1) {
25793 + DWC_READ_REG32(&core_if->dev_if->
25794 + dev_global_regs->dsts);
25795 + ep->frame_num = dsts.b.soffn + ep->bInterval;
25796 + if (ep->frame_num > 0x3FFF) {
25797 + ep->frm_overrun = 1;
25798 + ep->frame_num &= 0x3FFF;
25800 + ep->frm_overrun = 0;
25802 + if (ep->frame_num & 0x1) {
25803 + depctl.b.setd1pid = 1;
25805 + depctl.b.setd0pid = 1;
25811 + depctl.b.cnak = 1;
25812 + depctl.b.epena = 1;
25814 + DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
25816 + DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n",
25817 + DWC_READ_REG32(&out_regs->doepctl),
25818 + DWC_READ_REG32(&out_regs->doeptsiz));
25819 + DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
25820 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->
25822 + DWC_READ_REG32(&core_if->core_global_regs->
25825 + /* Timer is scheduling only for out bulk transfers for
25826 + * "Device DDMA OUT NAK Enhancement" feature to inform user
25827 + * about received data payload in case of timeout
25829 + if (core_if->core_params->dev_out_nak) {
25830 + if (ep->type == DWC_OTG_EP_TYPE_BULK) {
25831 + core_if->ep_xfer_info[ep->num].core_if = core_if;
25832 + core_if->ep_xfer_info[ep->num].ep = ep;
25833 + core_if->ep_xfer_info[ep->num].state = 1;
25835 + /* Start a timer for this transfer. */
25836 + DWC_TIMER_SCHEDULE(core_if->ep_xfer_timer[ep->num], 10000);
25843 + * This function setup a zero length transfer in Buffer DMA and
25844 + * Slave modes for usb requests with zero field set
25846 + * @param core_if Programming view of DWC_otg controller.
25847 + * @param ep The EP to start the transfer on.
25850 +void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
25853 + depctl_data_t depctl;
25854 + deptsiz_data_t deptsiz;
25855 + gintmsk_data_t intr_mask = {.d32 = 0 };
25857 + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
25858 + DWC_PRINTF("zero length transfer is called\n");
25860 + /* IN endpoint */
25861 + if (ep->is_in == 1) {
25862 + dwc_otg_dev_in_ep_regs_t *in_regs =
25863 + core_if->dev_if->in_ep_regs[ep->num];
25865 + depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));
25866 + deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));
25868 + deptsiz.b.xfersize = 0;
25869 + deptsiz.b.pktcnt = 1;
25871 + /* Write the DMA register */
25872 + if (core_if->dma_enable) {
25873 + if (core_if->dma_desc_enable == 0) {
25874 + deptsiz.b.mc = 1;
25875 + DWC_WRITE_REG32(&in_regs->dieptsiz,
25877 + DWC_WRITE_REG32(&(in_regs->diepdma),
25878 + (uint32_t) ep->dma_addr);
25881 + DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
25883 + * Enable the Non-Periodic Tx FIFO empty interrupt,
25884 + * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
25885 + * the data will be written into the fifo by the ISR.
25887 + if (core_if->en_multiple_tx_fifo == 0) {
25888 + intr_mask.b.nptxfempty = 1;
25889 + DWC_MODIFY_REG32(&core_if->
25890 + core_global_regs->gintmsk,
25891 + intr_mask.d32, intr_mask.d32);
25893 + /* Enable the Tx FIFO Empty Interrupt for this EP */
25894 + if (ep->xfer_len > 0) {
25895 + uint32_t fifoemptymsk = 0;
25896 + fifoemptymsk = 1 << ep->num;
25897 + DWC_MODIFY_REG32(&core_if->
25898 + dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
25899 + 0, fifoemptymsk);
25904 + if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
25905 + depctl.b.nextep = core_if->nextep_seq[ep->num];
25906 + /* EP enable, IN data in FIFO */
25907 + depctl.b.cnak = 1;
25908 + depctl.b.epena = 1;
25909 + DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
25912 + /* OUT endpoint */
25913 + dwc_otg_dev_out_ep_regs_t *out_regs =
25914 + core_if->dev_if->out_ep_regs[ep->num];
25916 + depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));
25917 + deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));
25919 + /* Zero Length Packet */
25920 + deptsiz.b.xfersize = ep->maxpacket;
25921 + deptsiz.b.pktcnt = 1;
25923 + if (core_if->dma_enable) {
25924 + if (!core_if->dma_desc_enable) {
25925 + DWC_WRITE_REG32(&out_regs->doeptsiz,
25928 + DWC_WRITE_REG32(&(out_regs->doepdma),
25929 + (uint32_t) ep->dma_addr);
25932 + DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
25936 + depctl.b.cnak = 1;
25937 + depctl.b.epena = 1;
25939 + DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
25945 + * This function does the setup for a data transfer for EP0 and starts
25946 + * the transfer. For an IN transfer, the packets will be loaded into
25947 + * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are
25948 + * unloaded from the Rx FIFO in the ISR.
25950 + * @param core_if Programming view of DWC_otg controller.
25951 + * @param ep The EP0 data.
25953 +void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
25955 + depctl_data_t depctl;
25956 + deptsiz0_data_t deptsiz;
25957 + gintmsk_data_t intr_mask = {.d32 = 0 };
25958 + dwc_otg_dev_dma_desc_t *dma_desc;
25960 + DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
25961 + "xfer_buff=%p start_xfer_buff=%p \n",
25962 + ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
25963 + ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff);
25965 + ep->total_len = ep->xfer_len;
25967 + /* IN endpoint */
25968 + if (ep->is_in == 1) {
25969 + dwc_otg_dev_in_ep_regs_t *in_regs =
25970 + core_if->dev_if->in_ep_regs[0];
25972 + gnptxsts_data_t gtxstatus;
25974 + if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
25975 + depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
25976 + if (depctl.b.epena)
25981 + DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
25983 + /* If dedicated FIFO every time flush fifo before enable ep*/
25984 + if (core_if->en_multiple_tx_fifo && core_if->snpsid >= OTG_CORE_REV_3_00a)
25985 + dwc_otg_flush_tx_fifo(core_if, ep->tx_fifo_num);
25987 + if (core_if->en_multiple_tx_fifo == 0
25988 + && gtxstatus.b.nptxqspcavail == 0
25989 + && !core_if->dma_enable) {
25991 + deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
25992 + DWC_DEBUGPL(DBG_PCD, "DIEPCTL0=%0x\n",
25993 + DWC_READ_REG32(&in_regs->diepctl));
25994 + DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n",
25996 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
25997 + DWC_PRINTF("TX Queue or FIFO Full (0x%0x)\n",
26003 + depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
26004 + deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
26006 + /* Zero Length Packet? */
26007 + if (ep->xfer_len == 0) {
26008 + deptsiz.b.xfersize = 0;
26009 + deptsiz.b.pktcnt = 1;
26011 + /* Program the transfer size and packet count
26012 + * as follows: xfersize = N * maxpacket +
26013 + * short_packet pktcnt = N + (short_packet
26016 + if (ep->xfer_len > ep->maxpacket) {
26017 + ep->xfer_len = ep->maxpacket;
26018 + deptsiz.b.xfersize = ep->maxpacket;
26020 + deptsiz.b.xfersize = ep->xfer_len;
26022 + deptsiz.b.pktcnt = 1;
26025 + DWC_DEBUGPL(DBG_PCDV,
26026 + "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
26027 + ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
26030 + /* Write the DMA register */
26031 + if (core_if->dma_enable) {
26032 + if (core_if->dma_desc_enable == 0) {
26033 + DWC_WRITE_REG32(&in_regs->dieptsiz,
26036 + DWC_WRITE_REG32(&(in_regs->diepdma),
26037 + (uint32_t) ep->dma_addr);
26039 + dma_desc = core_if->dev_if->in_desc_addr;
26041 + /** DMA Descriptor Setup */
26042 + dma_desc->status.b.bs = BS_HOST_BUSY;
26043 + dma_desc->status.b.l = 1;
26044 + dma_desc->status.b.ioc = 1;
26045 + dma_desc->status.b.sp =
26046 + (ep->xfer_len == ep->maxpacket) ? 0 : 1;
26047 + dma_desc->status.b.bytes = ep->xfer_len;
26048 + dma_desc->buf = ep->dma_addr;
26049 + dma_desc->status.b.sts = 0;
26050 + dma_desc->status.b.bs = BS_HOST_READY;
26052 + /** DIEPDMA0 Register write */
26053 + DWC_WRITE_REG32(&in_regs->diepdma,
26055 + dev_if->dma_in_desc_addr);
26058 + DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
26061 + if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
26062 + depctl.b.nextep = core_if->nextep_seq[ep->num];
26063 + /* EP enable, IN data in FIFO */
26064 + depctl.b.cnak = 1;
26065 + depctl.b.epena = 1;
26066 + DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
26069 + * Enable the Non-Periodic Tx FIFO empty interrupt, the
26070 + * data will be written into the fifo by the ISR.
26072 + if (!core_if->dma_enable) {
26073 + if (core_if->en_multiple_tx_fifo == 0) {
26074 + intr_mask.b.nptxfempty = 1;
26075 + DWC_MODIFY_REG32(&core_if->
26076 + core_global_regs->gintmsk,
26077 + intr_mask.d32, intr_mask.d32);
26079 + /* Enable the Tx FIFO Empty Interrupt for this EP */
26080 + if (ep->xfer_len > 0) {
26081 + uint32_t fifoemptymsk = 0;
26082 + fifoemptymsk |= 1 << ep->num;
26083 + DWC_MODIFY_REG32(&core_if->
26084 + dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
26085 + 0, fifoemptymsk);
26090 + /* OUT endpoint */
26091 + dwc_otg_dev_out_ep_regs_t *out_regs =
26092 + core_if->dev_if->out_ep_regs[0];
26094 + depctl.d32 = DWC_READ_REG32(&out_regs->doepctl);
26095 + deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);
26097 + /* Program the transfer size and packet count as follows:
26098 + * xfersize = N * (maxpacket + 4 - (maxpacket % 4))
26100 + /* Zero Length Packet */
26101 + deptsiz.b.xfersize = ep->maxpacket;
26102 + deptsiz.b.pktcnt = 1;
26103 + if (core_if->snpsid >= OTG_CORE_REV_3_00a)
26104 + deptsiz.b.supcnt = 3;
26106 + DWC_DEBUGPL(DBG_PCDV, "len=%d xfersize=%d pktcnt=%d\n",
26107 + ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt);
26109 + if (core_if->dma_enable) {
26110 + if (!core_if->dma_desc_enable) {
26111 + DWC_WRITE_REG32(&out_regs->doeptsiz,
26114 + DWC_WRITE_REG32(&(out_regs->doepdma),
26115 + (uint32_t) ep->dma_addr);
26117 + dma_desc = core_if->dev_if->out_desc_addr;
26119 + /** DMA Descriptor Setup */
26120 + dma_desc->status.b.bs = BS_HOST_BUSY;
26121 + if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
26122 + dma_desc->status.b.mtrf = 0;
26123 + dma_desc->status.b.sr = 0;
26125 + dma_desc->status.b.l = 1;
26126 + dma_desc->status.b.ioc = 1;
26127 + dma_desc->status.b.bytes = ep->maxpacket;
26128 + dma_desc->buf = ep->dma_addr;
26129 + dma_desc->status.b.sts = 0;
26130 + dma_desc->status.b.bs = BS_HOST_READY;
26132 + /** DOEPDMA0 Register write */
26133 + DWC_WRITE_REG32(&out_regs->doepdma,
26134 + core_if->dev_if->
26135 + dma_out_desc_addr);
26138 + DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
26142 + depctl.b.cnak = 1;
26143 + depctl.b.epena = 1;
26144 + DWC_WRITE_REG32(&(out_regs->doepctl), depctl.d32);
26149 + * This function continues control IN transfers started by
26150 + * dwc_otg_ep0_start_transfer, when the transfer does not fit in a
26151 + * single packet. NOTE: The DIEPCTL0/DOEPCTL0 registers only have one
26152 + * bit for the packet count.
26154 + * @param core_if Programming view of DWC_otg controller.
26155 + * @param ep The EP0 data.
26157 +void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
26159 + depctl_data_t depctl;
26160 + deptsiz0_data_t deptsiz;
26161 + gintmsk_data_t intr_mask = {.d32 = 0 };
26162 + dwc_otg_dev_dma_desc_t *dma_desc;
26164 + if (ep->is_in == 1) {
26165 + dwc_otg_dev_in_ep_regs_t *in_regs =
26166 + core_if->dev_if->in_ep_regs[0];
26167 + gnptxsts_data_t tx_status = {.d32 = 0 };
26170 + DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
26171 + /** @todo Should there be check for room in the Tx
26172 + * Status Queue. If not remove the code above this comment. */
26174 + depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
26175 + deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
26177 + /* Program the transfer size and packet count
26178 + * as follows: xfersize = N * maxpacket +
26179 + * short_packet pktcnt = N + (short_packet
26183 + if (core_if->dma_desc_enable == 0) {
26184 + deptsiz.b.xfersize =
26185 + (ep->total_len - ep->xfer_count) >
26186 + ep->maxpacket ? ep->maxpacket : (ep->total_len -
26188 + deptsiz.b.pktcnt = 1;
26189 + if (core_if->dma_enable == 0) {
26190 + ep->xfer_len += deptsiz.b.xfersize;
26192 + ep->xfer_len = deptsiz.b.xfersize;
26194 + DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
26197 + (ep->total_len - ep->xfer_count) >
26198 + ep->maxpacket ? ep->maxpacket : (ep->total_len -
26201 + dma_desc = core_if->dev_if->in_desc_addr;
26203 + /** DMA Descriptor Setup */
26204 + dma_desc->status.b.bs = BS_HOST_BUSY;
26205 + dma_desc->status.b.l = 1;
26206 + dma_desc->status.b.ioc = 1;
26207 + dma_desc->status.b.sp =
26208 + (ep->xfer_len == ep->maxpacket) ? 0 : 1;
26209 + dma_desc->status.b.bytes = ep->xfer_len;
26210 + dma_desc->buf = ep->dma_addr;
26211 + dma_desc->status.b.sts = 0;
26212 + dma_desc->status.b.bs = BS_HOST_READY;
26214 + /** DIEPDMA0 Register write */
26215 + DWC_WRITE_REG32(&in_regs->diepdma,
26216 + core_if->dev_if->dma_in_desc_addr);
26219 + DWC_DEBUGPL(DBG_PCDV,
26220 + "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
26221 + ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
26224 + /* Write the DMA register */
26225 + if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
26226 + if (core_if->dma_desc_enable == 0)
26227 + DWC_WRITE_REG32(&(in_regs->diepdma),
26228 + (uint32_t) ep->dma_addr);
26230 + if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
26231 + depctl.b.nextep = core_if->nextep_seq[ep->num];
26232 + /* EP enable, IN data in FIFO */
26233 + depctl.b.cnak = 1;
26234 + depctl.b.epena = 1;
26235 + DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
26238 + * Enable the Non-Periodic Tx FIFO empty interrupt, the
26239 + * data will be written into the fifo by the ISR.
26241 + if (!core_if->dma_enable) {
26242 + if (core_if->en_multiple_tx_fifo == 0) {
26243 + /* First clear it from GINTSTS */
26244 + intr_mask.b.nptxfempty = 1;
26245 + DWC_MODIFY_REG32(&core_if->
26246 + core_global_regs->gintmsk,
26247 + intr_mask.d32, intr_mask.d32);
26250 + /* Enable the Tx FIFO Empty Interrupt for this EP */
26251 + if (ep->xfer_len > 0) {
26252 + uint32_t fifoemptymsk = 0;
26253 + fifoemptymsk |= 1 << ep->num;
26254 + DWC_MODIFY_REG32(&core_if->
26255 + dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
26256 + 0, fifoemptymsk);
26261 + dwc_otg_dev_out_ep_regs_t *out_regs =
26262 + core_if->dev_if->out_ep_regs[0];
26264 + depctl.d32 = DWC_READ_REG32(&out_regs->doepctl);
26265 + deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);
26267 + /* Program the transfer size and packet count
26268 + * as follows: xfersize = N * maxpacket +
26269 + * short_packet pktcnt = N + (short_packet
26272 + deptsiz.b.xfersize = ep->maxpacket;
26273 + deptsiz.b.pktcnt = 1;
26275 + if (core_if->dma_desc_enable == 0) {
26276 + DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
26278 + dma_desc = core_if->dev_if->out_desc_addr;
26280 + /** DMA Descriptor Setup */
26281 + dma_desc->status.b.bs = BS_HOST_BUSY;
26282 + dma_desc->status.b.l = 1;
26283 + dma_desc->status.b.ioc = 1;
26284 + dma_desc->status.b.bytes = ep->maxpacket;
26285 + dma_desc->buf = ep->dma_addr;
26286 + dma_desc->status.b.sts = 0;
26287 + dma_desc->status.b.bs = BS_HOST_READY;
26289 + /** DOEPDMA0 Register write */
26290 + DWC_WRITE_REG32(&out_regs->doepdma,
26291 + core_if->dev_if->dma_out_desc_addr);
26294 + DWC_DEBUGPL(DBG_PCDV,
26295 + "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
26296 + ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
26299 + /* Write the DMA register */
26300 + if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
26301 + if (core_if->dma_desc_enable == 0)
26302 + DWC_WRITE_REG32(&(out_regs->doepdma),
26303 + (uint32_t) ep->dma_addr);
26307 + /* EP enable, IN data in FIFO */
26308 + depctl.b.cnak = 1;
26309 + depctl.b.epena = 1;
26310 + DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
26316 +void dump_msg(const u8 * buf, unsigned int length)
26318 + unsigned int start, num, i;
26319 + char line[52], *p;
26321 + if (length >= 512)
26324 + while (length > 0) {
26325 + num = length < 16u ? length : 16u;
26327 + for (i = 0; i < num; ++i) {
26330 + DWC_SPRINTF(p, " %02x", buf[i]);
26334 + DWC_PRINTF("%6x: %s\n", start, line);
26341 +static inline void dump_msg(const u8 * buf, unsigned int length)
26347 + * This function writes a packet into the Tx FIFO associated with the
26348 + * EP. For non-periodic EPs the non-periodic Tx FIFO is written. For
26349 + * periodic EPs the periodic Tx FIFO associated with the EP is written
26350 + * with all packets for the next micro-frame.
26352 + * @param core_if Programming view of DWC_otg controller.
26353 + * @param ep The EP to write packet for.
26354 + * @param dma Indicates if DMA is being used.
26356 +void dwc_otg_ep_write_packet(dwc_otg_core_if_t * core_if, dwc_ep_t * ep,
26360 + * The buffer is padded to DWORD on a per packet basis in
26361 + * slave/dma mode if the MPS is not DWORD aligned. The last
26362 + * packet, if short, is also padded to a multiple of DWORD.
26364 + * ep->xfer_buff always starts DWORD aligned in memory and is a
26365 + * multiple of DWORD in length
26367 + * ep->xfer_len can be any number of bytes
26369 + * ep->xfer_count is a multiple of ep->maxpacket until the last
26372 + * FIFO access is DWORD */
26375 + uint32_t byte_count;
26376 + uint32_t dword_count;
26378 + uint32_t *data_buff = (uint32_t *) ep->xfer_buff;
26380 + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, core_if,
26382 + if (ep->xfer_count >= ep->xfer_len) {
26383 + DWC_WARN("%s() No data for EP%d!!!\n", __func__, ep->num);
26387 + /* Find the byte length of the packet either short packet or MPS */
26388 + if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket) {
26389 + byte_count = ep->xfer_len - ep->xfer_count;
26391 + byte_count = ep->maxpacket;
26394 + /* Find the DWORD length, padded by extra bytes as neccessary if MPS
26395 + * is not a multiple of DWORD */
26396 + dword_count = (byte_count + 3) / 4;
26399 + dump_msg(ep->xfer_buff, byte_count);
26402 + /**@todo NGS Where are the Periodic Tx FIFO addresses
26403 + * intialized? What should this be? */
26405 + fifo = core_if->data_fifo[ep->num];
26407 + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n",
26408 + fifo, data_buff, *data_buff, byte_count);
26411 + for (i = 0; i < dword_count; i++, data_buff++) {
26412 + DWC_WRITE_REG32(fifo, *data_buff);
26416 + ep->xfer_count += byte_count;
26417 + ep->xfer_buff += byte_count;
26418 + ep->dma_addr += byte_count;
26422 + * Set the EP STALL.
26424 + * @param core_if Programming view of DWC_otg controller.
26425 + * @param ep The EP to set the stall on.
26427 +void dwc_otg_ep_set_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
26429 + depctl_data_t depctl;
26430 + volatile uint32_t *depctl_addr;
26432 + DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
26433 + (ep->is_in ? "IN" : "OUT"));
26435 + if (ep->is_in == 1) {
26436 + depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
26437 + depctl.d32 = DWC_READ_REG32(depctl_addr);
26439 + /* set the disable and stall bits */
26440 + if (depctl.b.epena) {
26441 + depctl.b.epdis = 1;
26443 + depctl.b.stall = 1;
26444 + DWC_WRITE_REG32(depctl_addr, depctl.d32);
26446 + depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
26447 + depctl.d32 = DWC_READ_REG32(depctl_addr);
26449 + /* set the stall bit */
26450 + depctl.b.stall = 1;
26451 + DWC_WRITE_REG32(depctl_addr, depctl.d32);
26454 + DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr));
26460 + * Clear the EP STALL.
26462 + * @param core_if Programming view of DWC_otg controller.
26463 + * @param ep The EP to clear stall from.
26465 +void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
26467 + depctl_data_t depctl;
26468 + volatile uint32_t *depctl_addr;
26470 + DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
26471 + (ep->is_in ? "IN" : "OUT"));
26473 + if (ep->is_in == 1) {
26474 + depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
26476 + depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
26479 + depctl.d32 = DWC_READ_REG32(depctl_addr);
26481 + /* clear the stall bits */
26482 + depctl.b.stall = 0;
26485 + * USB Spec 9.4.5: For endpoints using data toggle, regardless
26486 + * of whether an endpoint has the Halt feature set, a
26487 + * ClearFeature(ENDPOINT_HALT) request always results in the
26488 + * data toggle being reinitialized to DATA0.
26490 + if (ep->type == DWC_OTG_EP_TYPE_INTR ||
26491 + ep->type == DWC_OTG_EP_TYPE_BULK) {
26492 + depctl.b.setd0pid = 1; /* DATA0 */
26495 + DWC_WRITE_REG32(depctl_addr, depctl.d32);
26496 + DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr));
26501 + * This function reads a packet from the Rx FIFO into the destination
26502 + * buffer. To read SETUP data use dwc_otg_read_setup_packet.
26504 + * @param core_if Programming view of DWC_otg controller.
26505 + * @param dest Destination buffer for the packet.
26506 + * @param bytes Number of bytes to copy to the destination.
26508 +void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
26509 + uint8_t * dest, uint16_t bytes)
26512 + int word_count = (bytes + 3) / 4;
26514 + volatile uint32_t *fifo = core_if->data_fifo[0];
26515 + uint32_t *data_buff = (uint32_t *) dest;
26518 + * @todo Account for the case where _dest is not dword aligned. This
26519 + * requires reading data from the FIFO into a uint32_t temp buffer,
26520 + * then moving it into the data buffer.
26523 + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__,
26524 + core_if, dest, bytes);
26526 + for (i = 0; i < word_count; i++, data_buff++) {
26527 + *data_buff = DWC_READ_REG32(fifo);
26534 + * This functions reads the device registers and prints them
26536 + * @param core_if Programming view of DWC_otg controller.
26538 +void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * core_if)
26541 + volatile uint32_t *addr;
26543 + DWC_PRINTF("Device Global Registers\n");
26544 + addr = &core_if->dev_if->dev_global_regs->dcfg;
26545 + DWC_PRINTF("DCFG @0x%08lX : 0x%08X\n",
26546 + (unsigned long)addr, DWC_READ_REG32(addr));
26547 + addr = &core_if->dev_if->dev_global_regs->dctl;
26548 + DWC_PRINTF("DCTL @0x%08lX : 0x%08X\n",
26549 + (unsigned long)addr, DWC_READ_REG32(addr));
26550 + addr = &core_if->dev_if->dev_global_regs->dsts;
26551 + DWC_PRINTF("DSTS @0x%08lX : 0x%08X\n",
26552 + (unsigned long)addr, DWC_READ_REG32(addr));
26553 + addr = &core_if->dev_if->dev_global_regs->diepmsk;
26554 + DWC_PRINTF("DIEPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
26555 + DWC_READ_REG32(addr));
26556 + addr = &core_if->dev_if->dev_global_regs->doepmsk;
26557 + DWC_PRINTF("DOEPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
26558 + DWC_READ_REG32(addr));
26559 + addr = &core_if->dev_if->dev_global_regs->daint;
26560 + DWC_PRINTF("DAINT @0x%08lX : 0x%08X\n", (unsigned long)addr,
26561 + DWC_READ_REG32(addr));
26562 + addr = &core_if->dev_if->dev_global_regs->daintmsk;
26563 + DWC_PRINTF("DAINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
26564 + DWC_READ_REG32(addr));
26565 + addr = &core_if->dev_if->dev_global_regs->dtknqr1;
26566 + DWC_PRINTF("DTKNQR1 @0x%08lX : 0x%08X\n", (unsigned long)addr,
26567 + DWC_READ_REG32(addr));
26568 + if (core_if->hwcfg2.b.dev_token_q_depth > 6) {
26569 + addr = &core_if->dev_if->dev_global_regs->dtknqr2;
26570 + DWC_PRINTF("DTKNQR2 @0x%08lX : 0x%08X\n",
26571 + (unsigned long)addr, DWC_READ_REG32(addr));
26574 + addr = &core_if->dev_if->dev_global_regs->dvbusdis;
26575 + DWC_PRINTF("DVBUSID @0x%08lX : 0x%08X\n", (unsigned long)addr,
26576 + DWC_READ_REG32(addr));
26578 + addr = &core_if->dev_if->dev_global_regs->dvbuspulse;
26579 + DWC_PRINTF("DVBUSPULSE @0x%08lX : 0x%08X\n",
26580 + (unsigned long)addr, DWC_READ_REG32(addr));
26582 + addr = &core_if->dev_if->dev_global_regs->dtknqr3_dthrctl;
26583 + DWC_PRINTF("DTKNQR3_DTHRCTL @0x%08lX : 0x%08X\n",
26584 + (unsigned long)addr, DWC_READ_REG32(addr));
26586 + if (core_if->hwcfg2.b.dev_token_q_depth > 22) {
26587 + addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
26588 + DWC_PRINTF("DTKNQR4 @0x%08lX : 0x%08X\n",
26589 + (unsigned long)addr, DWC_READ_REG32(addr));
26592 + addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
26593 + DWC_PRINTF("FIFOEMPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
26594 + DWC_READ_REG32(addr));
26596 + if (core_if->hwcfg2.b.multi_proc_int) {
26598 + addr = &core_if->dev_if->dev_global_regs->deachint;
26599 + DWC_PRINTF("DEACHINT @0x%08lX : 0x%08X\n",
26600 + (unsigned long)addr, DWC_READ_REG32(addr));
26601 + addr = &core_if->dev_if->dev_global_regs->deachintmsk;
26602 + DWC_PRINTF("DEACHINTMSK @0x%08lX : 0x%08X\n",
26603 + (unsigned long)addr, DWC_READ_REG32(addr));
26605 + for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
26607 + &core_if->dev_if->
26608 + dev_global_regs->diepeachintmsk[i];
26609 + DWC_PRINTF("DIEPEACHINTMSK[%d] @0x%08lX : 0x%08X\n",
26610 + i, (unsigned long)addr,
26611 + DWC_READ_REG32(addr));
26614 + for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
26616 + &core_if->dev_if->
26617 + dev_global_regs->doepeachintmsk[i];
26618 + DWC_PRINTF("DOEPEACHINTMSK[%d] @0x%08lX : 0x%08X\n",
26619 + i, (unsigned long)addr,
26620 + DWC_READ_REG32(addr));
26624 + for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
26625 + DWC_PRINTF("Device IN EP %d Registers\n", i);
26626 + addr = &core_if->dev_if->in_ep_regs[i]->diepctl;
26627 + DWC_PRINTF("DIEPCTL @0x%08lX : 0x%08X\n",
26628 + (unsigned long)addr, DWC_READ_REG32(addr));
26629 + addr = &core_if->dev_if->in_ep_regs[i]->diepint;
26630 + DWC_PRINTF("DIEPINT @0x%08lX : 0x%08X\n",
26631 + (unsigned long)addr, DWC_READ_REG32(addr));
26632 + addr = &core_if->dev_if->in_ep_regs[i]->dieptsiz;
26633 + DWC_PRINTF("DIETSIZ @0x%08lX : 0x%08X\n",
26634 + (unsigned long)addr, DWC_READ_REG32(addr));
26635 + addr = &core_if->dev_if->in_ep_regs[i]->diepdma;
26636 + DWC_PRINTF("DIEPDMA @0x%08lX : 0x%08X\n",
26637 + (unsigned long)addr, DWC_READ_REG32(addr));
26638 + addr = &core_if->dev_if->in_ep_regs[i]->dtxfsts;
26639 + DWC_PRINTF("DTXFSTS @0x%08lX : 0x%08X\n",
26640 + (unsigned long)addr, DWC_READ_REG32(addr));
26641 + addr = &core_if->dev_if->in_ep_regs[i]->diepdmab;
26642 + DWC_PRINTF("DIEPDMAB @0x%08lX : 0x%08X\n",
26643 + (unsigned long)addr, 0 /*DWC_READ_REG32(addr) */ );
26646 + for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
26647 + DWC_PRINTF("Device OUT EP %d Registers\n", i);
26648 + addr = &core_if->dev_if->out_ep_regs[i]->doepctl;
26649 + DWC_PRINTF("DOEPCTL @0x%08lX : 0x%08X\n",
26650 + (unsigned long)addr, DWC_READ_REG32(addr));
26651 + addr = &core_if->dev_if->out_ep_regs[i]->doepint;
26652 + DWC_PRINTF("DOEPINT @0x%08lX : 0x%08X\n",
26653 + (unsigned long)addr, DWC_READ_REG32(addr));
26654 + addr = &core_if->dev_if->out_ep_regs[i]->doeptsiz;
26655 + DWC_PRINTF("DOETSIZ @0x%08lX : 0x%08X\n",
26656 + (unsigned long)addr, DWC_READ_REG32(addr));
26657 + addr = &core_if->dev_if->out_ep_regs[i]->doepdma;
26658 + DWC_PRINTF("DOEPDMA @0x%08lX : 0x%08X\n",
26659 + (unsigned long)addr, DWC_READ_REG32(addr));
26660 + if (core_if->dma_enable) { /* Don't access this register in SLAVE mode */
26661 + addr = &core_if->dev_if->out_ep_regs[i]->doepdmab;
26662 + DWC_PRINTF("DOEPDMAB @0x%08lX : 0x%08X\n",
26663 + (unsigned long)addr, DWC_READ_REG32(addr));
26670 + * This functions reads the SPRAM and prints its content
26672 + * @param core_if Programming view of DWC_otg controller.
26674 +void dwc_otg_dump_spram(dwc_otg_core_if_t * core_if)
26676 + volatile uint8_t *addr, *start_addr, *end_addr;
26678 + DWC_PRINTF("SPRAM Data:\n");
26679 + start_addr = (void *)core_if->core_global_regs;
26680 + DWC_PRINTF("Base Address: 0x%8lX\n", (unsigned long)start_addr);
26681 + start_addr += 0x00028000;
26682 + end_addr = (void *)core_if->core_global_regs;
26683 + end_addr += 0x000280e0;
26685 + for (addr = start_addr; addr < end_addr; addr += 16) {
26687 + ("0x%8lX:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n",
26688 + (unsigned long)addr, addr[0], addr[1], addr[2], addr[3],
26689 + addr[4], addr[5], addr[6], addr[7], addr[8], addr[9],
26690 + addr[10], addr[11], addr[12], addr[13], addr[14], addr[15]
26698 + * This function reads the host registers and prints them
26700 + * @param core_if Programming view of DWC_otg controller.
26702 +void dwc_otg_dump_host_registers(dwc_otg_core_if_t * core_if)
26705 + volatile uint32_t *addr;
26707 + DWC_PRINTF("Host Global Registers\n");
26708 + addr = &core_if->host_if->host_global_regs->hcfg;
26709 + DWC_PRINTF("HCFG @0x%08lX : 0x%08X\n",
26710 + (unsigned long)addr, DWC_READ_REG32(addr));
26711 + addr = &core_if->host_if->host_global_regs->hfir;
26712 + DWC_PRINTF("HFIR @0x%08lX : 0x%08X\n",
26713 + (unsigned long)addr, DWC_READ_REG32(addr));
26714 + addr = &core_if->host_if->host_global_regs->hfnum;
26715 + DWC_PRINTF("HFNUM @0x%08lX : 0x%08X\n", (unsigned long)addr,
26716 + DWC_READ_REG32(addr));
26717 + addr = &core_if->host_if->host_global_regs->hptxsts;
26718 + DWC_PRINTF("HPTXSTS @0x%08lX : 0x%08X\n", (unsigned long)addr,
26719 + DWC_READ_REG32(addr));
26720 + addr = &core_if->host_if->host_global_regs->haint;
26721 + DWC_PRINTF("HAINT @0x%08lX : 0x%08X\n", (unsigned long)addr,
26722 + DWC_READ_REG32(addr));
26723 + addr = &core_if->host_if->host_global_regs->haintmsk;
26724 + DWC_PRINTF("HAINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
26725 + DWC_READ_REG32(addr));
26726 + if (core_if->dma_desc_enable) {
26727 + addr = &core_if->host_if->host_global_regs->hflbaddr;
26728 + DWC_PRINTF("HFLBADDR @0x%08lX : 0x%08X\n",
26729 + (unsigned long)addr, DWC_READ_REG32(addr));
26732 + addr = core_if->host_if->hprt0;
26733 + DWC_PRINTF("HPRT0 @0x%08lX : 0x%08X\n", (unsigned long)addr,
26734 + DWC_READ_REG32(addr));
26736 + for (i = 0; i < core_if->core_params->host_channels; i++) {
26737 + DWC_PRINTF("Host Channel %d Specific Registers\n", i);
26738 + addr = &core_if->host_if->hc_regs[i]->hcchar;
26739 + DWC_PRINTF("HCCHAR @0x%08lX : 0x%08X\n",
26740 + (unsigned long)addr, DWC_READ_REG32(addr));
26741 + addr = &core_if->host_if->hc_regs[i]->hcsplt;
26742 + DWC_PRINTF("HCSPLT @0x%08lX : 0x%08X\n",
26743 + (unsigned long)addr, DWC_READ_REG32(addr));
26744 + addr = &core_if->host_if->hc_regs[i]->hcint;
26745 + DWC_PRINTF("HCINT @0x%08lX : 0x%08X\n",
26746 + (unsigned long)addr, DWC_READ_REG32(addr));
26747 + addr = &core_if->host_if->hc_regs[i]->hcintmsk;
26748 + DWC_PRINTF("HCINTMSK @0x%08lX : 0x%08X\n",
26749 + (unsigned long)addr, DWC_READ_REG32(addr));
26750 + addr = &core_if->host_if->hc_regs[i]->hctsiz;
26751 + DWC_PRINTF("HCTSIZ @0x%08lX : 0x%08X\n",
26752 + (unsigned long)addr, DWC_READ_REG32(addr));
26753 + addr = &core_if->host_if->hc_regs[i]->hcdma;
26754 + DWC_PRINTF("HCDMA @0x%08lX : 0x%08X\n",
26755 + (unsigned long)addr, DWC_READ_REG32(addr));
26756 + if (core_if->dma_desc_enable) {
26757 + addr = &core_if->host_if->hc_regs[i]->hcdmab;
26758 + DWC_PRINTF("HCDMAB @0x%08lX : 0x%08X\n",
26759 + (unsigned long)addr, DWC_READ_REG32(addr));
26767 + * This function reads the core global registers and prints them
26769 + * @param core_if Programming view of DWC_otg controller.
26771 +void dwc_otg_dump_global_registers(dwc_otg_core_if_t * core_if)
26774 + volatile uint32_t *addr;
26777 + DWC_PRINTF("Core Global Registers\n");
26778 + addr = &core_if->core_global_regs->gotgctl;
26779 + DWC_PRINTF("GOTGCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
26780 + DWC_READ_REG32(addr));
26781 + addr = &core_if->core_global_regs->gotgint;
26782 + DWC_PRINTF("GOTGINT @0x%08lX : 0x%08X\n", (unsigned long)addr,
26783 + DWC_READ_REG32(addr));
26784 + addr = &core_if->core_global_regs->gahbcfg;
26785 + DWC_PRINTF("GAHBCFG @0x%08lX : 0x%08X\n", (unsigned long)addr,
26786 + DWC_READ_REG32(addr));
26787 + addr = &core_if->core_global_regs->gusbcfg;
26788 + DWC_PRINTF("GUSBCFG @0x%08lX : 0x%08X\n", (unsigned long)addr,
26789 + DWC_READ_REG32(addr));
26790 + addr = &core_if->core_global_regs->grstctl;
26791 + DWC_PRINTF("GRSTCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
26792 + DWC_READ_REG32(addr));
26793 + addr = &core_if->core_global_regs->gintsts;
26794 + DWC_PRINTF("GINTSTS @0x%08lX : 0x%08X\n", (unsigned long)addr,
26795 + DWC_READ_REG32(addr));
26796 + addr = &core_if->core_global_regs->gintmsk;
26797 + DWC_PRINTF("GINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
26798 + DWC_READ_REG32(addr));
26799 + addr = &core_if->core_global_regs->grxstsr;
26800 + DWC_PRINTF("GRXSTSR @0x%08lX : 0x%08X\n", (unsigned long)addr,
26801 + DWC_READ_REG32(addr));
26802 + addr = &core_if->core_global_regs->grxfsiz;
26803 + DWC_PRINTF("GRXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr,
26804 + DWC_READ_REG32(addr));
26805 + addr = &core_if->core_global_regs->gnptxfsiz;
26806 + DWC_PRINTF("GNPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr,
26807 + DWC_READ_REG32(addr));
26808 + addr = &core_if->core_global_regs->gnptxsts;
26809 + DWC_PRINTF("GNPTXSTS @0x%08lX : 0x%08X\n", (unsigned long)addr,
26810 + DWC_READ_REG32(addr));
26811 + addr = &core_if->core_global_regs->gi2cctl;
26812 + DWC_PRINTF("GI2CCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
26813 + DWC_READ_REG32(addr));
26814 + addr = &core_if->core_global_regs->gpvndctl;
26815 + DWC_PRINTF("GPVNDCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
26816 + DWC_READ_REG32(addr));
26817 + addr = &core_if->core_global_regs->ggpio;
26818 + DWC_PRINTF("GGPIO @0x%08lX : 0x%08X\n", (unsigned long)addr,
26819 + DWC_READ_REG32(addr));
26820 + addr = &core_if->core_global_regs->guid;
26821 + DWC_PRINTF("GUID @0x%08lX : 0x%08X\n",
26822 + (unsigned long)addr, DWC_READ_REG32(addr));
26823 + addr = &core_if->core_global_regs->gsnpsid;
26824 + DWC_PRINTF("GSNPSID @0x%08lX : 0x%08X\n", (unsigned long)addr,
26825 + DWC_READ_REG32(addr));
26826 + addr = &core_if->core_global_regs->ghwcfg1;
26827 + DWC_PRINTF("GHWCFG1 @0x%08lX : 0x%08X\n", (unsigned long)addr,
26828 + DWC_READ_REG32(addr));
26829 + addr = &core_if->core_global_regs->ghwcfg2;
26830 + DWC_PRINTF("GHWCFG2 @0x%08lX : 0x%08X\n", (unsigned long)addr,
26831 + DWC_READ_REG32(addr));
26832 + addr = &core_if->core_global_regs->ghwcfg3;
26833 + DWC_PRINTF("GHWCFG3 @0x%08lX : 0x%08X\n", (unsigned long)addr,
26834 + DWC_READ_REG32(addr));
26835 + addr = &core_if->core_global_regs->ghwcfg4;
26836 + DWC_PRINTF("GHWCFG4 @0x%08lX : 0x%08X\n", (unsigned long)addr,
26837 + DWC_READ_REG32(addr));
26838 + addr = &core_if->core_global_regs->glpmcfg;
26839 + DWC_PRINTF("GLPMCFG @0x%08lX : 0x%08X\n", (unsigned long)addr,
26840 + DWC_READ_REG32(addr));
26841 + addr = &core_if->core_global_regs->gpwrdn;
26842 + DWC_PRINTF("GPWRDN @0x%08lX : 0x%08X\n", (unsigned long)addr,
26843 + DWC_READ_REG32(addr));
26844 + addr = &core_if->core_global_regs->gdfifocfg;
26845 + DWC_PRINTF("GDFIFOCFG @0x%08lX : 0x%08X\n", (unsigned long)addr,
26846 + DWC_READ_REG32(addr));
26847 + addr = &core_if->core_global_regs->adpctl;
26848 + DWC_PRINTF("ADPCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
26849 + dwc_otg_adp_read_reg(core_if));
26850 + addr = &core_if->core_global_regs->hptxfsiz;
26851 + DWC_PRINTF("HPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr,
26852 + DWC_READ_REG32(addr));
26854 + if (core_if->en_multiple_tx_fifo == 0) {
26855 + ep_num = core_if->hwcfg4.b.num_dev_perio_in_ep;
26856 + txfsiz = "DPTXFSIZ";
26858 + ep_num = core_if->hwcfg4.b.num_in_eps;
26859 + txfsiz = "DIENPTXF";
26861 + for (i = 0; i < ep_num; i++) {
26862 + addr = &core_if->core_global_regs->dtxfsiz[i];
26863 + DWC_PRINTF("%s[%d] @0x%08lX : 0x%08X\n", txfsiz, i + 1,
26864 + (unsigned long)addr, DWC_READ_REG32(addr));
26866 + addr = core_if->pcgcctl;
26867 + DWC_PRINTF("PCGCCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
26868 + DWC_READ_REG32(addr));
26872 + * Flush a Tx FIFO.
26874 + * @param core_if Programming view of DWC_otg controller.
26875 + * @param num Tx FIFO to flush.
26877 +void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * core_if, const int num)
26879 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
26880 + volatile grstctl_t greset = {.d32 = 0 };
26883 + DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "Flush Tx FIFO %d\n", num);
26885 + greset.b.txfflsh = 1;
26886 + greset.b.txfnum = num;
26887 + DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
26890 + greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
26891 + if (++count > 10000) {
26892 + DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
26893 + __func__, greset.d32,
26894 + DWC_READ_REG32(&global_regs->gnptxsts));
26898 + } while (greset.b.txfflsh == 1);
26900 + /* Wait for 3 PHY Clocks */
26907 + * @param core_if Programming view of DWC_otg controller.
26909 +void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * core_if)
26911 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
26912 + volatile grstctl_t greset = {.d32 = 0 };
26915 + DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "%s\n", __func__);
26919 + greset.b.rxfflsh = 1;
26920 + DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
26923 + greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
26924 + if (++count > 10000) {
26925 + DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__,
26930 + } while (greset.b.rxfflsh == 1);
26932 + /* Wait for 3 PHY Clocks */
26937 + * Do core a soft reset of the core. Be careful with this because it
26938 + * resets all the internal state machines of the core.
26940 +void dwc_otg_core_reset(dwc_otg_core_if_t * core_if)
26942 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
26943 + volatile grstctl_t greset = {.d32 = 0 };
26946 + DWC_DEBUGPL(DBG_CILV, "%s\n", __func__);
26947 + /* Wait for AHB master IDLE state. */
26950 + greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
26951 + if (++count > 100000) {
26952 + DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__,
26957 + while (greset.b.ahbidle == 0);
26959 + /* Core Soft Reset */
26961 + greset.b.csftrst = 1;
26962 + DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
26964 + greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
26965 + if (++count > 10000) {
26966 + DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n",
26967 + __func__, greset.d32);
26972 + while (greset.b.csftrst == 1);
26974 + /* Wait for 3 PHY Clocks */
26978 +uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if)
26980 + return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
26983 +uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if)
26985 + return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
26989 + * Register HCD callbacks. The callbacks are used to start and stop
26990 + * the HCD for interrupt processing.
26992 + * @param core_if Programming view of DWC_otg controller.
26993 + * @param cb the HCD callback structure.
26994 + * @param p pointer to be passed to callback function (usb_hcd*).
26996 +void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * core_if,
26997 + dwc_otg_cil_callbacks_t * cb, void *p)
26999 + core_if->hcd_cb = cb;
27004 + * Register PCD callbacks. The callbacks are used to start and stop
27005 + * the PCD for interrupt processing.
27007 + * @param core_if Programming view of DWC_otg controller.
27008 + * @param cb the PCD callback structure.
27009 + * @param p pointer to be passed to callback function (pcd*).
27011 +void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * core_if,
27012 + dwc_otg_cil_callbacks_t * cb, void *p)
27014 + core_if->pcd_cb = cb;
27018 +#ifdef DWC_EN_ISOC
27021 + * This function writes isoc data per 1 (micro)frame into tx fifo
27023 + * @param core_if Programming view of DWC_otg controller.
27024 + * @param ep The EP to start the transfer on.
27027 +void write_isoc_frame_data(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
27029 + dwc_otg_dev_in_ep_regs_t *ep_regs;
27030 + dtxfsts_data_t txstatus = {.d32 = 0 };
27031 + uint32_t len = 0;
27034 + ep->xfer_len = ep->data_per_frame;
27035 + ep->xfer_count = 0;
27037 + ep_regs = core_if->dev_if->in_ep_regs[ep->num];
27039 + len = ep->xfer_len - ep->xfer_count;
27041 + if (len > ep->maxpacket) {
27042 + len = ep->maxpacket;
27045 + dwords = (len + 3) / 4;
27047 + /* While there is space in the queue and space in the FIFO and
27048 + * More data to tranfer, Write packets to the Tx FIFO */
27050 + DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts);
27051 + DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", ep->num, txstatus.d32);
27053 + while (txstatus.b.txfspcavail > dwords &&
27054 + ep->xfer_count < ep->xfer_len && ep->xfer_len != 0) {
27055 + /* Write the FIFO */
27056 + dwc_otg_ep_write_packet(core_if, ep, 0);
27058 + len = ep->xfer_len - ep->xfer_count;
27059 + if (len > ep->maxpacket) {
27060 + len = ep->maxpacket;
27063 + dwords = (len + 3) / 4;
27065 + DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
27067 + DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", ep->num,
27073 + * This function initializes a descriptor chain for Isochronous transfer
27075 + * @param core_if Programming view of DWC_otg controller.
27076 + * @param ep The EP to start the transfer on.
27079 +void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
27082 + deptsiz_data_t deptsiz = {.d32 = 0 };
27083 + depctl_data_t depctl = {.d32 = 0 };
27084 + dsts_data_t dsts = {.d32 = 0 };
27085 + volatile uint32_t *addr;
27088 + addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
27090 + addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
27093 + ep->xfer_len = ep->data_per_frame;
27094 + ep->xfer_count = 0;
27095 + ep->xfer_buff = ep->cur_pkt_addr;
27096 + ep->dma_addr = ep->cur_pkt_dma_addr;
27099 + /* Program the transfer size and packet count
27100 + * as follows: xfersize = N * maxpacket +
27101 + * short_packet pktcnt = N + (short_packet
27104 + deptsiz.b.xfersize = ep->xfer_len;
27105 + deptsiz.b.pktcnt =
27106 + (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
27107 + deptsiz.b.mc = deptsiz.b.pktcnt;
27108 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz,
27111 + /* Write the DMA register */
27112 + if (core_if->dma_enable) {
27113 + DWC_WRITE_REG32(&
27114 + (core_if->dev_if->in_ep_regs[ep->num]->
27115 + diepdma), (uint32_t) ep->dma_addr);
27118 + deptsiz.b.pktcnt =
27119 + (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket;
27120 + deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
27122 + DWC_WRITE_REG32(&core_if->dev_if->
27123 + out_ep_regs[ep->num]->doeptsiz, deptsiz.d32);
27125 + if (core_if->dma_enable) {
27126 + DWC_WRITE_REG32(&
27127 + (core_if->dev_if->
27128 + out_ep_regs[ep->num]->doepdma),
27129 + (uint32_t) ep->dma_addr);
27133 + /** Enable endpoint, clear nak */
27136 + if (ep->bInterval == 1) {
27138 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
27139 + ep->next_frame = dsts.b.soffn + ep->bInterval;
27141 + if (ep->next_frame & 0x1) {
27142 + depctl.b.setd1pid = 1;
27144 + depctl.b.setd0pid = 1;
27147 + ep->next_frame += ep->bInterval;
27149 + if (ep->next_frame & 0x1) {
27150 + depctl.b.setd1pid = 1;
27152 + depctl.b.setd0pid = 1;
27155 + depctl.b.epena = 1;
27156 + depctl.b.cnak = 1;
27158 + DWC_MODIFY_REG32(addr, 0, depctl.d32);
27159 + depctl.d32 = DWC_READ_REG32(addr);
27161 + if (ep->is_in && core_if->dma_enable == 0) {
27162 + write_isoc_frame_data(core_if, ep);
27166 +#endif /* DWC_EN_ISOC */
27168 +static void dwc_otg_set_uninitialized(int32_t * p, int size)
27171 + for (i = 0; i < size; i++) {
27176 +static int dwc_otg_param_initialized(int32_t val)
27178 + return val != -1;
27181 +static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if)
27184 + core_if->core_params = DWC_ALLOC(sizeof(*core_if->core_params));
27185 + if (!core_if->core_params) {
27186 + return -DWC_E_NO_MEMORY;
27188 + dwc_otg_set_uninitialized((int32_t *) core_if->core_params,
27189 + sizeof(*core_if->core_params) /
27190 + sizeof(int32_t));
27191 + DWC_PRINTF("Setting default values for core params\n");
27192 + dwc_otg_set_param_otg_cap(core_if, dwc_param_otg_cap_default);
27193 + dwc_otg_set_param_dma_enable(core_if, dwc_param_dma_enable_default);
27194 + dwc_otg_set_param_dma_desc_enable(core_if,
27195 + dwc_param_dma_desc_enable_default);
27196 + dwc_otg_set_param_opt(core_if, dwc_param_opt_default);
27197 + dwc_otg_set_param_dma_burst_size(core_if,
27198 + dwc_param_dma_burst_size_default);
27199 + dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
27200 + dwc_param_host_support_fs_ls_low_power_default);
27201 + dwc_otg_set_param_enable_dynamic_fifo(core_if,
27202 + dwc_param_enable_dynamic_fifo_default);
27203 + dwc_otg_set_param_data_fifo_size(core_if,
27204 + dwc_param_data_fifo_size_default);
27205 + dwc_otg_set_param_dev_rx_fifo_size(core_if,
27206 + dwc_param_dev_rx_fifo_size_default);
27207 + dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
27208 + dwc_param_dev_nperio_tx_fifo_size_default);
27209 + dwc_otg_set_param_host_rx_fifo_size(core_if,
27210 + dwc_param_host_rx_fifo_size_default);
27211 + dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
27212 + dwc_param_host_nperio_tx_fifo_size_default);
27213 + dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
27214 + dwc_param_host_perio_tx_fifo_size_default);
27215 + dwc_otg_set_param_max_transfer_size(core_if,
27216 + dwc_param_max_transfer_size_default);
27217 + dwc_otg_set_param_max_packet_count(core_if,
27218 + dwc_param_max_packet_count_default);
27219 + dwc_otg_set_param_host_channels(core_if,
27220 + dwc_param_host_channels_default);
27221 + dwc_otg_set_param_dev_endpoints(core_if,
27222 + dwc_param_dev_endpoints_default);
27223 + dwc_otg_set_param_phy_type(core_if, dwc_param_phy_type_default);
27224 + dwc_otg_set_param_speed(core_if, dwc_param_speed_default);
27225 + dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
27226 + dwc_param_host_ls_low_power_phy_clk_default);
27227 + dwc_otg_set_param_phy_ulpi_ddr(core_if, dwc_param_phy_ulpi_ddr_default);
27228 + dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
27229 + dwc_param_phy_ulpi_ext_vbus_default);
27230 + dwc_otg_set_param_phy_utmi_width(core_if,
27231 + dwc_param_phy_utmi_width_default);
27232 + dwc_otg_set_param_ts_dline(core_if, dwc_param_ts_dline_default);
27233 + dwc_otg_set_param_i2c_enable(core_if, dwc_param_i2c_enable_default);
27234 + dwc_otg_set_param_ulpi_fs_ls(core_if, dwc_param_ulpi_fs_ls_default);
27235 + dwc_otg_set_param_en_multiple_tx_fifo(core_if,
27236 + dwc_param_en_multiple_tx_fifo_default);
27237 + for (i = 0; i < 15; i++) {
27238 + dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
27239 + dwc_param_dev_perio_tx_fifo_size_default,
27243 + for (i = 0; i < 15; i++) {
27244 + dwc_otg_set_param_dev_tx_fifo_size(core_if,
27245 + dwc_param_dev_tx_fifo_size_default,
27248 + dwc_otg_set_param_thr_ctl(core_if, dwc_param_thr_ctl_default);
27249 + dwc_otg_set_param_mpi_enable(core_if, dwc_param_mpi_enable_default);
27250 + dwc_otg_set_param_pti_enable(core_if, dwc_param_pti_enable_default);
27251 + dwc_otg_set_param_lpm_enable(core_if, dwc_param_lpm_enable_default);
27252 + dwc_otg_set_param_ic_usb_cap(core_if, dwc_param_ic_usb_cap_default);
27253 + dwc_otg_set_param_tx_thr_length(core_if,
27254 + dwc_param_tx_thr_length_default);
27255 + dwc_otg_set_param_rx_thr_length(core_if,
27256 + dwc_param_rx_thr_length_default);
27257 + dwc_otg_set_param_ahb_thr_ratio(core_if,
27258 + dwc_param_ahb_thr_ratio_default);
27259 + dwc_otg_set_param_power_down(core_if, dwc_param_power_down_default);
27260 + dwc_otg_set_param_reload_ctl(core_if, dwc_param_reload_ctl_default);
27261 + dwc_otg_set_param_dev_out_nak(core_if, dwc_param_dev_out_nak_default);
27262 + dwc_otg_set_param_cont_on_bna(core_if, dwc_param_cont_on_bna_default);
27263 + dwc_otg_set_param_ahb_single(core_if, dwc_param_ahb_single_default);
27264 + dwc_otg_set_param_otg_ver(core_if, dwc_param_otg_ver_default);
27265 + dwc_otg_set_param_adp_enable(core_if, dwc_param_adp_enable_default);
27266 + DWC_PRINTF("Finished setting default values for core params\n");
27271 +uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if)
27273 + return core_if->dma_enable;
27276 +/* Checks if the parameter is outside of its valid range of values */
27277 +#define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \
27278 + (((_param_) < (_low_)) || \
27279 + ((_param_) > (_high_)))
27281 +/* Parameter access functions */
27282 +int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val)
27286 + if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
27287 + DWC_WARN("Wrong value for otg_cap parameter\n");
27288 + DWC_WARN("otg_cap parameter must be 0,1 or 2\n");
27289 + retval = -DWC_E_INVALID;
27295 + case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
27296 + if (core_if->hwcfg2.b.op_mode !=
27297 + DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
27300 + case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
27301 + if ((core_if->hwcfg2.b.op_mode !=
27302 + DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
27303 + && (core_if->hwcfg2.b.op_mode !=
27304 + DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
27305 + && (core_if->hwcfg2.b.op_mode !=
27306 + DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
27307 + && (core_if->hwcfg2.b.op_mode !=
27308 + DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
27312 + case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
27313 + /* always valid */
27317 + if (dwc_otg_param_initialized(core_if->core_params->otg_cap)) {
27319 + ("%d invalid for otg_cap paremter. Check HW configuration.\n",
27323 + (((core_if->hwcfg2.b.op_mode ==
27324 + DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
27325 + || (core_if->hwcfg2.b.op_mode ==
27326 + DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
27327 + || (core_if->hwcfg2.b.op_mode ==
27328 + DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
27329 + || (core_if->hwcfg2.b.op_mode ==
27330 + DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
27331 + DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
27332 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
27333 + retval = -DWC_E_INVALID;
27336 + core_if->core_params->otg_cap = val;
27341 +int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if)
27343 + return core_if->core_params->otg_cap;
27346 +int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val)
27348 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27349 + DWC_WARN("Wrong value for opt parameter\n");
27350 + return -DWC_E_INVALID;
27352 + core_if->core_params->opt = val;
27356 +int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if)
27358 + return core_if->core_params->opt;
27361 +int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if, int32_t val)
27364 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27365 + DWC_WARN("Wrong value for dma enable\n");
27366 + return -DWC_E_INVALID;
27369 + if ((val == 1) && (core_if->hwcfg2.b.architecture == 0)) {
27370 + if (dwc_otg_param_initialized(core_if->core_params->dma_enable)) {
27372 + ("%d invalid for dma_enable paremter. Check HW configuration.\n",
27376 + retval = -DWC_E_INVALID;
27379 + core_if->core_params->dma_enable = val;
27381 + dwc_otg_set_param_dma_desc_enable(core_if, 0);
27386 +int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if)
27388 + return core_if->core_params->dma_enable;
27391 +int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if, int32_t val)
27394 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27395 + DWC_WARN("Wrong value for dma_enable\n");
27396 + DWC_WARN("dma_desc_enable must be 0 or 1\n");
27397 + return -DWC_E_INVALID;
27401 + && ((dwc_otg_get_param_dma_enable(core_if) == 0)
27402 + || (core_if->hwcfg4.b.desc_dma == 0))) {
27403 + if (dwc_otg_param_initialized
27404 + (core_if->core_params->dma_desc_enable)) {
27406 + ("%d invalid for dma_desc_enable paremter. Check HW configuration.\n",
27410 + retval = -DWC_E_INVALID;
27412 + core_if->core_params->dma_desc_enable = val;
27416 +int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if)
27418 + return core_if->core_params->dma_desc_enable;
27421 +int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * core_if,
27424 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27425 + DWC_WARN("Wrong value for host_support_fs_low_power\n");
27426 + DWC_WARN("host_support_fs_low_power must be 0 or 1\n");
27427 + return -DWC_E_INVALID;
27429 + core_if->core_params->host_support_fs_ls_low_power = val;
27433 +int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
27436 + return core_if->core_params->host_support_fs_ls_low_power;
27439 +int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
27443 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27444 + DWC_WARN("Wrong value for enable_dynamic_fifo\n");
27445 + DWC_WARN("enable_dynamic_fifo must be 0 or 1\n");
27446 + return -DWC_E_INVALID;
27449 + if ((val == 1) && (core_if->hwcfg2.b.dynamic_fifo == 0)) {
27450 + if (dwc_otg_param_initialized
27451 + (core_if->core_params->enable_dynamic_fifo)) {
27453 + ("%d invalid for enable_dynamic_fifo paremter. Check HW configuration.\n",
27457 + retval = -DWC_E_INVALID;
27459 + core_if->core_params->enable_dynamic_fifo = val;
27463 +int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if)
27465 + return core_if->core_params->enable_dynamic_fifo;
27468 +int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
27471 + if (DWC_OTG_PARAM_TEST(val, 32, 32768)) {
27472 + DWC_WARN("Wrong value for data_fifo_size\n");
27473 + DWC_WARN("data_fifo_size must be 32-32768\n");
27474 + return -DWC_E_INVALID;
27477 + if (val > core_if->hwcfg3.b.dfifo_depth) {
27478 + if (dwc_otg_param_initialized
27479 + (core_if->core_params->data_fifo_size)) {
27481 + ("%d invalid for data_fifo_size parameter. Check HW configuration.\n",
27484 + val = core_if->hwcfg3.b.dfifo_depth;
27485 + retval = -DWC_E_INVALID;
27488 + core_if->core_params->data_fifo_size = val;
27492 +int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if)
27494 + return core_if->core_params->data_fifo_size;
27497 +int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
27500 + if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
27501 + DWC_WARN("Wrong value for dev_rx_fifo_size\n");
27502 + DWC_WARN("dev_rx_fifo_size must be 16-32768\n");
27503 + return -DWC_E_INVALID;
27506 + if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {
27507 + if (dwc_otg_param_initialized(core_if->core_params->dev_rx_fifo_size)) {
27508 + DWC_WARN("%d invalid for dev_rx_fifo_size parameter\n", val);
27510 + val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
27511 + retval = -DWC_E_INVALID;
27514 + core_if->core_params->dev_rx_fifo_size = val;
27518 +int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if)
27520 + return core_if->core_params->dev_rx_fifo_size;
27523 +int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
27528 + if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
27529 + DWC_WARN("Wrong value for dev_nperio_tx_fifo\n");
27530 + DWC_WARN("dev_nperio_tx_fifo must be 16-32768\n");
27531 + return -DWC_E_INVALID;
27534 + if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
27535 + if (dwc_otg_param_initialized
27536 + (core_if->core_params->dev_nperio_tx_fifo_size)) {
27538 + ("%d invalid for dev_nperio_tx_fifo_size. Check HW configuration.\n",
27542 + (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>
27544 + retval = -DWC_E_INVALID;
27547 + core_if->core_params->dev_nperio_tx_fifo_size = val;
27551 +int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
27553 + return core_if->core_params->dev_nperio_tx_fifo_size;
27556 +int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
27561 + if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
27562 + DWC_WARN("Wrong value for host_rx_fifo_size\n");
27563 + DWC_WARN("host_rx_fifo_size must be 16-32768\n");
27564 + return -DWC_E_INVALID;
27567 + if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {
27568 + if (dwc_otg_param_initialized
27569 + (core_if->core_params->host_rx_fifo_size)) {
27571 + ("%d invalid for host_rx_fifo_size. Check HW configuration.\n",
27574 + val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
27575 + retval = -DWC_E_INVALID;
27578 + core_if->core_params->host_rx_fifo_size = val;
27583 +int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if)
27585 + return core_if->core_params->host_rx_fifo_size;
27588 +int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
27593 + if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
27594 + DWC_WARN("Wrong value for host_nperio_tx_fifo_size\n");
27595 + DWC_WARN("host_nperio_tx_fifo_size must be 16-32768\n");
27596 + return -DWC_E_INVALID;
27599 + if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
27600 + if (dwc_otg_param_initialized
27601 + (core_if->core_params->host_nperio_tx_fifo_size)) {
27603 + ("%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
27607 + (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>
27609 + retval = -DWC_E_INVALID;
27612 + core_if->core_params->host_nperio_tx_fifo_size = val;
27616 +int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
27618 + return core_if->core_params->host_nperio_tx_fifo_size;
27621 +int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
27625 + if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
27626 + DWC_WARN("Wrong value for host_perio_tx_fifo_size\n");
27627 + DWC_WARN("host_perio_tx_fifo_size must be 16-32768\n");
27628 + return -DWC_E_INVALID;
27631 + if (val > ((core_if->hptxfsiz.d32) >> 16)) {
27632 + if (dwc_otg_param_initialized
27633 + (core_if->core_params->host_perio_tx_fifo_size)) {
27635 + ("%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
27638 + val = (core_if->hptxfsiz.d32) >> 16;
27639 + retval = -DWC_E_INVALID;
27642 + core_if->core_params->host_perio_tx_fifo_size = val;
27646 +int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if)
27648 + return core_if->core_params->host_perio_tx_fifo_size;
27651 +int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
27656 + if (DWC_OTG_PARAM_TEST(val, 2047, 524288)) {
27657 + DWC_WARN("Wrong value for max_transfer_size\n");
27658 + DWC_WARN("max_transfer_size must be 2047-524288\n");
27659 + return -DWC_E_INVALID;
27662 + if (val >= (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))) {
27663 + if (dwc_otg_param_initialized
27664 + (core_if->core_params->max_transfer_size)) {
27666 + ("%d invalid for max_transfer_size. Check HW configuration.\n",
27670 + ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 11)) -
27672 + retval = -DWC_E_INVALID;
27675 + core_if->core_params->max_transfer_size = val;
27679 +int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if)
27681 + return core_if->core_params->max_transfer_size;
27684 +int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if, int32_t val)
27688 + if (DWC_OTG_PARAM_TEST(val, 15, 511)) {
27689 + DWC_WARN("Wrong value for max_packet_count\n");
27690 + DWC_WARN("max_packet_count must be 15-511\n");
27691 + return -DWC_E_INVALID;
27694 + if (val > (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))) {
27695 + if (dwc_otg_param_initialized
27696 + (core_if->core_params->max_packet_count)) {
27698 + ("%d invalid for max_packet_count. Check HW configuration.\n",
27702 + ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1);
27703 + retval = -DWC_E_INVALID;
27706 + core_if->core_params->max_packet_count = val;
27710 +int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if)
27712 + return core_if->core_params->max_packet_count;
27715 +int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if, int32_t val)
27719 + if (DWC_OTG_PARAM_TEST(val, 1, 16)) {
27720 + DWC_WARN("Wrong value for host_channels\n");
27721 + DWC_WARN("host_channels must be 1-16\n");
27722 + return -DWC_E_INVALID;
27725 + if (val > (core_if->hwcfg2.b.num_host_chan + 1)) {
27726 + if (dwc_otg_param_initialized
27727 + (core_if->core_params->host_channels)) {
27729 + ("%d invalid for host_channels. Check HW configurations.\n",
27732 + val = (core_if->hwcfg2.b.num_host_chan + 1);
27733 + retval = -DWC_E_INVALID;
27736 + core_if->core_params->host_channels = val;
27740 +int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if)
27742 + return core_if->core_params->host_channels;
27745 +int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if, int32_t val)
27749 + if (DWC_OTG_PARAM_TEST(val, 1, 15)) {
27750 + DWC_WARN("Wrong value for dev_endpoints\n");
27751 + DWC_WARN("dev_endpoints must be 1-15\n");
27752 + return -DWC_E_INVALID;
27755 + if (val > (core_if->hwcfg2.b.num_dev_ep)) {
27756 + if (dwc_otg_param_initialized
27757 + (core_if->core_params->dev_endpoints)) {
27759 + ("%d invalid for dev_endpoints. Check HW configurations.\n",
27762 + val = core_if->hwcfg2.b.num_dev_ep;
27763 + retval = -DWC_E_INVALID;
27766 + core_if->core_params->dev_endpoints = val;
27770 +int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if)
27772 + return core_if->core_params->dev_endpoints;
27775 +int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val)
27780 + if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
27781 + DWC_WARN("Wrong value for phy_type\n");
27782 + DWC_WARN("phy_type must be 0,1 or 2\n");
27783 + return -DWC_E_INVALID;
27785 +#ifndef NO_FS_PHY_HW_CHECKS
27786 + if ((val == DWC_PHY_TYPE_PARAM_UTMI) &&
27787 + ((core_if->hwcfg2.b.hs_phy_type == 1) ||
27788 + (core_if->hwcfg2.b.hs_phy_type == 3))) {
27790 + } else if ((val == DWC_PHY_TYPE_PARAM_ULPI) &&
27791 + ((core_if->hwcfg2.b.hs_phy_type == 2) ||
27792 + (core_if->hwcfg2.b.hs_phy_type == 3))) {
27794 + } else if ((val == DWC_PHY_TYPE_PARAM_FS) &&
27795 + (core_if->hwcfg2.b.fs_phy_type == 1)) {
27799 + if (dwc_otg_param_initialized(core_if->core_params->phy_type)) {
27801 + ("%d invalid for phy_type. Check HW configurations.\n",
27804 + if (core_if->hwcfg2.b.hs_phy_type) {
27805 + if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
27806 + (core_if->hwcfg2.b.hs_phy_type == 1)) {
27807 + val = DWC_PHY_TYPE_PARAM_UTMI;
27809 + val = DWC_PHY_TYPE_PARAM_ULPI;
27812 + retval = -DWC_E_INVALID;
27815 + core_if->core_params->phy_type = val;
27819 +int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if)
27821 + return core_if->core_params->phy_type;
27824 +int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val)
27827 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27828 + DWC_WARN("Wrong value for speed parameter\n");
27829 + DWC_WARN("max_speed parameter must be 0 or 1\n");
27830 + return -DWC_E_INVALID;
27833 + && dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS) {
27834 + if (dwc_otg_param_initialized(core_if->core_params->speed)) {
27836 + ("%d invalid for speed paremter. Check HW configuration.\n",
27840 + (dwc_otg_get_param_phy_type(core_if) ==
27841 + DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
27842 + retval = -DWC_E_INVALID;
27844 + core_if->core_params->speed = val;
27848 +int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if)
27850 + return core_if->core_params->speed;
27853 +int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if,
27858 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27860 + ("Wrong value for host_ls_low_power_phy_clk parameter\n");
27861 + DWC_WARN("host_ls_low_power_phy_clk must be 0 or 1\n");
27862 + return -DWC_E_INVALID;
27865 + if ((val == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ)
27866 + && (dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS)) {
27867 + if (dwc_otg_param_initialized
27868 + (core_if->core_params->host_ls_low_power_phy_clk)) {
27870 + ("%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
27874 + (dwc_otg_get_param_phy_type(core_if) ==
27875 + DWC_PHY_TYPE_PARAM_FS) ?
27876 + DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ :
27877 + DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
27878 + retval = -DWC_E_INVALID;
27881 + core_if->core_params->host_ls_low_power_phy_clk = val;
27885 +int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if)
27887 + return core_if->core_params->host_ls_low_power_phy_clk;
27890 +int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if, int32_t val)
27892 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27893 + DWC_WARN("Wrong value for phy_ulpi_ddr\n");
27894 + DWC_WARN("phy_upli_ddr must be 0 or 1\n");
27895 + return -DWC_E_INVALID;
27898 + core_if->core_params->phy_ulpi_ddr = val;
27902 +int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if)
27904 + return core_if->core_params->phy_ulpi_ddr;
27907 +int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
27910 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27911 + DWC_WARN("Wrong valaue for phy_ulpi_ext_vbus\n");
27912 + DWC_WARN("phy_ulpi_ext_vbus must be 0 or 1\n");
27913 + return -DWC_E_INVALID;
27916 + core_if->core_params->phy_ulpi_ext_vbus = val;
27920 +int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if)
27922 + return core_if->core_params->phy_ulpi_ext_vbus;
27925 +int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if, int32_t val)
27927 + if (DWC_OTG_PARAM_TEST(val, 8, 8) && DWC_OTG_PARAM_TEST(val, 16, 16)) {
27928 + DWC_WARN("Wrong valaue for phy_utmi_width\n");
27929 + DWC_WARN("phy_utmi_width must be 8 or 16\n");
27930 + return -DWC_E_INVALID;
27933 + core_if->core_params->phy_utmi_width = val;
27937 +int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if)
27939 + return core_if->core_params->phy_utmi_width;
27942 +int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if, int32_t val)
27944 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27945 + DWC_WARN("Wrong valaue for ulpi_fs_ls\n");
27946 + DWC_WARN("ulpi_fs_ls must be 0 or 1\n");
27947 + return -DWC_E_INVALID;
27950 + core_if->core_params->ulpi_fs_ls = val;
27954 +int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if)
27956 + return core_if->core_params->ulpi_fs_ls;
27959 +int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val)
27961 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27962 + DWC_WARN("Wrong valaue for ts_dline\n");
27963 + DWC_WARN("ts_dline must be 0 or 1\n");
27964 + return -DWC_E_INVALID;
27967 + core_if->core_params->ts_dline = val;
27971 +int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if)
27973 + return core_if->core_params->ts_dline;
27976 +int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if, int32_t val)
27979 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27980 + DWC_WARN("Wrong valaue for i2c_enable\n");
27981 + DWC_WARN("i2c_enable must be 0 or 1\n");
27982 + return -DWC_E_INVALID;
27984 +#ifndef NO_FS_PHY_HW_CHECK
27985 + if (val == 1 && core_if->hwcfg3.b.i2c == 0) {
27986 + if (dwc_otg_param_initialized(core_if->core_params->i2c_enable)) {
27988 + ("%d invalid for i2c_enable. Check HW configuration.\n",
27992 + retval = -DWC_E_INVALID;
27996 + core_if->core_params->i2c_enable = val;
28000 +int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if)
28002 + return core_if->core_params->i2c_enable;
28005 +int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
28006 + int32_t val, int fifo_num)
28010 + if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
28011 + DWC_WARN("Wrong value for dev_perio_tx_fifo_size\n");
28012 + DWC_WARN("dev_perio_tx_fifo_size must be 4-768\n");
28013 + return -DWC_E_INVALID;
28017 + (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) {
28018 + if (dwc_otg_param_initialized
28019 + (core_if->core_params->dev_perio_tx_fifo_size[fifo_num])) {
28021 + ("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n",
28024 + val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]));
28025 + retval = -DWC_E_INVALID;
28028 + core_if->core_params->dev_perio_tx_fifo_size[fifo_num] = val;
28032 +int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
28035 + return core_if->core_params->dev_perio_tx_fifo_size[fifo_num];
28038 +int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
28042 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
28043 + DWC_WARN("Wrong valaue for en_multiple_tx_fifo,\n");
28044 + DWC_WARN("en_multiple_tx_fifo must be 0 or 1\n");
28045 + return -DWC_E_INVALID;
28048 + if (val == 1 && core_if->hwcfg4.b.ded_fifo_en == 0) {
28049 + if (dwc_otg_param_initialized
28050 + (core_if->core_params->en_multiple_tx_fifo)) {
28052 + ("%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
28056 + retval = -DWC_E_INVALID;
28059 + core_if->core_params->en_multiple_tx_fifo = val;
28063 +int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if)
28065 + return core_if->core_params->en_multiple_tx_fifo;
28068 +int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val,
28073 + if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
28074 + DWC_WARN("Wrong value for dev_tx_fifo_size\n");
28075 + DWC_WARN("dev_tx_fifo_size must be 4-768\n");
28076 + return -DWC_E_INVALID;
28080 + (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) {
28081 + if (dwc_otg_param_initialized
28082 + (core_if->core_params->dev_tx_fifo_size[fifo_num])) {
28084 + ("`%d' invalid for parameter `dev_tx_fifo_size_%d'. Check HW configuration.\n",
28087 + val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]));
28088 + retval = -DWC_E_INVALID;
28091 + core_if->core_params->dev_tx_fifo_size[fifo_num] = val;
28095 +int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
28098 + return core_if->core_params->dev_tx_fifo_size[fifo_num];
28101 +int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val)
28105 + if (DWC_OTG_PARAM_TEST(val, 0, 7)) {
28106 + DWC_WARN("Wrong value for thr_ctl\n");
28107 + DWC_WARN("thr_ctl must be 0-7\n");
28108 + return -DWC_E_INVALID;
28111 + if ((val != 0) &&
28112 + (!dwc_otg_get_param_dma_enable(core_if) ||
28113 + !core_if->hwcfg4.b.ded_fifo_en)) {
28114 + if (dwc_otg_param_initialized(core_if->core_params->thr_ctl)) {
28116 + ("%d invalid for parameter thr_ctl. Check HW configuration.\n",
28120 + retval = -DWC_E_INVALID;
28123 + core_if->core_params->thr_ctl = val;
28127 +int32_t dwc_otg_get_param_thr_ctl(dwc_otg_core_if_t * core_if)
28129 + return core_if->core_params->thr_ctl;
28132 +int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if, int32_t val)
28136 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
28137 + DWC_WARN("Wrong value for lpm_enable\n");
28138 + DWC_WARN("lpm_enable must be 0 or 1\n");
28139 + return -DWC_E_INVALID;
28142 + if (val && !core_if->hwcfg3.b.otg_lpm_en) {
28143 + if (dwc_otg_param_initialized(core_if->core_params->lpm_enable)) {
28145 + ("%d invalid for parameter lpm_enable. Check HW configuration.\n",
28149 + retval = -DWC_E_INVALID;
28152 + core_if->core_params->lpm_enable = val;
28156 +int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if)
28158 + return core_if->core_params->lpm_enable;
28161 +int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
28163 + if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
28164 + DWC_WARN("Wrong valaue for tx_thr_length\n");
28165 + DWC_WARN("tx_thr_length must be 8 - 128\n");
28166 + return -DWC_E_INVALID;
28169 + core_if->core_params->tx_thr_length = val;
28173 +int32_t dwc_otg_get_param_tx_thr_length(dwc_otg_core_if_t * core_if)
28175 + return core_if->core_params->tx_thr_length;
28178 +int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
28180 + if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
28181 + DWC_WARN("Wrong valaue for rx_thr_length\n");
28182 + DWC_WARN("rx_thr_length must be 8 - 128\n");
28183 + return -DWC_E_INVALID;
28186 + core_if->core_params->rx_thr_length = val;
28190 +int32_t dwc_otg_get_param_rx_thr_length(dwc_otg_core_if_t * core_if)
28192 + return core_if->core_params->rx_thr_length;
28195 +int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if, int32_t val)
28197 + if (DWC_OTG_PARAM_TEST(val, 1, 1) &&
28198 + DWC_OTG_PARAM_TEST(val, 4, 4) &&
28199 + DWC_OTG_PARAM_TEST(val, 8, 8) &&
28200 + DWC_OTG_PARAM_TEST(val, 16, 16) &&
28201 + DWC_OTG_PARAM_TEST(val, 32, 32) &&
28202 + DWC_OTG_PARAM_TEST(val, 64, 64) &&
28203 + DWC_OTG_PARAM_TEST(val, 128, 128) &&
28204 + DWC_OTG_PARAM_TEST(val, 256, 256)) {
28205 + DWC_WARN("`%d' invalid for parameter `dma_burst_size'\n", val);
28206 + return -DWC_E_INVALID;
28208 + core_if->core_params->dma_burst_size = val;
28212 +int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if)
28214 + return core_if->core_params->dma_burst_size;
28217 +int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if, int32_t val)
28220 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
28221 + DWC_WARN("`%d' invalid for parameter `pti_enable'\n", val);
28222 + return -DWC_E_INVALID;
28224 + if (val && (core_if->snpsid < OTG_CORE_REV_2_72a)) {
28225 + if (dwc_otg_param_initialized(core_if->core_params->pti_enable)) {
28227 + ("%d invalid for parameter pti_enable. Check HW configuration.\n",
28230 + retval = -DWC_E_INVALID;
28233 + core_if->core_params->pti_enable = val;
28237 +int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if)
28239 + return core_if->core_params->pti_enable;
28242 +int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if, int32_t val)
28245 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
28246 + DWC_WARN("`%d' invalid for parameter `mpi_enable'\n", val);
28247 + return -DWC_E_INVALID;
28249 + if (val && (core_if->hwcfg2.b.multi_proc_int == 0)) {
28250 + if (dwc_otg_param_initialized(core_if->core_params->mpi_enable)) {
28252 + ("%d invalid for parameter mpi_enable. Check HW configuration.\n",
28255 + retval = -DWC_E_INVALID;
28258 + core_if->core_params->mpi_enable = val;
28262 +int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if)
28264 + return core_if->core_params->mpi_enable;
28267 +int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if, int32_t val)
28270 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
28271 + DWC_WARN("`%d' invalid for parameter `adp_enable'\n", val);
28272 + return -DWC_E_INVALID;
28274 + if (val && (core_if->hwcfg3.b.adp_supp == 0)) {
28275 + if (dwc_otg_param_initialized
28276 + (core_if->core_params->adp_supp_enable)) {
28278 + ("%d invalid for parameter adp_enable. Check HW configuration.\n",
28281 + retval = -DWC_E_INVALID;
28284 + core_if->core_params->adp_supp_enable = val;
28285 + /*Set OTG version 2.0 in case of enabling ADP*/
28287 + dwc_otg_set_param_otg_ver(core_if, 1);
28292 +int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if)
28294 + return core_if->core_params->adp_supp_enable;
28297 +int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if, int32_t val)
28300 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
28301 + DWC_WARN("`%d' invalid for parameter `ic_usb_cap'\n", val);
28302 + DWC_WARN("ic_usb_cap must be 0 or 1\n");
28303 + return -DWC_E_INVALID;
28306 + if (val && (core_if->hwcfg2.b.otg_enable_ic_usb == 0)) {
28307 + if (dwc_otg_param_initialized(core_if->core_params->ic_usb_cap)) {
28309 + ("%d invalid for parameter ic_usb_cap. Check HW configuration.\n",
28312 + retval = -DWC_E_INVALID;
28315 + core_if->core_params->ic_usb_cap = val;
28319 +int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if)
28321 + return core_if->core_params->ic_usb_cap;
28324 +int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, int32_t val)
28329 + if (DWC_OTG_PARAM_TEST(val, 0, 3)) {
28330 + DWC_WARN("`%d' invalid for parameter `ahb_thr_ratio'\n", val);
28331 + DWC_WARN("ahb_thr_ratio must be 0 - 3\n");
28332 + return -DWC_E_INVALID;
28336 + && (core_if->snpsid < OTG_CORE_REV_2_81a
28337 + || !dwc_otg_get_param_thr_ctl(core_if))) {
28340 + && ((dwc_otg_get_param_tx_thr_length(core_if) / (1 << val)) <
28344 + if (valid == 0) {
28345 + if (dwc_otg_param_initialized
28346 + (core_if->core_params->ahb_thr_ratio)) {
28348 + ("%d invalid for parameter ahb_thr_ratio. Check HW configuration.\n",
28351 + retval = -DWC_E_INVALID;
28355 + core_if->core_params->ahb_thr_ratio = val;
28359 +int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if)
28361 + return core_if->core_params->ahb_thr_ratio;
28364 +int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if, int32_t val)
28368 + hwcfg4_data_t hwcfg4 = {.d32 = 0 };
28369 + hwcfg4.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4);
28371 + if (DWC_OTG_PARAM_TEST(val, 0, 3)) {
28372 + DWC_WARN("`%d' invalid for parameter `power_down'\n", val);
28373 + DWC_WARN("power_down must be 0 - 2\n");
28374 + return -DWC_E_INVALID;
28377 + if ((val == 2) && (core_if->snpsid < OTG_CORE_REV_2_91a)) {
28381 + && ((core_if->snpsid < OTG_CORE_REV_3_00a)
28382 + || (hwcfg4.b.xhiber == 0))) {
28385 + if (valid == 0) {
28386 + if (dwc_otg_param_initialized(core_if->core_params->power_down)) {
28388 + ("%d invalid for parameter power_down. Check HW configuration.\n",
28391 + retval = -DWC_E_INVALID;
28394 + core_if->core_params->power_down = val;
28398 +int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if)
28400 + return core_if->core_params->power_down;
28403 +int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if, int32_t val)
28408 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
28409 + DWC_WARN("`%d' invalid for parameter `reload_ctl'\n", val);
28410 + DWC_WARN("reload_ctl must be 0 or 1\n");
28411 + return -DWC_E_INVALID;
28414 + if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_92a)) {
28417 + if (valid == 0) {
28418 + if (dwc_otg_param_initialized(core_if->core_params->reload_ctl)) {
28419 + DWC_ERROR("%d invalid for parameter reload_ctl."
28420 + "Check HW configuration.\n", val);
28422 + retval = -DWC_E_INVALID;
28425 + core_if->core_params->reload_ctl = val;
28429 +int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if)
28431 + return core_if->core_params->reload_ctl;
28434 +int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if, int32_t val)
28439 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
28440 + DWC_WARN("`%d' invalid for parameter `dev_out_nak'\n", val);
28441 + DWC_WARN("dev_out_nak must be 0 or 1\n");
28442 + return -DWC_E_INVALID;
28445 + if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_93a) ||
28446 + !(core_if->core_params->dma_desc_enable))) {
28449 + if (valid == 0) {
28450 + if (dwc_otg_param_initialized(core_if->core_params->dev_out_nak)) {
28451 + DWC_ERROR("%d invalid for parameter dev_out_nak."
28452 + "Check HW configuration.\n", val);
28454 + retval = -DWC_E_INVALID;
28457 + core_if->core_params->dev_out_nak = val;
28461 +int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if)
28463 + return core_if->core_params->dev_out_nak;
28466 +int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if, int32_t val)
28471 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
28472 + DWC_WARN("`%d' invalid for parameter `cont_on_bna'\n", val);
28473 + DWC_WARN("cont_on_bna must be 0 or 1\n");
28474 + return -DWC_E_INVALID;
28477 + if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_94a) ||
28478 + !(core_if->core_params->dma_desc_enable))) {
28481 + if (valid == 0) {
28482 + if (dwc_otg_param_initialized(core_if->core_params->cont_on_bna)) {
28483 + DWC_ERROR("%d invalid for parameter cont_on_bna."
28484 + "Check HW configuration.\n", val);
28486 + retval = -DWC_E_INVALID;
28489 + core_if->core_params->cont_on_bna = val;
28493 +int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if)
28495 + return core_if->core_params->cont_on_bna;
28498 +int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if, int32_t val)
28503 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
28504 + DWC_WARN("`%d' invalid for parameter `ahb_single'\n", val);
28505 + DWC_WARN("ahb_single must be 0 or 1\n");
28506 + return -DWC_E_INVALID;
28509 + if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_94a)) {
28512 + if (valid == 0) {
28513 + if (dwc_otg_param_initialized(core_if->core_params->ahb_single)) {
28514 + DWC_ERROR("%d invalid for parameter ahb_single."
28515 + "Check HW configuration.\n", val);
28517 + retval = -DWC_E_INVALID;
28520 + core_if->core_params->ahb_single = val;
28524 +int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if)
28526 + return core_if->core_params->ahb_single;
28529 +int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val)
28533 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
28534 + DWC_WARN("`%d' invalid for parameter `otg_ver'\n", val);
28536 + ("otg_ver must be 0(for OTG 1.3 support) or 1(for OTG 2.0 support)\n");
28537 + return -DWC_E_INVALID;
28540 + core_if->core_params->otg_ver = val;
28544 +int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if)
28546 + return core_if->core_params->otg_ver;
28549 +uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if)
28551 + gotgctl_data_t otgctl;
28552 + otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
28553 + return otgctl.b.hstnegscs;
28556 +uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if)
28558 + gotgctl_data_t otgctl;
28559 + otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
28560 + return otgctl.b.sesreqscs;
28563 +void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val)
28565 + if(core_if->otg_ver == 0) {
28566 + gotgctl_data_t otgctl;
28567 + otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
28568 + otgctl.b.hnpreq = val;
28569 + DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, otgctl.d32);
28571 + core_if->otg_sts = val;
28575 +uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if)
28577 + return core_if->snpsid;
28580 +uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if)
28582 + gintsts_data_t gintsts;
28583 + gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
28584 + return gintsts.b.curmode;
28587 +uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if)
28589 + gusbcfg_data_t usbcfg;
28590 + usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
28591 + return usbcfg.b.hnpcap;
28594 +void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
28596 + gusbcfg_data_t usbcfg;
28597 + usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
28598 + usbcfg.b.hnpcap = val;
28599 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
28602 +uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if)
28604 + gusbcfg_data_t usbcfg;
28605 + usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
28606 + return usbcfg.b.srpcap;
28609 +void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
28611 + gusbcfg_data_t usbcfg;
28612 + usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
28613 + usbcfg.b.srpcap = val;
28614 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
28617 +uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if)
28619 + dcfg_data_t dcfg;
28620 + /* originally: dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); */
28622 + dcfg.d32 = -1; //GRAYG
28623 + DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)\n", __func__, core_if);
28624 + if (NULL == core_if)
28625 + DWC_ERROR("reg request with NULL core_if\n");
28626 + DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)->dev_if(%p)\n", __func__,
28627 + core_if, core_if->dev_if);
28628 + if (NULL == core_if->dev_if)
28629 + DWC_ERROR("reg request with NULL dev_if\n");
28630 + DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)->dev_if(%p)->"
28631 + "dev_global_regs(%p)\n", __func__,
28632 + core_if, core_if->dev_if,
28633 + core_if->dev_if->dev_global_regs);
28634 + if (NULL == core_if->dev_if->dev_global_regs)
28635 + DWC_ERROR("reg request with NULL dev_global_regs\n");
28637 + DWC_DEBUGPL(DBG_CILV, "%s - &core_if(%p)->dev_if(%p)->"
28638 + "dev_global_regs(%p)->dcfg = %p\n", __func__,
28639 + core_if, core_if->dev_if,
28640 + core_if->dev_if->dev_global_regs,
28641 + &core_if->dev_if->dev_global_regs->dcfg);
28642 + dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
28644 + return dcfg.b.devspd;
28647 +void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val)
28649 + dcfg_data_t dcfg;
28650 + dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
28651 + dcfg.b.devspd = val;
28652 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
28655 +uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if)
28657 + hprt0_data_t hprt0;
28658 + hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
28659 + return hprt0.b.prtconnsts;
28662 +uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if)
28664 + dsts_data_t dsts;
28665 + dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
28666 + return dsts.b.enumspd;
28669 +uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if)
28671 + hprt0_data_t hprt0;
28672 + hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
28673 + return hprt0.b.prtpwr;
28677 +uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if)
28679 + return core_if->hibernation_suspend;
28682 +void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val)
28684 + hprt0_data_t hprt0;
28685 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
28686 + hprt0.b.prtpwr = val;
28687 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
28690 +uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if)
28692 + hprt0_data_t hprt0;
28693 + hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
28694 + return hprt0.b.prtsusp;
28698 +void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val)
28700 + hprt0_data_t hprt0;
28701 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
28702 + hprt0.b.prtsusp = val;
28703 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
28706 +uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if)
28708 + hfir_data_t hfir;
28709 + hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
28710 + return hfir.b.frint;
28714 +void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val)
28716 + hfir_data_t hfir;
28717 + uint32_t fram_int;
28718 + fram_int = calc_frame_interval(core_if);
28719 + hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
28720 + if (!core_if->core_params->reload_ctl) {
28721 + DWC_WARN("\nCannot reload HFIR register.HFIR.HFIRRldCtrl bit is"
28722 + "not set to 1.\nShould load driver with reload_ctl=1"
28723 + " module parameter\n");
28726 + switch (fram_int) {
28728 + if ((val < 3350) || (val > 4150)) {
28729 + DWC_WARN("HFIR interval for HS core and 30 MHz"
28730 + "clock freq should be from 3350 to 4150\n");
28735 + if ((val < 26820) || (val > 33180)) {
28736 + DWC_WARN("HFIR interval for FS/LS core and 30 MHz"
28737 + "clock freq should be from 26820 to 33180\n");
28742 + if ((val < 5360) || (val > 6640)) {
28743 + DWC_WARN("HFIR interval for HS core and 48 MHz"
28744 + "clock freq should be from 5360 to 6640\n");
28749 + if ((val < 42912) || (val > 53088)) {
28750 + DWC_WARN("HFIR interval for FS/LS core and 48 MHz"
28751 + "clock freq should be from 42912 to 53088\n");
28756 + if ((val < 6700) || (val > 8300)) {
28757 + DWC_WARN("HFIR interval for HS core and 60 MHz"
28758 + "clock freq should be from 6700 to 8300\n");
28763 + if ((val < 53640) || (val > 65536)) {
28764 + DWC_WARN("HFIR interval for FS/LS core and 60 MHz"
28765 + "clock freq should be from 53640 to 65536\n");
28770 + DWC_WARN("Unknown frame interval\n");
28775 + hfir.b.frint = val;
28776 + DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hfir.d32);
28779 +uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if)
28781 + hcfg_data_t hcfg;
28782 + hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
28783 + return hcfg.b.modechtimen;
28787 +void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val)
28789 + hcfg_data_t hcfg;
28790 + hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
28791 + hcfg.b.modechtimen = val;
28792 + DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
28795 +void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val)
28797 + hprt0_data_t hprt0;
28798 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
28799 + hprt0.b.prtres = val;
28800 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
28803 +uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if)
28805 + dctl_data_t dctl;
28806 + dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
28807 + return dctl.b.rmtwkupsig;
28810 +uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if)
28812 + glpmcfg_data_t lpmcfg;
28813 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28816 + ((core_if->lx_state == DWC_OTG_L1) ^ lpmcfg.b.prt_sleep_sts),
28817 + "lx_state = %d, lmpcfg.prt_sleep_sts = %d\n",
28818 + core_if->lx_state, lpmcfg.b.prt_sleep_sts);
28820 + return lpmcfg.b.prt_sleep_sts;
28823 +uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if)
28825 + glpmcfg_data_t lpmcfg;
28826 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28827 + return lpmcfg.b.rem_wkup_en;
28830 +uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if)
28832 + glpmcfg_data_t lpmcfg;
28833 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28834 + return lpmcfg.b.appl_resp;
28837 +void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val)
28839 + glpmcfg_data_t lpmcfg;
28840 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28841 + lpmcfg.b.appl_resp = val;
28842 + DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
28845 +uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if)
28847 + glpmcfg_data_t lpmcfg;
28848 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28849 + return lpmcfg.b.hsic_connect;
28852 +void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val)
28854 + glpmcfg_data_t lpmcfg;
28855 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28856 + lpmcfg.b.hsic_connect = val;
28857 + DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
28860 +uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if)
28862 + glpmcfg_data_t lpmcfg;
28863 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28864 + return lpmcfg.b.inv_sel_hsic;
28868 +void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val)
28870 + glpmcfg_data_t lpmcfg;
28871 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28872 + lpmcfg.b.inv_sel_hsic = val;
28873 + DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
28876 +uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if)
28878 + return DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
28881 +void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val)
28883 + DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, val);
28886 +uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if)
28888 + return DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
28891 +void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val)
28893 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, val);
28896 +uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if)
28898 + return DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
28901 +void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
28903 + DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, val);
28906 +uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if)
28908 + return DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
28911 +void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
28913 + DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz, val);
28916 +uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if)
28918 + return DWC_READ_REG32(&core_if->core_global_regs->gpvndctl);
28921 +void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val)
28923 + DWC_WRITE_REG32(&core_if->core_global_regs->gpvndctl, val);
28926 +uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if)
28928 + return DWC_READ_REG32(&core_if->core_global_regs->ggpio);
28931 +void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val)
28933 + DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, val);
28936 +uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if)
28938 + return DWC_READ_REG32(core_if->host_if->hprt0);
28942 +void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val)
28944 + DWC_WRITE_REG32(core_if->host_if->hprt0, val);
28947 +uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if)
28949 + return DWC_READ_REG32(&core_if->core_global_regs->guid);
28952 +void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val)
28954 + DWC_WRITE_REG32(&core_if->core_global_regs->guid, val);
28957 +uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if)
28959 + return DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
28962 +uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if)
28964 + return ((core_if->otg_ver == 1) ? (uint16_t)0x0200 : (uint16_t)0x0103);
28968 + * Start the SRP timer to detect when the SRP does not complete within
28971 + * @param core_if the pointer to core_if strucure.
28973 +void dwc_otg_pcd_start_srp_timer(dwc_otg_core_if_t * core_if)
28975 + core_if->srp_timer_started = 1;
28976 + DWC_TIMER_SCHEDULE(core_if->srp_timer, 6000 /* 6 secs */ );
28979 +void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if)
28981 + uint32_t *addr = (uint32_t *) & (core_if->core_global_regs->gotgctl);
28982 + gotgctl_data_t mem;
28983 + gotgctl_data_t val;
28985 + val.d32 = DWC_READ_REG32(addr);
28986 + if (val.b.sesreq) {
28987 + DWC_ERROR("Session Request Already active!\n");
28991 + DWC_INFO("Session Request Initated\n"); //NOTICE
28992 + mem.d32 = DWC_READ_REG32(addr);
28993 + mem.b.sesreq = 1;
28994 + DWC_WRITE_REG32(addr, mem.d32);
28996 + /* Start the SRP timer */
28997 + dwc_otg_pcd_start_srp_timer(core_if);
29001 +++ b/drivers/usb/host/dwc_otg/dwc_otg_cil.h
29003 +/* ==========================================================================
29004 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $
29005 + * $Revision: #123 $
29006 + * $Date: 2012/08/10 $
29007 + * $Change: 2047372 $
29009 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
29010 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
29011 + * otherwise expressly agreed to in writing between Synopsys and you.
29013 + * The Software IS NOT an item of Licensed Software or Licensed Product under
29014 + * any End User Software License Agreement or Agreement for Licensed Product
29015 + * with Synopsys or any supplement thereto. You are permitted to use and
29016 + * redistribute this Software in source and binary forms, with or without
29017 + * modification, provided that redistributions of source code must retain this
29018 + * notice. You may not view, use, disclose, copy or distribute this file or
29019 + * any information contained herein except pursuant to this license grant from
29020 + * Synopsys. If you do not agree with this notice, including the disclaimer
29021 + * below, then you are not authorized to use the Software.
29023 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
29024 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29025 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29026 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
29027 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29028 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29029 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29030 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29031 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29032 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
29034 + * ========================================================================== */
29036 +#if !defined(__DWC_CIL_H__)
29037 +#define __DWC_CIL_H__
29039 +#include "dwc_list.h"
29040 +#include "dwc_otg_dbg.h"
29041 +#include "dwc_otg_regs.h"
29043 +#include "dwc_otg_core_if.h"
29044 +#include "dwc_otg_adp.h"
29048 + * This file contains the interface to the Core Interface Layer.
29051 +#ifdef DWC_UTE_CFI
29053 +#define MAX_DMA_DESCS_PER_EP 256
29056 + * Enumeration for the data buffer mode
29058 +typedef enum _data_buffer_mode {
29059 + BM_STANDARD = 0, /* data buffer is in normal mode */
29060 + BM_SG = 1, /* data buffer uses the scatter/gather mode */
29061 + BM_CONCAT = 2, /* data buffer uses the concatenation mode */
29062 + BM_CIRCULAR = 3, /* data buffer uses the circular DMA mode */
29063 + BM_ALIGN = 4 /* data buffer is in buffer alignment mode */
29064 +} data_buffer_mode_e;
29065 +#endif //DWC_UTE_CFI
29067 +/** Macros defined for DWC OTG HW Release version */
29069 +#define OTG_CORE_REV_2_60a 0x4F54260A
29070 +#define OTG_CORE_REV_2_71a 0x4F54271A
29071 +#define OTG_CORE_REV_2_72a 0x4F54272A
29072 +#define OTG_CORE_REV_2_80a 0x4F54280A
29073 +#define OTG_CORE_REV_2_81a 0x4F54281A
29074 +#define OTG_CORE_REV_2_90a 0x4F54290A
29075 +#define OTG_CORE_REV_2_91a 0x4F54291A
29076 +#define OTG_CORE_REV_2_92a 0x4F54292A
29077 +#define OTG_CORE_REV_2_93a 0x4F54293A
29078 +#define OTG_CORE_REV_2_94a 0x4F54294A
29079 +#define OTG_CORE_REV_3_00a 0x4F54300A
29082 + * Information for each ISOC packet.
29084 +typedef struct iso_pkt_info {
29091 + * The <code>dwc_ep</code> structure represents the state of a single
29092 + * endpoint when acting in device mode. It contains the data items
29093 + * needed for an endpoint to be activated and transfer packets.
29095 +typedef struct dwc_ep {
29096 + /** EP number used for register address lookup */
29098 + /** EP direction 0 = OUT */
29099 + unsigned is_in:1;
29100 + /** EP active. */
29101 + unsigned active:1;
29104 + * Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic
29105 + * Tx FIFO. If dedicated Tx FIFOs are enabled Tx FIFO # FOR IN EPs*/
29106 + unsigned tx_fifo_num:4;
29107 + /** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */
29109 +#define DWC_OTG_EP_TYPE_CONTROL 0
29110 +#define DWC_OTG_EP_TYPE_ISOC 1
29111 +#define DWC_OTG_EP_TYPE_BULK 2
29112 +#define DWC_OTG_EP_TYPE_INTR 3
29114 + /** DATA start PID for INTR and BULK EP */
29115 + unsigned data_pid_start:1;
29116 + /** Frame (even/odd) for ISOC EP */
29117 + unsigned even_odd_frame:1;
29118 + /** Max Packet bytes */
29119 + unsigned maxpacket:11;
29121 + /** Max Transfer size */
29122 + uint32_t maxxfer;
29124 + /** @name Transfer state */
29128 + * Pointer to the beginning of the transfer buffer -- do not modify
29129 + * during transfer.
29132 + dwc_dma_t dma_addr;
29134 + dwc_dma_t dma_desc_addr;
29135 + dwc_otg_dev_dma_desc_t *desc_addr;
29137 + uint8_t *start_xfer_buff;
29138 + /** pointer to the transfer buffer */
29139 + uint8_t *xfer_buff;
29140 + /** Number of bytes to transfer */
29141 + unsigned xfer_len:19;
29142 + /** Number of bytes transferred. */
29143 + unsigned xfer_count:19;
29145 + unsigned sent_zlp:1;
29146 + /** Total len for control transfer */
29147 + unsigned total_len:19;
29149 + /** stall clear flag */
29150 + unsigned stall_clear_flag:1;
29152 + /** SETUP pkt cnt rollover flag for EP0 out*/
29153 + unsigned stp_rollover;
29155 +#ifdef DWC_UTE_CFI
29156 + /* The buffer mode */
29157 + data_buffer_mode_e buff_mode;
29159 + /* The chain of DMA descriptors.
29160 + * MAX_DMA_DESCS_PER_EP will be allocated for each active EP.
29162 + dwc_otg_dma_desc_t *descs;
29164 + /* The DMA address of the descriptors chain start */
29165 + dma_addr_t descs_dma_addr;
29166 + /** This variable stores the length of the last enqueued request */
29167 + uint32_t cfi_req_len;
29168 +#endif //DWC_UTE_CFI
29170 +/** Max DMA Descriptor count for any EP */
29171 +#define MAX_DMA_DESC_CNT 256
29172 + /** Allocated DMA Desc count */
29173 + uint32_t desc_cnt;
29176 + uint32_t bInterval;
29177 + /** Next frame num to setup next ISOC transfer */
29178 + uint32_t frame_num;
29179 + /** Indicates SOF number overrun in DSTS */
29180 + uint8_t frm_overrun;
29182 +#ifdef DWC_UTE_PER_IO
29183 + /** Next frame num for which will be setup DMA Desc */
29184 + uint32_t xiso_frame_num;
29186 + uint32_t xiso_bInterval;
29187 + /** Count of currently active transfers - shall be either 0 or 1 */
29188 + int xiso_active_xfers;
29189 + int xiso_queued_xfers;
29191 +#ifdef DWC_EN_ISOC
29193 + * Variables specific for ISOC EPs
29196 + /** DMA addresses of ISOC buffers */
29197 + dwc_dma_t dma_addr0;
29198 + dwc_dma_t dma_addr1;
29200 + dwc_dma_t iso_dma_desc_addr;
29201 + dwc_otg_dev_dma_desc_t *iso_desc_addr;
29203 + /** pointer to the transfer buffers */
29204 + uint8_t *xfer_buff0;
29205 + uint8_t *xfer_buff1;
29207 + /** number of ISOC Buffer is processing */
29208 + uint32_t proc_buf_num;
29209 + /** Interval of ISOC Buffer processing */
29210 + uint32_t buf_proc_intrvl;
29211 + /** Data size for regular frame */
29212 + uint32_t data_per_frame;
29214 + /* todo - pattern data support is to be implemented in the future */
29215 + /** Data size for pattern frame */
29216 + uint32_t data_pattern_frame;
29217 + /** Frame number of pattern data */
29218 + uint32_t sync_frame;
29221 + uint32_t bInterval;
29222 + /** ISO Packet number per frame */
29223 + uint32_t pkt_per_frm;
29224 + /** Next frame num for which will be setup DMA Desc */
29225 + uint32_t next_frame;
29226 + /** Number of packets per buffer processing */
29227 + uint32_t pkt_cnt;
29228 + /** Info for all isoc packets */
29229 + iso_pkt_info_t *pkt_info;
29230 + /** current pkt number */
29231 + uint32_t cur_pkt;
29232 + /** current pkt number */
29233 + uint8_t *cur_pkt_addr;
29234 + /** current pkt number */
29235 + uint32_t cur_pkt_dma_addr;
29236 +#endif /* DWC_EN_ISOC */
29242 + * Reasons for halting a host channel.
29244 +typedef enum dwc_otg_halt_status {
29245 + DWC_OTG_HC_XFER_NO_HALT_STATUS,
29246 + DWC_OTG_HC_XFER_COMPLETE,
29247 + DWC_OTG_HC_XFER_URB_COMPLETE,
29248 + DWC_OTG_HC_XFER_ACK,
29249 + DWC_OTG_HC_XFER_NAK,
29250 + DWC_OTG_HC_XFER_NYET,
29251 + DWC_OTG_HC_XFER_STALL,
29252 + DWC_OTG_HC_XFER_XACT_ERR,
29253 + DWC_OTG_HC_XFER_FRAME_OVERRUN,
29254 + DWC_OTG_HC_XFER_BABBLE_ERR,
29255 + DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
29256 + DWC_OTG_HC_XFER_AHB_ERR,
29257 + DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
29258 + DWC_OTG_HC_XFER_URB_DEQUEUE
29259 +} dwc_otg_halt_status_e;
29262 + * Host channel descriptor. This structure represents the state of a single
29263 + * host channel when acting in host mode. It contains the data items needed to
29264 + * transfer packets to an endpoint via a host channel.
29266 +typedef struct dwc_hc {
29267 + /** Host channel number used for register address lookup */
29270 + /** Device to access */
29271 + unsigned dev_addr:7;
29273 + /** EP to access */
29274 + unsigned ep_num:4;
29276 + /** EP direction. 0: OUT, 1: IN */
29277 + unsigned ep_is_in:1;
29281 + * One of the following values:
29282 + * - DWC_OTG_EP_SPEED_LOW
29283 + * - DWC_OTG_EP_SPEED_FULL
29284 + * - DWC_OTG_EP_SPEED_HIGH
29286 + unsigned speed:2;
29287 +#define DWC_OTG_EP_SPEED_LOW 0
29288 +#define DWC_OTG_EP_SPEED_FULL 1
29289 +#define DWC_OTG_EP_SPEED_HIGH 2
29293 + * One of the following values:
29294 + * - DWC_OTG_EP_TYPE_CONTROL: 0
29295 + * - DWC_OTG_EP_TYPE_ISOC: 1
29296 + * - DWC_OTG_EP_TYPE_BULK: 2
29297 + * - DWC_OTG_EP_TYPE_INTR: 3
29299 + unsigned ep_type:2;
29301 + /** Max packet size in bytes */
29302 + unsigned max_packet:11;
29305 + * PID for initial transaction.
29309 + * 3: MDATA (non-Control EP),
29310 + * SETUP (Control EP)
29312 + unsigned data_pid_start:2;
29313 +#define DWC_OTG_HC_PID_DATA0 0
29314 +#define DWC_OTG_HC_PID_DATA2 1
29315 +#define DWC_OTG_HC_PID_DATA1 2
29316 +#define DWC_OTG_HC_PID_MDATA 3
29317 +#define DWC_OTG_HC_PID_SETUP 3
29319 + /** Number of periodic transactions per (micro)frame */
29320 + unsigned multi_count:2;
29322 + /** @name Transfer State */
29325 + /** Pointer to the current transfer buffer position. */
29326 + uint8_t *xfer_buff;
29328 + * In Buffer DMA mode this buffer will be used
29329 + * if xfer_buff is not DWORD aligned.
29331 + dwc_dma_t align_buff;
29332 + /** Total number of bytes to transfer. */
29333 + uint32_t xfer_len;
29334 + /** Number of bytes transferred so far. */
29335 + uint32_t xfer_count;
29336 + /** Packet count at start of transfer.*/
29337 + uint16_t start_pkt_count;
29340 + * Flag to indicate whether the transfer has been started. Set to 1 if
29341 + * it has been started, 0 otherwise.
29343 + uint8_t xfer_started;
29346 + * Set to 1 to indicate that a PING request should be issued on this
29347 + * channel. If 0, process normally.
29352 + * Set to 1 to indicate that the error count for this transaction is
29353 + * non-zero. Set to 0 if the error count is 0.
29355 + uint8_t error_state;
29358 + * Set to 1 to indicate that this channel should be halted the next
29359 + * time a request is queued for the channel. This is necessary in
29360 + * slave mode if no request queue space is available when an attempt
29361 + * is made to halt the channel.
29363 + uint8_t halt_on_queue;
29366 + * Set to 1 if the host channel has been halted, but the core is not
29367 + * finished flushing queued requests. Otherwise 0.
29369 + uint8_t halt_pending;
29372 + * Reason for halting the host channel.
29374 + dwc_otg_halt_status_e halt_status;
29377 + * Split settings for the host channel
29379 + uint8_t do_split; /**< Enable split for the channel */
29380 + uint8_t complete_split; /**< Enable complete split */
29381 + uint8_t hub_addr; /**< Address of high speed hub */
29383 + uint8_t port_addr; /**< Port of the low/full speed device */
29384 + /** Split transaction position
29385 + * One of the following values:
29386 + * - DWC_HCSPLIT_XACTPOS_MID
29387 + * - DWC_HCSPLIT_XACTPOS_BEGIN
29388 + * - DWC_HCSPLIT_XACTPOS_END
29389 + * - DWC_HCSPLIT_XACTPOS_ALL */
29390 + uint8_t xact_pos;
29392 + /** Set when the host channel does a short read. */
29393 + uint8_t short_read;
29396 + * Number of requests issued for this channel since it was assigned to
29397 + * the current transfer (not counting PINGs).
29399 + uint8_t requests;
29402 + * Queue Head for the transfer being processed by this channel.
29404 + struct dwc_otg_qh *qh;
29408 + /** Entry in list of host channels. */
29409 + DWC_CIRCLEQ_ENTRY(dwc_hc) hc_list_entry;
29411 + /** @name Descriptor DMA support */
29414 + /** Number of Transfer Descriptors */
29417 + /** Descriptor List DMA address */
29418 + dwc_dma_t desc_list_addr;
29420 + /** Scheduling micro-frame bitmap. */
29427 + * The following parameters may be specified when starting the module. These
29428 + * parameters define how the DWC_otg controller should be configured.
29430 +typedef struct dwc_otg_core_params {
29434 + * Specifies the OTG capabilities. The driver will automatically
29435 + * detect the value for this parameter if none is specified.
29436 + * 0 - HNP and SRP capable (default)
29437 + * 1 - SRP Only capable
29438 + * 2 - No HNP/SRP capable
29443 + * Specifies whether to use slave or DMA mode for accessing the data
29444 + * FIFOs. The driver will automatically detect the value for this
29445 + * parameter if none is specified.
29447 + * 1 - DMA (default, if available)
29449 + int32_t dma_enable;
29452 + * When DMA mode is enabled specifies whether to use address DMA or DMA
29453 + * Descriptor mode for accessing the data FIFOs in device mode. The driver
29454 + * will automatically detect the value for this if none is specified.
29455 + * 0 - address DMA
29456 + * 1 - DMA Descriptor(default, if available)
29458 + int32_t dma_desc_enable;
29459 + /** The DMA Burst size (applicable only for External DMA
29460 + * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
29462 + int32_t dma_burst_size; /* Translate this to GAHBCFG values */
29465 + * Specifies the maximum speed of operation in host and device mode.
29466 + * The actual speed depends on the speed of the attached device and
29467 + * the value of phy_type. The actual speed depends on the speed of the
29468 + * attached device.
29469 + * 0 - High Speed (default)
29473 + /** Specifies whether low power mode is supported when attached
29474 + * to a Full Speed or Low Speed device in host mode.
29475 + * 0 - Don't support low power mode (default)
29476 + * 1 - Support low power mode
29478 + int32_t host_support_fs_ls_low_power;
29480 + /** Specifies the PHY clock rate in low power mode when connected to a
29481 + * Low Speed device in host mode. This parameter is applicable only if
29482 + * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
29483 + * then defaults to 6 MHZ otherwise 48 MHZ.
29488 + int32_t host_ls_low_power_phy_clk;
29491 + * 0 - Use cC FIFO size parameters
29492 + * 1 - Allow dynamic FIFO sizing (default)
29494 + int32_t enable_dynamic_fifo;
29496 + /** Total number of 4-byte words in the data FIFO memory. This
29497 + * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
29499 + * 32 to 32768 (default 8192)
29500 + * Note: The total FIFO memory depth in the FPGA configuration is 8192.
29502 + int32_t data_fifo_size;
29504 + /** Number of 4-byte words in the Rx FIFO in device mode when dynamic
29505 + * FIFO sizing is enabled.
29506 + * 16 to 32768 (default 1064)
29508 + int32_t dev_rx_fifo_size;
29510 + /** Number of 4-byte words in the non-periodic Tx FIFO in device mode
29511 + * when dynamic FIFO sizing is enabled.
29512 + * 16 to 32768 (default 1024)
29514 + int32_t dev_nperio_tx_fifo_size;
29516 + /** Number of 4-byte words in each of the periodic Tx FIFOs in device
29517 + * mode when dynamic FIFO sizing is enabled.
29518 + * 4 to 768 (default 256)
29520 + uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
29522 + /** Number of 4-byte words in the Rx FIFO in host mode when dynamic
29523 + * FIFO sizing is enabled.
29524 + * 16 to 32768 (default 1024)
29526 + int32_t host_rx_fifo_size;
29528 + /** Number of 4-byte words in the non-periodic Tx FIFO in host mode
29529 + * when Dynamic FIFO sizing is enabled in the core.
29530 + * 16 to 32768 (default 1024)
29532 + int32_t host_nperio_tx_fifo_size;
29534 + /** Number of 4-byte words in the host periodic Tx FIFO when dynamic
29535 + * FIFO sizing is enabled.
29536 + * 16 to 32768 (default 1024)
29538 + int32_t host_perio_tx_fifo_size;
29540 + /** The maximum transfer size supported in bytes.
29541 + * 2047 to 65,535 (default 65,535)
29543 + int32_t max_transfer_size;
29545 + /** The maximum number of packets in a transfer.
29546 + * 15 to 511 (default 511)
29548 + int32_t max_packet_count;
29550 + /** The number of host channel registers to use.
29551 + * 1 to 16 (default 12)
29552 + * Note: The FPGA configuration supports a maximum of 12 host channels.
29554 + int32_t host_channels;
29556 + /** The number of endpoints in addition to EP0 available for device
29557 + * mode operations.
29558 + * 1 to 15 (default 6 IN and OUT)
29559 + * Note: The FPGA configuration supports a maximum of 6 IN and OUT
29560 + * endpoints in addition to EP0.
29562 + int32_t dev_endpoints;
29565 + * Specifies the type of PHY interface to use. By default, the driver
29566 + * will automatically detect the phy_type.
29568 + * 0 - Full Speed PHY
29569 + * 1 - UTMI+ (default)
29572 + int32_t phy_type;
29575 + * Specifies the UTMI+ Data Width. This parameter is
29576 + * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
29577 + * PHY_TYPE, this parameter indicates the data width between
29578 + * the MAC and the ULPI Wrapper.) Also, this parameter is
29579 + * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
29580 + * to "8 and 16 bits", meaning that the core has been
29581 + * configured to work at either data path width.
29583 + * 8 or 16 bits (default 16)
29585 + int32_t phy_utmi_width;
29588 + * Specifies whether the ULPI operates at double or single
29589 + * data rate. This parameter is only applicable if PHY_TYPE is
29592 + * 0 - single data rate ULPI interface with 8 bit wide data
29594 + * 1 - double data rate ULPI interface with 4 bit wide data
29597 + int32_t phy_ulpi_ddr;
29600 + * Specifies whether to use the internal or external supply to
29601 + * drive the vbus with a ULPI phy.
29603 + int32_t phy_ulpi_ext_vbus;
29606 + * Specifies whether to use the I2Cinterface for full speed PHY. This
29607 + * parameter is only applicable if PHY_TYPE is FS.
29608 + * 0 - No (default)
29611 + int32_t i2c_enable;
29613 + int32_t ulpi_fs_ls;
29615 + int32_t ts_dline;
29618 + * Specifies whether dedicated transmit FIFOs are
29619 + * enabled for non periodic IN endpoints in device mode
29623 + int32_t en_multiple_tx_fifo;
29625 + /** Number of 4-byte words in each of the Tx FIFOs in device
29626 + * mode when dynamic FIFO sizing is enabled.
29627 + * 4 to 768 (default 256)
29629 + uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
29631 + /** Thresholding enable flag-
29632 + * bit 0 - enable non-ISO Tx thresholding
29633 + * bit 1 - enable ISO Tx thresholding
29634 + * bit 2 - enable Rx thresholding
29636 + uint32_t thr_ctl;
29638 + /** Thresholding length for Tx
29639 + * FIFOs in 32 bit DWORDs
29641 + uint32_t tx_thr_length;
29643 + /** Thresholding length for Rx
29644 + * FIFOs in 32 bit DWORDs
29646 + uint32_t rx_thr_length;
29649 + * Specifies whether LPM (Link Power Management) support is enabled
29651 + int32_t lpm_enable;
29653 + /** Per Transfer Interrupt
29654 + * mode enable flag
29658 + int32_t pti_enable;
29660 + /** Multi Processor Interrupt
29661 + * mode enable flag
29665 + int32_t mpi_enable;
29667 + /** IS_USB Capability
29671 + int32_t ic_usb_cap;
29673 + /** AHB Threshold Ratio
29674 + * 2'b00 AHB Threshold = MAC Threshold
29675 + * 2'b01 AHB Threshold = 1/2 MAC Threshold
29676 + * 2'b10 AHB Threshold = 1/4 MAC Threshold
29677 + * 2'b11 AHB Threshold = 1/8 MAC Threshold
29679 + int32_t ahb_thr_ratio;
29685 + int32_t adp_supp_enable;
29687 + /** HFIR Reload Control
29688 + * 0 - The HFIR cannot be reloaded dynamically.
29689 + * 1 - Allow dynamic reloading of the HFIR register during runtime.
29691 + int32_t reload_ctl;
29693 + /** DCFG: Enable device Out NAK
29694 + * 0 - The core does not set NAK after Bulk Out transfer complete.
29695 + * 1 - The core sets NAK after Bulk OUT transfer complete.
29697 + int32_t dev_out_nak;
29699 + /** DCFG: Enable Continue on BNA
29700 + * After receiving BNA interrupt the core disables the endpoint,when the
29701 + * endpoint is re-enabled by the application the core starts processing
29702 + * 0 - from the DOEPDMA descriptor
29703 + * 1 - from the descriptor which received the BNA.
29705 + int32_t cont_on_bna;
29707 + /** GAHBCFG: AHB Single Support
29708 + * This bit when programmed supports SINGLE transfers for remainder
29709 + * data in a transfer for DMA mode of operation.
29710 + * 0 - in this case the remainder data will be sent using INCR burst size.
29711 + * 1 - in this case the remainder data will be sent using SINGLE burst size.
29713 + int32_t ahb_single;
29715 + /** Core Power down mode
29716 + * 0 - No Power Down is enabled
29718 + * 2 - Complete Power Down (Hibernation)
29720 + int32_t power_down;
29722 + /** OTG revision supported
29723 + * 0 - OTG 1.3 revision
29724 + * 1 - OTG 2.0 revision
29728 +} dwc_otg_core_params_t;
29731 +struct dwc_otg_core_if;
29732 +typedef struct hc_xfer_info {
29733 + struct dwc_otg_core_if *core_if;
29738 +typedef struct ep_xfer_info {
29739 + struct dwc_otg_core_if *core_if;
29746 +typedef enum dwc_otg_lx_state {
29749 + /** LPM sleep state*/
29751 + /** USB suspend state*/
29755 +} dwc_otg_lx_state_e;
29757 +struct dwc_otg_global_regs_backup {
29758 + uint32_t gotgctl_local;
29759 + uint32_t gintmsk_local;
29760 + uint32_t gahbcfg_local;
29761 + uint32_t gusbcfg_local;
29762 + uint32_t grxfsiz_local;
29763 + uint32_t gnptxfsiz_local;
29764 +#ifdef CONFIG_USB_DWC_OTG_LPM
29765 + uint32_t glpmcfg_local;
29767 + uint32_t gi2cctl_local;
29768 + uint32_t hptxfsiz_local;
29769 + uint32_t pcgcctl_local;
29770 + uint32_t gdfifocfg_local;
29771 + uint32_t dtxfsiz_local[MAX_EPS_CHANNELS];
29772 + uint32_t gpwrdn_local;
29773 + uint32_t xhib_pcgcctl;
29774 + uint32_t xhib_gpwrdn;
29777 +struct dwc_otg_host_regs_backup {
29778 + uint32_t hcfg_local;
29779 + uint32_t haintmsk_local;
29780 + uint32_t hcintmsk_local[MAX_EPS_CHANNELS];
29781 + uint32_t hprt0_local;
29782 + uint32_t hfir_local;
29785 +struct dwc_otg_dev_regs_backup {
29788 + uint32_t daintmsk;
29789 + uint32_t diepmsk;
29790 + uint32_t doepmsk;
29791 + uint32_t diepctl[MAX_EPS_CHANNELS];
29792 + uint32_t dieptsiz[MAX_EPS_CHANNELS];
29793 + uint32_t diepdma[MAX_EPS_CHANNELS];
29796 + * The <code>dwc_otg_core_if</code> structure contains information needed to manage
29797 + * the DWC_otg controller acting in either host or device mode. It
29798 + * represents the programming view of the controller as a whole.
29800 +struct dwc_otg_core_if {
29801 + /** Parameters that define how the core should be configured.*/
29802 + dwc_otg_core_params_t *core_params;
29804 + /** Core Global registers starting at offset 000h. */
29805 + dwc_otg_core_global_regs_t *core_global_regs;
29807 + /** Device-specific information */
29808 + dwc_otg_dev_if_t *dev_if;
29809 + /** Host-specific information */
29810 + dwc_otg_host_if_t *host_if;
29812 + /** Value from SNPSID register */
29816 + * Set to 1 if the core PHY interface bits in USBCFG have been
29819 + uint8_t phy_init_done;
29822 + * SRP Success flag, set by srp success interrupt in FS I2C mode
29824 + uint8_t srp_success;
29825 + uint8_t srp_timer_started;
29826 + /** Timer for SRP. If it expires before SRP is successful
29827 + * clear the SRP. */
29828 + dwc_timer_t *srp_timer;
29830 +#ifdef DWC_DEV_SRPCAP
29831 + /* This timer is needed to power on the hibernated host core if SRP is not
29832 + * initiated on connected SRP capable device for limited period of time
29834 + uint8_t pwron_timer_started;
29835 + dwc_timer_t *pwron_timer;
29837 + /* Common configuration information */
29838 + /** Power and Clock Gating Control Register */
29839 + volatile uint32_t *pcgcctl;
29840 +#define DWC_OTG_PCGCCTL_OFFSET 0xE00
29842 + /** Push/pop addresses for endpoints or host channels.*/
29843 + uint32_t *data_fifo[MAX_EPS_CHANNELS];
29844 +#define DWC_OTG_DATA_FIFO_OFFSET 0x1000
29845 +#define DWC_OTG_DATA_FIFO_SIZE 0x1000
29847 + /** Total RAM for FIFOs (Bytes) */
29848 + uint16_t total_fifo_size;
29849 + /** Size of Rx FIFO (Bytes) */
29850 + uint16_t rx_fifo_size;
29851 + /** Size of Non-periodic Tx FIFO (Bytes) */
29852 + uint16_t nperio_tx_fifo_size;
29854 + /** 1 if DMA is enabled, 0 otherwise. */
29855 + uint8_t dma_enable;
29857 + /** 1 if DMA descriptor is enabled, 0 otherwise. */
29858 + uint8_t dma_desc_enable;
29860 + /** 1 if PTI Enhancement mode is enabled, 0 otherwise. */
29861 + uint8_t pti_enh_enable;
29863 + /** 1 if MPI Enhancement mode is enabled, 0 otherwise. */
29864 + uint8_t multiproc_int_enable;
29866 + /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */
29867 + uint8_t en_multiple_tx_fifo;
29869 + /** Set to 1 if multiple packets of a high-bandwidth transfer is in
29870 + * process of being queued */
29871 + uint8_t queuing_high_bandwidth;
29873 + /** Hardware Configuration -- stored here for convenience.*/
29874 + hwcfg1_data_t hwcfg1;
29875 + hwcfg2_data_t hwcfg2;
29876 + hwcfg3_data_t hwcfg3;
29877 + hwcfg4_data_t hwcfg4;
29878 + fifosize_data_t hptxfsiz;
29880 + /** Host and Device Configuration -- stored here for convenience.*/
29881 + hcfg_data_t hcfg;
29882 + dcfg_data_t dcfg;
29884 + /** The operational State, during transations
29885 + * (a_host>>a_peripherial and b_device=>b_host) this may not
29886 + * match the core but allows the software to determine
29889 + uint8_t op_state;
29892 + * Set to 1 if the HCD needs to be restarted on a session request
29893 + * interrupt. This is required if no connector ID status change has
29894 + * occurred since the HCD was last disconnected.
29896 + uint8_t restart_hcd_on_session_req;
29898 + /** HCD callbacks */
29899 + /** A-Device is a_host */
29900 +#define A_HOST (1)
29901 + /** A-Device is a_suspend */
29902 +#define A_SUSPEND (2)
29903 + /** A-Device is a_peripherial */
29904 +#define A_PERIPHERAL (3)
29905 + /** B-Device is operating as a Peripheral. */
29906 +#define B_PERIPHERAL (4)
29907 + /** B-Device is operating as a Host. */
29908 +#define B_HOST (5)
29910 + /** HCD callbacks */
29911 + struct dwc_otg_cil_callbacks *hcd_cb;
29912 + /** PCD callbacks */
29913 + struct dwc_otg_cil_callbacks *pcd_cb;
29915 + /** Device mode Periodic Tx FIFO Mask */
29916 + uint32_t p_tx_msk;
29917 + /** Device mode Periodic Tx FIFO Mask */
29920 + /** Workqueue object used for handling several interrupts */
29921 + dwc_workq_t *wq_otg;
29923 + /** Timer object used for handling "Wakeup Detected" Interrupt */
29924 + dwc_timer_t *wkp_timer;
29925 + /** This arrays used for debug purposes for DEV OUT NAK enhancement */
29926 + uint32_t start_doeptsiz_val[MAX_EPS_CHANNELS];
29927 + ep_xfer_info_t ep_xfer_info[MAX_EPS_CHANNELS];
29928 + dwc_timer_t *ep_xfer_timer[MAX_EPS_CHANNELS];
29930 + uint32_t start_hcchar_val[MAX_EPS_CHANNELS];
29932 + hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS];
29933 + dwc_timer_t *hc_xfer_timer[MAX_EPS_CHANNELS];
29935 + uint32_t hfnum_7_samples;
29936 + uint64_t hfnum_7_frrem_accum;
29937 + uint32_t hfnum_0_samples;
29938 + uint64_t hfnum_0_frrem_accum;
29939 + uint32_t hfnum_other_samples;
29940 + uint64_t hfnum_other_frrem_accum;
29943 +#ifdef DWC_UTE_CFI
29944 + uint16_t pwron_rxfsiz;
29945 + uint16_t pwron_gnptxfsiz;
29946 + uint16_t pwron_txfsiz[15];
29948 + uint16_t init_rxfsiz;
29949 + uint16_t init_gnptxfsiz;
29950 + uint16_t init_txfsiz[15];
29953 + /** Lx state of device */
29954 + dwc_otg_lx_state_e lx_state;
29956 + /** Saved Core Global registers */
29957 + struct dwc_otg_global_regs_backup *gr_backup;
29958 + /** Saved Host registers */
29959 + struct dwc_otg_host_regs_backup *hr_backup;
29960 + /** Saved Device registers */
29961 + struct dwc_otg_dev_regs_backup *dr_backup;
29963 + /** Power Down Enable */
29964 + uint32_t power_down;
29966 + /** ADP support Enable */
29967 + uint32_t adp_enable;
29969 + /** ADP structure object */
29970 + dwc_otg_adp_t adp;
29972 + /** hibernation/suspend flag */
29973 + int hibernation_suspend;
29975 + /** Device mode extended hibernation flag */
29978 + /** OTG revision supported */
29979 + uint32_t otg_ver;
29981 + /** OTG status flag used for HNP polling */
29984 + /** Pointer to either hcd->lock or pcd->lock */
29985 + dwc_spinlock_t *lock;
29987 + /** Start predict NextEP based on Learning Queue if equal 1,
29988 + * also used as counter of disabled NP IN EP's */
29989 + uint8_t start_predict;
29991 + /** NextEp sequence, including EP0: nextep_seq[] = EP if non-periodic and
29992 + * active, 0xff otherwise */
29993 + uint8_t nextep_seq[MAX_EPS_CHANNELS];
29995 + /** Index of fisrt EP in nextep_seq array which should be re-enabled **/
29996 + uint8_t first_in_nextep_seq;
29998 + /** Frame number while entering to ISR - needed for ISOCs **/
29999 + uint32_t frame_num;
30005 + * This function is called when transfer is timed out.
30007 +extern void hc_xfer_timeout(void *ptr);
30011 + * This function is called when transfer is timed out on endpoint.
30013 +extern void ep_xfer_timeout(void *ptr);
30016 + * The following functions are functions for works
30017 + * using during handling some interrupts
30019 +extern void w_conn_id_status_change(void *p);
30021 +extern void w_wakeup_detected(void *p);
30023 +/** Saves global register values into system memory. */
30024 +extern int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if);
30025 +/** Saves device register values into system memory. */
30026 +extern int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if);
30027 +/** Saves host register values into system memory. */
30028 +extern int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if);
30029 +/** Restore global register values. */
30030 +extern int dwc_otg_restore_global_regs(dwc_otg_core_if_t * core_if);
30031 +/** Restore host register values. */
30032 +extern int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset);
30033 +/** Restore device register values. */
30034 +extern int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if,
30036 +extern int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if);
30037 +extern int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode,
30040 +extern int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if,
30041 + int restore_mode, int reset);
30042 +extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
30043 + int rem_wakeup, int reset);
30046 + * The following functions support initialization of the CIL driver component
30047 + * and the DWC_otg controller.
30049 +extern void dwc_otg_core_host_init(dwc_otg_core_if_t * _core_if);
30050 +extern void dwc_otg_core_dev_init(dwc_otg_core_if_t * _core_if);
30052 +/** @name Device CIL Functions
30053 + * The following functions support managing the DWC_otg controller in device
30057 +extern void dwc_otg_wakeup(dwc_otg_core_if_t * _core_if);
30058 +extern void dwc_otg_read_setup_packet(dwc_otg_core_if_t * _core_if,
30059 + uint32_t * _dest);
30060 +extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * _core_if);
30061 +extern void dwc_otg_ep0_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
30062 +extern void dwc_otg_ep_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
30063 +extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
30064 +extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * _core_if,
30066 +extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * _core_if,
30068 +extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * _core_if,
30070 +extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * _core_if,
30072 +extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t * _core_if,
30073 + dwc_ep_t * _ep, int _dma);
30074 +extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
30075 +extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * _core_if,
30077 +extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * _core_if);
30079 +#ifdef DWC_EN_ISOC
30080 +extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
30082 +extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
30084 +#endif /* DWC_EN_ISOC */
30087 +/** @name Host CIL Functions
30088 + * The following functions support managing the DWC_otg controller in host
30092 +extern void dwc_otg_hc_init(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
30093 +extern void dwc_otg_hc_halt(dwc_otg_core_if_t * _core_if,
30094 + dwc_hc_t * _hc, dwc_otg_halt_status_e _halt_status);
30095 +extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
30096 +extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * _core_if,
30098 +extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * _core_if,
30100 +extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
30101 +extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t * _core_if,
30103 +extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * _core_if);
30104 +extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * _core_if);
30106 +extern void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if,
30109 +extern uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if);
30111 +/* Macro used to clear one channel interrupt */
30112 +#define clear_hc_int(_hc_regs_, _intr_) \
30114 + hcint_data_t hcint_clear = {.d32 = 0}; \
30115 + hcint_clear.b._intr_ = 1; \
30116 + DWC_WRITE_REG32(&(_hc_regs_)->hcint, hcint_clear.d32); \
30120 + * Macro used to disable one channel interrupt. Channel interrupts are
30121 + * disabled when the channel is halted or released by the interrupt handler.
30122 + * There is no need to handle further interrupts of that type until the
30123 + * channel is re-assigned. In fact, subsequent handling may cause crashes
30124 + * because the channel structures are cleaned up when the channel is released.
30126 +#define disable_hc_int(_hc_regs_, _intr_) \
30128 + hcintmsk_data_t hcintmsk = {.d32 = 0}; \
30129 + hcintmsk.b._intr_ = 1; \
30130 + DWC_MODIFY_REG32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \
30134 + * This function Reads HPRT0 in preparation to modify. It keeps the
30135 + * WC bits 0 so that if they are read as 1, they won't clear when you
30138 +static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t * _core_if)
30140 + hprt0_data_t hprt0;
30141 + hprt0.d32 = DWC_READ_REG32(_core_if->host_if->hprt0);
30142 + hprt0.b.prtena = 0;
30143 + hprt0.b.prtconndet = 0;
30144 + hprt0.b.prtenchng = 0;
30145 + hprt0.b.prtovrcurrchng = 0;
30146 + return hprt0.d32;
30151 +/** @name Common CIL Functions
30152 + * The following functions support managing the DWC_otg controller in either
30153 + * device or host mode.
30157 +extern void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
30158 + uint8_t * dest, uint16_t bytes);
30160 +extern void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * _core_if, const int _num);
30161 +extern void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * _core_if);
30162 +extern void dwc_otg_core_reset(dwc_otg_core_if_t * _core_if);
30165 + * This function returns the Core Interrupt register.
30167 +static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t * core_if)
30169 + return (DWC_READ_REG32(&core_if->core_global_regs->gintsts) &
30170 + DWC_READ_REG32(&core_if->core_global_regs->gintmsk));
30174 + * This function returns the OTG Interrupt register.
30176 +static inline uint32_t dwc_otg_read_otg_intr(dwc_otg_core_if_t * core_if)
30178 + return (DWC_READ_REG32(&core_if->core_global_regs->gotgint));
30182 + * This function reads the Device All Endpoints Interrupt register and
30183 + * returns the IN endpoint interrupt bits.
30185 +static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *
30191 + if (core_if->multiproc_int_enable) {
30192 + v = DWC_READ_REG32(&core_if->dev_if->
30193 + dev_global_regs->deachint) &
30194 + DWC_READ_REG32(&core_if->
30195 + dev_if->dev_global_regs->deachintmsk);
30197 + v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) &
30198 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
30200 + return (v & 0xffff);
30204 + * This function reads the Device All Endpoints Interrupt register and
30205 + * returns the OUT endpoint interrupt bits.
30207 +static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *
30212 + if (core_if->multiproc_int_enable) {
30213 + v = DWC_READ_REG32(&core_if->dev_if->
30214 + dev_global_regs->deachint) &
30215 + DWC_READ_REG32(&core_if->
30216 + dev_if->dev_global_regs->deachintmsk);
30218 + v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) &
30219 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
30222 + return ((v & 0xffff0000) >> 16);
30226 + * This function returns the Device IN EP Interrupt register
30228 +static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t * core_if,
30231 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
30232 + uint32_t v, msk, emp;
30234 + if (core_if->multiproc_int_enable) {
30236 + DWC_READ_REG32(&dev_if->
30237 + dev_global_regs->diepeachintmsk[ep->num]);
30239 + DWC_READ_REG32(&dev_if->
30240 + dev_global_regs->dtknqr4_fifoemptymsk);
30241 + msk |= ((emp >> ep->num) & 0x1) << 7;
30242 + v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
30244 + msk = DWC_READ_REG32(&dev_if->dev_global_regs->diepmsk);
30246 + DWC_READ_REG32(&dev_if->
30247 + dev_global_regs->dtknqr4_fifoemptymsk);
30248 + msk |= ((emp >> ep->num) & 0x1) << 7;
30249 + v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
30256 + * This function returns the Device OUT EP Interrupt register
30258 +static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *
30259 + _core_if, dwc_ep_t * _ep)
30261 + dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
30263 + doepmsk_data_t msk = {.d32 = 0 };
30265 + if (_core_if->multiproc_int_enable) {
30267 + DWC_READ_REG32(&dev_if->
30268 + dev_global_regs->doepeachintmsk[_ep->num]);
30269 + if (_core_if->pti_enh_enable) {
30270 + msk.b.pktdrpsts = 1;
30272 + v = DWC_READ_REG32(&dev_if->
30273 + out_ep_regs[_ep->num]->doepint) & msk.d32;
30275 + msk.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->doepmsk);
30276 + if (_core_if->pti_enh_enable) {
30277 + msk.b.pktdrpsts = 1;
30279 + v = DWC_READ_REG32(&dev_if->
30280 + out_ep_regs[_ep->num]->doepint) & msk.d32;
30286 + * This function returns the Host All Channel Interrupt register
30288 +static inline uint32_t dwc_otg_read_host_all_channels_intr(dwc_otg_core_if_t *
30291 + return (DWC_READ_REG32(&_core_if->host_if->host_global_regs->haint));
30294 +static inline uint32_t dwc_otg_read_host_channel_intr(dwc_otg_core_if_t *
30295 + _core_if, dwc_hc_t * _hc)
30297 + return (DWC_READ_REG32
30298 + (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint));
30302 + * This function returns the mode of the operation, host or device.
30304 + * @return 0 - Device Mode, 1 - Host Mode
30306 +static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t * _core_if)
30308 + return (DWC_READ_REG32(&_core_if->core_global_regs->gintsts) & 0x1);
30314 + * DWC_otg CIL callback structure. This structure allows the HCD and
30315 + * PCD to register functions used for starting and stopping the PCD
30316 + * and HCD for role change on for a DRD.
30318 +typedef struct dwc_otg_cil_callbacks {
30319 + /** Start function for role change */
30320 + int (*start) (void *_p);
30321 + /** Stop Function for role change */
30322 + int (*stop) (void *_p);
30323 + /** Disconnect Function for role change */
30324 + int (*disconnect) (void *_p);
30325 + /** Resume/Remote wakeup Function */
30326 + int (*resume_wakeup) (void *_p);
30327 + /** Suspend function */
30328 + int (*suspend) (void *_p);
30329 + /** Session Start (SRP) */
30330 + int (*session_start) (void *_p);
30331 +#ifdef CONFIG_USB_DWC_OTG_LPM
30332 + /** Sleep (switch to L0 state) */
30333 + int (*sleep) (void *_p);
30335 + /** Pointer passed to start() and stop() */
30337 +} dwc_otg_cil_callbacks_t;
30339 +extern void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * _core_if,
30340 + dwc_otg_cil_callbacks_t * _cb,
30342 +extern void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * _core_if,
30343 + dwc_otg_cil_callbacks_t * _cb,
30346 +void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if);
30348 +//////////////////////////////////////////////////////////////////////
30349 +/** Start the HCD. Helper function for using the HCD callbacks.
30351 + * @param core_if Programming view of DWC_otg controller.
30353 +static inline void cil_hcd_start(dwc_otg_core_if_t * core_if)
30355 + if (core_if->hcd_cb && core_if->hcd_cb->start) {
30356 + core_if->hcd_cb->start(core_if->hcd_cb->p);
30360 +/** Stop the HCD. Helper function for using the HCD callbacks.
30362 + * @param core_if Programming view of DWC_otg controller.
30364 +static inline void cil_hcd_stop(dwc_otg_core_if_t * core_if)
30366 + if (core_if->hcd_cb && core_if->hcd_cb->stop) {
30367 + core_if->hcd_cb->stop(core_if->hcd_cb->p);
30371 +/** Disconnect the HCD. Helper function for using the HCD callbacks.
30373 + * @param core_if Programming view of DWC_otg controller.
30375 +static inline void cil_hcd_disconnect(dwc_otg_core_if_t * core_if)
30377 + if (core_if->hcd_cb && core_if->hcd_cb->disconnect) {
30378 + core_if->hcd_cb->disconnect(core_if->hcd_cb->p);
30382 +/** Inform the HCD the a New Session has begun. Helper function for
30383 + * using the HCD callbacks.
30385 + * @param core_if Programming view of DWC_otg controller.
30387 +static inline void cil_hcd_session_start(dwc_otg_core_if_t * core_if)
30389 + if (core_if->hcd_cb && core_if->hcd_cb->session_start) {
30390 + core_if->hcd_cb->session_start(core_if->hcd_cb->p);
30394 +#ifdef CONFIG_USB_DWC_OTG_LPM
30396 + * Inform the HCD about LPM sleep.
30397 + * Helper function for using the HCD callbacks.
30399 + * @param core_if Programming view of DWC_otg controller.
30401 +static inline void cil_hcd_sleep(dwc_otg_core_if_t * core_if)
30403 + if (core_if->hcd_cb && core_if->hcd_cb->sleep) {
30404 + core_if->hcd_cb->sleep(core_if->hcd_cb->p);
30409 +/** Resume the HCD. Helper function for using the HCD callbacks.
30411 + * @param core_if Programming view of DWC_otg controller.
30413 +static inline void cil_hcd_resume(dwc_otg_core_if_t * core_if)
30415 + if (core_if->hcd_cb && core_if->hcd_cb->resume_wakeup) {
30416 + core_if->hcd_cb->resume_wakeup(core_if->hcd_cb->p);
30420 +/** Start the PCD. Helper function for using the PCD callbacks.
30422 + * @param core_if Programming view of DWC_otg controller.
30424 +static inline void cil_pcd_start(dwc_otg_core_if_t * core_if)
30426 + if (core_if->pcd_cb && core_if->pcd_cb->start) {
30427 + core_if->pcd_cb->start(core_if->pcd_cb->p);
30431 +/** Stop the PCD. Helper function for using the PCD callbacks.
30433 + * @param core_if Programming view of DWC_otg controller.
30435 +static inline void cil_pcd_stop(dwc_otg_core_if_t * core_if)
30437 + if (core_if->pcd_cb && core_if->pcd_cb->stop) {
30438 + core_if->pcd_cb->stop(core_if->pcd_cb->p);
30442 +/** Suspend the PCD. Helper function for using the PCD callbacks.
30444 + * @param core_if Programming view of DWC_otg controller.
30446 +static inline void cil_pcd_suspend(dwc_otg_core_if_t * core_if)
30448 + if (core_if->pcd_cb && core_if->pcd_cb->suspend) {
30449 + core_if->pcd_cb->suspend(core_if->pcd_cb->p);
30453 +/** Resume the PCD. Helper function for using the PCD callbacks.
30455 + * @param core_if Programming view of DWC_otg controller.
30457 +static inline void cil_pcd_resume(dwc_otg_core_if_t * core_if)
30459 + if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
30460 + core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
30464 +//////////////////////////////////////////////////////////////////////
30468 +++ b/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c
30470 +/* ==========================================================================
30471 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $
30472 + * $Revision: #32 $
30473 + * $Date: 2012/08/10 $
30474 + * $Change: 2047372 $
30476 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
30477 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
30478 + * otherwise expressly agreed to in writing between Synopsys and you.
30480 + * The Software IS NOT an item of Licensed Software or Licensed Product under
30481 + * any End User Software License Agreement or Agreement for Licensed Product
30482 + * with Synopsys or any supplement thereto. You are permitted to use and
30483 + * redistribute this Software in source and binary forms, with or without
30484 + * modification, provided that redistributions of source code must retain this
30485 + * notice. You may not view, use, disclose, copy or distribute this file or
30486 + * any information contained herein except pursuant to this license grant from
30487 + * Synopsys. If you do not agree with this notice, including the disclaimer
30488 + * below, then you are not authorized to use the Software.
30490 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
30491 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30492 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30493 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
30494 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30495 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30496 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
30497 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30498 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30499 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
30501 + * ========================================================================== */
30505 + * The Core Interface Layer provides basic services for accessing and
30506 + * managing the DWC_otg hardware. These services are used by both the
30507 + * Host Controller Driver and the Peripheral Controller Driver.
30509 + * This file contains the Common Interrupt handlers.
30511 +#include "dwc_os.h"
30512 +#include "dwc_otg_regs.h"
30513 +#include "dwc_otg_cil.h"
30514 +#include "dwc_otg_driver.h"
30515 +#include "dwc_otg_pcd.h"
30516 +#include "dwc_otg_hcd.h"
30519 +inline const char *op_state_str(dwc_otg_core_if_t * core_if)
30521 + return (core_if->op_state == A_HOST ? "a_host" :
30522 + (core_if->op_state == A_SUSPEND ? "a_suspend" :
30523 + (core_if->op_state == A_PERIPHERAL ? "a_peripheral" :
30524 + (core_if->op_state == B_PERIPHERAL ? "b_peripheral" :
30525 + (core_if->op_state == B_HOST ? "b_host" : "unknown")))));
30529 +/** This function will log a debug message
30531 + * @param core_if Programming view of DWC_otg controller.
30533 +int32_t dwc_otg_handle_mode_mismatch_intr(dwc_otg_core_if_t * core_if)
30535 + gintsts_data_t gintsts;
30536 + DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n",
30537 + dwc_otg_mode(core_if) ? "Host" : "Device");
30539 + /* Clear interrupt */
30541 + gintsts.b.modemismatch = 1;
30542 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
30547 + * This function handles the OTG Interrupts. It reads the OTG
30548 + * Interrupt Register (GOTGINT) to determine what interrupt has
30551 + * @param core_if Programming view of DWC_otg controller.
30553 +int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t * core_if)
30555 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
30556 + gotgint_data_t gotgint;
30557 + gotgctl_data_t gotgctl;
30558 + gintmsk_data_t gintmsk;
30559 + gpwrdn_data_t gpwrdn;
30561 + gotgint.d32 = DWC_READ_REG32(&global_regs->gotgint);
30562 + gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
30563 + DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32,
30564 + op_state_str(core_if));
30566 + if (gotgint.b.sesenddet) {
30567 + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
30568 + "Session End Detected++ (%s)\n",
30569 + op_state_str(core_if));
30570 + gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
30572 + if (core_if->op_state == B_HOST) {
30573 + cil_pcd_start(core_if);
30574 + core_if->op_state = B_PERIPHERAL;
30576 + /* If not B_HOST and Device HNP still set. HNP
30577 + * Did not succeed!*/
30578 + if (gotgctl.b.devhnpen) {
30579 + DWC_DEBUGPL(DBG_ANY, "Session End Detected\n");
30580 + __DWC_ERROR("Device Not Connected/Responding!\n");
30583 + /* If Session End Detected the B-Cable has
30584 + * been disconnected. */
30585 + /* Reset PCD and Gadget driver to a
30586 + * clean state. */
30587 + core_if->lx_state = DWC_OTG_L0;
30588 + DWC_SPINUNLOCK(core_if->lock);
30589 + cil_pcd_stop(core_if);
30590 + DWC_SPINLOCK(core_if->lock);
30592 + if (core_if->adp_enable) {
30593 + if (core_if->power_down == 2) {
30595 + gpwrdn.b.pwrdnswtch = 1;
30596 + DWC_MODIFY_REG32(&core_if->
30597 + core_global_regs->
30598 + gpwrdn, gpwrdn.d32, 0);
30602 + gpwrdn.b.pmuintsel = 1;
30603 + gpwrdn.b.pmuactv = 1;
30604 + DWC_MODIFY_REG32(&core_if->core_global_regs->
30605 + gpwrdn, 0, gpwrdn.d32);
30607 + dwc_otg_adp_sense_start(core_if);
30612 + gotgctl.b.devhnpen = 1;
30613 + DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
30615 + if (gotgint.b.sesreqsucstschng) {
30616 + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
30617 + "Session Reqeust Success Status Change++\n");
30618 + gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
30619 + if (gotgctl.b.sesreqscs) {
30621 + if ((core_if->core_params->phy_type ==
30622 + DWC_PHY_TYPE_PARAM_FS) && (core_if->core_params->i2c_enable)) {
30623 + core_if->srp_success = 1;
30625 + DWC_SPINUNLOCK(core_if->lock);
30626 + cil_pcd_resume(core_if);
30627 + DWC_SPINLOCK(core_if->lock);
30628 + /* Clear Session Request */
30630 + gotgctl.b.sesreq = 1;
30631 + DWC_MODIFY_REG32(&global_regs->gotgctl,
30636 + if (gotgint.b.hstnegsucstschng) {
30637 + /* Print statements during the HNP interrupt handling
30638 + * can cause it to fail.*/
30639 + gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
30640 + /* WA for 3.00a- HW is not setting cur_mode, even sometimes
30641 + * this does not help*/
30642 + if (core_if->snpsid >= OTG_CORE_REV_3_00a)
30644 + if (gotgctl.b.hstnegscs) {
30645 + if (dwc_otg_is_host_mode(core_if)) {
30646 + core_if->op_state = B_HOST;
30648 + * Need to disable SOF interrupt immediately.
30649 + * When switching from device to host, the PCD
30650 + * interrupt handler won't handle the
30651 + * interrupt if host mode is already set. The
30652 + * HCD interrupt handler won't get called if
30653 + * the HCD state is HALT. This means that the
30654 + * interrupt does not get handled and Linux
30655 + * complains loudly.
30658 + gintmsk.b.sofintr = 1;
30659 + DWC_MODIFY_REG32(&global_regs->gintmsk,
30661 + /* Call callback function with spin lock released */
30662 + DWC_SPINUNLOCK(core_if->lock);
30663 + cil_pcd_stop(core_if);
30665 + * Initialize the Core for Host mode.
30667 + cil_hcd_start(core_if);
30668 + DWC_SPINLOCK(core_if->lock);
30669 + core_if->op_state = B_HOST;
30673 + gotgctl.b.hnpreq = 1;
30674 + gotgctl.b.devhnpen = 1;
30675 + DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
30676 + DWC_DEBUGPL(DBG_ANY, "HNP Failed\n");
30677 + __DWC_ERROR("Device Not Connected/Responding\n");
30680 + if (gotgint.b.hstnegdet) {
30681 + /* The disconnect interrupt is set at the same time as
30682 + * Host Negotiation Detected. During the mode
30683 + * switch all interrupts are cleared so the disconnect
30684 + * interrupt handler will not get executed.
30686 + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
30687 + "Host Negotiation Detected++ (%s)\n",
30688 + (dwc_otg_is_host_mode(core_if) ? "Host" :
30690 + if (dwc_otg_is_device_mode(core_if)) {
30691 + DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n",
30692 + core_if->op_state);
30693 + DWC_SPINUNLOCK(core_if->lock);
30694 + cil_hcd_disconnect(core_if);
30695 + cil_pcd_start(core_if);
30696 + DWC_SPINLOCK(core_if->lock);
30697 + core_if->op_state = A_PERIPHERAL;
30700 + * Need to disable SOF interrupt immediately. When
30701 + * switching from device to host, the PCD interrupt
30702 + * handler won't handle the interrupt if host mode is
30703 + * already set. The HCD interrupt handler won't get
30704 + * called if the HCD state is HALT. This means that
30705 + * the interrupt does not get handled and Linux
30706 + * complains loudly.
30709 + gintmsk.b.sofintr = 1;
30710 + DWC_MODIFY_REG32(&global_regs->gintmsk, gintmsk.d32, 0);
30711 + DWC_SPINUNLOCK(core_if->lock);
30712 + cil_pcd_stop(core_if);
30713 + cil_hcd_start(core_if);
30714 + DWC_SPINLOCK(core_if->lock);
30715 + core_if->op_state = A_HOST;
30718 + if (gotgint.b.adevtoutchng) {
30719 + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
30720 + "A-Device Timeout Change++\n");
30722 + if (gotgint.b.debdone) {
30723 + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " "Debounce Done++\n");
30726 + /* Clear GOTGINT */
30727 + DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, gotgint.d32);
30732 +void w_conn_id_status_change(void *p)
30734 + dwc_otg_core_if_t *core_if = p;
30735 + uint32_t count = 0;
30736 + gotgctl_data_t gotgctl = {.d32 = 0 };
30738 + gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
30739 + DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
30740 + DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
30742 + /* B-Device connector (Device Mode) */
30743 + if (gotgctl.b.conidsts) {
30744 + /* Wait for switch to device mode. */
30745 + while (!dwc_otg_is_device_mode(core_if)) {
30746 + DWC_PRINTF("Waiting for Peripheral Mode, Mode=%s\n",
30747 + (dwc_otg_is_host_mode(core_if) ? "Host" :
30750 + if (++count > 10000)
30753 + DWC_ASSERT(++count < 10000,
30754 + "Connection id status change timed out");
30755 + core_if->op_state = B_PERIPHERAL;
30756 + dwc_otg_core_init(core_if);
30757 + dwc_otg_enable_global_interrupts(core_if);
30758 + cil_pcd_start(core_if);
30760 + /* A-Device connector (Host Mode) */
30761 + while (!dwc_otg_is_host_mode(core_if)) {
30762 + DWC_PRINTF("Waiting for Host Mode, Mode=%s\n",
30763 + (dwc_otg_is_host_mode(core_if) ? "Host" :
30766 + if (++count > 10000)
30769 + DWC_ASSERT(++count < 10000,
30770 + "Connection id status change timed out");
30771 + core_if->op_state = A_HOST;
30773 + * Initialize the Core for Host mode.
30775 + dwc_otg_core_init(core_if);
30776 + dwc_otg_enable_global_interrupts(core_if);
30777 + cil_hcd_start(core_if);
30782 + * This function handles the Connector ID Status Change Interrupt. It
30783 + * reads the OTG Interrupt Register (GOTCTL) to determine whether this
30784 + * is a Device to Host Mode transition or a Host Mode to Device
30787 + * This only occurs when the cable is connected/removed from the PHY
30790 + * @param core_if Programming view of DWC_otg controller.
30792 +int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t * core_if)
30796 + * Need to disable SOF interrupt immediately. If switching from device
30797 + * to host, the PCD interrupt handler won't handle the interrupt if
30798 + * host mode is already set. The HCD interrupt handler won't get
30799 + * called if the HCD state is HALT. This means that the interrupt does
30800 + * not get handled and Linux complains loudly.
30802 + gintmsk_data_t gintmsk = {.d32 = 0 };
30803 + gintsts_data_t gintsts = {.d32 = 0 };
30805 + gintmsk.b.sofintr = 1;
30806 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
30808 + DWC_DEBUGPL(DBG_CIL,
30809 + " ++Connector ID Status Change Interrupt++ (%s)\n",
30810 + (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"));
30812 + DWC_SPINUNLOCK(core_if->lock);
30815 + * Need to schedule a work, as there are possible DELAY function calls
30816 + * Release lock before scheduling workq as it holds spinlock during scheduling
30819 + DWC_WORKQ_SCHEDULE(core_if->wq_otg, w_conn_id_status_change,
30820 + core_if, "connection id status change");
30821 + DWC_SPINLOCK(core_if->lock);
30823 + /* Set flag and clear interrupt */
30824 + gintsts.b.conidstschng = 1;
30825 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
30831 + * This interrupt indicates that a device is initiating the Session
30832 + * Request Protocol to request the host to turn on bus power so a new
30833 + * session can begin. The handler responds by turning on bus power. If
30834 + * the DWC_otg controller is in low power mode, the handler brings the
30835 + * controller out of low power mode before turning on bus power.
30837 + * @param core_if Programming view of DWC_otg controller.
30839 +int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t * core_if)
30841 + gintsts_data_t gintsts;
30843 +#ifndef DWC_HOST_ONLY
30844 + DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
30846 + if (dwc_otg_is_device_mode(core_if)) {
30847 + DWC_PRINTF("SRP: Device mode\n");
30849 + hprt0_data_t hprt0;
30850 + DWC_PRINTF("SRP: Host mode\n");
30852 + /* Turn on the port power bit. */
30853 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
30854 + hprt0.b.prtpwr = 1;
30855 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
30857 + /* Start the Connection timer. So a message can be displayed
30858 + * if connect does not occur within 10 seconds. */
30859 + cil_hcd_session_start(core_if);
30863 + /* Clear interrupt */
30865 + gintsts.b.sessreqintr = 1;
30866 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
30871 +void w_wakeup_detected(void *p)
30873 + dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) p;
30875 + * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
30876 + * so that OPT tests pass with all PHYs).
30878 + hprt0_data_t hprt0 = {.d32 = 0 };
30880 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
30881 + /* Restart the Phy Clock */
30882 + pcgcctl.b.stoppclk = 1;
30883 + DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
30886 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
30887 + DWC_DEBUGPL(DBG_ANY, "Resume: HPRT0=%0x\n", hprt0.d32);
30888 +// dwc_mdelay(70);
30889 + hprt0.b.prtres = 0; /* Resume */
30890 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
30891 + DWC_DEBUGPL(DBG_ANY, "Clear Resume: HPRT0=%0x\n",
30892 + DWC_READ_REG32(core_if->host_if->hprt0));
30894 + cil_hcd_resume(core_if);
30896 + /** Change to L0 state*/
30897 + core_if->lx_state = DWC_OTG_L0;
30901 + * This interrupt indicates that the DWC_otg controller has detected a
30902 + * resume or remote wakeup sequence. If the DWC_otg controller is in
30903 + * low power mode, the handler must brings the controller out of low
30904 + * power mode. The controller automatically begins resume
30905 + * signaling. The handler schedules a time to stop resume signaling.
30907 +int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t * core_if)
30909 + gintsts_data_t gintsts;
30911 + DWC_DEBUGPL(DBG_ANY,
30912 + "++Resume and Remote Wakeup Detected Interrupt++\n");
30914 + DWC_PRINTF("%s lxstate = %d\n", __func__, core_if->lx_state);
30916 + if (dwc_otg_is_device_mode(core_if)) {
30917 + dctl_data_t dctl = {.d32 = 0 };
30918 + DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
30919 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->
30921 + if (core_if->lx_state == DWC_OTG_L2) {
30922 +#ifdef PARTIAL_POWER_DOWN
30923 + if (core_if->hwcfg4.b.power_optimiz) {
30924 + pcgcctl_data_t power = {.d32 = 0 };
30926 + power.d32 = DWC_READ_REG32(core_if->pcgcctl);
30927 + DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n",
30930 + power.b.stoppclk = 0;
30931 + DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
30933 + power.b.pwrclmp = 0;
30934 + DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
30936 + power.b.rstpdwnmodule = 0;
30937 + DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
30940 + /* Clear the Remote Wakeup Signaling */
30941 + dctl.b.rmtwkupsig = 1;
30942 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
30943 + dctl, dctl.d32, 0);
30945 + DWC_SPINUNLOCK(core_if->lock);
30946 + if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
30947 + core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
30949 + DWC_SPINLOCK(core_if->lock);
30951 + glpmcfg_data_t lpmcfg;
30953 + DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
30954 + lpmcfg.b.hird_thres &= (~(1 << 4));
30955 + DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg,
30958 + /** Change to L0 state*/
30959 + core_if->lx_state = DWC_OTG_L0;
30961 + if (core_if->lx_state != DWC_OTG_L1) {
30962 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
30964 + /* Restart the Phy Clock */
30965 + pcgcctl.b.stoppclk = 1;
30966 + DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
30967 + DWC_TIMER_SCHEDULE(core_if->wkp_timer, 71);
30969 + /** Change to L0 state*/
30970 + core_if->lx_state = DWC_OTG_L0;
30974 + /* Clear interrupt */
30976 + gintsts.b.wkupintr = 1;
30977 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
30983 + * This interrupt indicates that the Wakeup Logic has detected a
30984 + * Device disconnect.
30986 +static int32_t dwc_otg_handle_pwrdn_disconnect_intr(dwc_otg_core_if_t *core_if)
30988 + gpwrdn_data_t gpwrdn = { .d32 = 0 };
30989 + gpwrdn_data_t gpwrdn_temp = { .d32 = 0 };
30990 + gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
30992 + DWC_PRINTF("%s called\n", __FUNCTION__);
30994 + if (!core_if->hibernation_suspend) {
30995 + DWC_PRINTF("Already exited from Hibernation\n");
30999 + /* Switch on the voltage to the core */
31000 + gpwrdn.b.pwrdnswtch = 1;
31001 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31004 + /* Reset the core */
31006 + gpwrdn.b.pwrdnrstn = 1;
31007 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31010 + /* Disable power clamps*/
31012 + gpwrdn.b.pwrdnclmp = 1;
31013 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31015 + /* Remove reset the core signal */
31017 + gpwrdn.b.pwrdnrstn = 1;
31018 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
31021 + /* Disable PMU interrupt */
31023 + gpwrdn.b.pmuintsel = 1;
31024 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31026 + core_if->hibernation_suspend = 0;
31028 + /* Disable PMU */
31030 + gpwrdn.b.pmuactv = 1;
31031 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31034 + if (gpwrdn_temp.b.idsts) {
31035 + core_if->op_state = B_PERIPHERAL;
31036 + dwc_otg_core_init(core_if);
31037 + dwc_otg_enable_global_interrupts(core_if);
31038 + cil_pcd_start(core_if);
31040 + core_if->op_state = A_HOST;
31041 + dwc_otg_core_init(core_if);
31042 + dwc_otg_enable_global_interrupts(core_if);
31043 + cil_hcd_start(core_if);
31050 + * This interrupt indicates that the Wakeup Logic has detected a
31051 + * remote wakeup sequence.
31053 +static int32_t dwc_otg_handle_pwrdn_wakeup_detected_intr(dwc_otg_core_if_t * core_if)
31055 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
31056 + DWC_DEBUGPL(DBG_ANY,
31057 + "++Powerdown Remote Wakeup Detected Interrupt++\n");
31059 + if (!core_if->hibernation_suspend) {
31060 + DWC_PRINTF("Already exited from Hibernation\n");
31064 + gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
31065 + if (gpwrdn.b.idsts) { // Device Mode
31066 + if ((core_if->power_down == 2)
31067 + && (core_if->hibernation_suspend == 1)) {
31068 + dwc_otg_device_hibernation_restore(core_if, 0, 0);
31071 + if ((core_if->power_down == 2)
31072 + && (core_if->hibernation_suspend == 1)) {
31073 + dwc_otg_host_hibernation_restore(core_if, 1, 0);
31079 +static int32_t dwc_otg_handle_pwrdn_idsts_change(dwc_otg_device_t *otg_dev)
31081 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
31082 + gpwrdn_data_t gpwrdn_temp = {.d32 = 0 };
31083 + dwc_otg_core_if_t *core_if = otg_dev->core_if;
31085 + DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
31086 + gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
31087 + if (core_if->power_down == 2) {
31088 + if (!core_if->hibernation_suspend) {
31089 + DWC_PRINTF("Already exited from Hibernation\n");
31092 + DWC_DEBUGPL(DBG_ANY, "Exit from hibernation on ID sts change\n");
31093 + /* Switch on the voltage to the core */
31094 + gpwrdn.b.pwrdnswtch = 1;
31095 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31098 + /* Reset the core */
31100 + gpwrdn.b.pwrdnrstn = 1;
31101 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31104 + /* Disable power clamps */
31106 + gpwrdn.b.pwrdnclmp = 1;
31107 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31109 + /* Remove reset the core signal */
31111 + gpwrdn.b.pwrdnrstn = 1;
31112 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
31115 + /* Disable PMU interrupt */
31117 + gpwrdn.b.pmuintsel = 1;
31118 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31120 + /*Indicates that we are exiting from hibernation */
31121 + core_if->hibernation_suspend = 0;
31123 + /* Disable PMU */
31125 + gpwrdn.b.pmuactv = 1;
31126 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31129 + gpwrdn.d32 = core_if->gr_backup->gpwrdn_local;
31130 + if (gpwrdn.b.dis_vbus == 1) {
31132 + gpwrdn.b.dis_vbus = 1;
31133 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31136 + if (gpwrdn_temp.b.idsts) {
31137 + core_if->op_state = B_PERIPHERAL;
31138 + dwc_otg_core_init(core_if);
31139 + dwc_otg_enable_global_interrupts(core_if);
31140 + cil_pcd_start(core_if);
31142 + core_if->op_state = A_HOST;
31143 + dwc_otg_core_init(core_if);
31144 + dwc_otg_enable_global_interrupts(core_if);
31145 + cil_hcd_start(core_if);
31149 + if (core_if->adp_enable) {
31150 + uint8_t is_host = 0;
31151 + DWC_SPINUNLOCK(core_if->lock);
31152 + /* Change the core_if's lock to hcd/pcd lock depend on mode? */
31153 +#ifndef DWC_HOST_ONLY
31154 + if (gpwrdn_temp.b.idsts)
31155 + core_if->lock = otg_dev->pcd->lock;
31157 +#ifndef DWC_DEVICE_ONLY
31158 + if (!gpwrdn_temp.b.idsts) {
31159 + core_if->lock = otg_dev->hcd->lock;
31163 + DWC_PRINTF("RESTART ADP\n");
31164 + if (core_if->adp.probe_enabled)
31165 + dwc_otg_adp_probe_stop(core_if);
31166 + if (core_if->adp.sense_enabled)
31167 + dwc_otg_adp_sense_stop(core_if);
31168 + if (core_if->adp.sense_timer_started)
31169 + DWC_TIMER_CANCEL(core_if->adp.sense_timer);
31170 + if (core_if->adp.vbuson_timer_started)
31171 + DWC_TIMER_CANCEL(core_if->adp.vbuson_timer);
31172 + core_if->adp.probe_timer_values[0] = -1;
31173 + core_if->adp.probe_timer_values[1] = -1;
31174 + core_if->adp.sense_timer_started = 0;
31175 + core_if->adp.vbuson_timer_started = 0;
31176 + core_if->adp.probe_counter = 0;
31177 + core_if->adp.gpwrdn = 0;
31179 + /* Disable PMU and restart ADP */
31180 + gpwrdn_temp.d32 = 0;
31181 + gpwrdn_temp.b.pmuactv = 1;
31182 + gpwrdn_temp.b.pmuintsel = 1;
31183 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31184 + DWC_PRINTF("Check point 1\n");
31186 + dwc_otg_adp_start(core_if, is_host);
31187 + DWC_SPINLOCK(core_if->lock);
31194 +static int32_t dwc_otg_handle_pwrdn_session_change(dwc_otg_core_if_t * core_if)
31196 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
31197 + int32_t otg_cap_param = core_if->core_params->otg_cap;
31198 + DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
31200 + gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
31201 + if (core_if->power_down == 2) {
31202 + if (!core_if->hibernation_suspend) {
31203 + DWC_PRINTF("Already exited from Hibernation\n");
31207 + if ((otg_cap_param != DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE ||
31208 + otg_cap_param != DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) &&
31209 + gpwrdn.b.bsessvld == 0) {
31210 + /* Save gpwrdn register for further usage if stschng interrupt */
31211 + core_if->gr_backup->gpwrdn_local =
31212 + DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
31213 + /*Exit from ISR and wait for stschng interrupt with bsessvld = 1 */
31217 + /* Switch on the voltage to the core */
31219 + gpwrdn.b.pwrdnswtch = 1;
31220 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31223 + /* Reset the core */
31225 + gpwrdn.b.pwrdnrstn = 1;
31226 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31229 + /* Disable power clamps */
31231 + gpwrdn.b.pwrdnclmp = 1;
31232 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31234 + /* Remove reset the core signal */
31236 + gpwrdn.b.pwrdnrstn = 1;
31237 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
31240 + /* Disable PMU interrupt */
31242 + gpwrdn.b.pmuintsel = 1;
31243 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31246 + /*Indicates that we are exiting from hibernation */
31247 + core_if->hibernation_suspend = 0;
31249 + /* Disable PMU */
31251 + gpwrdn.b.pmuactv = 1;
31252 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31255 + core_if->op_state = B_PERIPHERAL;
31256 + dwc_otg_core_init(core_if);
31257 + dwc_otg_enable_global_interrupts(core_if);
31258 + cil_pcd_start(core_if);
31260 + if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE ||
31261 + otg_cap_param == DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) {
31263 + * Initiate SRP after initial ADP probe.
31265 + dwc_otg_initiate_srp(core_if);
31272 + * This interrupt indicates that the Wakeup Logic has detected a
31273 + * status change either on IDDIG or BSessVld.
31275 +static uint32_t dwc_otg_handle_pwrdn_stschng_intr(dwc_otg_device_t *otg_dev)
31278 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
31279 + gpwrdn_data_t gpwrdn_temp = {.d32 = 0 };
31280 + dwc_otg_core_if_t *core_if = otg_dev->core_if;
31282 + DWC_PRINTF("%s called\n", __FUNCTION__);
31284 + if (core_if->power_down == 2) {
31285 + if (core_if->hibernation_suspend <= 0) {
31286 + DWC_PRINTF("Already exited from Hibernation\n");
31289 + gpwrdn_temp.d32 = core_if->gr_backup->gpwrdn_local;
31292 + gpwrdn_temp.d32 = core_if->adp.gpwrdn;
31295 + gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
31297 + if (gpwrdn.b.idsts ^ gpwrdn_temp.b.idsts) {
31298 + retval = dwc_otg_handle_pwrdn_idsts_change(otg_dev);
31299 + } else if (gpwrdn.b.bsessvld ^ gpwrdn_temp.b.bsessvld) {
31300 + retval = dwc_otg_handle_pwrdn_session_change(core_if);
31307 + * This interrupt indicates that the Wakeup Logic has detected a
31310 +static int32_t dwc_otg_handle_pwrdn_srp_intr(dwc_otg_core_if_t * core_if)
31312 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
31314 + DWC_PRINTF("%s called\n", __FUNCTION__);
31316 + if (!core_if->hibernation_suspend) {
31317 + DWC_PRINTF("Already exited from Hibernation\n");
31320 +#ifdef DWC_DEV_SRPCAP
31321 + if (core_if->pwron_timer_started) {
31322 + core_if->pwron_timer_started = 0;
31323 + DWC_TIMER_CANCEL(core_if->pwron_timer);
31327 + /* Switch on the voltage to the core */
31328 + gpwrdn.b.pwrdnswtch = 1;
31329 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31332 + /* Reset the core */
31334 + gpwrdn.b.pwrdnrstn = 1;
31335 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31338 + /* Disable power clamps */
31340 + gpwrdn.b.pwrdnclmp = 1;
31341 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31343 + /* Remove reset the core signal */
31345 + gpwrdn.b.pwrdnrstn = 1;
31346 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
31349 + /* Disable PMU interrupt */
31351 + gpwrdn.b.pmuintsel = 1;
31352 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31354 + /* Indicates that we are exiting from hibernation */
31355 + core_if->hibernation_suspend = 0;
31357 + /* Disable PMU */
31359 + gpwrdn.b.pmuactv = 1;
31360 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31363 + /* Programm Disable VBUS to 0 */
31365 + gpwrdn.b.dis_vbus = 1;
31366 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31368 + /*Initialize the core as Host */
31369 + core_if->op_state = A_HOST;
31370 + dwc_otg_core_init(core_if);
31371 + dwc_otg_enable_global_interrupts(core_if);
31372 + cil_hcd_start(core_if);
31377 +/** This interrupt indicates that restore command after Hibernation
31378 + * was completed by the core. */
31379 +int32_t dwc_otg_handle_restore_done_intr(dwc_otg_core_if_t * core_if)
31381 + pcgcctl_data_t pcgcctl;
31382 + DWC_DEBUGPL(DBG_ANY, "++Restore Done Interrupt++\n");
31384 + //TODO De-assert restore signal. 8.a
31385 + pcgcctl.d32 = DWC_READ_REG32(core_if->pcgcctl);
31386 + if (pcgcctl.b.restoremode == 1) {
31387 + gintmsk_data_t gintmsk = {.d32 = 0 };
31389 + * If restore mode is Remote Wakeup,
31390 + * unmask Remote Wakeup interrupt.
31392 + gintmsk.b.wkupintr = 1;
31393 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
31401 + * This interrupt indicates that a device has been disconnected from
31404 +int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t * core_if)
31406 + gintsts_data_t gintsts;
31408 + DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n",
31409 + (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"),
31410 + op_state_str(core_if));
31412 +/** @todo Consolidate this if statement. */
31413 +#ifndef DWC_HOST_ONLY
31414 + if (core_if->op_state == B_HOST) {
31415 + /* If in device mode Disconnect and stop the HCD, then
31416 + * start the PCD. */
31417 + DWC_SPINUNLOCK(core_if->lock);
31418 + cil_hcd_disconnect(core_if);
31419 + cil_pcd_start(core_if);
31420 + DWC_SPINLOCK(core_if->lock);
31421 + core_if->op_state = B_PERIPHERAL;
31422 + } else if (dwc_otg_is_device_mode(core_if)) {
31423 + gotgctl_data_t gotgctl = {.d32 = 0 };
31425 + DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
31426 + if (gotgctl.b.hstsethnpen == 1) {
31427 + /* Do nothing, if HNP in process the OTG
31428 + * interrupt "Host Negotiation Detected"
31429 + * interrupt will do the mode switch.
31431 + } else if (gotgctl.b.devhnpen == 0) {
31432 + /* If in device mode Disconnect and stop the HCD, then
31433 + * start the PCD. */
31434 + DWC_SPINUNLOCK(core_if->lock);
31435 + cil_hcd_disconnect(core_if);
31436 + cil_pcd_start(core_if);
31437 + DWC_SPINLOCK(core_if->lock);
31438 + core_if->op_state = B_PERIPHERAL;
31440 + DWC_DEBUGPL(DBG_ANY, "!a_peripheral && !devhnpen\n");
31443 + if (core_if->op_state == A_HOST) {
31444 + /* A-Cable still connected but device disconnected. */
31445 + DWC_SPINUNLOCK(core_if->lock);
31446 + cil_hcd_disconnect(core_if);
31447 + DWC_SPINLOCK(core_if->lock);
31448 + if (core_if->adp_enable) {
31449 + gpwrdn_data_t gpwrdn = { .d32 = 0 };
31450 + cil_hcd_stop(core_if);
31451 + /* Enable Power Down Logic */
31452 + gpwrdn.b.pmuintsel = 1;
31453 + gpwrdn.b.pmuactv = 1;
31454 + DWC_MODIFY_REG32(&core_if->core_global_regs->
31455 + gpwrdn, 0, gpwrdn.d32);
31456 + dwc_otg_adp_probe_start(core_if);
31458 + /* Power off the core */
31459 + if (core_if->power_down == 2) {
31461 + gpwrdn.b.pwrdnswtch = 1;
31463 + (&core_if->core_global_regs->gpwrdn,
31470 + /* Change to L3(OFF) state */
31471 + core_if->lx_state = DWC_OTG_L3;
31474 + gintsts.b.disconnect = 1;
31475 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
31480 + * This interrupt indicates that SUSPEND state has been detected on
31483 + * For HNP the USB Suspend interrupt signals the change from
31484 + * "a_peripheral" to "a_host".
31486 + * When power management is enabled the core will be put in low power
31489 +int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t * core_if)
31491 + dsts_data_t dsts;
31492 + gintsts_data_t gintsts;
31493 + dcfg_data_t dcfg;
31495 + DWC_DEBUGPL(DBG_ANY, "USB SUSPEND\n");
31497 + if (dwc_otg_is_device_mode(core_if)) {
31498 + /* Check the Device status register to determine if the Suspend
31499 + * state is active. */
31501 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
31502 + DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32);
31503 + DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d "
31504 + "HWCFG4.power Optimize=%d\n",
31505 + dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz);
31507 +#ifdef PARTIAL_POWER_DOWN
31508 +/** @todo Add a module parameter for power management. */
31510 + if (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) {
31511 + pcgcctl_data_t power = {.d32 = 0 };
31512 + DWC_DEBUGPL(DBG_CIL, "suspend\n");
31514 + power.b.pwrclmp = 1;
31515 + DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
31517 + power.b.rstpdwnmodule = 1;
31518 + DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32);
31520 + power.b.stoppclk = 1;
31521 + DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32);
31524 + DWC_DEBUGPL(DBG_ANY, "disconnect?\n");
31527 + /* PCD callback for suspend. Release the lock inside of callback function */
31528 + cil_pcd_suspend(core_if);
31529 + if (core_if->power_down == 2)
31531 + dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
31532 + DWC_DEBUGPL(DBG_ANY,"lx_state = %08x\n",core_if->lx_state);
31533 + DWC_DEBUGPL(DBG_ANY," device address = %08d\n",dcfg.b.devaddr);
31535 + if (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) {
31536 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
31537 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
31538 + gusbcfg_data_t gusbcfg = {.d32 = 0 };
31540 + /* Change to L2(suspend) state */
31541 + core_if->lx_state = DWC_OTG_L2;
31543 + /* Clear interrupt in gintsts */
31545 + gintsts.b.usbsuspend = 1;
31546 + DWC_WRITE_REG32(&core_if->core_global_regs->
31547 + gintsts, gintsts.d32);
31548 + DWC_PRINTF("Start of hibernation completed\n");
31549 + dwc_otg_save_global_regs(core_if);
31550 + dwc_otg_save_dev_regs(core_if);
31553 + DWC_READ_REG32(&core_if->core_global_regs->
31555 + if (gusbcfg.b.ulpi_utmi_sel == 1) {
31556 + /* ULPI interface */
31557 + /* Suspend the Phy Clock */
31559 + pcgcctl.b.stoppclk = 1;
31560 + DWC_MODIFY_REG32(core_if->pcgcctl, 0,
31563 + gpwrdn.b.pmuactv = 1;
31564 + DWC_MODIFY_REG32(&core_if->
31565 + core_global_regs->
31566 + gpwrdn, 0, gpwrdn.d32);
31568 + /* UTMI+ Interface */
31569 + gpwrdn.b.pmuactv = 1;
31570 + DWC_MODIFY_REG32(&core_if->
31571 + core_global_regs->
31572 + gpwrdn, 0, gpwrdn.d32);
31574 + pcgcctl.b.stoppclk = 1;
31575 + DWC_MODIFY_REG32(core_if->pcgcctl, 0,
31580 + /* Set flag to indicate that we are in hibernation */
31581 + core_if->hibernation_suspend = 1;
31582 + /* Enable interrupts from wake up logic */
31584 + gpwrdn.b.pmuintsel = 1;
31585 + DWC_MODIFY_REG32(&core_if->core_global_regs->
31586 + gpwrdn, 0, gpwrdn.d32);
31589 + /* Unmask device mode interrupts in GPWRDN */
31591 + gpwrdn.b.rst_det_msk = 1;
31592 + gpwrdn.b.lnstchng_msk = 1;
31593 + gpwrdn.b.sts_chngint_msk = 1;
31594 + DWC_MODIFY_REG32(&core_if->core_global_regs->
31595 + gpwrdn, 0, gpwrdn.d32);
31598 + /* Enable Power Down Clamp */
31600 + gpwrdn.b.pwrdnclmp = 1;
31601 + DWC_MODIFY_REG32(&core_if->core_global_regs->
31602 + gpwrdn, 0, gpwrdn.d32);
31605 + /* Switch off VDD */
31607 + gpwrdn.b.pwrdnswtch = 1;
31608 + DWC_MODIFY_REG32(&core_if->core_global_regs->
31609 + gpwrdn, 0, gpwrdn.d32);
31611 + /* Save gpwrdn register for further usage if stschng interrupt */
31612 + core_if->gr_backup->gpwrdn_local =
31613 + DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
31614 + DWC_PRINTF("Hibernation completed\n");
31618 + } else if (core_if->power_down == 3) {
31619 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
31620 + dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
31621 + DWC_DEBUGPL(DBG_ANY, "lx_state = %08x\n",core_if->lx_state);
31622 + DWC_DEBUGPL(DBG_ANY, " device address = %08d\n",dcfg.b.devaddr);
31624 + if (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) {
31625 + DWC_DEBUGPL(DBG_ANY, "Start entering to extended hibernation\n");
31626 + core_if->xhib = 1;
31628 + /* Clear interrupt in gintsts */
31630 + gintsts.b.usbsuspend = 1;
31631 + DWC_WRITE_REG32(&core_if->core_global_regs->
31632 + gintsts, gintsts.d32);
31634 + dwc_otg_save_global_regs(core_if);
31635 + dwc_otg_save_dev_regs(core_if);
31637 + /* Wait for 10 PHY clocks */
31640 + /* Program GPIO register while entering to xHib */
31641 + DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, 0x1);
31643 + pcgcctl.b.enbl_extnd_hiber = 1;
31644 + DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
31645 + DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
31648 + pcgcctl.b.extnd_hiber_pwrclmp = 1;
31649 + DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
31652 + pcgcctl.b.extnd_hiber_switch = 1;
31653 + core_if->gr_backup->xhib_gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
31654 + core_if->gr_backup->xhib_pcgcctl = DWC_READ_REG32(core_if->pcgcctl) | pcgcctl.d32;
31655 + DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
31657 + DWC_DEBUGPL(DBG_ANY, "Finished entering to extended hibernation\n");
31663 + if (core_if->op_state == A_PERIPHERAL) {
31664 + DWC_DEBUGPL(DBG_ANY, "a_peripheral->a_host\n");
31665 + /* Clear the a_peripheral flag, back to a_host. */
31666 + DWC_SPINUNLOCK(core_if->lock);
31667 + cil_pcd_stop(core_if);
31668 + cil_hcd_start(core_if);
31669 + DWC_SPINLOCK(core_if->lock);
31670 + core_if->op_state = A_HOST;
31674 + /* Change to L2(suspend) state */
31675 + core_if->lx_state = DWC_OTG_L2;
31677 + /* Clear interrupt */
31679 + gintsts.b.usbsuspend = 1;
31680 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
31685 +static int32_t dwc_otg_handle_xhib_exit_intr(dwc_otg_core_if_t * core_if)
31687 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
31688 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
31689 + gahbcfg_data_t gahbcfg = {.d32 = 0 };
31693 + /* Program GPIO register while entering to xHib */
31694 + DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, 0x0);
31696 + pcgcctl.d32 = core_if->gr_backup->xhib_pcgcctl;
31697 + pcgcctl.b.extnd_hiber_pwrclmp = 0;
31698 + DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
31701 + gpwrdn.d32 = core_if->gr_backup->xhib_gpwrdn;
31702 + gpwrdn.b.restore = 1;
31703 + DWC_WRITE_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32);
31706 + restore_lpm_i2c_regs(core_if);
31708 + pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);
31709 + pcgcctl.b.max_xcvrselect = 1;
31710 + pcgcctl.b.ess_reg_restored = 0;
31711 + pcgcctl.b.extnd_hiber_switch = 0;
31712 + pcgcctl.b.extnd_hiber_pwrclmp = 0;
31713 + pcgcctl.b.enbl_extnd_hiber = 1;
31714 + DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
31716 + gahbcfg.d32 = core_if->gr_backup->gahbcfg_local;
31717 + gahbcfg.b.glblintrmsk = 1;
31718 + DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32);
31720 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
31721 + DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0x1 << 16);
31723 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
31724 + core_if->gr_backup->gusbcfg_local);
31725 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
31726 + core_if->dr_backup->dcfg);
31729 + pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);
31730 + pcgcctl.b.max_xcvrselect = 1;
31731 + pcgcctl.d32 |= 0x608;
31732 + DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
31736 + pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);
31737 + pcgcctl.b.max_xcvrselect = 1;
31738 + pcgcctl.b.ess_reg_restored = 1;
31739 + pcgcctl.b.enbl_extnd_hiber = 1;
31740 + pcgcctl.b.rstpdwnmodule = 1;
31741 + pcgcctl.b.restoremode = 1;
31742 + DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
31744 + DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
31749 +#ifdef CONFIG_USB_DWC_OTG_LPM
31751 + * This function hadles LPM transaction received interrupt.
31753 +static int32_t dwc_otg_handle_lpm_intr(dwc_otg_core_if_t * core_if)
31755 + glpmcfg_data_t lpmcfg;
31756 + gintsts_data_t gintsts;
31758 + if (!core_if->core_params->lpm_enable) {
31759 + DWC_PRINTF("Unexpected LPM interrupt\n");
31762 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
31763 + DWC_PRINTF("LPM config register = 0x%08x\n", lpmcfg.d32);
31765 + if (dwc_otg_is_host_mode(core_if)) {
31766 + cil_hcd_sleep(core_if);
31768 + lpmcfg.b.hird_thres |= (1 << 4);
31769 + DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg,
31773 + /* Examine prt_sleep_sts after TL1TokenTetry period max (10 us) */
31775 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
31776 + if (lpmcfg.b.prt_sleep_sts) {
31777 + /* Save the current state */
31778 + core_if->lx_state = DWC_OTG_L1;
31781 + /* Clear interrupt */
31783 + gintsts.b.lpmtranrcvd = 1;
31784 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
31787 +#endif /* CONFIG_USB_DWC_OTG_LPM */
31790 + * This function returns the Core Interrupt register.
31792 +static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if, gintmsk_data_t *reenable_gintmsk, dwc_otg_hcd_t *hcd)
31794 + gahbcfg_data_t gahbcfg = {.d32 = 0 };
31795 + gintsts_data_t gintsts;
31796 + gintmsk_data_t gintmsk;
31797 + gintmsk_data_t gintmsk_common = {.d32 = 0 };
31798 + gintmsk_common.b.wkupintr = 1;
31799 + gintmsk_common.b.sessreqintr = 1;
31800 + gintmsk_common.b.conidstschng = 1;
31801 + gintmsk_common.b.otgintr = 1;
31802 + gintmsk_common.b.modemismatch = 1;
31803 + gintmsk_common.b.disconnect = 1;
31804 + gintmsk_common.b.usbsuspend = 1;
31805 +#ifdef CONFIG_USB_DWC_OTG_LPM
31806 + gintmsk_common.b.lpmtranrcvd = 1;
31808 + gintmsk_common.b.restoredone = 1;
31809 + if(dwc_otg_is_device_mode(core_if))
31811 + /** @todo: The port interrupt occurs while in device
31812 + * mode. Added code to CIL to clear the interrupt for now!
31814 + gintmsk_common.b.portintr = 1;
31817 + local_fiq_disable();
31818 + fiq_fsm_spin_lock(&hcd->fiq_state->lock);
31819 + gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
31820 + gintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
31821 + /* Pull in the interrupts that the FIQ has masked */
31822 + gintmsk.d32 |= ~(hcd->fiq_state->gintmsk_saved.d32);
31823 + gintmsk.d32 |= gintmsk_common.d32;
31824 + /* for the upstairs function to reenable - have to read it here in case FIQ triggers again */
31825 + reenable_gintmsk->d32 = gintmsk.d32;
31826 + fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
31827 + local_fiq_enable();
31829 + gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
31830 + gintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
31833 + gahbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg);
31836 + /* if any common interrupts set */
31837 + if (gintsts.d32 & gintmsk_common.d32) {
31838 + DWC_DEBUGPL(DBG_ANY, "common_intr: gintsts=%08x gintmsk=%08x\n",
31839 + gintsts.d32, gintmsk.d32);
31842 + if (!fiq_enable){
31843 + if (gahbcfg.b.glblintrmsk)
31844 + return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
31848 + /* Our IRQ kicker is no longer the USB hardware, it's the MPHI interface.
31849 + * Can't trust the global interrupt mask bit in this case.
31851 + return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
31856 +/* MACRO for clearing interupt bits in GPWRDN register */
31857 +#define CLEAR_GPWRDN_INTR(__core_if,__intr) \
31859 + gpwrdn_data_t gpwrdn = {.d32=0}; \
31860 + gpwrdn.b.__intr = 1; \
31861 + DWC_MODIFY_REG32(&__core_if->core_global_regs->gpwrdn, \
31862 + 0, gpwrdn.d32); \
31866 + * Common interrupt handler.
31868 + * The common interrupts are those that occur in both Host and Device mode.
31869 + * This handler handles the following interrupts:
31870 + * - Mode Mismatch Interrupt
31871 + * - Disconnect Interrupt
31872 + * - OTG Interrupt
31873 + * - Connector ID Status Change Interrupt
31874 + * - Session Request Interrupt.
31875 + * - Resume / Remote Wakeup Detected Interrupt.
31876 + * - LPM Transaction Received Interrupt
31877 + * - ADP Transaction Received Interrupt
31880 +int32_t dwc_otg_handle_common_intr(void *dev)
31883 + gintsts_data_t gintsts;
31884 + gintmsk_data_t gintmsk_reenable = { .d32 = 0 };
31885 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
31886 + dwc_otg_device_t *otg_dev = dev;
31887 + dwc_otg_core_if_t *core_if = otg_dev->core_if;
31888 + gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
31889 + if (dwc_otg_is_device_mode(core_if))
31890 + core_if->frame_num = dwc_otg_get_frame_number(core_if);
31892 + if (core_if->lock)
31893 + DWC_SPINLOCK(core_if->lock);
31895 + if (core_if->power_down == 3 && core_if->xhib == 1) {
31896 + DWC_DEBUGPL(DBG_ANY, "Exiting from xHIB state\n");
31897 + retval |= dwc_otg_handle_xhib_exit_intr(core_if);
31898 + core_if->xhib = 2;
31899 + if (core_if->lock)
31900 + DWC_SPINUNLOCK(core_if->lock);
31905 + if (core_if->hibernation_suspend <= 0) {
31906 + /* read_common will have to poke the FIQ's saved mask. We must then clear this mask at the end
31907 + * of this handler - god only knows why it's done like this
31909 + gintsts.d32 = dwc_otg_read_common_intr(core_if, &gintmsk_reenable, otg_dev->hcd);
31911 + if (gintsts.b.modemismatch) {
31912 + retval |= dwc_otg_handle_mode_mismatch_intr(core_if);
31914 + if (gintsts.b.otgintr) {
31915 + retval |= dwc_otg_handle_otg_intr(core_if);
31917 + if (gintsts.b.conidstschng) {
31919 + dwc_otg_handle_conn_id_status_change_intr(core_if);
31921 + if (gintsts.b.disconnect) {
31922 + retval |= dwc_otg_handle_disconnect_intr(core_if);
31924 + if (gintsts.b.sessreqintr) {
31925 + retval |= dwc_otg_handle_session_req_intr(core_if);
31927 + if (gintsts.b.wkupintr) {
31928 + retval |= dwc_otg_handle_wakeup_detected_intr(core_if);
31930 + if (gintsts.b.usbsuspend) {
31931 + retval |= dwc_otg_handle_usb_suspend_intr(core_if);
31933 +#ifdef CONFIG_USB_DWC_OTG_LPM
31934 + if (gintsts.b.lpmtranrcvd) {
31935 + retval |= dwc_otg_handle_lpm_intr(core_if);
31938 + if (gintsts.b.restoredone) {
31940 + if (core_if->power_down == 2)
31941 + core_if->hibernation_suspend = -1;
31942 + else if (core_if->power_down == 3 && core_if->xhib == 2) {
31943 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
31944 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
31945 + dctl_data_t dctl = {.d32 = 0 };
31947 + DWC_WRITE_REG32(&core_if->core_global_regs->
31948 + gintsts, 0xFFFFFFFF);
31950 + DWC_DEBUGPL(DBG_ANY,
31951 + "RESTORE DONE generated\n");
31953 + gpwrdn.b.restore = 1;
31954 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31957 + pcgcctl.b.rstpdwnmodule = 1;
31958 + DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
31960 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, core_if->gr_backup->gusbcfg_local);
31961 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, core_if->dr_backup->dcfg);
31962 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, core_if->dr_backup->dctl);
31965 + dctl.b.pwronprgdone = 1;
31966 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
31969 + dwc_otg_restore_global_regs(core_if);
31970 + dwc_otg_restore_dev_regs(core_if, 0);
31973 + dctl.b.pwronprgdone = 1;
31974 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
31978 + pcgcctl.b.enbl_extnd_hiber = 1;
31979 + DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
31981 + /* The core will be in ON STATE */
31982 + core_if->lx_state = DWC_OTG_L0;
31983 + core_if->xhib = 0;
31985 + DWC_SPINUNLOCK(core_if->lock);
31986 + if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
31987 + core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
31989 + DWC_SPINLOCK(core_if->lock);
31993 + gintsts.b.restoredone = 1;
31994 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32);
31995 + DWC_PRINTF(" --Restore done interrupt received-- \n");
31998 + if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) {
31999 + /* The port interrupt occurs while in device mode with HPRT0
32000 + * Port Enable/Disable.
32003 + gintsts.b.portintr = 1;
32004 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32);
32006 + gintmsk_reenable.b.portintr = 1;
32009 + /* Did we actually handle anything? if so, unmask the interrupt */
32010 +// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "CILOUT %1d", retval);
32011 +// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "%08x", gintsts.d32);
32012 +// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "%08x", gintmsk_reenable.d32);
32013 + if (retval && fiq_enable) {
32014 + DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_reenable.d32);
32018 + DWC_DEBUGPL(DBG_ANY, "gpwrdn=%08x\n", gpwrdn.d32);
32020 + if (gpwrdn.b.disconn_det && gpwrdn.b.disconn_det_msk) {
32021 + CLEAR_GPWRDN_INTR(core_if, disconn_det);
32022 + if (gpwrdn.b.linestate == 0) {
32023 + dwc_otg_handle_pwrdn_disconnect_intr(core_if);
32025 + DWC_PRINTF("Disconnect detected while linestate is not 0\n");
32030 + if (gpwrdn.b.lnstschng && gpwrdn.b.lnstchng_msk) {
32031 + CLEAR_GPWRDN_INTR(core_if, lnstschng);
32032 + /* remote wakeup from hibernation */
32033 + if (gpwrdn.b.linestate == 2 || gpwrdn.b.linestate == 1) {
32034 + dwc_otg_handle_pwrdn_wakeup_detected_intr(core_if);
32036 + DWC_PRINTF("gpwrdn.linestate = %d\n", gpwrdn.b.linestate);
32040 + if (gpwrdn.b.rst_det && gpwrdn.b.rst_det_msk) {
32041 + CLEAR_GPWRDN_INTR(core_if, rst_det);
32042 + if (gpwrdn.b.linestate == 0) {
32043 + DWC_PRINTF("Reset detected\n");
32044 + retval |= dwc_otg_device_hibernation_restore(core_if, 0, 1);
32047 + if (gpwrdn.b.srp_det && gpwrdn.b.srp_det_msk) {
32048 + CLEAR_GPWRDN_INTR(core_if, srp_det);
32049 + dwc_otg_handle_pwrdn_srp_intr(core_if);
32053 + /* Handle ADP interrupt here */
32054 + if (gpwrdn.b.adp_int) {
32055 + DWC_PRINTF("ADP interrupt\n");
32056 + CLEAR_GPWRDN_INTR(core_if, adp_int);
32057 + dwc_otg_adp_handle_intr(core_if);
32060 + if (gpwrdn.b.sts_chngint && gpwrdn.b.sts_chngint_msk) {
32061 + DWC_PRINTF("STS CHNG interrupt asserted\n");
32062 + CLEAR_GPWRDN_INTR(core_if, sts_chngint);
32063 + dwc_otg_handle_pwrdn_stschng_intr(otg_dev);
32067 + if (core_if->lock)
32068 + DWC_SPINUNLOCK(core_if->lock);
32072 +++ b/drivers/usb/host/dwc_otg/dwc_otg_core_if.h
32074 +/* ==========================================================================
32075 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_core_if.h $
32076 + * $Revision: #13 $
32077 + * $Date: 2012/08/10 $
32078 + * $Change: 2047372 $
32080 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
32081 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
32082 + * otherwise expressly agreed to in writing between Synopsys and you.
32084 + * The Software IS NOT an item of Licensed Software or Licensed Product under
32085 + * any End User Software License Agreement or Agreement for Licensed Product
32086 + * with Synopsys or any supplement thereto. You are permitted to use and
32087 + * redistribute this Software in source and binary forms, with or without
32088 + * modification, provided that redistributions of source code must retain this
32089 + * notice. You may not view, use, disclose, copy or distribute this file or
32090 + * any information contained herein except pursuant to this license grant from
32091 + * Synopsys. If you do not agree with this notice, including the disclaimer
32092 + * below, then you are not authorized to use the Software.
32094 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
32095 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32096 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32097 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
32098 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
32099 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32100 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
32101 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32102 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32103 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32105 + * ========================================================================== */
32106 +#if !defined(__DWC_CORE_IF_H__)
32107 +#define __DWC_CORE_IF_H__
32109 +#include "dwc_os.h"
32112 + * This file defines DWC_OTG Core API
32115 +struct dwc_otg_core_if;
32116 +typedef struct dwc_otg_core_if dwc_otg_core_if_t;
32118 +/** Maximum number of Periodic FIFOs */
32119 +#define MAX_PERIO_FIFOS 15
32120 +/** Maximum number of Periodic FIFOs */
32121 +#define MAX_TX_FIFOS 15
32123 +/** Maximum number of Endpoints/HostChannels */
32124 +#define MAX_EPS_CHANNELS 16
32126 +extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * _reg_base_addr);
32127 +extern void dwc_otg_core_init(dwc_otg_core_if_t * _core_if);
32128 +extern void dwc_otg_cil_remove(dwc_otg_core_if_t * _core_if);
32130 +extern void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * _core_if);
32131 +extern void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * _core_if);
32133 +extern uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if);
32134 +extern uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if);
32136 +extern uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if);
32138 +/** This function should be called on every hardware interrupt. */
32139 +extern int32_t dwc_otg_handle_common_intr(void *otg_dev);
32141 +/** @name OTG Core Parameters */
32145 + * Specifies the OTG capabilities. The driver will automatically
32146 + * detect the value for this parameter if none is specified.
32147 + * 0 - HNP and SRP capable (default)
32148 + * 1 - SRP Only capable
32149 + * 2 - No HNP/SRP capable
32151 +extern int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val);
32152 +extern int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if);
32153 +#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
32154 +#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
32155 +#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
32156 +#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
32158 +extern int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val);
32159 +extern int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if);
32160 +#define dwc_param_opt_default 1
32163 + * Specifies whether to use slave or DMA mode for accessing the data
32164 + * FIFOs. The driver will automatically detect the value for this
32165 + * parameter if none is specified.
32167 + * 1 - DMA (default, if available)
32169 +extern int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if,
32171 +extern int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if);
32172 +#define dwc_param_dma_enable_default 1
32175 + * When DMA mode is enabled specifies whether to use
32176 + * address DMA or DMA Descritor mode for accessing the data
32177 + * FIFOs in device mode. The driver will automatically detect
32178 + * the value for this parameter if none is specified.
32179 + * 0 - address DMA
32180 + * 1 - DMA Descriptor(default, if available)
32182 +extern int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if,
32184 +extern int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if);
32185 +//#define dwc_param_dma_desc_enable_default 1
32186 +#define dwc_param_dma_desc_enable_default 0 // Broadcom BCM2708
32188 +/** The DMA Burst size (applicable only for External DMA
32189 + * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
32191 +extern int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if,
32193 +extern int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if);
32194 +#define dwc_param_dma_burst_size_default 32
32197 + * Specifies the maximum speed of operation in host and device mode.
32198 + * The actual speed depends on the speed of the attached device and
32199 + * the value of phy_type. The actual speed depends on the speed of the
32200 + * attached device.
32201 + * 0 - High Speed (default)
32204 +extern int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val);
32205 +extern int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if);
32206 +#define dwc_param_speed_default 0
32207 +#define DWC_SPEED_PARAM_HIGH 0
32208 +#define DWC_SPEED_PARAM_FULL 1
32210 +/** Specifies whether low power mode is supported when attached
32211 + * to a Full Speed or Low Speed device in host mode.
32212 + * 0 - Don't support low power mode (default)
32213 + * 1 - Support low power mode
32215 +extern int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
32216 + core_if, int32_t val);
32217 +extern int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t
32219 +#define dwc_param_host_support_fs_ls_low_power_default 0
32221 +/** Specifies the PHY clock rate in low power mode when connected to a
32222 + * Low Speed device in host mode. This parameter is applicable only if
32223 + * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
32224 + * then defaults to 6 MHZ otherwise 48 MHZ.
32229 +extern int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
32230 + core_if, int32_t val);
32231 +extern int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
32233 +#define dwc_param_host_ls_low_power_phy_clk_default 0
32234 +#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
32235 +#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
32238 + * 0 - Use cC FIFO size parameters
32239 + * 1 - Allow dynamic FIFO sizing (default)
32241 +extern int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
32243 +extern int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t *
32245 +#define dwc_param_enable_dynamic_fifo_default 1
32247 +/** Total number of 4-byte words in the data FIFO memory. This
32248 + * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
32250 + * 32 to 32768 (default 8192)
32251 + * Note: The total FIFO memory depth in the FPGA configuration is 8192.
32253 +extern int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if,
32255 +extern int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if);
32256 +//#define dwc_param_data_fifo_size_default 8192
32257 +#define dwc_param_data_fifo_size_default 0xFF0 // Broadcom BCM2708
32259 +/** Number of 4-byte words in the Rx FIFO in device mode when dynamic
32260 + * FIFO sizing is enabled.
32261 + * 16 to 32768 (default 1064)
32263 +extern int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if,
32265 +extern int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if);
32266 +#define dwc_param_dev_rx_fifo_size_default 1064
32268 +/** Number of 4-byte words in the non-periodic Tx FIFO in device mode
32269 + * when dynamic FIFO sizing is enabled.
32270 + * 16 to 32768 (default 1024)
32272 +extern int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
32273 + core_if, int32_t val);
32274 +extern int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
32276 +#define dwc_param_dev_nperio_tx_fifo_size_default 1024
32278 +/** Number of 4-byte words in each of the periodic Tx FIFOs in device
32279 + * mode when dynamic FIFO sizing is enabled.
32280 + * 4 to 768 (default 256)
32282 +extern int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
32283 + int32_t val, int fifo_num);
32284 +extern int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t *
32285 + core_if, int fifo_num);
32286 +#define dwc_param_dev_perio_tx_fifo_size_default 256
32288 +/** Number of 4-byte words in the Rx FIFO in host mode when dynamic
32289 + * FIFO sizing is enabled.
32290 + * 16 to 32768 (default 1024)
32292 +extern int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
32294 +extern int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if);
32295 +//#define dwc_param_host_rx_fifo_size_default 1024
32296 +#define dwc_param_host_rx_fifo_size_default 774 // Broadcom BCM2708
32298 +/** Number of 4-byte words in the non-periodic Tx FIFO in host mode
32299 + * when Dynamic FIFO sizing is enabled in the core.
32300 + * 16 to 32768 (default 1024)
32302 +extern int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
32303 + core_if, int32_t val);
32304 +extern int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
32306 +//#define dwc_param_host_nperio_tx_fifo_size_default 1024
32307 +#define dwc_param_host_nperio_tx_fifo_size_default 0x100 // Broadcom BCM2708
32309 +/** Number of 4-byte words in the host periodic Tx FIFO when dynamic
32310 + * FIFO sizing is enabled.
32311 + * 16 to 32768 (default 1024)
32313 +extern int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
32314 + core_if, int32_t val);
32315 +extern int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
32317 +//#define dwc_param_host_perio_tx_fifo_size_default 1024
32318 +#define dwc_param_host_perio_tx_fifo_size_default 0x200 // Broadcom BCM2708
32320 +/** The maximum transfer size supported in bytes.
32321 + * 2047 to 65,535 (default 65,535)
32323 +extern int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
32325 +extern int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if);
32326 +#define dwc_param_max_transfer_size_default 65535
32328 +/** The maximum number of packets in a transfer.
32329 + * 15 to 511 (default 511)
32331 +extern int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if,
32333 +extern int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if);
32334 +#define dwc_param_max_packet_count_default 511
32336 +/** The number of host channel registers to use.
32337 + * 1 to 16 (default 12)
32338 + * Note: The FPGA configuration supports a maximum of 12 host channels.
32340 +extern int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if,
32342 +extern int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if);
32343 +//#define dwc_param_host_channels_default 12
32344 +#define dwc_param_host_channels_default 8 // Broadcom BCM2708
32346 +/** The number of endpoints in addition to EP0 available for device
32347 + * mode operations.
32348 + * 1 to 15 (default 6 IN and OUT)
32349 + * Note: The FPGA configuration supports a maximum of 6 IN and OUT
32350 + * endpoints in addition to EP0.
32352 +extern int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if,
32354 +extern int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if);
32355 +#define dwc_param_dev_endpoints_default 6
32358 + * Specifies the type of PHY interface to use. By default, the driver
32359 + * will automatically detect the phy_type.
32361 + * 0 - Full Speed PHY
32362 + * 1 - UTMI+ (default)
32365 +extern int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val);
32366 +extern int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if);
32367 +#define DWC_PHY_TYPE_PARAM_FS 0
32368 +#define DWC_PHY_TYPE_PARAM_UTMI 1
32369 +#define DWC_PHY_TYPE_PARAM_ULPI 2
32370 +#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
32373 + * Specifies the UTMI+ Data Width. This parameter is
32374 + * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
32375 + * PHY_TYPE, this parameter indicates the data width between
32376 + * the MAC and the ULPI Wrapper.) Also, this parameter is
32377 + * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
32378 + * to "8 and 16 bits", meaning that the core has been
32379 + * configured to work at either data path width.
32381 + * 8 or 16 bits (default 16)
32383 +extern int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if,
32385 +extern int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if);
32386 +//#define dwc_param_phy_utmi_width_default 16
32387 +#define dwc_param_phy_utmi_width_default 8 // Broadcom BCM2708
32390 + * Specifies whether the ULPI operates at double or single
32391 + * data rate. This parameter is only applicable if PHY_TYPE is
32394 + * 0 - single data rate ULPI interface with 8 bit wide data
32396 + * 1 - double data rate ULPI interface with 4 bit wide data
32399 +extern int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if,
32401 +extern int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if);
32402 +#define dwc_param_phy_ulpi_ddr_default 0
32405 + * Specifies whether to use the internal or external supply to
32406 + * drive the vbus with a ULPI phy.
32408 +extern int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
32410 +extern int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if);
32411 +#define DWC_PHY_ULPI_INTERNAL_VBUS 0
32412 +#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
32413 +#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
32416 + * Specifies whether to use the I2Cinterface for full speed PHY. This
32417 + * parameter is only applicable if PHY_TYPE is FS.
32418 + * 0 - No (default)
32421 +extern int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if,
32423 +extern int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if);
32424 +#define dwc_param_i2c_enable_default 0
32426 +extern int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if,
32428 +extern int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if);
32429 +#define dwc_param_ulpi_fs_ls_default 0
32431 +extern int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val);
32432 +extern int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if);
32433 +#define dwc_param_ts_dline_default 0
32436 + * Specifies whether dedicated transmit FIFOs are
32437 + * enabled for non periodic IN endpoints in device mode
32441 +extern int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
32443 +extern int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t *
32445 +#define dwc_param_en_multiple_tx_fifo_default 1
32447 +/** Number of 4-byte words in each of the Tx FIFOs in device
32448 + * mode when dynamic FIFO sizing is enabled.
32449 + * 4 to 768 (default 256)
32451 +extern int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
32452 + int fifo_num, int32_t val);
32453 +extern int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
32455 +#define dwc_param_dev_tx_fifo_size_default 768
32457 +/** Thresholding enable flag-
32458 + * bit 0 - enable non-ISO Tx thresholding
32459 + * bit 1 - enable ISO Tx thresholding
32460 + * bit 2 - enable Rx thresholding
32462 +extern int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val);
32463 +extern int32_t dwc_otg_get_thr_ctl(dwc_otg_core_if_t * core_if, int fifo_num);
32464 +#define dwc_param_thr_ctl_default 0
32466 +/** Thresholding length for Tx
32467 + * FIFOs in 32 bit DWORDs
32469 +extern int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if,
32471 +extern int32_t dwc_otg_get_tx_thr_length(dwc_otg_core_if_t * core_if);
32472 +#define dwc_param_tx_thr_length_default 64
32474 +/** Thresholding length for Rx
32475 + * FIFOs in 32 bit DWORDs
32477 +extern int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if,
32479 +extern int32_t dwc_otg_get_rx_thr_length(dwc_otg_core_if_t * core_if);
32480 +#define dwc_param_rx_thr_length_default 64
32483 + * Specifies whether LPM (Link Power Management) support is enabled
32485 +extern int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if,
32487 +extern int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if);
32488 +#define dwc_param_lpm_enable_default 1
32491 + * Specifies whether PTI enhancement is enabled
32493 +extern int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if,
32495 +extern int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if);
32496 +#define dwc_param_pti_enable_default 0
32499 + * Specifies whether MPI enhancement is enabled
32501 +extern int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if,
32503 +extern int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if);
32504 +#define dwc_param_mpi_enable_default 0
32507 + * Specifies whether ADP capability is enabled
32509 +extern int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if,
32511 +extern int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if);
32512 +#define dwc_param_adp_enable_default 0
32515 + * Specifies whether IC_USB capability is enabled
32518 +extern int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if,
32520 +extern int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if);
32521 +#define dwc_param_ic_usb_cap_default 0
32523 +extern int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if,
32525 +extern int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if);
32526 +#define dwc_param_ahb_thr_ratio_default 0
32528 +extern int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if,
32530 +extern int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if);
32531 +#define dwc_param_power_down_default 0
32533 +extern int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if,
32535 +extern int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if);
32536 +#define dwc_param_reload_ctl_default 0
32538 +extern int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if,
32540 +extern int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if);
32541 +#define dwc_param_dev_out_nak_default 0
32543 +extern int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if,
32545 +extern int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if);
32546 +#define dwc_param_cont_on_bna_default 0
32548 +extern int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if,
32550 +extern int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if);
32551 +#define dwc_param_ahb_single_default 0
32553 +extern int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val);
32554 +extern int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if);
32555 +#define dwc_param_otg_ver_default 0
32559 +/** @name Access to registers and bit-fields */
32562 + * Dump core registers and SPRAM
32564 +extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * _core_if);
32565 +extern void dwc_otg_dump_spram(dwc_otg_core_if_t * _core_if);
32566 +extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t * _core_if);
32567 +extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t * _core_if);
32570 + * Get host negotiation status.
32572 +extern uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if);
32577 +extern uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if);
32580 + * Set hnpreq bit in the GOTGCTL register.
32582 +extern void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val);
32585 + * Get Content of SNPSID register.
32587 +extern uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if);
32590 + * Get current mode.
32591 + * Returns 0 if in device mode, and 1 if in host mode.
32593 +extern uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if);
32596 + * Get value of hnpcapable field in the GUSBCFG register
32598 +extern uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if);
32600 + * Set value of hnpcapable field in the GUSBCFG register
32602 +extern void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
32605 + * Get value of srpcapable field in the GUSBCFG register
32607 +extern uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if);
32609 + * Set value of srpcapable field in the GUSBCFG register
32611 +extern void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
32614 + * Get value of devspeed field in the DCFG register
32616 +extern uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if);
32618 + * Set value of devspeed field in the DCFG register
32620 +extern void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val);
32623 + * Get the value of busconnected field from the HPRT0 register
32625 +extern uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if);
32628 + * Gets the device enumeration Speed.
32630 +extern uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if);
32633 + * Get value of prtpwr field from the HPRT0 register
32635 +extern uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if);
32638 + * Get value of flag indicating core state - hibernated or not
32640 +extern uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if);
32643 + * Set value of prtpwr field from the HPRT0 register
32645 +extern void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val);
32648 + * Get value of prtsusp field from the HPRT0 regsiter
32650 +extern uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if);
32652 + * Set value of prtpwr field from the HPRT0 register
32654 +extern void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val);
32657 + * Get value of ModeChTimEn field from the HCFG regsiter
32659 +extern uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if);
32661 + * Set value of ModeChTimEn field from the HCFG regsiter
32663 +extern void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val);
32666 + * Get value of Fram Interval field from the HFIR regsiter
32668 +extern uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if);
32670 + * Set value of Frame Interval field from the HFIR regsiter
32672 +extern void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val);
32675 + * Set value of prtres field from the HPRT0 register
32678 +extern void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val);
32681 + * Get value of rmtwkupsig bit in DCTL register
32683 +extern uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if);
32686 + * Get value of prt_sleep_sts field from the GLPMCFG register
32688 +extern uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if);
32691 + * Get value of rem_wkup_en field from the GLPMCFG register
32693 +extern uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if);
32696 + * Get value of appl_resp field from the GLPMCFG register
32698 +extern uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if);
32700 + * Set value of appl_resp field from the GLPMCFG register
32702 +extern void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val);
32705 + * Get value of hsic_connect field from the GLPMCFG register
32707 +extern uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if);
32709 + * Set value of hsic_connect field from the GLPMCFG register
32711 +extern void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val);
32714 + * Get value of inv_sel_hsic field from the GLPMCFG register.
32716 +extern uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if);
32718 + * Set value of inv_sel_hsic field from the GLPMFG register.
32720 +extern void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val);
32723 + * Some functions for accessing registers
32727 + * GOTGCTL register
32729 +extern uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if);
32730 +extern void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val);
32733 + * GUSBCFG register
32735 +extern uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if);
32736 +extern void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val);
32739 + * GRXFSIZ register
32741 +extern uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if);
32742 +extern void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
32745 + * GNPTXFSIZ register
32747 +extern uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if);
32748 +extern void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
32750 +extern uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if);
32751 +extern void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val);
32756 +extern uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if);
32757 +extern void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val);
32762 +extern uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if);
32763 +extern void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val);
32768 +extern uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if);
32769 +extern void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val);
32774 +extern uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if);
32778 +#endif /* __DWC_CORE_IF_H__ */
32780 +++ b/drivers/usb/host/dwc_otg/dwc_otg_dbg.h
32782 +/* ==========================================================================
32784 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
32785 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
32786 + * otherwise expressly agreed to in writing between Synopsys and you.
32788 + * The Software IS NOT an item of Licensed Software or Licensed Product under
32789 + * any End User Software License Agreement or Agreement for Licensed Product
32790 + * with Synopsys or any supplement thereto. You are permitted to use and
32791 + * redistribute this Software in source and binary forms, with or without
32792 + * modification, provided that redistributions of source code must retain this
32793 + * notice. You may not view, use, disclose, copy or distribute this file or
32794 + * any information contained herein except pursuant to this license grant from
32795 + * Synopsys. If you do not agree with this notice, including the disclaimer
32796 + * below, then you are not authorized to use the Software.
32798 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
32799 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32800 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32801 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
32802 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
32803 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32804 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
32805 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32806 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32807 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32809 + * ========================================================================== */
32811 +#ifndef __DWC_OTG_DBG_H__
32812 +#define __DWC_OTG_DBG_H__
32815 + * This file defines debug levels.
32816 + * Debugging support vanishes in non-debug builds.
32820 + * The Debug Level bit-mask variable.
32822 +extern uint32_t g_dbg_lvl;
32824 + * Set the Debug Level variable.
32826 +static inline uint32_t SET_DEBUG_LEVEL(const uint32_t new)
32828 + uint32_t old = g_dbg_lvl;
32833 +#define DBG_USER (0x1)
32834 +/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */
32835 +#define DBG_CIL (0x2)
32836 +/** When debug level has the DBG_CILV bit set, display CIL Verbose debug
32838 +#define DBG_CILV (0x20)
32839 +/** When debug level has the DBG_PCD bit set, display PCD (Device) debug
32841 +#define DBG_PCD (0x4)
32842 +/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug
32844 +#define DBG_PCDV (0x40)
32845 +/** When debug level has the DBG_HCD bit set, display Host debug messages */
32846 +#define DBG_HCD (0x8)
32847 +/** When debug level has the DBG_HCDV bit set, display Verbose Host debug
32849 +#define DBG_HCDV (0x80)
32850 +/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host
32852 +#define DBG_HCD_URB (0x800)
32853 +/** When debug level has the DBG_HCDI bit set, display host interrupt
32855 +#define DBG_HCDI (0x1000)
32857 +/** When debug level has any bit set, display debug messages */
32858 +#define DBG_ANY (0xFF)
32860 +/** All debug messages off */
32863 +/** Prefix string for DWC_DEBUG print macros. */
32864 +#define USB_DWC "DWC_otg: "
32867 + * Print a debug message when the Global debug level variable contains
32868 + * the bit defined in <code>lvl</code>.
32870 + * @param[in] lvl - Debug level, use one of the DBG_ constants above.
32871 + * @param[in] x - like printf
32875 + * DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr);
32878 + * results in:<br>
32880 + * usb-DWC_otg: dwc_otg_cil_init(ca867000)
32885 +# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)__DWC_DEBUG(USB_DWC x ); }while(0)
32886 +# define DWC_DEBUGP(x...) DWC_DEBUGPL(DBG_ANY, x )
32888 +# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl)
32892 +# define DWC_DEBUGPL(lvl, x...) do{}while(0)
32893 +# define DWC_DEBUGP(x...)
32895 +# define CHK_DEBUG_LEVEL(level) (0)
32900 +++ b/drivers/usb/host/dwc_otg/dwc_otg_driver.c
32902 +/* ==========================================================================
32903 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
32904 + * $Revision: #92 $
32905 + * $Date: 2012/08/10 $
32906 + * $Change: 2047372 $
32908 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
32909 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
32910 + * otherwise expressly agreed to in writing between Synopsys and you.
32912 + * The Software IS NOT an item of Licensed Software or Licensed Product under
32913 + * any End User Software License Agreement or Agreement for Licensed Product
32914 + * with Synopsys or any supplement thereto. You are permitted to use and
32915 + * redistribute this Software in source and binary forms, with or without
32916 + * modification, provided that redistributions of source code must retain this
32917 + * notice. You may not view, use, disclose, copy or distribute this file or
32918 + * any information contained herein except pursuant to this license grant from
32919 + * Synopsys. If you do not agree with this notice, including the disclaimer
32920 + * below, then you are not authorized to use the Software.
32922 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
32923 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32924 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32925 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
32926 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
32927 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32928 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
32929 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32930 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32931 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32933 + * ========================================================================== */
32936 + * The dwc_otg_driver module provides the initialization and cleanup entry
32937 + * points for the DWC_otg driver. This module will be dynamically installed
32938 + * after Linux is booted using the insmod command. When the module is
32939 + * installed, the dwc_otg_driver_init function is called. When the module is
32940 + * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
32942 + * This module also defines a data structure for the dwc_otg_driver, which is
32943 + * used in conjunction with the standard ARM lm_device structure. These
32944 + * structures allow the OTG driver to comply with the standard Linux driver
32945 + * model in which devices and drivers are registered with a bus driver. This
32946 + * has the benefit that Linux can expose attributes of the driver and device
32947 + * in its special sysfs file system. Users can then read or write files in
32948 + * this file system to perform diagnostics on the driver components or the
32952 +#include "dwc_otg_os_dep.h"
32953 +#include "dwc_os.h"
32954 +#include "dwc_otg_dbg.h"
32955 +#include "dwc_otg_driver.h"
32956 +#include "dwc_otg_attr.h"
32957 +#include "dwc_otg_core_if.h"
32958 +#include "dwc_otg_pcd_if.h"
32959 +#include "dwc_otg_hcd_if.h"
32960 +#include "dwc_otg_fiq_fsm.h"
32962 +#define DWC_DRIVER_VERSION "3.00a 10-AUG-2012"
32963 +#define DWC_DRIVER_DESC "HS OTG USB Controller driver"
32965 +bool microframe_schedule=true;
32967 +static const char dwc_driver_name[] = "dwc_otg";
32970 +extern int pcd_init(
32971 +#ifdef LM_INTERFACE
32972 + struct lm_device *_dev
32973 +#elif defined(PCI_INTERFACE)
32974 + struct pci_dev *_dev
32975 +#elif defined(PLATFORM_INTERFACE)
32976 + struct platform_device *dev
32979 +extern int hcd_init(
32980 +#ifdef LM_INTERFACE
32981 + struct lm_device *_dev
32982 +#elif defined(PCI_INTERFACE)
32983 + struct pci_dev *_dev
32984 +#elif defined(PLATFORM_INTERFACE)
32985 + struct platform_device *dev
32989 +extern int pcd_remove(
32990 +#ifdef LM_INTERFACE
32991 + struct lm_device *_dev
32992 +#elif defined(PCI_INTERFACE)
32993 + struct pci_dev *_dev
32994 +#elif defined(PLATFORM_INTERFACE)
32995 + struct platform_device *_dev
32999 +extern void hcd_remove(
33000 +#ifdef LM_INTERFACE
33001 + struct lm_device *_dev
33002 +#elif defined(PCI_INTERFACE)
33003 + struct pci_dev *_dev
33004 +#elif defined(PLATFORM_INTERFACE)
33005 + struct platform_device *_dev
33009 +extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);
33011 +/*-------------------------------------------------------------------------*/
33012 +/* Encapsulate the module parameter settings */
33014 +struct dwc_otg_driver_module_params {
33017 + int32_t dma_enable;
33018 + int32_t dma_desc_enable;
33019 + int32_t dma_burst_size;
33021 + int32_t host_support_fs_ls_low_power;
33022 + int32_t host_ls_low_power_phy_clk;
33023 + int32_t enable_dynamic_fifo;
33024 + int32_t data_fifo_size;
33025 + int32_t dev_rx_fifo_size;
33026 + int32_t dev_nperio_tx_fifo_size;
33027 + uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
33028 + int32_t host_rx_fifo_size;
33029 + int32_t host_nperio_tx_fifo_size;
33030 + int32_t host_perio_tx_fifo_size;
33031 + int32_t max_transfer_size;
33032 + int32_t max_packet_count;
33033 + int32_t host_channels;
33034 + int32_t dev_endpoints;
33035 + int32_t phy_type;
33036 + int32_t phy_utmi_width;
33037 + int32_t phy_ulpi_ddr;
33038 + int32_t phy_ulpi_ext_vbus;
33039 + int32_t i2c_enable;
33040 + int32_t ulpi_fs_ls;
33041 + int32_t ts_dline;
33042 + int32_t en_multiple_tx_fifo;
33043 + uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
33044 + uint32_t thr_ctl;
33045 + uint32_t tx_thr_length;
33046 + uint32_t rx_thr_length;
33047 + int32_t pti_enable;
33048 + int32_t mpi_enable;
33049 + int32_t lpm_enable;
33050 + int32_t ic_usb_cap;
33051 + int32_t ahb_thr_ratio;
33052 + int32_t power_down;
33053 + int32_t reload_ctl;
33054 + int32_t dev_out_nak;
33055 + int32_t cont_on_bna;
33056 + int32_t ahb_single;
33058 + int32_t adp_enable;
33061 +static struct dwc_otg_driver_module_params dwc_otg_module_params = {
33064 + .dma_enable = -1,
33065 + .dma_desc_enable = -1,
33066 + .dma_burst_size = -1,
33068 + .host_support_fs_ls_low_power = -1,
33069 + .host_ls_low_power_phy_clk = -1,
33070 + .enable_dynamic_fifo = -1,
33071 + .data_fifo_size = -1,
33072 + .dev_rx_fifo_size = -1,
33073 + .dev_nperio_tx_fifo_size = -1,
33074 + .dev_perio_tx_fifo_size = {
33075 + /* dev_perio_tx_fifo_size_1 */
33093 + .host_rx_fifo_size = -1,
33094 + .host_nperio_tx_fifo_size = -1,
33095 + .host_perio_tx_fifo_size = -1,
33096 + .max_transfer_size = -1,
33097 + .max_packet_count = -1,
33098 + .host_channels = -1,
33099 + .dev_endpoints = -1,
33101 + .phy_utmi_width = -1,
33102 + .phy_ulpi_ddr = -1,
33103 + .phy_ulpi_ext_vbus = -1,
33104 + .i2c_enable = -1,
33105 + .ulpi_fs_ls = -1,
33107 + .en_multiple_tx_fifo = -1,
33108 + .dev_tx_fifo_size = {
33109 + /* dev_tx_fifo_size */
33128 + .tx_thr_length = -1,
33129 + .rx_thr_length = -1,
33130 + .pti_enable = -1,
33131 + .mpi_enable = -1,
33133 + .ic_usb_cap = -1,
33134 + .ahb_thr_ratio = -1,
33135 + .power_down = -1,
33136 + .reload_ctl = -1,
33137 + .dev_out_nak = -1,
33138 + .cont_on_bna = -1,
33139 + .ahb_single = -1,
33141 + .adp_enable = -1,
33144 +//Global variable to switch the fiq fix on or off
33145 +bool fiq_enable = 1;
33146 +// Global variable to enable the split transaction fix
33147 +bool fiq_fsm_enable = true;
33148 +//Bulk split-transaction NAK holdoff in microframes
33149 +uint16_t nak_holdoff = 8;
33151 +//Force host mode during CIL re-init
33152 +bool cil_force_host = true;
33154 +unsigned short fiq_fsm_mask = 0x0F;
33156 +unsigned short int_ep_interval_min = 0;
33158 + * This function shows the Driver Version.
33160 +static ssize_t version_show(struct device_driver *dev, char *buf)
33162 + return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
33163 + DWC_DRIVER_VERSION);
33166 +static DRIVER_ATTR_RO(version);
33169 + * Global Debug Level Mask.
33171 +uint32_t g_dbg_lvl = 0; /* OFF */
33174 + * This function shows the driver Debug Level.
33176 +static ssize_t debuglevel_show(struct device_driver *drv, char *buf)
33178 + return sprintf(buf, "0x%0x\n", g_dbg_lvl);
33182 + * This function stores the driver Debug Level.
33184 +static ssize_t debuglevel_store(struct device_driver *drv, const char *buf,
33187 + g_dbg_lvl = simple_strtoul(buf, NULL, 16);
33191 +static DRIVER_ATTR_RW(debuglevel);
33194 + * This function is called during module intialization
33195 + * to pass module parameters to the DWC_OTG CORE.
33197 +static int set_parameters(dwc_otg_core_if_t * core_if)
33202 + if (dwc_otg_module_params.otg_cap != -1) {
33204 + dwc_otg_set_param_otg_cap(core_if,
33205 + dwc_otg_module_params.otg_cap);
33207 + if (dwc_otg_module_params.dma_enable != -1) {
33209 + dwc_otg_set_param_dma_enable(core_if,
33210 + dwc_otg_module_params.
33213 + if (dwc_otg_module_params.dma_desc_enable != -1) {
33215 + dwc_otg_set_param_dma_desc_enable(core_if,
33216 + dwc_otg_module_params.
33217 + dma_desc_enable);
33219 + if (dwc_otg_module_params.opt != -1) {
33221 + dwc_otg_set_param_opt(core_if, dwc_otg_module_params.opt);
33223 + if (dwc_otg_module_params.dma_burst_size != -1) {
33225 + dwc_otg_set_param_dma_burst_size(core_if,
33226 + dwc_otg_module_params.
33229 + if (dwc_otg_module_params.host_support_fs_ls_low_power != -1) {
33231 + dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
33232 + dwc_otg_module_params.
33233 + host_support_fs_ls_low_power);
33235 + if (dwc_otg_module_params.enable_dynamic_fifo != -1) {
33237 + dwc_otg_set_param_enable_dynamic_fifo(core_if,
33238 + dwc_otg_module_params.
33239 + enable_dynamic_fifo);
33241 + if (dwc_otg_module_params.data_fifo_size != -1) {
33243 + dwc_otg_set_param_data_fifo_size(core_if,
33244 + dwc_otg_module_params.
33247 + if (dwc_otg_module_params.dev_rx_fifo_size != -1) {
33249 + dwc_otg_set_param_dev_rx_fifo_size(core_if,
33250 + dwc_otg_module_params.
33251 + dev_rx_fifo_size);
33253 + if (dwc_otg_module_params.dev_nperio_tx_fifo_size != -1) {
33255 + dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
33256 + dwc_otg_module_params.
33257 + dev_nperio_tx_fifo_size);
33259 + if (dwc_otg_module_params.host_rx_fifo_size != -1) {
33261 + dwc_otg_set_param_host_rx_fifo_size(core_if,
33262 + dwc_otg_module_params.host_rx_fifo_size);
33264 + if (dwc_otg_module_params.host_nperio_tx_fifo_size != -1) {
33266 + dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
33267 + dwc_otg_module_params.
33268 + host_nperio_tx_fifo_size);
33270 + if (dwc_otg_module_params.host_perio_tx_fifo_size != -1) {
33272 + dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
33273 + dwc_otg_module_params.
33274 + host_perio_tx_fifo_size);
33276 + if (dwc_otg_module_params.max_transfer_size != -1) {
33278 + dwc_otg_set_param_max_transfer_size(core_if,
33279 + dwc_otg_module_params.
33280 + max_transfer_size);
33282 + if (dwc_otg_module_params.max_packet_count != -1) {
33284 + dwc_otg_set_param_max_packet_count(core_if,
33285 + dwc_otg_module_params.
33286 + max_packet_count);
33288 + if (dwc_otg_module_params.host_channels != -1) {
33290 + dwc_otg_set_param_host_channels(core_if,
33291 + dwc_otg_module_params.
33294 + if (dwc_otg_module_params.dev_endpoints != -1) {
33296 + dwc_otg_set_param_dev_endpoints(core_if,
33297 + dwc_otg_module_params.
33300 + if (dwc_otg_module_params.phy_type != -1) {
33302 + dwc_otg_set_param_phy_type(core_if,
33303 + dwc_otg_module_params.phy_type);
33305 + if (dwc_otg_module_params.speed != -1) {
33307 + dwc_otg_set_param_speed(core_if,
33308 + dwc_otg_module_params.speed);
33310 + if (dwc_otg_module_params.host_ls_low_power_phy_clk != -1) {
33312 + dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
33313 + dwc_otg_module_params.
33314 + host_ls_low_power_phy_clk);
33316 + if (dwc_otg_module_params.phy_ulpi_ddr != -1) {
33318 + dwc_otg_set_param_phy_ulpi_ddr(core_if,
33319 + dwc_otg_module_params.
33322 + if (dwc_otg_module_params.phy_ulpi_ext_vbus != -1) {
33324 + dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
33325 + dwc_otg_module_params.
33326 + phy_ulpi_ext_vbus);
33328 + if (dwc_otg_module_params.phy_utmi_width != -1) {
33330 + dwc_otg_set_param_phy_utmi_width(core_if,
33331 + dwc_otg_module_params.
33334 + if (dwc_otg_module_params.ulpi_fs_ls != -1) {
33336 + dwc_otg_set_param_ulpi_fs_ls(core_if,
33337 + dwc_otg_module_params.ulpi_fs_ls);
33339 + if (dwc_otg_module_params.ts_dline != -1) {
33341 + dwc_otg_set_param_ts_dline(core_if,
33342 + dwc_otg_module_params.ts_dline);
33344 + if (dwc_otg_module_params.i2c_enable != -1) {
33346 + dwc_otg_set_param_i2c_enable(core_if,
33347 + dwc_otg_module_params.
33350 + if (dwc_otg_module_params.en_multiple_tx_fifo != -1) {
33352 + dwc_otg_set_param_en_multiple_tx_fifo(core_if,
33353 + dwc_otg_module_params.
33354 + en_multiple_tx_fifo);
33356 + for (i = 0; i < 15; i++) {
33357 + if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
33359 + dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
33360 + dwc_otg_module_params.
33361 + dev_perio_tx_fifo_size
33366 + for (i = 0; i < 15; i++) {
33367 + if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
33368 + retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
33369 + dwc_otg_module_params.
33374 + if (dwc_otg_module_params.thr_ctl != -1) {
33376 + dwc_otg_set_param_thr_ctl(core_if,
33377 + dwc_otg_module_params.thr_ctl);
33379 + if (dwc_otg_module_params.mpi_enable != -1) {
33381 + dwc_otg_set_param_mpi_enable(core_if,
33382 + dwc_otg_module_params.
33385 + if (dwc_otg_module_params.pti_enable != -1) {
33387 + dwc_otg_set_param_pti_enable(core_if,
33388 + dwc_otg_module_params.
33391 + if (dwc_otg_module_params.lpm_enable != -1) {
33393 + dwc_otg_set_param_lpm_enable(core_if,
33394 + dwc_otg_module_params.
33397 + if (dwc_otg_module_params.ic_usb_cap != -1) {
33399 + dwc_otg_set_param_ic_usb_cap(core_if,
33400 + dwc_otg_module_params.
33403 + if (dwc_otg_module_params.tx_thr_length != -1) {
33405 + dwc_otg_set_param_tx_thr_length(core_if,
33406 + dwc_otg_module_params.tx_thr_length);
33408 + if (dwc_otg_module_params.rx_thr_length != -1) {
33410 + dwc_otg_set_param_rx_thr_length(core_if,
33411 + dwc_otg_module_params.
33414 + if (dwc_otg_module_params.ahb_thr_ratio != -1) {
33416 + dwc_otg_set_param_ahb_thr_ratio(core_if,
33417 + dwc_otg_module_params.ahb_thr_ratio);
33419 + if (dwc_otg_module_params.power_down != -1) {
33421 + dwc_otg_set_param_power_down(core_if,
33422 + dwc_otg_module_params.power_down);
33424 + if (dwc_otg_module_params.reload_ctl != -1) {
33426 + dwc_otg_set_param_reload_ctl(core_if,
33427 + dwc_otg_module_params.reload_ctl);
33430 + if (dwc_otg_module_params.dev_out_nak != -1) {
33432 + dwc_otg_set_param_dev_out_nak(core_if,
33433 + dwc_otg_module_params.dev_out_nak);
33436 + if (dwc_otg_module_params.cont_on_bna != -1) {
33438 + dwc_otg_set_param_cont_on_bna(core_if,
33439 + dwc_otg_module_params.cont_on_bna);
33442 + if (dwc_otg_module_params.ahb_single != -1) {
33444 + dwc_otg_set_param_ahb_single(core_if,
33445 + dwc_otg_module_params.ahb_single);
33448 + if (dwc_otg_module_params.otg_ver != -1) {
33450 + dwc_otg_set_param_otg_ver(core_if,
33451 + dwc_otg_module_params.otg_ver);
33453 + if (dwc_otg_module_params.adp_enable != -1) {
33455 + dwc_otg_set_param_adp_enable(core_if,
33456 + dwc_otg_module_params.
33463 + * This function is the top level interrupt handler for the Common
33464 + * (Device and host modes) interrupts.
33466 +static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
33468 + int32_t retval = IRQ_NONE;
33470 + retval = dwc_otg_handle_common_intr(dev);
33471 + if (retval != 0) {
33472 + S3C2410X_CLEAR_EINTPEND();
33474 + return IRQ_RETVAL(retval);
33478 + * This function is called when a lm_device is unregistered with the
33479 + * dwc_otg_driver. This happens, for example, when the rmmod command is
33480 + * executed. The device may or may not be electrically present. If it is
33481 + * present, the driver stops device processing. Any resources used on behalf
33482 + * of this device are freed.
33486 +#ifdef LM_INTERFACE
33487 +#define REM_RETVAL(n)
33488 +static void dwc_otg_driver_remove( struct lm_device *_dev )
33489 +{ dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
33490 +#elif defined(PCI_INTERFACE)
33491 +#define REM_RETVAL(n)
33492 +static void dwc_otg_driver_remove( struct pci_dev *_dev )
33493 +{ dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
33494 +#elif defined(PLATFORM_INTERFACE)
33495 +#define REM_RETVAL(n) n
33496 +static int dwc_otg_driver_remove( struct platform_device *_dev )
33497 +{ dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev);
33500 + DWC_DEBUGPL(DBG_ANY, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev);
33503 + /* Memory allocation for the dwc_otg_device failed. */
33504 + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
33505 + return REM_RETVAL(-ENOMEM);
33507 +#ifndef DWC_DEVICE_ONLY
33508 + if (otg_dev->hcd) {
33509 + hcd_remove(_dev);
33511 + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
33512 + return REM_RETVAL(-EINVAL);
33516 +#ifndef DWC_HOST_ONLY
33517 + if (otg_dev->pcd) {
33518 + pcd_remove(_dev);
33520 + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
33521 + return REM_RETVAL(-EINVAL);
33527 + if (otg_dev->common_irq_installed) {
33528 + free_irq(otg_dev->os_dep.irq_num, otg_dev);
33530 + DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n", __func__);
33531 + return REM_RETVAL(-ENXIO);
33534 + if (otg_dev->core_if) {
33535 + dwc_otg_cil_remove(otg_dev->core_if);
33537 + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
33538 + return REM_RETVAL(-ENXIO);
33542 + * Remove the device attributes
33544 + dwc_otg_attr_remove(_dev);
33547 + * Return the memory.
33549 + if (otg_dev->os_dep.base) {
33550 + iounmap(otg_dev->os_dep.base);
33552 + DWC_FREE(otg_dev);
33555 + * Clear the drvdata pointer.
33557 +#ifdef LM_INTERFACE
33558 + lm_set_drvdata(_dev, 0);
33559 +#elif defined(PCI_INTERFACE)
33560 + release_mem_region(otg_dev->os_dep.rsrc_start,
33561 + otg_dev->os_dep.rsrc_len);
33562 + pci_set_drvdata(_dev, 0);
33563 +#elif defined(PLATFORM_INTERFACE)
33564 + platform_set_drvdata(_dev, 0);
33566 + return REM_RETVAL(0);
33570 + * This function is called when an lm_device is bound to a
33571 + * dwc_otg_driver. It creates the driver components required to
33572 + * control the device (CIL, HCD, and PCD) and it initializes the
33573 + * device. The driver components are stored in a dwc_otg_device
33574 + * structure. A reference to the dwc_otg_device is saved in the
33575 + * lm_device. This allows the driver to access the dwc_otg_device
33576 + * structure on subsequent calls to driver methods for this device.
33578 + * @param _dev Bus device
33580 +static int dwc_otg_driver_probe(
33581 +#ifdef LM_INTERFACE
33582 + struct lm_device *_dev
33583 +#elif defined(PCI_INTERFACE)
33584 + struct pci_dev *_dev,
33585 + const struct pci_device_id *id
33586 +#elif defined(PLATFORM_INTERFACE)
33587 + struct platform_device *_dev
33592 + dwc_otg_device_t *dwc_otg_device;
33595 + dev_dbg(&_dev->dev, "dwc_otg_driver_probe(%p)\n", _dev);
33596 +#ifdef LM_INTERFACE
33597 + dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)_dev->resource.start);
33598 +#elif defined(PCI_INTERFACE)
33600 + DWC_ERROR("Invalid pci_device_id %p", id);
33604 + if (!_dev || (pci_enable_device(_dev) < 0)) {
33605 + DWC_ERROR("Invalid pci_device %p", _dev);
33608 + dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)pci_resource_start(_dev,0));
33609 + /* other stuff needed as well? */
33611 +#elif defined(PLATFORM_INTERFACE)
33612 + dev_dbg(&_dev->dev, "start=0x%08x (len 0x%x)\n",
33613 + (unsigned)_dev->resource->start,
33614 + (unsigned)(_dev->resource->end - _dev->resource->start));
33617 + dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
33619 + if (!dwc_otg_device) {
33620 + dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
33624 + memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
33625 + dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
33626 + dwc_otg_device->os_dep.platformdev = _dev;
33629 + * Map the DWC_otg Core memory into virtual address space.
33631 +#ifdef LM_INTERFACE
33632 + dwc_otg_device->os_dep.base = ioremap(_dev->resource.start, SZ_256K);
33634 + if (!dwc_otg_device->os_dep.base) {
33635 + dev_err(&_dev->dev, "ioremap() failed\n");
33636 + DWC_FREE(dwc_otg_device);
33639 + dev_dbg(&_dev->dev, "base=0x%08x\n",
33640 + (unsigned)dwc_otg_device->os_dep.base);
33641 +#elif defined(PCI_INTERFACE)
33642 + _dev->current_state = PCI_D0;
33643 + _dev->dev.power.power_state = PMSG_ON;
33645 + if (!_dev->irq) {
33646 + DWC_ERROR("Found HC with no IRQ. Check BIOS/PCI %s setup!",
33648 + iounmap(dwc_otg_device->os_dep.base);
33649 + DWC_FREE(dwc_otg_device);
33653 + dwc_otg_device->os_dep.rsrc_start = pci_resource_start(_dev, 0);
33654 + dwc_otg_device->os_dep.rsrc_len = pci_resource_len(_dev, 0);
33655 + DWC_DEBUGPL(DBG_ANY, "PCI resource: start=%08x, len=%08x\n",
33656 + (unsigned)dwc_otg_device->os_dep.rsrc_start,
33657 + (unsigned)dwc_otg_device->os_dep.rsrc_len);
33658 + if (!request_mem_region
33659 + (dwc_otg_device->os_dep.rsrc_start, dwc_otg_device->os_dep.rsrc_len,
33661 + dev_dbg(&_dev->dev, "error requesting memory\n");
33662 + iounmap(dwc_otg_device->os_dep.base);
33663 + DWC_FREE(dwc_otg_device);
33667 + dwc_otg_device->os_dep.base =
33668 + ioremap_nocache(dwc_otg_device->os_dep.rsrc_start,
33669 + dwc_otg_device->os_dep.rsrc_len);
33670 + if (dwc_otg_device->os_dep.base == NULL) {
33671 + dev_dbg(&_dev->dev, "error mapping memory\n");
33672 + release_mem_region(dwc_otg_device->os_dep.rsrc_start,
33673 + dwc_otg_device->os_dep.rsrc_len);
33674 + iounmap(dwc_otg_device->os_dep.base);
33675 + DWC_FREE(dwc_otg_device);
33678 + dev_dbg(&_dev->dev, "base=0x%p (before adjust) \n",
33679 + dwc_otg_device->os_dep.base);
33680 + dwc_otg_device->os_dep.base = (char *)dwc_otg_device->os_dep.base;
33681 + dev_dbg(&_dev->dev, "base=0x%p (after adjust) \n",
33682 + dwc_otg_device->os_dep.base);
33683 + dev_dbg(&_dev->dev, "%s: mapped PA 0x%x to VA 0x%p\n", __func__,
33684 + (unsigned)dwc_otg_device->os_dep.rsrc_start,
33685 + dwc_otg_device->os_dep.base);
33687 + pci_set_master(_dev);
33688 + pci_set_drvdata(_dev, dwc_otg_device);
33689 +#elif defined(PLATFORM_INTERFACE)
33690 + DWC_DEBUGPL(DBG_ANY,"Platform resource: start=%08x, len=%08x\n",
33691 + _dev->resource->start,
33692 + _dev->resource->end - _dev->resource->start + 1);
33694 + if (!request_mem_region(_dev->resource[0].start,
33695 + _dev->resource[0].end - _dev->resource[0].start + 1,
33697 + dev_dbg(&_dev->dev, "error reserving mapped memory\n");
33698 + retval = -EFAULT;
33702 + dwc_otg_device->os_dep.base = ioremap_nocache(_dev->resource[0].start,
33703 + _dev->resource[0].end -
33704 + _dev->resource[0].start+1);
33707 + if (!request_mem_region(_dev->resource[1].start,
33708 + _dev->resource[1].end - _dev->resource[1].start + 1,
33710 + dev_dbg(&_dev->dev, "error reserving mapped memory\n");
33711 + retval = -EFAULT;
33715 + dwc_otg_device->os_dep.mphi_base = ioremap_nocache(_dev->resource[1].start,
33716 + _dev->resource[1].end -
33717 + _dev->resource[1].start + 1);
33718 + dwc_otg_device->os_dep.use_swirq = (_dev->resource[1].end - _dev->resource[1].start) == 0x200;
33723 + struct map_desc desc = {
33724 + .virtual = IO_ADDRESS((unsigned)_dev->resource->start),
33725 + .pfn = __phys_to_pfn((unsigned)_dev->resource->start),
33726 + .length = SZ_128K,
33727 + .type = MT_DEVICE
33729 + iotable_init(&desc, 1);
33730 + dwc_otg_device->os_dep.base = (void *)desc.virtual;
33733 + if (!dwc_otg_device->os_dep.base) {
33734 + dev_err(&_dev->dev, "ioremap() failed\n");
33735 + retval = -ENOMEM;
33741 + * Initialize driver data to point to the global DWC_otg
33742 + * Device structure.
33744 +#ifdef LM_INTERFACE
33745 + lm_set_drvdata(_dev, dwc_otg_device);
33746 +#elif defined(PLATFORM_INTERFACE)
33747 + platform_set_drvdata(_dev, dwc_otg_device);
33749 + dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
33751 + dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
33752 + DWC_DEBUGPL(DBG_HCDV, "probe of device %p given core_if %p\n",
33753 + dwc_otg_device, dwc_otg_device->core_if);//GRAYG
33755 + if (!dwc_otg_device->core_if) {
33756 + dev_err(&_dev->dev, "CIL initialization failed!\n");
33757 + retval = -ENOMEM;
33761 + dev_dbg(&_dev->dev, "Calling get_gsnpsid\n");
33763 + * Attempt to ensure this device is really a DWC_otg Controller.
33764 + * Read and verify the SNPSID register contents. The value should be
33765 + * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
33766 + * as in "OTG version 2.XX" or "OTG version 3.XX".
33769 + if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F542000) &&
33770 + ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F543000)) {
33771 + dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
33772 + dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
33773 + retval = -EINVAL;
33778 + * Validate parameter values.
33780 + dev_dbg(&_dev->dev, "Calling set_parameters\n");
33781 + if (set_parameters(dwc_otg_device->core_if)) {
33782 + retval = -EINVAL;
33787 + * Create Device Attributes in sysfs
33789 + dev_dbg(&_dev->dev, "Calling attr_create\n");
33790 + dwc_otg_attr_create(_dev);
33793 + * Disable the global interrupt until all the interrupt
33794 + * handlers are installed.
33796 + dev_dbg(&_dev->dev, "Calling disable_global_interrupts\n");
33797 + dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
33800 + * Install the interrupt handler for the common interrupts before
33801 + * enabling common interrupts in core_init below.
33804 +#if defined(PLATFORM_INTERFACE)
33805 + devirq = platform_get_irq_byname(_dev, fiq_enable ? "soft" : "usb");
33807 + devirq = platform_get_irq(_dev, fiq_enable ? 0 : 1);
33809 + devirq = _dev->irq;
33811 + DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n",
33813 + dev_dbg(&_dev->dev, "Calling request_irq(%d)\n", devirq);
33814 + retval = request_irq(devirq, dwc_otg_common_irq,
33816 + "dwc_otg", dwc_otg_device);
33818 + DWC_ERROR("request of irq%d failed\n", devirq);
33822 + dwc_otg_device->common_irq_installed = 1;
33824 + dwc_otg_device->os_dep.irq_num = devirq;
33825 + dwc_otg_device->os_dep.fiq_num = -EINVAL;
33826 + if (fiq_enable) {
33827 + int devfiq = platform_get_irq_byname(_dev, "usb");
33829 + devfiq = platform_get_irq(_dev, 1);
33830 + dwc_otg_device->os_dep.fiq_num = devfiq;
33833 +#ifndef IRQF_TRIGGER_LOW
33834 +#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)
33835 + dev_dbg(&_dev->dev, "Calling set_irq_type\n");
33836 + set_irq_type(devirq,
33837 + IRQ_TYPE_LEVEL_LOW
33840 +#endif /*IRQF_TRIGGER_LOW*/
33843 + * Initialize the DWC_otg core.
33845 + dev_dbg(&_dev->dev, "Calling dwc_otg_core_init\n");
33846 + dwc_otg_core_init(dwc_otg_device->core_if);
33848 +#ifndef DWC_HOST_ONLY
33850 + * Initialize the PCD
33852 + dev_dbg(&_dev->dev, "Calling pcd_init\n");
33853 + retval = pcd_init(_dev);
33854 + if (retval != 0) {
33855 + DWC_ERROR("pcd_init failed\n");
33856 + dwc_otg_device->pcd = NULL;
33860 +#ifndef DWC_DEVICE_ONLY
33862 + * Initialize the HCD
33864 + dev_dbg(&_dev->dev, "Calling hcd_init\n");
33865 + retval = hcd_init(_dev);
33866 + if (retval != 0) {
33867 + DWC_ERROR("hcd_init failed\n");
33868 + dwc_otg_device->hcd = NULL;
33872 + /* Recover from drvdata having been overwritten by hcd_init() */
33873 +#ifdef LM_INTERFACE
33874 + lm_set_drvdata(_dev, dwc_otg_device);
33875 +#elif defined(PLATFORM_INTERFACE)
33876 + platform_set_drvdata(_dev, dwc_otg_device);
33877 +#elif defined(PCI_INTERFACE)
33878 + pci_set_drvdata(_dev, dwc_otg_device);
33879 + dwc_otg_device->os_dep.pcidev = _dev;
33883 + * Enable the global interrupt after all the interrupt
33884 + * handlers are installed if there is no ADP support else
33885 + * perform initial actions required for Internal ADP logic.
33887 + if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
33888 + dev_dbg(&_dev->dev, "Calling enable_global_interrupts\n");
33889 + dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
33890 + dev_dbg(&_dev->dev, "Done\n");
33892 + dwc_otg_adp_start(dwc_otg_device->core_if,
33893 + dwc_otg_is_host_mode(dwc_otg_device->core_if));
33898 + dwc_otg_driver_remove(_dev);
33903 + * This structure defines the methods to be called by a bus driver
33904 + * during the lifecycle of a device on that bus. Both drivers and
33905 + * devices are registered with a bus driver. The bus driver matches
33906 + * devices to drivers based on information in the device and driver
33909 + * The probe function is called when the bus driver matches a device
33910 + * to this driver. The remove function is called when a device is
33911 + * unregistered with the bus driver.
33913 +#ifdef LM_INTERFACE
33914 +static struct lm_driver dwc_otg_driver = {
33915 + .drv = {.name = (char *)dwc_driver_name,},
33916 + .probe = dwc_otg_driver_probe,
33917 + .remove = dwc_otg_driver_remove,
33918 + // 'suspend' and 'resume' absent
33920 +#elif defined(PCI_INTERFACE)
33921 +static const struct pci_device_id pci_ids[] = { {
33922 + PCI_DEVICE(0x16c3, 0xabcd),
33924 + (unsigned long)0xdeadbeef,
33925 + }, { /* end: all zeroes */ }
33928 +MODULE_DEVICE_TABLE(pci, pci_ids);
33930 +/* pci driver glue; this is a "new style" PCI driver module */
33931 +static struct pci_driver dwc_otg_driver = {
33932 + .name = "dwc_otg",
33933 + .id_table = pci_ids,
33935 + .probe = dwc_otg_driver_probe,
33936 + .remove = dwc_otg_driver_remove,
33939 + .name = (char *)dwc_driver_name,
33942 +#elif defined(PLATFORM_INTERFACE)
33943 +static struct platform_device_id platform_ids[] = {
33945 + .name = "bcm2708_usb",
33946 + .driver_data = (kernel_ulong_t) 0xdeadbeef,
33948 + { /* end: all zeroes */ }
33950 +MODULE_DEVICE_TABLE(platform, platform_ids);
33952 +static const struct of_device_id dwc_otg_of_match_table[] = {
33953 + { .compatible = "brcm,bcm2708-usb", },
33956 +MODULE_DEVICE_TABLE(of, dwc_otg_of_match_table);
33958 +static struct platform_driver dwc_otg_driver = {
33960 + .name = (char *)dwc_driver_name,
33961 + .of_match_table = dwc_otg_of_match_table,
33963 + .id_table = platform_ids,
33965 + .probe = dwc_otg_driver_probe,
33966 + .remove = dwc_otg_driver_remove,
33967 + // no 'shutdown', 'suspend', 'resume', 'suspend_late' or 'resume_early'
33972 + * This function is called when the dwc_otg_driver is installed with the
33973 + * insmod command. It registers the dwc_otg_driver structure with the
33974 + * appropriate bus driver. This will cause the dwc_otg_driver_probe function
33975 + * to be called. In addition, the bus driver will automatically expose
33976 + * attributes defined for the device and driver in the special sysfs file
33981 +static int __init dwc_otg_driver_init(void)
33985 + struct device_driver *drv;
33987 + if(fiq_fsm_enable && !fiq_enable) {
33988 + printk(KERN_WARNING "dwc_otg: fiq_fsm_enable was set without fiq_enable! Correcting.\n");
33992 + printk(KERN_INFO "%s: version %s (%s bus)\n", dwc_driver_name,
33993 + DWC_DRIVER_VERSION,
33994 +#ifdef LM_INTERFACE
33996 + retval = lm_driver_register(&dwc_otg_driver);
33997 + drv = &dwc_otg_driver.drv;
33998 +#elif defined(PCI_INTERFACE)
34000 + retval = pci_register_driver(&dwc_otg_driver);
34001 + drv = &dwc_otg_driver.driver;
34002 +#elif defined(PLATFORM_INTERFACE)
34004 + retval = platform_driver_register(&dwc_otg_driver);
34005 + drv = &dwc_otg_driver.driver;
34007 + if (retval < 0) {
34008 + printk(KERN_ERR "%s retval=%d\n", __func__, retval);
34011 + printk(KERN_DEBUG "dwc_otg: FIQ %s\n", fiq_enable ? "enabled":"disabled");
34012 + printk(KERN_DEBUG "dwc_otg: NAK holdoff %s\n", nak_holdoff ? "enabled":"disabled");
34013 + printk(KERN_DEBUG "dwc_otg: FIQ split-transaction FSM %s\n", fiq_fsm_enable ? "enabled":"disabled");
34015 + error = driver_create_file(drv, &driver_attr_version);
34017 + error = driver_create_file(drv, &driver_attr_debuglevel);
34022 +module_init(dwc_otg_driver_init);
34025 + * This function is called when the driver is removed from the kernel
34026 + * with the rmmod command. The driver unregisters itself with its bus
34030 +static void __exit dwc_otg_driver_cleanup(void)
34032 + printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
34034 +#ifdef LM_INTERFACE
34035 + driver_remove_file(&dwc_otg_driver.drv, &driver_attr_debuglevel);
34036 + driver_remove_file(&dwc_otg_driver.drv, &driver_attr_version);
34037 + lm_driver_unregister(&dwc_otg_driver);
34038 +#elif defined(PCI_INTERFACE)
34039 + driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
34040 + driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
34041 + pci_unregister_driver(&dwc_otg_driver);
34042 +#elif defined(PLATFORM_INTERFACE)
34043 + driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
34044 + driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
34045 + platform_driver_unregister(&dwc_otg_driver);
34048 + printk(KERN_INFO "%s module removed\n", dwc_driver_name);
34051 +module_exit(dwc_otg_driver_cleanup);
34053 +MODULE_DESCRIPTION(DWC_DRIVER_DESC);
34054 +MODULE_AUTHOR("Synopsys Inc.");
34055 +MODULE_LICENSE("GPL");
34057 +module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
34058 +MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
34059 +module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
34060 +MODULE_PARM_DESC(opt, "OPT Mode");
34061 +module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
34062 +MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
34064 +module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
34066 +MODULE_PARM_DESC(dma_desc_enable,
34067 + "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
34069 +module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
34071 +MODULE_PARM_DESC(dma_burst_size,
34072 + "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
34073 +module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
34074 +MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
34075 +module_param_named(host_support_fs_ls_low_power,
34076 + dwc_otg_module_params.host_support_fs_ls_low_power, int,
34078 +MODULE_PARM_DESC(host_support_fs_ls_low_power,
34079 + "Support Low Power w/FS or LS 0=Support 1=Don't Support");
34080 +module_param_named(host_ls_low_power_phy_clk,
34081 + dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
34082 +MODULE_PARM_DESC(host_ls_low_power_phy_clk,
34083 + "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
34084 +module_param_named(enable_dynamic_fifo,
34085 + dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
34086 +MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
34087 +module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
34089 +MODULE_PARM_DESC(data_fifo_size,
34090 + "Total number of words in the data FIFO memory 32-32768");
34091 +module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
34093 +MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
34094 +module_param_named(dev_nperio_tx_fifo_size,
34095 + dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
34096 +MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
34097 + "Number of words in the non-periodic Tx FIFO 16-32768");
34098 +module_param_named(dev_perio_tx_fifo_size_1,
34099 + dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
34100 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
34101 + "Number of words in the periodic Tx FIFO 4-768");
34102 +module_param_named(dev_perio_tx_fifo_size_2,
34103 + dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
34104 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
34105 + "Number of words in the periodic Tx FIFO 4-768");
34106 +module_param_named(dev_perio_tx_fifo_size_3,
34107 + dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
34108 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
34109 + "Number of words in the periodic Tx FIFO 4-768");
34110 +module_param_named(dev_perio_tx_fifo_size_4,
34111 + dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
34112 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
34113 + "Number of words in the periodic Tx FIFO 4-768");
34114 +module_param_named(dev_perio_tx_fifo_size_5,
34115 + dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
34116 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
34117 + "Number of words in the periodic Tx FIFO 4-768");
34118 +module_param_named(dev_perio_tx_fifo_size_6,
34119 + dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
34120 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
34121 + "Number of words in the periodic Tx FIFO 4-768");
34122 +module_param_named(dev_perio_tx_fifo_size_7,
34123 + dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
34124 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
34125 + "Number of words in the periodic Tx FIFO 4-768");
34126 +module_param_named(dev_perio_tx_fifo_size_8,
34127 + dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
34128 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
34129 + "Number of words in the periodic Tx FIFO 4-768");
34130 +module_param_named(dev_perio_tx_fifo_size_9,
34131 + dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
34132 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
34133 + "Number of words in the periodic Tx FIFO 4-768");
34134 +module_param_named(dev_perio_tx_fifo_size_10,
34135 + dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
34136 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
34137 + "Number of words in the periodic Tx FIFO 4-768");
34138 +module_param_named(dev_perio_tx_fifo_size_11,
34139 + dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
34140 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
34141 + "Number of words in the periodic Tx FIFO 4-768");
34142 +module_param_named(dev_perio_tx_fifo_size_12,
34143 + dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
34144 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
34145 + "Number of words in the periodic Tx FIFO 4-768");
34146 +module_param_named(dev_perio_tx_fifo_size_13,
34147 + dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
34148 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
34149 + "Number of words in the periodic Tx FIFO 4-768");
34150 +module_param_named(dev_perio_tx_fifo_size_14,
34151 + dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
34152 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
34153 + "Number of words in the periodic Tx FIFO 4-768");
34154 +module_param_named(dev_perio_tx_fifo_size_15,
34155 + dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
34156 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
34157 + "Number of words in the periodic Tx FIFO 4-768");
34158 +module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
34160 +MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
34161 +module_param_named(host_nperio_tx_fifo_size,
34162 + dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
34163 +MODULE_PARM_DESC(host_nperio_tx_fifo_size,
34164 + "Number of words in the non-periodic Tx FIFO 16-32768");
34165 +module_param_named(host_perio_tx_fifo_size,
34166 + dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
34167 +MODULE_PARM_DESC(host_perio_tx_fifo_size,
34168 + "Number of words in the host periodic Tx FIFO 16-32768");
34169 +module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
34171 +/** @todo Set the max to 512K, modify checks */
34172 +MODULE_PARM_DESC(max_transfer_size,
34173 + "The maximum transfer size supported in bytes 2047-65535");
34174 +module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
34176 +MODULE_PARM_DESC(max_packet_count,
34177 + "The maximum number of packets in a transfer 15-511");
34178 +module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
34180 +MODULE_PARM_DESC(host_channels,
34181 + "The number of host channel registers to use 1-16");
34182 +module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
34184 +MODULE_PARM_DESC(dev_endpoints,
34185 + "The number of endpoints in addition to EP0 available for device mode 1-15");
34186 +module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
34187 +MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
34188 +module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
34190 +MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
34191 +module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
34192 +MODULE_PARM_DESC(phy_ulpi_ddr,
34193 + "ULPI at double or single data rate 0=Single 1=Double");
34194 +module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
34196 +MODULE_PARM_DESC(phy_ulpi_ext_vbus,
34197 + "ULPI PHY using internal or external vbus 0=Internal");
34198 +module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
34199 +MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
34200 +module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
34201 +MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
34202 +module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
34203 +MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
34204 +module_param_named(debug, g_dbg_lvl, int, 0444);
34205 +MODULE_PARM_DESC(debug, "");
34207 +module_param_named(en_multiple_tx_fifo,
34208 + dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
34209 +MODULE_PARM_DESC(en_multiple_tx_fifo,
34210 + "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
34211 +module_param_named(dev_tx_fifo_size_1,
34212 + dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
34213 +MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
34214 +module_param_named(dev_tx_fifo_size_2,
34215 + dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
34216 +MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
34217 +module_param_named(dev_tx_fifo_size_3,
34218 + dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
34219 +MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
34220 +module_param_named(dev_tx_fifo_size_4,
34221 + dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
34222 +MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
34223 +module_param_named(dev_tx_fifo_size_5,
34224 + dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
34225 +MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
34226 +module_param_named(dev_tx_fifo_size_6,
34227 + dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
34228 +MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
34229 +module_param_named(dev_tx_fifo_size_7,
34230 + dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
34231 +MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
34232 +module_param_named(dev_tx_fifo_size_8,
34233 + dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
34234 +MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
34235 +module_param_named(dev_tx_fifo_size_9,
34236 + dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
34237 +MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
34238 +module_param_named(dev_tx_fifo_size_10,
34239 + dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
34240 +MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
34241 +module_param_named(dev_tx_fifo_size_11,
34242 + dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
34243 +MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
34244 +module_param_named(dev_tx_fifo_size_12,
34245 + dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
34246 +MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
34247 +module_param_named(dev_tx_fifo_size_13,
34248 + dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
34249 +MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
34250 +module_param_named(dev_tx_fifo_size_14,
34251 + dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
34252 +MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
34253 +module_param_named(dev_tx_fifo_size_15,
34254 + dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
34255 +MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
34257 +module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
34258 +MODULE_PARM_DESC(thr_ctl,
34259 + "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
34260 +module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
34262 +MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
34263 +module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
34265 +MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
34267 +module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
34268 +module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
34269 +module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
34270 +MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
34271 +module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
34272 +MODULE_PARM_DESC(ic_usb_cap,
34273 + "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
34274 +module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
34276 +MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
34277 +module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
34278 +MODULE_PARM_DESC(power_down, "Power Down Mode");
34279 +module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
34280 +MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
34281 +module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
34282 +MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
34283 +module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
34284 +MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
34285 +module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
34286 +MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
34287 +module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
34288 +MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
34289 +module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
34290 +MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
34291 +module_param(microframe_schedule, bool, 0444);
34292 +MODULE_PARM_DESC(microframe_schedule, "Enable the microframe scheduler");
34294 +module_param(fiq_enable, bool, 0444);
34295 +MODULE_PARM_DESC(fiq_enable, "Enable the FIQ");
34296 +module_param(nak_holdoff, ushort, 0644);
34297 +MODULE_PARM_DESC(nak_holdoff, "Throttle duration for bulk split-transaction endpoints on a NAK. Default 8");
34298 +module_param(fiq_fsm_enable, bool, 0444);
34299 +MODULE_PARM_DESC(fiq_fsm_enable, "Enable the FIQ to perform split transactions as defined by fiq_fsm_mask");
34300 +module_param(fiq_fsm_mask, ushort, 0444);
34301 +MODULE_PARM_DESC(fiq_fsm_mask, "Bitmask of transactions to perform in the FIQ.\n"
34302 + "Bit 0 : Non-periodic split transactions\n"
34303 + "Bit 1 : Periodic split transactions\n"
34304 + "Bit 2 : High-speed multi-transfer isochronous\n"
34305 + "All other bits should be set 0.");
34306 +module_param(int_ep_interval_min, ushort, 0644);
34307 +MODULE_PARM_DESC(int_ep_interval_min, "Clamp high-speed Interrupt endpoints to a minimum polling interval.\n"
34308 + "0..1 = Use endpoint default\n"
34309 + "2..n = Minimum interval n microframes. Use powers of 2.\n");
34311 +module_param(cil_force_host, bool, 0644);
34312 +MODULE_PARM_DESC(cil_force_host, "On a connector-ID status change, "
34313 + "force Host Mode regardless of OTG state.");
34315 +/** @page "Module Parameters"
34317 + * The following parameters may be specified when starting the module.
34318 + * These parameters define how the DWC_otg controller should be
34319 + * configured. Parameter values are passed to the CIL initialization
34320 + * function dwc_otg_cil_init
34322 + * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
34326 + <tr><td>Parameter Name</td><td>Meaning</td></tr>
34330 + <td>Specifies the OTG capabilities. The driver will automatically detect the
34331 + value for this parameter if none is specified.
34332 + - 0: HNP and SRP capable (default, if available)
34333 + - 1: SRP Only capable
34334 + - 2: No HNP/SRP capable
34338 + <td>dma_enable</td>
34339 + <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
34340 + The driver will automatically detect the value for this parameter if none is
34343 + - 1: DMA (default, if available)
34347 + <td>dma_burst_size</td>
34348 + <td>The DMA Burst size (applicable only for External DMA Mode).
34349 + - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
34354 + <td>Specifies the maximum speed of operation in host and device mode. The
34355 + actual speed depends on the speed of the attached device and the value of
34357 + - 0: High Speed (default)
34362 + <td>host_support_fs_ls_low_power</td>
34363 + <td>Specifies whether low power mode is supported when attached to a Full
34364 + Speed or Low Speed device in host mode.
34365 + - 0: Don't support low power mode (default)
34366 + - 1: Support low power mode
34370 + <td>host_ls_low_power_phy_clk</td>
34371 + <td>Specifies the PHY clock rate in low power mode when connected to a Low
34372 + Speed device in host mode. This parameter is applicable only if
34373 + HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
34374 + - 0: 48 MHz (default)
34379 + <td>enable_dynamic_fifo</td>
34380 + <td> Specifies whether FIFOs may be resized by the driver software.
34381 + - 0: Use cC FIFO size parameters
34382 + - 1: Allow dynamic FIFO sizing (default)
34386 + <td>data_fifo_size</td>
34387 + <td>Total number of 4-byte words in the data FIFO memory. This memory
34388 + includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
34389 + - Values: 32 to 32768 (default 8192)
34391 + Note: The total FIFO memory depth in the FPGA configuration is 8192.
34395 + <td>dev_rx_fifo_size</td>
34396 + <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
34397 + FIFO sizing is enabled.
34398 + - Values: 16 to 32768 (default 1064)
34402 + <td>dev_nperio_tx_fifo_size</td>
34403 + <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
34404 + dynamic FIFO sizing is enabled.
34405 + - Values: 16 to 32768 (default 1024)
34409 + <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
34410 + <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
34411 + when dynamic FIFO sizing is enabled.
34412 + - Values: 4 to 768 (default 256)
34416 + <td>host_rx_fifo_size</td>
34417 + <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
34418 + sizing is enabled.
34419 + - Values: 16 to 32768 (default 1024)
34423 + <td>host_nperio_tx_fifo_size</td>
34424 + <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
34425 + dynamic FIFO sizing is enabled in the core.
34426 + - Values: 16 to 32768 (default 1024)
34430 + <td>host_perio_tx_fifo_size</td>
34431 + <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
34432 + sizing is enabled.
34433 + - Values: 16 to 32768 (default 1024)
34437 + <td>max_transfer_size</td>
34438 + <td>The maximum transfer size supported in bytes.
34439 + - Values: 2047 to 65,535 (default 65,535)
34443 + <td>max_packet_count</td>
34444 + <td>The maximum number of packets in a transfer.
34445 + - Values: 15 to 511 (default 511)
34449 + <td>host_channels</td>
34450 + <td>The number of host channel registers to use.
34451 + - Values: 1 to 16 (default 12)
34453 + Note: The FPGA configuration supports a maximum of 12 host channels.
34457 + <td>dev_endpoints</td>
34458 + <td>The number of endpoints in addition to EP0 available for device mode
34460 + - Values: 1 to 15 (default 6 IN and OUT)
34462 + Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
34467 + <td>phy_type</td>
34468 + <td>Specifies the type of PHY interface to use. By default, the driver will
34469 + automatically detect the phy_type.
34471 + - 1: UTMI+ (default, if available)
34476 + <td>phy_utmi_width</td>
34477 + <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
34478 + phy_type of UTMI+. Also, this parameter is applicable only if the
34479 + OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
34480 + core has been configured to work at either data path width.
34481 + - Values: 8 or 16 bits (default 16)
34485 + <td>phy_ulpi_ddr</td>
34486 + <td>Specifies whether the ULPI operates at double or single data rate. This
34487 + parameter is only applicable if phy_type is ULPI.
34488 + - 0: single data rate ULPI interface with 8 bit wide data bus (default)
34489 + - 1: double data rate ULPI interface with 4 bit wide data bus
34493 + <td>i2c_enable</td>
34494 + <td>Specifies whether to use the I2C interface for full speed PHY. This
34495 + parameter is only applicable if PHY_TYPE is FS.
34496 + - 0: Disabled (default)
34501 + <td>ulpi_fs_ls</td>
34502 + <td>Specifies whether to use ULPI FS/LS mode only.
34503 + - 0: Disabled (default)
34508 + <td>ts_dline</td>
34509 + <td>Specifies whether term select D-Line pulsing for all PHYs is enabled.
34510 + - 0: Disabled (default)
34515 + <td>en_multiple_tx_fifo</td>
34516 + <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
34517 + The driver will automatically detect the value for this parameter if none is
34520 + - 1: Enabled (default, if available)
34524 + <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
34525 + <td>Number of 4-byte words in each of the Tx FIFOs in device mode
34526 + when dynamic FIFO sizing is enabled.
34527 + - Values: 4 to 768 (default 256)
34531 + <td>tx_thr_length</td>
34532 + <td>Transmit Threshold length in 32 bit double words
34533 + - Values: 8 to 128 (default 64)
34537 + <td>rx_thr_length</td>
34538 + <td>Receive Threshold length in 32 bit double words
34539 + - Values: 8 to 128 (default 64)
34544 + <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of
34545 + this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and
34546 + Rx transfers accordingly.
34547 + The driver will automatically detect the value for this parameter if none is
34549 + - Values: 0 to 7 (default 0)
34550 + Bit values indicate:
34551 + - 0: Thresholding disabled
34552 + - 1: Thresholding enabled
34556 + <td>dma_desc_enable</td>
34557 + <td>Specifies whether to enable Descriptor DMA mode.
34558 + The driver will automatically detect the value for this parameter if none is
34560 + - 0: Descriptor DMA disabled
34561 + - 1: Descriptor DMA (default, if available)
34565 + <td>mpi_enable</td>
34566 + <td>Specifies whether to enable MPI enhancement mode.
34567 + The driver will automatically detect the value for this parameter if none is
34569 + - 0: MPI disabled (default)
34574 + <td>pti_enable</td>
34575 + <td>Specifies whether to enable PTI enhancement support.
34576 + The driver will automatically detect the value for this parameter if none is
34578 + - 0: PTI disabled (default)
34583 + <td>lpm_enable</td>
34584 + <td>Specifies whether to enable LPM support.
34585 + The driver will automatically detect the value for this parameter if none is
34587 + - 0: LPM disabled
34588 + - 1: LPM enable (default, if available)
34592 + <td>ic_usb_cap</td>
34593 + <td>Specifies whether to enable IC_USB capability.
34594 + The driver will automatically detect the value for this parameter if none is
34596 + - 0: IC_USB disabled (default, if available)
34597 + - 1: IC_USB enable
34601 + <td>ahb_thr_ratio</td>
34602 + <td>Specifies AHB Threshold ratio.
34603 + - Values: 0 to 3 (default 0)
34607 + <td>power_down</td>
34608 + <td>Specifies Power Down(Hibernation) Mode.
34609 + The driver will automatically detect the value for this parameter if none is
34611 + - 0: Power Down disabled (default)
34612 + - 2: Power Down enabled
34616 + <td>reload_ctl</td>
34617 + <td>Specifies whether dynamic reloading of the HFIR register is allowed during
34618 + run time. The driver will automatically detect the value for this parameter if
34619 + none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0
34620 + the core might misbehave.
34621 + - 0: Reload Control disabled (default)
34622 + - 1: Reload Control enabled
34626 + <td>dev_out_nak</td>
34627 + <td>Specifies whether Device OUT NAK enhancement enabled or no.
34628 + The driver will automatically detect the value for this parameter if
34629 + none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1b1.
34630 + - 0: The core does not set NAK after Bulk OUT transfer complete (default)
34631 + - 1: The core sets NAK after Bulk OUT transfer complete
34635 + <td>cont_on_bna</td>
34636 + <td>Specifies whether Enable Continue on BNA enabled or no.
34637 + After receiving BNA interrupt the core disables the endpoint,when the
34638 + endpoint is re-enabled by the application the
34639 + - 0: Core starts processing from the DOEPDMA descriptor (default)
34640 + - 1: Core starts processing from the descriptor which received the BNA.
34641 + This parameter is valid only when OTG_EN_DESC_DMA == 1b1.
34645 + <td>ahb_single</td>
34646 + <td>This bit when programmed supports SINGLE transfers for remainder data
34647 + in a transfer for DMA mode of operation.
34648 + - 0: The remainder data will be sent using INCR burst size (default)
34649 + - 1: The remainder data will be sent using SINGLE burst size.
34653 + <td>adp_enable</td>
34654 + <td>Specifies whether ADP feature is enabled.
34655 + The driver will automatically detect the value for this parameter if none is
34657 + - 0: ADP feature disabled (default)
34658 + - 1: ADP feature enabled
34663 + <td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3
34665 + - 0: OTG 2.0 support disabled (default)
34666 + - 1: OTG 2.0 support enabled
34671 +++ b/drivers/usb/host/dwc_otg/dwc_otg_driver.h
34673 +/* ==========================================================================
34674 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $
34675 + * $Revision: #19 $
34676 + * $Date: 2010/11/15 $
34677 + * $Change: 1627671 $
34679 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
34680 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
34681 + * otherwise expressly agreed to in writing between Synopsys and you.
34683 + * The Software IS NOT an item of Licensed Software or Licensed Product under
34684 + * any End User Software License Agreement or Agreement for Licensed Product
34685 + * with Synopsys or any supplement thereto. You are permitted to use and
34686 + * redistribute this Software in source and binary forms, with or without
34687 + * modification, provided that redistributions of source code must retain this
34688 + * notice. You may not view, use, disclose, copy or distribute this file or
34689 + * any information contained herein except pursuant to this license grant from
34690 + * Synopsys. If you do not agree with this notice, including the disclaimer
34691 + * below, then you are not authorized to use the Software.
34693 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
34694 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
34695 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
34696 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
34697 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
34698 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34699 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
34700 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34701 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34702 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
34704 + * ========================================================================== */
34706 +#ifndef __DWC_OTG_DRIVER_H__
34707 +#define __DWC_OTG_DRIVER_H__
34710 + * This file contains the interface to the Linux driver.
34712 +#include "dwc_otg_os_dep.h"
34713 +#include "dwc_otg_core_if.h"
34715 +/* Type declarations */
34716 +struct dwc_otg_pcd;
34717 +struct dwc_otg_hcd;
34720 + * This structure is a wrapper that encapsulates the driver components used to
34721 + * manage a single DWC_otg controller.
34723 +typedef struct dwc_otg_device {
34724 + /** Structure containing OS-dependent stuff. KEEP THIS STRUCT AT THE
34725 + * VERY BEGINNING OF THE DEVICE STRUCT. OSes such as FreeBSD and NetBSD
34726 + * require this. */
34727 + struct os_dependent os_dep;
34729 + /** Pointer to the core interface structure. */
34730 + dwc_otg_core_if_t *core_if;
34732 + /** Pointer to the PCD structure. */
34733 + struct dwc_otg_pcd *pcd;
34735 + /** Pointer to the HCD structure. */
34736 + struct dwc_otg_hcd *hcd;
34738 + /** Flag to indicate whether the common IRQ handler is installed. */
34739 + uint8_t common_irq_installed;
34741 +} dwc_otg_device_t;
34743 +/*We must clear S3C24XX_EINTPEND external interrupt register
34744 + * because after clearing in this register trigerred IRQ from
34745 + * H/W core in kernel interrupt can be occured again before OTG
34746 + * handlers clear all IRQ sources of Core registers because of
34747 + * timing latencies and Low Level IRQ Type.
34749 +#ifdef CONFIG_MACH_IPMATE
34750 +#define S3C2410X_CLEAR_EINTPEND() \
34752 + __raw_writel(1UL << 11,S3C24XX_EINTPEND); \
34755 +#define S3C2410X_CLEAR_EINTPEND() do { } while (0)
34760 +++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
34763 + * dwc_otg_fiq_fsm.c - The finite state machine FIQ
34765 + * Copyright (c) 2013 Raspberry Pi Foundation
34767 + * Author: Jonathan Bell <jonathan@raspberrypi.org>
34768 + * All rights reserved.
34770 + * Redistribution and use in source and binary forms, with or without
34771 + * modification, are permitted provided that the following conditions are met:
34772 + * * Redistributions of source code must retain the above copyright
34773 + * notice, this list of conditions and the following disclaimer.
34774 + * * Redistributions in binary form must reproduce the above copyright
34775 + * notice, this list of conditions and the following disclaimer in the
34776 + * documentation and/or other materials provided with the distribution.
34777 + * * Neither the name of Raspberry Pi nor the
34778 + * names of its contributors may be used to endorse or promote products
34779 + * derived from this software without specific prior written permission.
34781 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
34782 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34783 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34784 + * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
34785 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
34786 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
34787 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
34788 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34789 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34790 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34792 + * This FIQ implements functionality that performs split transactions on
34793 + * the dwc_otg hardware without any outside intervention. A split transaction
34794 + * is "queued" by nominating a specific host channel to perform the entirety
34795 + * of a split transaction. This FIQ will then perform the microframe-precise
34796 + * scheduling required in each phase of the transaction until completion.
34798 + * The FIQ functionality is glued into the Synopsys driver via the entry point
34799 + * in the FSM enqueue function, and at the exit point in handling a HC interrupt
34800 + * for a FSM-enabled channel.
34802 + * NB: Large parts of this implementation have architecture-specific code.
34803 + * For porting this functionality to other ARM machines, the minimum is required:
34804 + * - An interrupt controller allowing the top-level dwc USB interrupt to be routed
34806 + * - A method of forcing a software generated interrupt from FIQ mode that then
34807 + * triggers an IRQ entry (with the dwc USB handler called by this IRQ number)
34808 + * - Guaranteed interrupt routing such that both the FIQ and SGI occur on the same
34809 + * processor core - there is no locking between the FIQ and IRQ (aside from
34810 + * local_fiq_disable)
34814 +#include "dwc_otg_fiq_fsm.h"
34817 +char buffer[1000*16];
34819 +void notrace _fiq_print(enum fiq_debug_level dbg_lvl, volatile struct fiq_state *state, char *fmt, ...)
34821 + enum fiq_debug_level dbg_lvl_req = FIQDBG_ERR;
34824 + hfnum_data_t hfnum = { .d32 = FIQ_READ(state->dwc_regs_base + 0x408) };
34826 + if((dbg_lvl & dbg_lvl_req) || dbg_lvl == FIQDBG_ERR)
34828 + snprintf(text, 9, " %4d:%1u ", hfnum.b.frnum/8, hfnum.b.frnum & 7);
34829 + va_start(args, fmt);
34830 + vsnprintf(text+8, 9, fmt, args);
34833 + memcpy(buffer + wptr, text, 16);
34834 + wptr = (wptr + 16) % sizeof(buffer);
34839 +#ifdef CONFIG_ARM64
34841 +inline void fiq_fsm_spin_lock(fiq_lock_t *lock)
34843 + spin_lock((spinlock_t *)lock);
34846 +inline void fiq_fsm_spin_unlock(fiq_lock_t *lock)
34848 + spin_unlock((spinlock_t *)lock);
34854 + * fiq_fsm_spin_lock() - ARMv6+ bare bones spinlock
34855 + * Must be called with local interrupts and FIQ disabled.
34857 +#if defined(CONFIG_ARCH_BCM2835) && defined(CONFIG_SMP)
34858 +inline void fiq_fsm_spin_lock(fiq_lock_t *lock)
34860 + unsigned long tmp;
34862 + fiq_lock_t lockval;
34863 + /* Nested locking, yay. If we are on the same CPU as the fiq, then the disable
34864 + * will be sufficient. If we are on a different CPU, then the lock protects us. */
34865 + prefetchw(&lock->slock);
34867 + "1: ldrex %0, [%3]\n"
34868 + " add %1, %0, %4\n"
34869 + " strex %2, %1, [%3]\n"
34872 + : "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
34873 + : "r" (&lock->slock), "I" (1 << 16)
34876 + while (lockval.tickets.next != lockval.tickets.owner) {
34878 + lockval.tickets.owner = READ_ONCE(lock->tickets.owner);
34883 +inline void fiq_fsm_spin_lock(fiq_lock_t *lock) { }
34887 + * fiq_fsm_spin_unlock() - ARMv6+ bare bones spinunlock
34889 +#if defined(CONFIG_ARCH_BCM2835) && defined(CONFIG_SMP)
34890 +inline void fiq_fsm_spin_unlock(fiq_lock_t *lock)
34893 + lock->tickets.owner++;
34897 +inline void fiq_fsm_spin_unlock(fiq_lock_t *lock) { }
34903 + * fiq_fsm_restart_channel() - Poke channel enable bit for a split transaction
34904 + * @channel: channel to re-enable
34906 +static void fiq_fsm_restart_channel(struct fiq_state *st, int n, int force)
34908 + hcchar_data_t hcchar = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR) };
34910 + hcchar.b.chen = 0;
34911 + if (st->channel[n].hcchar_copy.b.eptype & 0x1) {
34912 + hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) };
34913 + /* Hardware bug workaround: update the ssplit index */
34914 + if (st->channel[n].hcsplt_copy.b.spltena)
34915 + st->channel[n].expected_uframe = (hfnum.b.frnum + 1) & 0x3FFF;
34917 + hcchar.b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
34920 + FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, hcchar.d32);
34921 + hcchar.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
34922 + hcchar.b.chen = 1;
34924 + FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, hcchar.d32);
34925 + fiq_print(FIQDBG_INT, st, "HCGO %01d %01d", n, force);
34929 + * fiq_fsm_setup_csplit() - Prepare a host channel for a CSplit transaction stage
34930 + * @st: Pointer to the channel's state
34931 + * @n : channel number
34933 + * Change host channel registers to perform a complete-split transaction. Being mindful of the
34934 + * endpoint direction, set control regs up correctly.
34936 +static void notrace fiq_fsm_setup_csplit(struct fiq_state *st, int n)
34938 + hcsplt_data_t hcsplt = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT) };
34939 + hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) };
34941 + hcsplt.b.compsplt = 1;
34942 + if (st->channel[n].hcchar_copy.b.epdir == 1) {
34943 + // If IN, the CSPLIT result contains the data or a hub handshake. hctsiz = maxpacket.
34944 + hctsiz.b.xfersize = st->channel[n].hctsiz_copy.b.xfersize;
34946 + // If OUT, the CSPLIT result contains handshake only.
34947 + hctsiz.b.xfersize = 0;
34949 + FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32);
34950 + FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32);
34955 + * fiq_fsm_restart_np_pending() - Restart a single non-periodic contended transfer
34956 + * @st: Pointer to the channel's state
34957 + * @num_channels: Total number of host channels
34958 + * @orig_channel: Channel index of completed transfer
34960 + * In the case where an IN and OUT transfer are simultaneously scheduled to the
34961 + * same device/EP, inadequate hub implementations will misbehave. Once the first
34962 + * transfer is complete, a pending non-periodic split can then be issued.
34964 +static void notrace fiq_fsm_restart_np_pending(struct fiq_state *st, int num_channels, int orig_channel)
34967 + int dev_addr = st->channel[orig_channel].hcchar_copy.b.devaddr;
34968 + int ep_num = st->channel[orig_channel].hcchar_copy.b.epnum;
34969 + for (i = 0; i < num_channels; i++) {
34970 + if (st->channel[i].fsm == FIQ_NP_SSPLIT_PENDING &&
34971 + st->channel[i].hcchar_copy.b.devaddr == dev_addr &&
34972 + st->channel[i].hcchar_copy.b.epnum == ep_num) {
34973 + st->channel[i].fsm = FIQ_NP_SSPLIT_STARTED;
34974 + fiq_fsm_restart_channel(st, i, 0);
34980 +static inline int notrace fiq_get_xfer_len(struct fiq_state *st, int n)
34982 + /* The xfersize register is a bit wonky. For IN transfers, it decrements by the packet size. */
34983 + hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) };
34985 + if (st->channel[n].hcchar_copy.b.epdir == 0) {
34986 + return st->channel[n].hctsiz_copy.b.xfersize;
34988 + return st->channel[n].hctsiz_copy.b.xfersize - hctsiz.b.xfersize;
34995 + * fiq_increment_dma_buf() - update DMA address for bounce buffers after a CSPLIT
34997 + * Of use only for IN periodic transfers.
34999 +static int notrace fiq_increment_dma_buf(struct fiq_state *st, int num_channels, int n)
35001 + hcdma_data_t hcdma;
35002 + int i = st->channel[n].dma_info.index;
35004 + struct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base;
35006 + len = fiq_get_xfer_len(st, n);
35007 + fiq_print(FIQDBG_INT, st, "LEN: %03d", len);
35008 + st->channel[n].dma_info.slot_len[i] = len;
35013 + hcdma.d32 = (dma_addr_t) &blob->channel[n].index[i].buf[0];
35014 + FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA, hcdma.d32);
35015 + st->channel[n].dma_info.index = i;
35020 + * fiq_reload_hctsiz() - for IN transactions, reset HCTSIZ
35022 +static void notrace fiq_fsm_reload_hctsiz(struct fiq_state *st, int n)
35024 + hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) };
35025 + hctsiz.b.xfersize = st->channel[n].hctsiz_copy.b.xfersize;
35026 + hctsiz.b.pktcnt = 1;
35027 + FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32);
35031 + * fiq_fsm_reload_hcdma() - for OUT transactions, rewind DMA pointer
35033 +static void notrace fiq_fsm_reload_hcdma(struct fiq_state *st, int n)
35035 + hcdma_data_t hcdma = st->channel[n].hcdma_copy;
35036 + FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA, hcdma.d32);
35040 + * fiq_iso_out_advance() - update DMA address and split position bits
35041 + * for isochronous OUT transactions.
35043 + * Returns 1 if this is the last packet queued, 0 otherwise. Split-ALL and
35044 + * Split-BEGIN states are not handled - this is done when the transaction was queued.
35046 + * This function must only be called from the FIQ_ISO_OUT_ACTIVE state.
35048 +static int notrace fiq_iso_out_advance(struct fiq_state *st, int num_channels, int n)
35050 + hcsplt_data_t hcsplt;
35051 + hctsiz_data_t hctsiz;
35052 + hcdma_data_t hcdma;
35053 + struct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base;
35055 + int i = st->channel[n].dma_info.index;
35057 + fiq_print(FIQDBG_INT, st, "ADV %01d %01d ", n, i);
35061 + if (st->channel[n].dma_info.slot_len[i+1] == 255)
35064 + /* New DMA address - address of bounce buffer referred to in index */
35065 + hcdma.d32 = (dma_addr_t) blob->channel[n].index[i].buf;
35066 + //hcdma.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA);
35067 + //hcdma.d32 += st->channel[n].dma_info.slot_len[i];
35068 + fiq_print(FIQDBG_INT, st, "LAST: %01d ", last);
35069 + fiq_print(FIQDBG_INT, st, "LEN: %03d", st->channel[n].dma_info.slot_len[i]);
35070 + hcsplt.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT);
35071 + hctsiz.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ);
35072 + hcsplt.b.xactpos = (last) ? ISOC_XACTPOS_END : ISOC_XACTPOS_MID;
35073 + /* Set up new packet length */
35074 + hctsiz.b.pktcnt = 1;
35075 + hctsiz.b.xfersize = st->channel[n].dma_info.slot_len[i];
35076 + fiq_print(FIQDBG_INT, st, "%08x", hctsiz.d32);
35078 + st->channel[n].dma_info.index++;
35079 + FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32);
35080 + FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32);
35081 + FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA, hcdma.d32);
35086 + * fiq_fsm_tt_next_isoc() - queue next pending isochronous out start-split on a TT
35088 + * Despite the limitations of the DWC core, we can force a microframe pipeline of
35089 + * isochronous OUT start-split transactions while waiting for a corresponding other-type
35090 + * of endpoint to finish its CSPLITs. TTs have big periodic buffers therefore it
35091 + * is very unlikely that filling the start-split FIFO will cause data loss.
35092 + * This allows much better interleaving of transactions in an order-independent way-
35093 + * there is no requirement to prioritise isochronous, just a state-space search has
35094 + * to be performed on each periodic start-split complete interrupt.
35096 +static int notrace fiq_fsm_tt_next_isoc(struct fiq_state *st, int num_channels, int n)
35098 + int hub_addr = st->channel[n].hub_addr;
35099 + int port_addr = st->channel[n].port_addr;
35100 + int i, poked = 0;
35101 + for (i = 0; i < num_channels; i++) {
35102 + if (i == n || st->channel[i].fsm == FIQ_PASSTHROUGH)
35104 + if (st->channel[i].hub_addr == hub_addr &&
35105 + st->channel[i].port_addr == port_addr) {
35106 + switch (st->channel[i].fsm) {
35107 + case FIQ_PER_ISO_OUT_PENDING:
35108 + if (st->channel[i].nrpackets == 1) {
35109 + st->channel[i].fsm = FIQ_PER_ISO_OUT_LAST;
35111 + st->channel[i].fsm = FIQ_PER_ISO_OUT_ACTIVE;
35113 + fiq_fsm_restart_channel(st, i, 0);
35128 + * fiq_fsm_tt_in_use() - search for host channels using this TT
35129 + * @n: Channel to use as reference
35132 +int notrace noinline fiq_fsm_tt_in_use(struct fiq_state *st, int num_channels, int n)
35134 + int hub_addr = st->channel[n].hub_addr;
35135 + int port_addr = st->channel[n].port_addr;
35136 + int i, in_use = 0;
35137 + for (i = 0; i < num_channels; i++) {
35138 + if (i == n || st->channel[i].fsm == FIQ_PASSTHROUGH)
35140 + switch (st->channel[i].fsm) {
35141 + /* TT is reserved for channels that are in the middle of a periodic
35142 + * split transaction.
35144 + case FIQ_PER_SSPLIT_STARTED:
35145 + case FIQ_PER_CSPLIT_WAIT:
35146 + case FIQ_PER_CSPLIT_NYET1:
35147 + //case FIQ_PER_CSPLIT_POLL:
35148 + case FIQ_PER_ISO_OUT_ACTIVE:
35149 + case FIQ_PER_ISO_OUT_LAST:
35150 + if (st->channel[i].hub_addr == hub_addr &&
35151 + st->channel[i].port_addr == port_addr) {
35165 + * fiq_fsm_more_csplits() - determine whether additional CSPLITs need
35166 + * to be issued for this IN transaction.
35168 + * We cannot tell the inbound PID of a data packet due to hardware limitations.
35169 + * we need to make an educated guess as to whether we need to queue another CSPLIT
35170 + * or not. A no-brainer is when we have received enough data to fill the endpoint
35171 + * size, but for endpoints that give variable-length data then we have to resort
35174 + * We also return whether this is the last CSPLIT to be queued, again based on
35175 + * heuristics. This is to allow a 1-uframe overlap of periodic split transactions.
35176 + * Note: requires at least 1 CSPLIT to have been performed prior to being called.
35180 + * We need some way of guaranteeing if a returned periodic packet of size X
35181 + * has a DATA0 PID.
35182 + * The heuristic value of 144 bytes assumes that the received data has maximal
35183 + * bit-stuffing and the clock frequency of the transmitting device is at the lowest
35184 + * permissible limit. If the transfer length results in a final packet size
35185 + * 144 < p <= 188, then an erroneous CSPLIT will be issued.
35186 + * Also used to ensure that an endpoint will nominally only return a single
35187 + * complete-split worth of data.
35189 +#define DATA0_PID_HEURISTIC 144
35191 +static int notrace noinline fiq_fsm_more_csplits(struct fiq_state *state, int n, int *probably_last)
35195 + int total_len = 0;
35196 + int more_needed = 1;
35197 + struct fiq_channel_state *st = &state->channel[n];
35199 + for (i = 0; i < st->dma_info.index; i++) {
35200 + total_len += st->dma_info.slot_len[i];
35203 + *probably_last = 0;
35205 + if (st->hcchar_copy.b.eptype == 0x3) {
35207 + * An interrupt endpoint will take max 2 CSPLITs. if we are receiving data
35208 + * then this is definitely the last CSPLIT.
35210 + *probably_last = 1;
35212 + /* Isoc IN. This is a bit risky if we are the first transaction:
35213 + * we may have been held off slightly. */
35214 + if (i > 1 && st->dma_info.slot_len[st->dma_info.index-1] <= DATA0_PID_HEURISTIC) {
35217 + /* If in the next uframe we will receive enough data to fill the endpoint,
35218 + * then only issue 1 more csplit.
35220 + if (st->hctsiz_copy.b.xfersize - total_len <= DATA0_PID_HEURISTIC)
35221 + *probably_last = 1;
35224 + if (total_len >= st->hctsiz_copy.b.xfersize ||
35225 + i == 6 || total_len == 0)
35226 + /* Note: due to bit stuffing it is possible to have > 6 CSPLITs for
35227 + * a single endpoint. Accepting more would completely break our scheduling mechanism though
35228 + * - in these extreme cases we will pass through a truncated packet.
35232 + return more_needed;
35236 + * fiq_fsm_too_late() - Test transaction for lateness
35238 + * If a SSPLIT for a large IN transaction is issued too late in a frame,
35239 + * the hub will disable the port to the device and respond with ERR handshakes.
35240 + * The hub status endpoint will not reflect this change.
35241 + * Returns 1 if we will issue a SSPLIT that will result in a device babble.
35243 +int notrace fiq_fsm_too_late(struct fiq_state *st, int n)
35246 + hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) };
35247 + uframe = hfnum.b.frnum & 0x7;
35248 + if ((uframe < 6) && (st->channel[n].nrpackets + 1 + uframe > 7)) {
35257 + * fiq_fsm_start_next_periodic() - A half-arsed attempt at a microframe pipeline
35259 + * Search pending transactions in the start-split pending state and queue them.
35260 + * Don't queue packets in uframe .5 (comes out in .6) (USB2.0 11.18.4).
35261 + * Note: we specifically don't do isochronous OUT transactions first because better
35262 + * use of the TT's start-split fifo can be achieved by pipelining an IN before an OUT.
35264 +static void notrace noinline fiq_fsm_start_next_periodic(struct fiq_state *st, int num_channels)
35267 + hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) };
35268 + if ((hfnum.b.frnum & 0x7) == 5)
35270 + for (n = 0; n < num_channels; n++) {
35271 + if (st->channel[n].fsm == FIQ_PER_SSPLIT_QUEUED) {
35272 + /* Check to see if any other transactions are using this TT */
35273 + if(!fiq_fsm_tt_in_use(st, num_channels, n)) {
35274 + if (!fiq_fsm_too_late(st, n)) {
35275 + st->channel[n].fsm = FIQ_PER_SSPLIT_STARTED;
35276 + fiq_print(FIQDBG_INT, st, "NEXTPER ");
35277 + fiq_fsm_restart_channel(st, n, 0);
35279 + st->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT;
35285 + for (n = 0; n < num_channels; n++) {
35286 + if (st->channel[n].fsm == FIQ_PER_ISO_OUT_PENDING) {
35287 + if (!fiq_fsm_tt_in_use(st, num_channels, n)) {
35288 + fiq_print(FIQDBG_INT, st, "NEXTISO ");
35289 + if (st->channel[n].nrpackets == 1)
35290 + st->channel[n].fsm = FIQ_PER_ISO_OUT_LAST;
35292 + st->channel[n].fsm = FIQ_PER_ISO_OUT_ACTIVE;
35293 + fiq_fsm_restart_channel(st, n, 0);
35301 + * fiq_fsm_update_hs_isoc() - update isochronous frame and transfer data
35302 + * @state: Pointer to fiq_state
35303 + * @n: Channel transaction is active on
35304 + * @hcint: Copy of host channel interrupt register
35306 + * Returns 0 if there are no more transactions for this HC to do, 1
35309 +static int notrace noinline fiq_fsm_update_hs_isoc(struct fiq_state *state, int n, hcint_data_t hcint)
35311 + struct fiq_channel_state *st = &state->channel[n];
35312 + int xfer_len = 0, nrpackets = 0;
35313 + hcdma_data_t hcdma;
35314 + fiq_print(FIQDBG_INT, state, "HSISO %02d", n);
35316 + xfer_len = fiq_get_xfer_len(state, n);
35317 + st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].actual_length = xfer_len;
35319 + st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].status = hcint.d32;
35321 + st->hs_isoc_info.index++;
35322 + if (st->hs_isoc_info.index == st->hs_isoc_info.nrframes) {
35326 + /* grab the next DMA address offset from the array */
35327 + hcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].offset;
35328 + FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA, hcdma.d32);
35330 + /* We need to set multi_count. This is a bit tricky - has to be set per-transaction as
35331 + * the core needs to be told to send the correct number. Caution: for IN transfers,
35332 + * this is always set to the maximum size of the endpoint. */
35333 + xfer_len = st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].length;
35334 + /* Integer divide in a FIQ: fun. FIXME: make this not suck */
35335 + nrpackets = (xfer_len + st->hcchar_copy.b.mps - 1) / st->hcchar_copy.b.mps;
35336 + if (nrpackets == 0)
35338 + st->hcchar_copy.b.multicnt = nrpackets;
35339 + st->hctsiz_copy.b.pktcnt = nrpackets;
35341 + /* Initial PID also needs to be set */
35342 + if (st->hcchar_copy.b.epdir == 0) {
35343 + st->hctsiz_copy.b.xfersize = xfer_len;
35344 + switch (st->hcchar_copy.b.multicnt) {
35346 + st->hctsiz_copy.b.pid = DWC_PID_DATA0;
35350 + st->hctsiz_copy.b.pid = DWC_PID_MDATA;
35355 + st->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps;
35356 + switch (st->hcchar_copy.b.multicnt) {
35358 + st->hctsiz_copy.b.pid = DWC_PID_DATA0;
35361 + st->hctsiz_copy.b.pid = DWC_PID_DATA1;
35364 + st->hctsiz_copy.b.pid = DWC_PID_DATA2;
35368 + FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, st->hctsiz_copy.d32);
35369 + FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, st->hcchar_copy.d32);
35370 + /* Channel is enabled on hcint handler exit */
35371 + fiq_print(FIQDBG_INT, state, "HSISOOUT");
35377 + * fiq_fsm_do_sof() - FSM start-of-frame interrupt handler
35378 + * @state: Pointer to the state struct passed from banked FIQ mode registers.
35379 + * @num_channels: set according to the DWC hardware configuration
35381 + * The SOF handler in FSM mode has two functions
35382 + * 1. Hold off SOF from causing schedule advancement in IRQ context if there's
35384 + * 2. Advance certain FSM states that require either a microframe delay, or a microframe
35387 + * The second part is architecture-specific to mach-bcm2835 -
35388 + * a sane interrupt controller would have a mask register for ARM interrupt sources
35389 + * to be promoted to the nFIQ line, but it doesn't. Instead a single interrupt
35390 + * number (USB) can be enabled. This means that certain parts of the USB specification
35391 + * that require "wait a little while, then issue another packet" cannot be fulfilled with
35392 + * the timing granularity required to achieve optimal throughout. The workaround is to use
35393 + * the SOF "timer" (125uS) to perform this task.
35395 +static int notrace noinline fiq_fsm_do_sof(struct fiq_state *state, int num_channels)
35397 + hfnum_data_t hfnum = { .d32 = FIQ_READ(state->dwc_regs_base + HFNUM) };
35399 + int kick_irq = 0;
35401 + if ((hfnum.b.frnum & 0x7) == 1) {
35402 + /* We cannot issue csplits for transactions in the last frame past (n+1).1
35403 + * Check to see if there are any transactions that are stale.
35406 + for (n = 0; n < num_channels; n++) {
35407 + switch (state->channel[n].fsm) {
35408 + case FIQ_PER_CSPLIT_WAIT:
35409 + case FIQ_PER_CSPLIT_NYET1:
35410 + case FIQ_PER_CSPLIT_POLL:
35411 + case FIQ_PER_CSPLIT_LAST:
35412 + /* Check if we are no longer in the same full-speed frame. */
35413 + if (((state->channel[n].expected_uframe & 0x3FFF) & ~0x7) <
35414 + (hfnum.b.frnum & ~0x7))
35415 + state->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT;
35423 + for (n = 0; n < num_channels; n++) {
35424 + switch (state->channel[n].fsm) {
35426 + case FIQ_NP_SSPLIT_RETRY:
35427 + case FIQ_NP_IN_CSPLIT_RETRY:
35428 + case FIQ_NP_OUT_CSPLIT_RETRY:
35429 + fiq_fsm_restart_channel(state, n, 0);
35432 + case FIQ_HS_ISOC_SLEEPING:
35433 + /* Is it time to wake this channel yet? */
35434 + if (--state->channel[n].uframe_sleeps == 0) {
35435 + state->channel[n].fsm = FIQ_HS_ISOC_TURBO;
35436 + fiq_fsm_restart_channel(state, n, 0);
35440 + case FIQ_PER_SSPLIT_QUEUED:
35441 + if ((hfnum.b.frnum & 0x7) == 5)
35443 + if(!fiq_fsm_tt_in_use(state, num_channels, n)) {
35444 + if (!fiq_fsm_too_late(state, n)) {
35445 + fiq_print(FIQDBG_INT, state, "SOF GO %01d", n);
35446 + fiq_fsm_restart_channel(state, n, 0);
35447 + state->channel[n].fsm = FIQ_PER_SSPLIT_STARTED;
35449 + /* Transaction cannot be started without risking a device babble error */
35450 + state->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT;
35451 + state->haintmsk_saved.b2.chint &= ~(1 << n);
35452 + FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, 0);
35458 + case FIQ_PER_ISO_OUT_PENDING:
35459 + /* Ordinarily, this should be poked after the SSPLIT
35460 + * complete interrupt for a competing transfer on the same
35461 + * TT. Doesn't happen for aborted transactions though.
35463 + if ((hfnum.b.frnum & 0x7) >= 5)
35465 + if (!fiq_fsm_tt_in_use(state, num_channels, n)) {
35466 + /* Hardware bug. SOF can sometimes occur after the channel halt interrupt
35467 + * that caused this.
35469 + fiq_fsm_restart_channel(state, n, 0);
35470 + fiq_print(FIQDBG_INT, state, "SOF ISOC");
35471 + if (state->channel[n].nrpackets == 1) {
35472 + state->channel[n].fsm = FIQ_PER_ISO_OUT_LAST;
35474 + state->channel[n].fsm = FIQ_PER_ISO_OUT_ACTIVE;
35479 + case FIQ_PER_CSPLIT_WAIT:
35480 + /* we are guaranteed to be in this state if and only if the SSPLIT interrupt
35481 + * occurred when the bus transaction occurred. The SOF interrupt reversal bug
35482 + * will utterly bugger this up though.
35484 + if (hfnum.b.frnum != state->channel[n].expected_uframe) {
35485 + fiq_print(FIQDBG_INT, state, "SOFCS %d ", n);
35486 + state->channel[n].fsm = FIQ_PER_CSPLIT_POLL;
35487 + fiq_fsm_restart_channel(state, n, 0);
35488 + fiq_fsm_start_next_periodic(state, num_channels);
35493 + case FIQ_PER_SPLIT_TIMEOUT:
35494 + case FIQ_DEQUEUE_ISSUED:
35495 + /* Ugly: we have to force a HCD interrupt.
35496 + * Poke the mask for the channel in question.
35497 + * We will take a fake SOF because of this, but
35500 + state->haintmsk_saved.b2.chint &= ~(1 << n);
35501 + FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, 0);
35510 + if (state->kick_np_queues ||
35511 + dwc_frame_num_le(state->next_sched_frame, hfnum.b.frnum))
35514 + return !kick_irq;
35519 + * fiq_fsm_do_hcintr() - FSM host channel interrupt handler
35520 + * @state: Pointer to the FIQ state struct
35521 + * @num_channels: Number of channels as per hardware config
35522 + * @n: channel for which HAINT(i) was raised
35524 + * An important property is that only the CHHLT interrupt is unmasked. Unfortunately, AHBerr is as well.
35526 +static int notrace noinline fiq_fsm_do_hcintr(struct fiq_state *state, int num_channels, int n)
35528 + hcint_data_t hcint;
35529 + hcintmsk_data_t hcintmsk;
35530 + hcint_data_t hcint_probe;
35531 + hcchar_data_t hcchar;
35534 + int last_csplit = 0;
35535 + int start_next_periodic = 0;
35536 + struct fiq_channel_state *st = &state->channel[n];
35537 + hfnum_data_t hfnum;
35539 + hcint.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINT);
35540 + hcintmsk.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK);
35541 + hcint_probe.d32 = hcint.d32 & hcintmsk.d32;
35543 + if (st->fsm != FIQ_PASSTHROUGH) {
35544 + fiq_print(FIQDBG_INT, state, "HC%01d ST%02d", n, st->fsm);
35545 + fiq_print(FIQDBG_INT, state, "%08x", hcint.d32);
35548 + switch (st->fsm) {
35550 + case FIQ_PASSTHROUGH:
35551 + case FIQ_DEQUEUE_ISSUED:
35552 + /* doesn't belong to us, kick it upstairs */
35555 + case FIQ_PASSTHROUGH_ERRORSTATE:
35556 + /* We are here to emulate the error recovery mechanism of the dwc HCD.
35557 + * Several interrupts are unmasked if a previous transaction failed - it's
35558 + * death for the FIQ to attempt to handle them as the channel isn't halted.
35559 + * Emulate what the HCD does in this situation: mask and continue.
35560 + * The FSM has no other state setup so this has to be handled out-of-band.
35562 + fiq_print(FIQDBG_ERR, state, "ERRST %02d", n);
35563 + if (hcint_probe.b.nak || hcint_probe.b.ack || hcint_probe.b.datatglerr) {
35564 + fiq_print(FIQDBG_ERR, state, "RESET %02d", n);
35565 + /* In some random cases we can get a NAK interrupt coincident with a Xacterr
35566 + * interrupt, after the device has disappeared.
35568 + if (!hcint.b.xacterr)
35569 + st->nr_errors = 0;
35570 + hcintmsk.b.nak = 0;
35571 + hcintmsk.b.ack = 0;
35572 + hcintmsk.b.datatglerr = 0;
35573 + FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, hcintmsk.d32);
35576 + if (hcint_probe.b.chhltd) {
35577 + fiq_print(FIQDBG_ERR, state, "CHHLT %02d", n);
35578 + fiq_print(FIQDBG_ERR, state, "%08x", hcint.d32);
35583 + /* Non-periodic state groups */
35584 + case FIQ_NP_SSPLIT_STARTED:
35585 + case FIQ_NP_SSPLIT_RETRY:
35586 + /* Got a HCINT for a NP SSPLIT. Expected ACK / NAK / fail */
35587 + if (hcint.b.ack) {
35588 + /* SSPLIT complete. For OUT, the data has been sent. For IN, the LS transaction
35589 + * will start shortly. SOF needs to kick the transaction to prevent a NYET flood.
35591 + if(st->hcchar_copy.b.epdir == 1)
35592 + st->fsm = FIQ_NP_IN_CSPLIT_RETRY;
35594 + st->fsm = FIQ_NP_OUT_CSPLIT_RETRY;
35595 + st->nr_errors = 0;
35597 + fiq_fsm_setup_csplit(state, n);
35598 + } else if (hcint.b.nak) {
35599 + // No buffer space in TT. Retry on a uframe boundary.
35600 + fiq_fsm_reload_hcdma(state, n);
35601 + st->fsm = FIQ_NP_SSPLIT_RETRY;
35603 + } else if (hcint.b.xacterr) {
35604 + // The only other one we care about is xacterr. This implies HS bus error - retry.
35606 + if(st->hcchar_copy.b.epdir == 0)
35607 + fiq_fsm_reload_hcdma(state, n);
35608 + st->fsm = FIQ_NP_SSPLIT_RETRY;
35609 + if (st->nr_errors >= 3) {
35610 + st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
35616 + st->fsm = FIQ_NP_SPLIT_LS_ABORTED;
35622 + case FIQ_NP_IN_CSPLIT_RETRY:
35623 + /* Received a CSPLIT done interrupt.
35624 + * Expected Data/NAK/STALL/NYET for IN.
35626 + if (hcint.b.xfercomp) {
35627 + /* For IN, data is present. */
35628 + st->fsm = FIQ_NP_SPLIT_DONE;
35629 + } else if (hcint.b.nak) {
35630 + /* no endpoint data. Punt it upstairs */
35631 + st->fsm = FIQ_NP_SPLIT_DONE;
35632 + } else if (hcint.b.nyet) {
35633 + /* CSPLIT NYET - retry on a uframe boundary. */
35635 + st->nr_errors = 0;
35636 + } else if (hcint.b.datatglerr) {
35637 + /* data toggle errors do not set the xfercomp bit. */
35638 + st->fsm = FIQ_NP_SPLIT_LS_ABORTED;
35639 + } else if (hcint.b.xacterr) {
35640 + /* HS error. Retry immediate */
35641 + st->fsm = FIQ_NP_IN_CSPLIT_RETRY;
35643 + if (st->nr_errors >= 3) {
35644 + st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
35649 + } else if (hcint.b.stall || hcint.b.bblerr) {
35650 + /* A STALL implies either a LS bus error or a genuine STALL. */
35651 + st->fsm = FIQ_NP_SPLIT_LS_ABORTED;
35653 + /* Hardware bug. It's possible in some cases to
35654 + * get a channel halt with nothing else set when
35655 + * the response was a NYET. Treat as local 3-strikes retry.
35657 + hcint_data_t hcint_test = hcint;
35658 + hcint_test.b.chhltd = 0;
35659 + if (!hcint_test.d32) {
35661 + if (st->nr_errors >= 3) {
35662 + st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
35667 + /* Bail out if something unexpected happened */
35668 + st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
35671 + if (st->fsm != FIQ_NP_IN_CSPLIT_RETRY) {
35672 + fiq_fsm_restart_np_pending(state, num_channels, n);
35676 + case FIQ_NP_OUT_CSPLIT_RETRY:
35677 + /* Received a CSPLIT done interrupt.
35678 + * Expected ACK/NAK/STALL/NYET/XFERCOMP for OUT.*/
35679 + if (hcint.b.xfercomp) {
35680 + st->fsm = FIQ_NP_SPLIT_DONE;
35681 + } else if (hcint.b.nak) {
35682 + // The HCD will implement the holdoff on frame boundaries.
35683 + st->fsm = FIQ_NP_SPLIT_DONE;
35684 + } else if (hcint.b.nyet) {
35685 + // Hub still processing.
35686 + st->fsm = FIQ_NP_OUT_CSPLIT_RETRY;
35688 + st->nr_errors = 0;
35690 + } else if (hcint.b.xacterr) {
35691 + /* HS error. retry immediate */
35692 + st->fsm = FIQ_NP_OUT_CSPLIT_RETRY;
35694 + if (st->nr_errors >= 3) {
35695 + st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
35700 + } else if (hcint.b.stall) {
35701 + /* LS bus error or genuine stall */
35702 + st->fsm = FIQ_NP_SPLIT_LS_ABORTED;
35705 + * Hardware bug. It's possible in some cases to get a
35706 + * channel halt with nothing else set when the response was a NYET.
35707 + * Treat as local 3-strikes retry.
35709 + hcint_data_t hcint_test = hcint;
35710 + hcint_test.b.chhltd = 0;
35711 + if (!hcint_test.d32) {
35713 + if (st->nr_errors >= 3) {
35714 + st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
35719 + // Something unexpected happened. AHBerror or babble perhaps. Let the IRQ deal with it.
35720 + st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
35723 + if (st->fsm != FIQ_NP_OUT_CSPLIT_RETRY) {
35724 + fiq_fsm_restart_np_pending(state, num_channels, n);
35728 + /* Periodic split states (except isoc out) */
35729 + case FIQ_PER_SSPLIT_STARTED:
35730 + /* Expect an ACK or failure for SSPLIT */
35731 + if (hcint.b.ack) {
35733 + * SSPLIT transfer complete interrupt - the generation of this interrupt is fraught with bugs.
35734 + * For a packet queued in microframe n-3 to appear in n-2, if the channel is enabled near the EOF1
35735 + * point for microframe n-3, the packet will not appear on the bus until microframe n.
35736 + * Additionally, the generation of the actual interrupt is dodgy. For a packet appearing on the bus
35737 + * in microframe n, sometimes the interrupt is generated immediately. Sometimes, it appears in n+1
35738 + * coincident with SOF for n+1.
35739 + * SOF is also buggy. It can sometimes be raised AFTER the first bus transaction has taken place.
35740 + * These appear to be caused by timing/clock crossing bugs within the core itself.
35741 + * State machine workaround.
35743 + hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
35744 + hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
35745 + fiq_fsm_setup_csplit(state, n);
35746 + /* Poke the oddfrm bit. If we are equivalent, we received the interrupt at the correct
35747 + * time. If not, then we're in the next SOF.
35749 + if ((hfnum.b.frnum & 0x1) == hcchar.b.oddfrm) {
35750 + fiq_print(FIQDBG_INT, state, "CSWAIT %01d", n);
35751 + st->expected_uframe = hfnum.b.frnum;
35752 + st->fsm = FIQ_PER_CSPLIT_WAIT;
35754 + fiq_print(FIQDBG_INT, state, "CSPOL %01d", n);
35755 + /* For isochronous IN endpoints,
35756 + * we need to hold off if we are expecting a lot of data */
35757 + if (st->hcchar_copy.b.mps < DATA0_PID_HEURISTIC) {
35758 + start_next_periodic = 1;
35760 + /* Danger will robinson: we are in a broken state. If our first interrupt after
35761 + * this is a NYET, it will be delayed by 1 uframe and result in an unrecoverable
35762 + * lag. Unmask the NYET interrupt.
35764 + st->expected_uframe = (hfnum.b.frnum + 1) & 0x3FFF;
35765 + st->fsm = FIQ_PER_CSPLIT_BROKEN_NYET1;
35769 + } else if (hcint.b.xacterr) {
35770 + /* 3-strikes retry is enabled, we have hit our max nr_errors */
35771 + st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
35772 + start_next_periodic = 1;
35774 + st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
35775 + start_next_periodic = 1;
35777 + /* We can now queue the next isochronous OUT transaction, if one is pending. */
35778 + if(fiq_fsm_tt_next_isoc(state, num_channels, n)) {
35779 + fiq_print(FIQDBG_INT, state, "NEXTISO ");
35783 + case FIQ_PER_CSPLIT_NYET1:
35784 + /* First CSPLIT attempt was a NYET. If we get a subsequent NYET,
35785 + * we are too late and the TT has dropped its CSPLIT fifo.
35787 + hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
35788 + hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
35789 + start_next_periodic = 1;
35790 + if (hcint.b.nak) {
35791 + st->fsm = FIQ_PER_SPLIT_DONE;
35792 + } else if (hcint.b.xfercomp) {
35793 + fiq_increment_dma_buf(state, num_channels, n);
35794 + st->fsm = FIQ_PER_CSPLIT_POLL;
35795 + st->nr_errors = 0;
35796 + if (fiq_fsm_more_csplits(state, n, &last_csplit)) {
35799 + if (!last_csplit)
35800 + start_next_periodic = 0;
35802 + st->fsm = FIQ_PER_SPLIT_DONE;
35804 + } else if (hcint.b.nyet) {
35805 + /* Doh. Data lost. */
35806 + st->fsm = FIQ_PER_SPLIT_NYET_ABORTED;
35807 + } else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) {
35808 + st->fsm = FIQ_PER_SPLIT_LS_ABORTED;
35810 + st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
35814 + case FIQ_PER_CSPLIT_BROKEN_NYET1:
35816 + * we got here because our host channel is in the delayed-interrupt
35817 + * state and we cannot take a NYET interrupt any later than when it
35818 + * occurred. Disable then re-enable the channel if this happens to force
35819 + * CSPLITs to occur at the right time.
35821 + hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
35822 + hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
35823 + fiq_print(FIQDBG_INT, state, "BROK: %01d ", n);
35824 + if (hcint.b.nak) {
35825 + st->fsm = FIQ_PER_SPLIT_DONE;
35826 + start_next_periodic = 1;
35827 + } else if (hcint.b.xfercomp) {
35828 + fiq_increment_dma_buf(state, num_channels, n);
35829 + if (fiq_fsm_more_csplits(state, n, &last_csplit)) {
35830 + st->fsm = FIQ_PER_CSPLIT_POLL;
35833 + start_next_periodic = 1;
35834 + /* Reload HCTSIZ for the next transfer */
35835 + fiq_fsm_reload_hctsiz(state, n);
35836 + if (!last_csplit)
35837 + start_next_periodic = 0;
35839 + st->fsm = FIQ_PER_SPLIT_DONE;
35841 + } else if (hcint.b.nyet) {
35842 + st->fsm = FIQ_PER_SPLIT_NYET_ABORTED;
35843 + start_next_periodic = 1;
35844 + } else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) {
35845 + /* Local 3-strikes retry is handled by the core. This is a ERR response.*/
35846 + st->fsm = FIQ_PER_SPLIT_LS_ABORTED;
35848 + st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
35852 + case FIQ_PER_CSPLIT_POLL:
35853 + hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
35854 + hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
35855 + start_next_periodic = 1;
35856 + if (hcint.b.nak) {
35857 + st->fsm = FIQ_PER_SPLIT_DONE;
35858 + } else if (hcint.b.xfercomp) {
35859 + fiq_increment_dma_buf(state, num_channels, n);
35860 + if (fiq_fsm_more_csplits(state, n, &last_csplit)) {
35863 + /* Reload HCTSIZ for the next transfer */
35864 + fiq_fsm_reload_hctsiz(state, n);
35865 + if (!last_csplit)
35866 + start_next_periodic = 0;
35868 + st->fsm = FIQ_PER_SPLIT_DONE;
35870 + } else if (hcint.b.nyet) {
35871 + /* Are we a NYET after the first data packet? */
35872 + if (st->nrpackets == 0) {
35873 + st->fsm = FIQ_PER_CSPLIT_NYET1;
35877 + /* We got a NYET when polling CSPLITs. Can happen
35878 + * if our heuristic fails, or if someone disables us
35879 + * for any significant length of time.
35881 + if (st->nr_errors >= 3) {
35882 + st->fsm = FIQ_PER_SPLIT_NYET_ABORTED;
35884 + st->fsm = FIQ_PER_SPLIT_DONE;
35887 + } else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) {
35888 + /* For xacterr, Local 3-strikes retry is handled by the core. This is a ERR response.*/
35889 + st->fsm = FIQ_PER_SPLIT_LS_ABORTED;
35891 + st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
35895 + case FIQ_HS_ISOC_TURBO:
35896 + if (fiq_fsm_update_hs_isoc(state, n, hcint)) {
35897 + /* more transactions to come */
35899 + fiq_print(FIQDBG_INT, state, "HSISO M ");
35900 + /* For strided transfers, put ourselves to sleep */
35901 + if (st->hs_isoc_info.stride > 1) {
35902 + st->uframe_sleeps = st->hs_isoc_info.stride - 1;
35903 + st->fsm = FIQ_HS_ISOC_SLEEPING;
35908 + st->fsm = FIQ_HS_ISOC_DONE;
35909 + fiq_print(FIQDBG_INT, state, "HSISO F ");
35913 + case FIQ_HS_ISOC_ABORTED:
35914 + /* This abort is called by the driver rewriting the state mid-transaction
35915 + * which allows the dequeue mechanism to work more effectively.
35919 + case FIQ_PER_ISO_OUT_ACTIVE:
35920 + if (hcint.b.ack) {
35921 + if(fiq_iso_out_advance(state, num_channels, n)) {
35922 + /* last OUT transfer */
35923 + st->fsm = FIQ_PER_ISO_OUT_LAST;
35925 + * Assuming the periodic FIFO in the dwc core
35926 + * actually does its job properly, we can queue
35927 + * the next ssplit now and in theory, the wire
35928 + * transactions will be in-order.
35930 + // No it doesn't. It appears to process requests in host channel order.
35931 + //start_next_periodic = 1;
35937 + * Isochronous transactions carry on regardless. Log the error
35942 + if(fiq_iso_out_advance(state, num_channels, n)) {
35943 + st->fsm = FIQ_PER_ISO_OUT_LAST;
35944 + //start_next_periodic = 1;
35951 + case FIQ_PER_ISO_OUT_LAST:
35952 + if (hcint.b.ack) {
35953 + /* All done here */
35954 + st->fsm = FIQ_PER_ISO_OUT_DONE;
35956 + st->fsm = FIQ_PER_ISO_OUT_DONE;
35959 + start_next_periodic = 1;
35962 + case FIQ_PER_SPLIT_TIMEOUT:
35963 + /* SOF kicked us because we overran. */
35964 + start_next_periodic = 1;
35972 + FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINT, hcint.d32);
35974 + /* Copy the regs into the state so the IRQ knows what to do */
35975 + st->hcint_copy.d32 = hcint.d32;
35979 + /* Restart always implies handled. */
35980 + if (restart == 2) {
35981 + /* For complete-split INs, the show must go on.
35982 + * Force a channel restart */
35983 + fiq_fsm_restart_channel(state, n, 1);
35985 + fiq_fsm_restart_channel(state, n, 0);
35988 + if (start_next_periodic) {
35989 + fiq_fsm_start_next_periodic(state, num_channels);
35991 + if (st->fsm != FIQ_PASSTHROUGH)
35992 + fiq_print(FIQDBG_INT, state, "FSMOUT%02d", st->fsm);
35999 + * dwc_otg_fiq_fsm() - Flying State Machine (monster) FIQ
36000 + * @state: pointer to state struct passed from the banked FIQ mode registers.
36001 + * @num_channels: set according to the DWC hardware configuration
36002 + * @dma: pointer to DMA bounce buffers for split transaction slots
36004 + * The FSM FIQ performs the low-level tasks that normally would be performed by the microcode
36005 + * inside an EHCI or similar host controller regarding split transactions. The DWC core
36006 + * interrupts each and every time a split transaction packet is received or sent successfully.
36007 + * This results in either an interrupt storm when everything is working "properly", or
36008 + * the interrupt latency of the system in general breaks time-sensitive periodic split
36009 + * transactions. Pushing the low-level, but relatively easy state machine work into the FIQ
36010 + * solves these problems.
36014 +void notrace dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels)
36016 + gintsts_data_t gintsts, gintsts_handled;
36017 + gintmsk_data_t gintmsk;
36018 + //hfnum_data_t hfnum;
36019 + haint_data_t haint, haint_handled;
36020 + haintmsk_data_t haintmsk;
36021 + int kick_irq = 0;
36023 + gintsts_handled.d32 = 0;
36024 + haint_handled.d32 = 0;
36026 + fiq_fsm_spin_lock(&state->lock);
36027 + gintsts.d32 = FIQ_READ(state->dwc_regs_base + GINTSTS);
36028 + gintmsk.d32 = FIQ_READ(state->dwc_regs_base + GINTMSK);
36029 + gintsts.d32 &= gintmsk.d32;
36031 + if (gintsts.b.sofintr) {
36032 + /* For FSM mode, SOF is required to keep the state machine advance for
36033 + * certain stages of the periodic pipeline. It's death to mask this
36034 + * interrupt in that case.
36037 + if (!fiq_fsm_do_sof(state, num_channels)) {
36038 + /* Kick IRQ once. Queue advancement means that all pending transactions
36039 + * will get serviced when the IRQ finally executes.
36041 + if (state->gintmsk_saved.b.sofintr == 1)
36043 + state->gintmsk_saved.b.sofintr = 0;
36045 + gintsts_handled.b.sofintr = 1;
36048 + if (gintsts.b.hcintr) {
36050 + haint.d32 = FIQ_READ(state->dwc_regs_base + HAINT);
36051 + haintmsk.d32 = FIQ_READ(state->dwc_regs_base + HAINTMSK);
36052 + haint.d32 &= haintmsk.d32;
36053 + haint_handled.d32 = 0;
36054 + for (i=0; i<num_channels; i++) {
36055 + if (haint.b2.chint & (1 << i)) {
36056 + if(!fiq_fsm_do_hcintr(state, num_channels, i)) {
36057 + /* HCINT was not handled in FIQ
36058 + * HAINT is level-sensitive, leading to level-sensitive ginststs.b.hcint bit.
36059 + * Mask HAINT(i) but keep top-level hcint unmasked.
36061 + state->haintmsk_saved.b2.chint &= ~(1 << i);
36063 + /* do_hcintr cleaned up after itself, but clear haint */
36064 + haint_handled.b2.chint |= (1 << i);
36069 + if (haint_handled.b2.chint) {
36070 + FIQ_WRITE(state->dwc_regs_base + HAINT, haint_handled.d32);
36073 + if (haintmsk.d32 != (haintmsk.d32 & state->haintmsk_saved.d32)) {
36075 + * This is necessary to avoid multiple retriggers of the MPHI in the case
36076 + * where interrupts are held off and HCINTs start to pile up.
36077 + * Only wake up the IRQ if a new interrupt came in, was not handled and was
36080 + haintmsk.d32 &= state->haintmsk_saved.d32;
36081 + FIQ_WRITE(state->dwc_regs_base + HAINTMSK, haintmsk.d32);
36084 + /* Top-Level interrupt - always handled because it's level-sensitive */
36085 + gintsts_handled.b.hcintr = 1;
36089 + /* Clear the bits in the saved register that were not handled but were triggered. */
36090 + state->gintmsk_saved.d32 &= ~(gintsts.d32 & ~gintsts_handled.d32);
36092 + /* FIQ didn't handle something - mask has changed - write new mask */
36093 + if (gintmsk.d32 != (gintmsk.d32 & state->gintmsk_saved.d32)) {
36094 + gintmsk.d32 &= state->gintmsk_saved.d32;
36095 + gintmsk.b.sofintr = 1;
36096 + FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32);
36097 +// fiq_print(FIQDBG_INT, state, "KICKGINT");
36098 +// fiq_print(FIQDBG_INT, state, "%08x", gintmsk.d32);
36099 +// fiq_print(FIQDBG_INT, state, "%08x", state->gintmsk_saved.d32);
36103 + if (gintsts_handled.d32) {
36104 + /* Only applies to edge-sensitive bits in GINTSTS */
36105 + FIQ_WRITE(state->dwc_regs_base + GINTSTS, gintsts_handled.d32);
36108 + /* We got an interrupt, didn't handle it. */
36110 + state->mphi_int_count++;
36111 + if (state->mphi_regs.swirq_set) {
36112 + FIQ_WRITE(state->mphi_regs.swirq_set, 1);
36114 + FIQ_WRITE(state->mphi_regs.outdda, state->dummy_send_dma);
36115 + FIQ_WRITE(state->mphi_regs.outddb, (1<<29));
36119 + state->fiq_done++;
36121 + fiq_fsm_spin_unlock(&state->lock);
36126 + * dwc_otg_fiq_nop() - FIQ "lite"
36127 + * @state: pointer to state struct passed from the banked FIQ mode registers.
36129 + * The "nop" handler does not intervene on any interrupts other than SOF.
36130 + * It is limited in scope to deciding at each SOF if the IRQ SOF handler (which deals
36131 + * with non-periodic/periodic queues) needs to be kicked.
36133 + * This is done to hold off the SOF interrupt, which occurs at a rate of 8000 per second.
36137 +void notrace dwc_otg_fiq_nop(struct fiq_state *state)
36139 + gintsts_data_t gintsts, gintsts_handled;
36140 + gintmsk_data_t gintmsk;
36141 + hfnum_data_t hfnum;
36143 + fiq_fsm_spin_lock(&state->lock);
36144 + hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
36145 + gintsts.d32 = FIQ_READ(state->dwc_regs_base + GINTSTS);
36146 + gintmsk.d32 = FIQ_READ(state->dwc_regs_base + GINTMSK);
36147 + gintsts.d32 &= gintmsk.d32;
36148 + gintsts_handled.d32 = 0;
36150 + if (gintsts.b.sofintr) {
36151 + if (!state->kick_np_queues &&
36152 + dwc_frame_num_gt(state->next_sched_frame, hfnum.b.frnum)) {
36153 + /* SOF handled, no work to do, just ACK interrupt */
36154 + gintsts_handled.b.sofintr = 1;
36157 + state->gintmsk_saved.b.sofintr = 0;
36161 + /* Reset handled interrupts */
36162 + if(gintsts_handled.d32) {
36163 + FIQ_WRITE(state->dwc_regs_base + GINTSTS, gintsts_handled.d32);
36166 + /* Clear the bits in the saved register that were not handled but were triggered. */
36167 + state->gintmsk_saved.d32 &= ~(gintsts.d32 & ~gintsts_handled.d32);
36169 + /* We got an interrupt, didn't handle it and want to mask it */
36170 + if (~(state->gintmsk_saved.d32)) {
36171 + state->mphi_int_count++;
36172 + gintmsk.d32 &= state->gintmsk_saved.d32;
36173 + FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32);
36174 + if (state->mphi_regs.swirq_set) {
36175 + FIQ_WRITE(state->mphi_regs.swirq_set, 1);
36177 + /* Force a clear before another dummy send */
36178 + FIQ_WRITE(state->mphi_regs.intstat, (1<<29));
36179 + FIQ_WRITE(state->mphi_regs.outdda, state->dummy_send_dma);
36180 + FIQ_WRITE(state->mphi_regs.outddb, (1<<29));
36183 + state->fiq_done++;
36185 + fiq_fsm_spin_unlock(&state->lock);
36188 +++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h
36191 + * dwc_otg_fiq_fsm.h - Finite state machine FIQ header definitions
36193 + * Copyright (c) 2013 Raspberry Pi Foundation
36195 + * Author: Jonathan Bell <jonathan@raspberrypi.org>
36196 + * All rights reserved.
36198 + * Redistribution and use in source and binary forms, with or without
36199 + * modification, are permitted provided that the following conditions are met:
36200 + * * Redistributions of source code must retain the above copyright
36201 + * notice, this list of conditions and the following disclaimer.
36202 + * * Redistributions in binary form must reproduce the above copyright
36203 + * notice, this list of conditions and the following disclaimer in the
36204 + * documentation and/or other materials provided with the distribution.
36205 + * * Neither the name of Raspberry Pi nor the
36206 + * names of its contributors may be used to endorse or promote products
36207 + * derived from this software without specific prior written permission.
36209 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
36210 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
36211 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
36212 + * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
36213 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36214 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
36215 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
36216 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36217 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36218 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36220 + * This FIQ implements functionality that performs split transactions on
36221 + * the dwc_otg hardware without any outside intervention. A split transaction
36222 + * is "queued" by nominating a specific host channel to perform the entirety
36223 + * of a split transaction. This FIQ will then perform the microframe-precise
36224 + * scheduling required in each phase of the transaction until completion.
36226 + * The FIQ functionality has been surgically implanted into the Synopsys
36227 + * vendor-provided driver.
36231 +#ifndef DWC_OTG_FIQ_FSM_H_
36232 +#define DWC_OTG_FIQ_FSM_H_
36234 +#include "dwc_otg_regs.h"
36235 +#include "dwc_otg_cil.h"
36236 +#include "dwc_otg_hcd.h"
36237 +#include <linux/kernel.h>
36238 +#include <linux/irqflags.h>
36239 +#include <linux/string.h>
36240 +#include <asm/barrier.h>
36243 +#define FLAME_ON(x) \
36247 + gpioreg = readl(__io_address(0x20200000+0x8)); \
36248 + gpioreg &= ~(7 << (x-20)*3); \
36249 + gpioreg |= 0x1 << (x-20)*3; \
36250 + writel(gpioreg, __io_address(0x20200000+0x8)); \
36252 + writel(1<<x, __io_address(0x20200000+(0x1C))); \
36255 +#define FLAME_OFF(x) \
36257 + writel(1<<x, __io_address(0x20200000+(0x28))); \
36260 +#define FLAME_ON(x) do { } while (0)
36261 +#define FLAME_OFF(X) do { } while (0)
36264 +/* This is a quick-and-dirty arch-specific register read/write. We know that
36265 + * writes to a peripheral on BCM2835 will always arrive in-order, also that
36266 + * reads and writes are executed in-order therefore the need for memory barriers
36267 + * is obviated if we're only talking to USB.
36269 +#define FIQ_WRITE(_addr_,_data_) (*(volatile unsigned int *) (_addr_) = (_data_))
36270 +#define FIQ_READ(_addr_) (*(volatile unsigned int *) (_addr_))
36272 +/* FIQ-ified register definitions. Offsets are from dwc_regs_base. */
36273 +#define GINTSTS 0x014
36274 +#define GINTMSK 0x018
36275 +/* Debug register. Poll the top of the received packets FIFO. */
36276 +#define GRXSTSR 0x01C
36277 +#define HFNUM 0x408
36278 +#define HAINT 0x414
36279 +#define HAINTMSK 0x418
36280 +#define HPRT0 0x440
36282 +/* HC_regs start from an offset of 0x500 */
36283 +#define HC_START 0x500
36284 +#define HC_OFFSET 0x020
36286 +#define HC_DMA 0x14
36288 +#define HCCHAR 0x00
36289 +#define HCSPLT 0x04
36290 +#define HCINT 0x08
36291 +#define HCINTMSK 0x0C
36292 +#define HCTSIZ 0x10
36294 +#define ISOC_XACTPOS_ALL 0b11
36295 +#define ISOC_XACTPOS_BEGIN 0b10
36296 +#define ISOC_XACTPOS_MID 0b00
36297 +#define ISOC_XACTPOS_END 0b01
36299 +#define DWC_PID_DATA2 0b01
36300 +#define DWC_PID_MDATA 0b11
36301 +#define DWC_PID_DATA1 0b10
36302 +#define DWC_PID_DATA0 0b00
36305 + volatile void* base;
36306 + volatile void* ctrl;
36307 + volatile void* outdda;
36308 + volatile void* outddb;
36309 + volatile void* intstat;
36310 + volatile void* swirq_set;
36311 + volatile void* swirq_clr;
36314 +enum fiq_debug_level {
36315 + FIQDBG_SCHED = (1 << 0),
36316 + FIQDBG_INT = (1 << 1),
36317 + FIQDBG_ERR = (1 << 2),
36318 + FIQDBG_PORTHUB = (1 << 3),
36321 +#ifdef CONFIG_ARM64
36323 +typedef spinlock_t fiq_lock_t;
36330 + struct _tickets {
36341 +extern void _fiq_print (enum fiq_debug_level dbg_lvl, volatile struct fiq_state *state, char *fmt, ...);
36343 +#define fiq_print _fiq_print
36345 +#define fiq_print(x, y, ...)
36348 +extern bool fiq_enable, fiq_fsm_enable;
36349 +extern ushort nak_holdoff;
36352 + * enum fiq_fsm_state - The FIQ FSM states.
36354 + * This is the "core" of the FIQ FSM. Broadly, the FSM states follow the
36355 + * USB2.0 specification for host responses to various transaction states.
36356 + * There are modifications to this host state machine because of a variety of
36357 + * quirks and limitations in the dwc_otg hardware.
36359 + * The fsm state is also used to communicate back to the driver on completion of
36360 + * a split transaction. The end states are used in conjunction with the interrupts
36361 + * raised by the final transaction.
36363 +enum fiq_fsm_state {
36364 + /* FIQ isn't enabled for this host channel */
36365 + FIQ_PASSTHROUGH = 0,
36366 + /* For the first interrupt received for this channel,
36367 + * the FIQ has to ack any interrupts indicating success. */
36368 + FIQ_PASSTHROUGH_ERRORSTATE = 31,
36369 + /* Nonperiodic state groups */
36370 + FIQ_NP_SSPLIT_STARTED = 1,
36371 + FIQ_NP_SSPLIT_RETRY = 2,
36372 + /* TT contention - working around hub bugs */
36373 + FIQ_NP_SSPLIT_PENDING = 33,
36374 + FIQ_NP_OUT_CSPLIT_RETRY = 3,
36375 + FIQ_NP_IN_CSPLIT_RETRY = 4,
36376 + FIQ_NP_SPLIT_DONE = 5,
36377 + FIQ_NP_SPLIT_LS_ABORTED = 6,
36378 + /* This differentiates a HS transaction error from a LS one
36379 + * (handling the hub state is different) */
36380 + FIQ_NP_SPLIT_HS_ABORTED = 7,
36382 + /* Periodic state groups */
36383 + /* Periodic transactions are either started directly by the IRQ handler
36384 + * or deferred if the TT is already in use.
36386 + FIQ_PER_SSPLIT_QUEUED = 8,
36387 + FIQ_PER_SSPLIT_STARTED = 9,
36388 + FIQ_PER_SSPLIT_LAST = 10,
36391 + FIQ_PER_ISO_OUT_PENDING = 11,
36392 + FIQ_PER_ISO_OUT_ACTIVE = 12,
36393 + FIQ_PER_ISO_OUT_LAST = 13,
36394 + FIQ_PER_ISO_OUT_DONE = 27,
36396 + FIQ_PER_CSPLIT_WAIT = 14,
36397 + FIQ_PER_CSPLIT_NYET1 = 15,
36398 + FIQ_PER_CSPLIT_BROKEN_NYET1 = 28,
36399 + FIQ_PER_CSPLIT_NYET_FAFF = 29,
36400 + /* For multiple CSPLITs (large isoc IN, or delayed interrupt) */
36401 + FIQ_PER_CSPLIT_POLL = 16,
36402 + /* The last CSPLIT for a transaction has been issued, differentiates
36403 + * for the state machine to queue the next packet.
36405 + FIQ_PER_CSPLIT_LAST = 17,
36407 + FIQ_PER_SPLIT_DONE = 18,
36408 + FIQ_PER_SPLIT_LS_ABORTED = 19,
36409 + FIQ_PER_SPLIT_HS_ABORTED = 20,
36410 + FIQ_PER_SPLIT_NYET_ABORTED = 21,
36411 + /* Frame rollover has occurred without the transaction finishing. */
36412 + FIQ_PER_SPLIT_TIMEOUT = 22,
36414 + /* FIQ-accelerated HS Isochronous state groups */
36415 + FIQ_HS_ISOC_TURBO = 23,
36416 + /* For interval > 1, SOF wakes up the isochronous FSM */
36417 + FIQ_HS_ISOC_SLEEPING = 24,
36418 + FIQ_HS_ISOC_DONE = 25,
36419 + FIQ_HS_ISOC_ABORTED = 26,
36420 + FIQ_DEQUEUE_ISSUED = 30,
36424 +struct fiq_stack {
36426 + uint8_t stack[2048];
36432 + * struct fiq_dma_info - DMA bounce buffer utilisation information (per-channel)
36433 + * @index: Number of slots reported used for IN transactions / number of slots
36434 + * transmitted for an OUT transaction
36435 + * @slot_len[6]: Number of actual transfer bytes in each slot (255 if unused)
36437 + * Split transaction transfers can have variable length depending on other bus
36438 + * traffic. The OTG core DMA engine requires 4-byte aligned addresses therefore
36439 + * each transaction needs a guaranteed aligned address. A maximum of 6 split transfers
36440 + * can happen per-frame.
36442 +struct fiq_dma_info {
36447 +struct __attribute__((packed)) fiq_split_dma_slot {
36451 +struct fiq_dma_channel {
36452 + struct __attribute__((packed)) fiq_split_dma_slot index[6];
36455 +struct fiq_dma_blob {
36456 + struct __attribute__((packed)) fiq_dma_channel channel[0];
36460 + * struct fiq_hs_isoc_info - USB2.0 isochronous data
36461 + * @iso_frame: Pointer to the array of OTG URB iso_frame_descs.
36462 + * @nrframes: Total length of iso_frame_desc array
36463 + * @index: Current index (FIQ-maintained)
36464 + * @stride: Interval in uframes between HS isoc transactions
36466 +struct fiq_hs_isoc_info {
36467 + struct dwc_otg_hcd_iso_packet_desc *iso_desc;
36468 + unsigned int nrframes;
36469 + unsigned int index;
36470 + unsigned int stride;
36474 + * struct fiq_channel_state - FIQ state machine storage
36475 + * @fsm: Current state of the channel as understood by the FIQ
36476 + * @nr_errors: Number of transaction errors on this split-transaction
36477 + * @hub_addr: SSPLIT/CSPLIT destination hub
36478 + * @port_addr: SSPLIT/CSPLIT destination port - always 1 if single TT hub
36479 + * @nrpackets: For isoc OUT, the number of split-OUT packets to transmit. For
36480 + * split-IN, number of CSPLIT data packets that were received.
36483 + * @hcintmsk_copy:
36484 + * @hctsiz_copy: Copies of the host channel registers.
36485 + * For use as scratch, or for returning state.
36487 + * The fiq_channel_state is state storage between interrupts for a host channel. The
36488 + * FSM state is stored here. Members of this structure must only be set up by the
36489 + * driver prior to enabling the FIQ for this host channel, and not touched until the FIQ
36490 + * has updated the state to either a COMPLETE state group or ABORT state group.
36493 +struct fiq_channel_state {
36494 + enum fiq_fsm_state fsm;
36495 + unsigned int nr_errors;
36496 + unsigned int hub_addr;
36497 + unsigned int port_addr;
36498 + /* Hardware bug workaround: sometimes channel halt interrupts are
36499 + * delayed until the next SOF. Keep track of when we expected to get interrupted. */
36500 + unsigned int expected_uframe;
36501 + /* number of uframes remaining (for interval > 1 HS isoc transfers) before next transfer */
36502 + unsigned int uframe_sleeps;
36503 + /* in/out for communicating number of dma buffers used, or number of ISOC to do */
36504 + unsigned int nrpackets;
36505 + struct fiq_dma_info dma_info;
36506 + struct fiq_hs_isoc_info hs_isoc_info;
36507 + /* Copies of HC registers - in/out communication from/to IRQ handler
36508 + * and for ease of channel setup. A bit of mungeing is performed - for
36509 + * example the hctsiz.b.maxp is _always_ the max packet size of the endpoint.
36511 + hcchar_data_t hcchar_copy;
36512 + hcsplt_data_t hcsplt_copy;
36513 + hcint_data_t hcint_copy;
36514 + hcintmsk_data_t hcintmsk_copy;
36515 + hctsiz_data_t hctsiz_copy;
36516 + hcdma_data_t hcdma_copy;
36520 + * struct fiq_state - top-level FIQ state machine storage
36521 + * @mphi_regs: virtual address of the MPHI peripheral register file
36522 + * @dwc_regs_base: virtual address of the base of the DWC core register file
36523 + * @dma_base: physical address for the base of the DMA bounce buffers
36524 + * @dummy_send: Scratch area for sending a fake message to the MPHI peripheral
36525 + * @gintmsk_saved: Top-level mask of interrupts that the FIQ has not handled.
36526 + * Used for determining which interrupts fired to set off the IRQ handler.
36527 + * @haintmsk_saved: Mask of interrupts from host channels that the FIQ did not handle internally.
36528 + * @np_count: Non-periodic transactions in the active queue
36529 + * @np_sent: Count of non-periodic transactions that have completed
36530 + * @next_sched_frame: For periodic transactions handled by the driver's SOF-driven queuing mechanism,
36531 + * this is the next frame on which a SOF interrupt is required. Used to hold off
36532 + * passing SOF through to the driver until necessary.
36533 + * @channel[n]: Per-channel FIQ state. Allocated during init depending on the number of host
36534 + * channels configured into the core logic.
36536 + * This is passed as the first argument to the dwc_otg_fiq_fsm top-level FIQ handler from the asm stub.
36537 + * It contains top-level state information.
36539 +struct fiq_state {
36541 + mphi_regs_t mphi_regs;
36542 + void *dwc_regs_base;
36543 + dma_addr_t dma_base;
36544 + struct fiq_dma_blob *fiq_dmab;
36545 + void *dummy_send;
36546 + dma_addr_t dummy_send_dma;
36547 + gintmsk_data_t gintmsk_saved;
36548 + haintmsk_data_t haintmsk_saved;
36549 + int mphi_int_count;
36550 + unsigned int fiq_done;
36551 + unsigned int kick_np_queues;
36552 + unsigned int next_sched_frame;
36555 + unsigned int bufsiz;
36557 + struct fiq_channel_state channel[0];
36560 +#ifdef CONFIG_ARM64
36562 +#ifdef local_fiq_enable
36563 +#undef local_fiq_enable
36566 +#ifdef local_fiq_disable
36567 +#undef local_fiq_disable
36570 +extern void local_fiq_enable(void);
36572 +extern void local_fiq_disable(void);
36576 +extern void fiq_fsm_spin_lock(fiq_lock_t *lock);
36578 +extern void fiq_fsm_spin_unlock(fiq_lock_t *lock);
36580 +extern int fiq_fsm_too_late(struct fiq_state *st, int n);
36582 +extern int fiq_fsm_tt_in_use(struct fiq_state *st, int num_channels, int n);
36584 +extern void dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels);
36586 +extern void dwc_otg_fiq_nop(struct fiq_state *state);
36588 +#endif /* DWC_OTG_FIQ_FSM_H_ */
36590 +++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S
36593 + * dwc_otg_fiq_fsm.S - assembly stub for the FSM FIQ
36595 + * Copyright (c) 2013 Raspberry Pi Foundation
36597 + * Author: Jonathan Bell <jonathan@raspberrypi.org>
36598 + * All rights reserved.
36600 + * Redistribution and use in source and binary forms, with or without
36601 + * modification, are permitted provided that the following conditions are met:
36602 + * * Redistributions of source code must retain the above copyright
36603 + * notice, this list of conditions and the following disclaimer.
36604 + * * Redistributions in binary form must reproduce the above copyright
36605 + * notice, this list of conditions and the following disclaimer in the
36606 + * documentation and/or other materials provided with the distribution.
36607 + * * Neither the name of Raspberry Pi nor the
36608 + * names of its contributors may be used to endorse or promote products
36609 + * derived from this software without specific prior written permission.
36611 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
36612 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
36613 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
36614 + * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
36615 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36616 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
36617 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
36618 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36619 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36620 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36624 +#include <asm/assembler.h>
36625 +#include <linux/linkage.h>
36630 +.global _dwc_otg_fiq_stub_end;
36633 + * _dwc_otg_fiq_stub() - entry copied to the FIQ vector page to allow
36634 + * a C-style function call with arguments from the FIQ banked registers.
36635 + * r0 = &hcd->fiq_state
36636 + * r1 = &hcd->num_channels
36637 + * r2 = &hcd->dma_buffers
36638 + * Tramples: r0, r1, r2, r4, fp, ip
36641 +ENTRY(_dwc_otg_fiq_stub)
36642 + /* Stash unbanked regs - SP will have been set up for us */
36644 + stmdb sp!, {r0-r12, lr};
36646 + // Cycle profiling - read cycle counter at start
36647 + mrc p15, 0, r5, c15, c12, 1;
36649 + /* r11 = fp, don't trample it */
36651 + /* set EABI frame size */
36652 + sub fp, ip, #512;
36654 + /* for fiq NOP mode - just need state */
36656 + /* r9 = num_channels */
36658 + /* r10 = struct *dma_bufs */
36661 + /* r4 = &fiq_c_function */
36664 + mrc p15, 0, r4, c15, c12, 1;
36666 + // r5 is now the cycle count time for executing the FIQ. Store it somewhere?
36668 + ldmia sp!, {r0-r12, lr};
36670 +_dwc_otg_fiq_stub_end:
36671 +END(_dwc_otg_fiq_stub)
36673 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c
36676 +/* ==========================================================================
36677 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
36678 + * $Revision: #104 $
36679 + * $Date: 2011/10/24 $
36680 + * $Change: 1871159 $
36682 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
36683 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
36684 + * otherwise expressly agreed to in writing between Synopsys and you.
36686 + * The Software IS NOT an item of Licensed Software or Licensed Product under
36687 + * any End User Software License Agreement or Agreement for Licensed Product
36688 + * with Synopsys or any supplement thereto. You are permitted to use and
36689 + * redistribute this Software in source and binary forms, with or without
36690 + * modification, provided that redistributions of source code must retain this
36691 + * notice. You may not view, use, disclose, copy or distribute this file or
36692 + * any information contained herein except pursuant to this license grant from
36693 + * Synopsys. If you do not agree with this notice, including the disclaimer
36694 + * below, then you are not authorized to use the Software.
36696 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
36697 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
36698 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36699 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
36700 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36701 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36702 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
36703 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36704 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36705 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
36707 + * ========================================================================== */
36708 +#ifndef DWC_DEVICE_ONLY
36711 + * This file implements HCD Core. All code in this file is portable and doesn't
36712 + * use any OS specific functions.
36713 + * Interface provided by HCD Core is defined in <code><hcd_if.h></code>
36717 +#include <linux/usb.h>
36718 +#include <linux/usb/hcd.h>
36720 +#include "dwc_otg_hcd.h"
36721 +#include "dwc_otg_regs.h"
36722 +#include "dwc_otg_fiq_fsm.h"
36724 +extern bool microframe_schedule;
36725 +extern uint16_t fiq_fsm_mask, nak_holdoff;
36727 +//#define DEBUG_HOST_CHANNELS
36728 +#ifdef DEBUG_HOST_CHANNELS
36729 +static int last_sel_trans_num_per_scheduled = 0;
36730 +static int last_sel_trans_num_nonper_scheduled = 0;
36731 +static int last_sel_trans_num_avail_hc_at_start = 0;
36732 +static int last_sel_trans_num_avail_hc_at_end = 0;
36733 +#endif /* DEBUG_HOST_CHANNELS */
36736 +dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void)
36738 + return DWC_ALLOC(sizeof(dwc_otg_hcd_t));
36742 + * Connection timeout function. An OTG host is required to display a
36743 + * message if the device does not connect within 10 seconds.
36745 +void dwc_otg_hcd_connect_timeout(void *ptr)
36747 + DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, ptr);
36748 + DWC_PRINTF("Connect Timeout\n");
36749 + __DWC_ERROR("Device Not Connected/Responding\n");
36752 +#if defined(DEBUG)
36753 +static void dump_channel_info(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
36755 + if (qh->channel != NULL) {
36756 + dwc_hc_t *hc = qh->channel;
36757 + dwc_list_link_t *item;
36758 + dwc_otg_qh_t *qh_item;
36759 + int num_channels = hcd->core_if->core_params->host_channels;
36762 + dwc_otg_hc_regs_t *hc_regs;
36763 + hcchar_data_t hcchar;
36764 + hcsplt_data_t hcsplt;
36765 + hctsiz_data_t hctsiz;
36768 + hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
36769 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
36770 + hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
36771 + hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
36772 + hcdma = DWC_READ_REG32(&hc_regs->hcdma);
36774 + DWC_PRINTF(" Assigned to channel %p:\n", hc);
36775 + DWC_PRINTF(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32,
36777 + DWC_PRINTF(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32,
36779 + DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
36780 + hc->dev_addr, hc->ep_num, hc->ep_is_in);
36781 + DWC_PRINTF(" ep_type: %d\n", hc->ep_type);
36782 + DWC_PRINTF(" max_packet: %d\n", hc->max_packet);
36783 + DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start);
36784 + DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started);
36785 + DWC_PRINTF(" halt_status: %d\n", hc->halt_status);
36786 + DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff);
36787 + DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len);
36788 + DWC_PRINTF(" qh: %p\n", hc->qh);
36789 + DWC_PRINTF(" NP inactive sched:\n");
36790 + DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) {
36792 + DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
36793 + DWC_PRINTF(" %p\n", qh_item);
36795 + DWC_PRINTF(" NP active sched:\n");
36796 + DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) {
36798 + DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
36799 + DWC_PRINTF(" %p\n", qh_item);
36801 + DWC_PRINTF(" Channels: \n");
36802 + for (i = 0; i < num_channels; i++) {
36803 + dwc_hc_t *hc = hcd->hc_ptr_array[i];
36804 + DWC_PRINTF(" %2d: %p\n", i, hc);
36809 +#define dump_channel_info(hcd, qh)
36810 +#endif /* DEBUG */
36813 + * Work queue function for starting the HCD when A-Cable is connected.
36814 + * The hcd_start() must be called in a process context.
36816 +static void hcd_start_func(void *_vp)
36818 + dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp;
36820 + DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, hcd);
36822 + hcd->fops->start(hcd);
36826 +static void del_xfer_timers(dwc_otg_hcd_t * hcd)
36830 + int num_channels = hcd->core_if->core_params->host_channels;
36831 + for (i = 0; i < num_channels; i++) {
36832 + DWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]);
36837 +static void del_timers(dwc_otg_hcd_t * hcd)
36839 + del_xfer_timers(hcd);
36840 + DWC_TIMER_CANCEL(hcd->conn_timer);
36844 + * Processes all the URBs in a single list of QHs. Completes them with
36845 + * -ESHUTDOWN and frees the QTD.
36847 +static void kill_urbs_in_qh_list(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
36849 + dwc_list_link_t *qh_item, *qh_tmp;
36850 + dwc_otg_qh_t *qh;
36851 + dwc_otg_qtd_t *qtd, *qtd_tmp;
36853 + DWC_LIST_FOREACH_SAFE(qh_item, qh_tmp, qh_list) {
36854 + qh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry);
36855 + DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp,
36856 + &qh->qtd_list, qtd_list_entry) {
36857 + qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
36858 + if (qtd->urb != NULL) {
36859 + hcd->fops->complete(hcd, qtd->urb->priv,
36860 + qtd->urb, -DWC_E_SHUTDOWN);
36861 + dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
36865 + if(qh->channel) {
36866 + int n = qh->channel->hc_num;
36867 + /* Using hcchar.chen == 1 is not a reliable test.
36868 + * It is possible that the channel has already halted
36869 + * but not yet been through the IRQ handler.
36871 + if (fiq_fsm_enable && (hcd->fiq_state->channel[qh->channel->hc_num].fsm != FIQ_PASSTHROUGH)) {
36872 + qh->channel->halt_status = DWC_OTG_HC_XFER_URB_DEQUEUE;
36873 + qh->channel->halt_pending = 1;
36874 + if (hcd->fiq_state->channel[n].fsm == FIQ_HS_ISOC_TURBO ||
36875 + hcd->fiq_state->channel[n].fsm == FIQ_HS_ISOC_SLEEPING)
36876 + hcd->fiq_state->channel[n].fsm = FIQ_HS_ISOC_ABORTED;
36878 + dwc_otg_hc_halt(hcd->core_if, qh->channel,
36879 + DWC_OTG_HC_XFER_URB_DEQUEUE);
36881 + qh->channel = NULL;
36883 + dwc_otg_hcd_qh_remove(hcd, qh);
36888 + * Responds with an error status of ESHUTDOWN to all URBs in the non-periodic
36889 + * and periodic schedules. The QTD associated with each URB is removed from
36890 + * the schedule and freed. This function may be called when a disconnect is
36891 + * detected or when the HCD is being stopped.
36893 +static void kill_all_urbs(dwc_otg_hcd_t * hcd)
36895 + kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
36896 + kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
36897 + kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
36898 + kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
36899 + kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
36900 + kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
36904 + * Start the connection timer. An OTG host is required to display a
36905 + * message if the device does not connect within 10 seconds. The
36906 + * timer is deleted if a port connect interrupt occurs before the
36909 +static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t * hcd)
36911 + DWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */ );
36915 + * HCD Callback function for disconnect of the HCD.
36917 + * @param p void pointer to the <code>struct usb_hcd</code>
36919 +static int32_t dwc_otg_hcd_session_start_cb(void *p)
36921 + dwc_otg_hcd_t *dwc_otg_hcd;
36922 + DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
36924 + dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
36929 + * HCD Callback function for starting the HCD when A-Cable is
36932 + * @param p void pointer to the <code>struct usb_hcd</code>
36934 +static int32_t dwc_otg_hcd_start_cb(void *p)
36936 + dwc_otg_hcd_t *dwc_otg_hcd = p;
36937 + dwc_otg_core_if_t *core_if;
36938 + hprt0_data_t hprt0;
36940 + core_if = dwc_otg_hcd->core_if;
36942 + if (core_if->op_state == B_HOST) {
36944 + * Reset the port. During a HNP mode switch the reset
36945 + * needs to occur within 1ms and have a duration of at
36948 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
36949 + hprt0.b.prtrst = 1;
36950 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
36952 + DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg,
36953 + hcd_start_func, dwc_otg_hcd, 50,
36960 + * HCD Callback function for disconnect of the HCD.
36962 + * @param p void pointer to the <code>struct usb_hcd</code>
36964 +static int32_t dwc_otg_hcd_disconnect_cb(void *p)
36966 + gintsts_data_t intr;
36967 + dwc_otg_hcd_t *dwc_otg_hcd = p;
36969 + DWC_SPINLOCK(dwc_otg_hcd->lock);
36971 + * Set status flags for the hub driver.
36973 + dwc_otg_hcd->flags.b.port_connect_status_change = 1;
36974 + dwc_otg_hcd->flags.b.port_connect_status = 0;
36976 + local_fiq_disable();
36977 + fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);
36980 + * Shutdown any transfers in process by clearing the Tx FIFO Empty
36981 + * interrupt mask and status bits and disabling subsequent host
36982 + * channel interrupts.
36985 + intr.b.nptxfempty = 1;
36986 + intr.b.ptxfempty = 1;
36987 + intr.b.hcintr = 1;
36988 + DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk,
36990 + DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintsts,
36993 + del_timers(dwc_otg_hcd);
36996 + * Turn off the vbus power only if the core has transitioned to device
36997 + * mode. If still in host mode, need to keep power on to detect a
37000 + if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
37001 + if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
37002 + hprt0_data_t hprt0 = {.d32 = 0 };
37003 + DWC_PRINTF("Disconnect: PortPower off\n");
37004 + hprt0.b.prtpwr = 0;
37005 + DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0,
37009 + dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
37012 + /* Respond with an error status to all URBs in the schedule. */
37013 + kill_all_urbs(dwc_otg_hcd);
37015 + if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
37016 + /* Clean up any host channels that were in use. */
37017 + int num_channels;
37019 + dwc_hc_t *channel;
37020 + dwc_otg_hc_regs_t *hc_regs;
37021 + hcchar_data_t hcchar;
37023 + num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
37025 + if (!dwc_otg_hcd->core_if->dma_enable) {
37026 + /* Flush out any channel requests in slave mode. */
37027 + for (i = 0; i < num_channels; i++) {
37028 + channel = dwc_otg_hcd->hc_ptr_array[i];
37029 + if (DWC_CIRCLEQ_EMPTY_ENTRY
37030 + (channel, hc_list_entry)) {
37032 + dwc_otg_hcd->core_if->
37033 + host_if->hc_regs[i];
37035 + DWC_READ_REG32(&hc_regs->hcchar);
37036 + if (hcchar.b.chen) {
37037 + hcchar.b.chen = 0;
37038 + hcchar.b.chdis = 1;
37039 + hcchar.b.epdir = 0;
37041 + (&hc_regs->hcchar,
37048 + if(fiq_fsm_enable) {
37049 + for(i=0; i < 128; i++) {
37050 + dwc_otg_hcd->hub_port[i] = 0;
37056 + fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);
37057 + local_fiq_enable();
37060 + if (dwc_otg_hcd->fops->disconnect) {
37061 + dwc_otg_hcd->fops->disconnect(dwc_otg_hcd);
37064 + DWC_SPINUNLOCK(dwc_otg_hcd->lock);
37069 + * HCD Callback function for stopping the HCD.
37071 + * @param p void pointer to the <code>struct usb_hcd</code>
37073 +static int32_t dwc_otg_hcd_stop_cb(void *p)
37075 + dwc_otg_hcd_t *dwc_otg_hcd = p;
37077 + DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
37078 + dwc_otg_hcd_stop(dwc_otg_hcd);
37082 +#ifdef CONFIG_USB_DWC_OTG_LPM
37084 + * HCD Callback function for sleep of HCD.
37086 + * @param p void pointer to the <code>struct usb_hcd</code>
37088 +static int dwc_otg_hcd_sleep_cb(void *p)
37090 + dwc_otg_hcd_t *hcd = p;
37092 + dwc_otg_hcd_free_hc_from_lpm(hcd);
37100 + * HCD Callback function for Remote Wakeup.
37102 + * @param p void pointer to the <code>struct usb_hcd</code>
37104 +static int dwc_otg_hcd_rem_wakeup_cb(void *p)
37106 + dwc_otg_hcd_t *hcd = p;
37108 + if (hcd->core_if->lx_state == DWC_OTG_L2) {
37109 + hcd->flags.b.port_suspend_change = 1;
37111 +#ifdef CONFIG_USB_DWC_OTG_LPM
37113 + hcd->flags.b.port_l1_change = 1;
37120 + * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
37123 +void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd)
37125 + hprt0_data_t hprt0 = {.d32 = 0 };
37127 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
37130 + * The root hub should be disconnected before this function is called.
37131 + * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
37132 + * and the QH lists (via ..._hcd_endpoint_disable).
37135 + /* Turn off all host-specific interrupts. */
37136 + dwc_otg_disable_host_interrupts(hcd->core_if);
37138 + /* Turn off the vbus power */
37139 + DWC_PRINTF("PortPower off\n");
37140 + hprt0.b.prtpwr = 0;
37141 + DWC_WRITE_REG32(hcd->core_if->host_if->hprt0, hprt0.d32);
37145 +int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * hcd,
37146 + dwc_otg_hcd_urb_t * dwc_otg_urb, void **ep_handle,
37147 + int atomic_alloc)
37150 + uint8_t needs_scheduling = 0;
37151 + dwc_otg_transaction_type_e tr_type;
37152 + dwc_otg_qtd_t *qtd;
37153 + gintmsk_data_t intr_mask = {.d32 = 0 };
37154 + hprt0_data_t hprt0 = { .d32 = 0 };
37156 +#ifdef DEBUG /* integrity checks (Broadcom) */
37157 + if (NULL == hcd->core_if) {
37158 + DWC_ERROR("**** DWC OTG HCD URB Enqueue - HCD has NULL core_if\n");
37159 + /* No longer connected. */
37160 + return -DWC_E_INVALID;
37163 + if (!hcd->flags.b.port_connect_status) {
37164 + /* No longer connected. */
37165 + DWC_ERROR("Not connected\n");
37166 + return -DWC_E_NO_DEVICE;
37169 + /* Some core configurations cannot support LS traffic on a FS root port */
37170 + if ((hcd->fops->speed(hcd, dwc_otg_urb->priv) == USB_SPEED_LOW) &&
37171 + (hcd->core_if->hwcfg2.b.fs_phy_type == 1) &&
37172 + (hcd->core_if->hwcfg2.b.hs_phy_type == 1)) {
37173 + hprt0.d32 = DWC_READ_REG32(hcd->core_if->host_if->hprt0);
37174 + if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_FULL_SPEED) {
37175 + return -DWC_E_NO_DEVICE;
37179 + qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb, atomic_alloc);
37180 + if (qtd == NULL) {
37181 + DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
37182 + return -DWC_E_NO_MEMORY;
37184 +#ifdef DEBUG /* integrity checks (Broadcom) */
37185 + if (qtd->urb == NULL) {
37186 + DWC_ERROR("**** DWC OTG HCD URB Enqueue created QTD with no URBs\n");
37187 + return -DWC_E_NO_MEMORY;
37189 + if (qtd->urb->priv == NULL) {
37190 + DWC_ERROR("**** DWC OTG HCD URB Enqueue created QTD URB with no URB handle\n");
37191 + return -DWC_E_NO_MEMORY;
37194 + intr_mask.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->gintmsk);
37195 + if(!intr_mask.b.sofintr || fiq_enable) needs_scheduling = 1;
37196 + if((((dwc_otg_qh_t *)ep_handle)->ep_type == UE_BULK) && !(qtd->urb->flags & URB_GIVEBACK_ASAP))
37197 + /* Do not schedule SG transactions until qtd has URB_GIVEBACK_ASAP set */
37198 + needs_scheduling = 0;
37200 + retval = dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle, atomic_alloc);
37201 + // creates a new queue in ep_handle if it doesn't exist already
37202 + if (retval < 0) {
37203 + DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
37204 + "Error status %d\n", retval);
37205 + dwc_otg_hcd_qtd_free(qtd);
37209 + if(needs_scheduling) {
37210 + tr_type = dwc_otg_hcd_select_transactions(hcd);
37211 + if (tr_type != DWC_OTG_TRANSACTION_NONE) {
37212 + dwc_otg_hcd_queue_transactions(hcd, tr_type);
37218 +int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * hcd,
37219 + dwc_otg_hcd_urb_t * dwc_otg_urb)
37221 + dwc_otg_qh_t *qh;
37222 + dwc_otg_qtd_t *urb_qtd;
37224 + BUG_ON(!dwc_otg_urb);
37226 +#ifdef DEBUG /* integrity checks (Broadcom) */
37228 + if (hcd == NULL) {
37229 + DWC_ERROR("**** DWC OTG HCD URB Dequeue has NULL HCD\n");
37230 + return -DWC_E_INVALID;
37232 + if (dwc_otg_urb == NULL) {
37233 + DWC_ERROR("**** DWC OTG HCD URB Dequeue has NULL URB\n");
37234 + return -DWC_E_INVALID;
37236 + if (dwc_otg_urb->qtd == NULL) {
37237 + DWC_ERROR("**** DWC OTG HCD URB Dequeue with NULL QTD\n");
37238 + return -DWC_E_INVALID;
37240 + urb_qtd = dwc_otg_urb->qtd;
37241 + BUG_ON(!urb_qtd);
37242 + if (urb_qtd->qh == NULL) {
37243 + DWC_ERROR("**** DWC OTG HCD URB Dequeue with QTD with NULL Q handler\n");
37244 + return -DWC_E_INVALID;
37247 + urb_qtd = dwc_otg_urb->qtd;
37248 + BUG_ON(!urb_qtd);
37250 + qh = urb_qtd->qh;
37252 + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
37253 + if (urb_qtd->in_process) {
37254 + dump_channel_info(hcd, qh);
37257 +#ifdef DEBUG /* integrity checks (Broadcom) */
37258 + if (hcd->core_if == NULL) {
37259 + DWC_ERROR("**** DWC OTG HCD URB Dequeue HCD has NULL core_if\n");
37260 + return -DWC_E_INVALID;
37263 + if (urb_qtd->in_process && qh->channel) {
37264 + /* The QTD is in process (it has been assigned to a channel). */
37265 + if (hcd->flags.b.port_connect_status) {
37266 + int n = qh->channel->hc_num;
37268 + * If still connected (i.e. in host mode), halt the
37269 + * channel so it can be used for other transfers. If
37270 + * no longer connected, the host registers can't be
37271 + * written to halt the channel since the core is in
37274 + /* In FIQ FSM mode, we need to shut down carefully.
37275 + * The FIQ may attempt to restart a disabled channel */
37276 + if (fiq_fsm_enable && (hcd->fiq_state->channel[n].fsm != FIQ_PASSTHROUGH)) {
37277 + local_fiq_disable();
37278 + fiq_fsm_spin_lock(&hcd->fiq_state->lock);
37279 + qh->channel->halt_status = DWC_OTG_HC_XFER_URB_DEQUEUE;
37280 + qh->channel->halt_pending = 1;
37281 + if (hcd->fiq_state->channel[n].fsm == FIQ_HS_ISOC_TURBO ||
37282 + hcd->fiq_state->channel[n].fsm == FIQ_HS_ISOC_SLEEPING)
37283 + hcd->fiq_state->channel[n].fsm = FIQ_HS_ISOC_ABORTED;
37284 + fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
37285 + local_fiq_enable();
37287 + dwc_otg_hc_halt(hcd->core_if, qh->channel,
37288 + DWC_OTG_HC_XFER_URB_DEQUEUE);
37294 + * Free the QTD and clean up the associated QH. Leave the QH in the
37295 + * schedule if it has any remaining QTDs.
37298 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue - "
37299 + "delete %sQueue handler\n",
37300 + hcd->core_if->dma_desc_enable?"DMA ":"");
37301 + if (!hcd->core_if->dma_desc_enable) {
37302 + uint8_t b = urb_qtd->in_process;
37303 + if (nak_holdoff && qh->do_split && dwc_qh_is_non_per(qh))
37304 + qh->nak_frame = 0xFFFF;
37305 + dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
37307 + dwc_otg_hcd_qh_deactivate(hcd, qh, 0);
37308 + qh->channel = NULL;
37309 + } else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
37310 + dwc_otg_hcd_qh_remove(hcd, qh);
37313 + dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
37318 +int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
37321 + dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
37323 + dwc_irqflags_t flags;
37326 + retval = -DWC_E_INVALID;
37331 + retval = -DWC_E_INVALID;
37335 + DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
37337 + while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) {
37338 + DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
37341 + DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
37344 + dwc_otg_hcd_qh_remove(hcd, qh);
37346 + DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
37348 + * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove
37349 + * and qh_free to prevent stack dump on DWC_DMA_FREE() with
37350 + * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free()
37351 + * and dwc_otg_hcd_frame_list_alloc().
37353 + dwc_otg_hcd_qh_free(hcd, qh);
37359 +int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle)
37362 + dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
37364 + return -DWC_E_INVALID;
37366 + qh->data_toggle = DWC_OTG_HC_PID_DATA0;
37371 + * HCD Callback structure for handling mode switching.
37373 +static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
37374 + .start = dwc_otg_hcd_start_cb,
37375 + .stop = dwc_otg_hcd_stop_cb,
37376 + .disconnect = dwc_otg_hcd_disconnect_cb,
37377 + .session_start = dwc_otg_hcd_session_start_cb,
37378 + .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,
37379 +#ifdef CONFIG_USB_DWC_OTG_LPM
37380 + .sleep = dwc_otg_hcd_sleep_cb,
37386 + * Reset tasklet function
37388 +static void reset_tasklet_func(void *data)
37390 + dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data;
37391 + dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
37392 + hprt0_data_t hprt0;
37394 + DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
37396 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
37397 + hprt0.b.prtrst = 1;
37398 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
37401 + hprt0.b.prtrst = 0;
37402 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
37403 + dwc_otg_hcd->flags.b.port_reset_change = 1;
37406 +static void completion_tasklet_func(void *ptr)
37408 + dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) ptr;
37410 + urb_tq_entry_t *item;
37411 + dwc_irqflags_t flags;
37413 + /* This could just be spin_lock_irq */
37414 + DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
37415 + while (!DWC_TAILQ_EMPTY(&hcd->completed_urb_list)) {
37416 + item = DWC_TAILQ_FIRST(&hcd->completed_urb_list);
37418 + DWC_TAILQ_REMOVE(&hcd->completed_urb_list, item,
37420 + DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
37423 + usb_hcd_giveback_urb(hcd->priv, urb, urb->status);
37426 + DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
37428 + DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
37432 +static void qh_list_free(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
37434 + dwc_list_link_t *item;
37435 + dwc_otg_qh_t *qh;
37436 + dwc_irqflags_t flags;
37438 + if (!qh_list->next) {
37439 + /* The list hasn't been initialized yet. */
37443 + * Hold spinlock here. Not needed in that case if bellow
37444 + * function is being called from ISR
37446 + DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
37447 + /* Ensure there are no QTDs or URBs left. */
37448 + kill_urbs_in_qh_list(hcd, qh_list);
37449 + DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
37451 + DWC_LIST_FOREACH(item, qh_list) {
37452 + qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
37453 + dwc_otg_hcd_qh_remove_and_free(hcd, qh);
37458 + * Exit from Hibernation if Host did not detect SRP from connected SRP capable
37459 + * Device during SRP time by host power up.
37461 +void dwc_otg_hcd_power_up(void *ptr)
37463 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
37464 + dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
37466 + DWC_PRINTF("%s called\n", __FUNCTION__);
37468 + if (!core_if->hibernation_suspend) {
37469 + DWC_PRINTF("Already exited from Hibernation\n");
37473 + /* Switch on the voltage to the core */
37474 + gpwrdn.b.pwrdnswtch = 1;
37475 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
37478 + /* Reset the core */
37480 + gpwrdn.b.pwrdnrstn = 1;
37481 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
37484 + /* Disable power clamps */
37486 + gpwrdn.b.pwrdnclmp = 1;
37487 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
37489 + /* Remove reset the core signal */
37491 + gpwrdn.b.pwrdnrstn = 1;
37492 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
37495 + /* Disable PMU interrupt */
37497 + gpwrdn.b.pmuintsel = 1;
37498 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
37500 + core_if->hibernation_suspend = 0;
37502 + /* Disable PMU */
37504 + gpwrdn.b.pmuactv = 1;
37505 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
37508 + /* Enable VBUS */
37510 + gpwrdn.b.dis_vbus = 1;
37511 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
37513 + core_if->op_state = A_HOST;
37514 + dwc_otg_core_init(core_if);
37515 + dwc_otg_enable_global_interrupts(core_if);
37516 + cil_hcd_start(core_if);
37519 +void dwc_otg_cleanup_fiq_channel(dwc_otg_hcd_t *hcd, uint32_t num)
37521 + struct fiq_channel_state *st = &hcd->fiq_state->channel[num];
37522 + struct fiq_dma_blob *blob = hcd->fiq_dmab;
37525 + st->fsm = FIQ_PASSTHROUGH;
37526 + st->hcchar_copy.d32 = 0;
37527 + st->hcsplt_copy.d32 = 0;
37528 + st->hcint_copy.d32 = 0;
37529 + st->hcintmsk_copy.d32 = 0;
37530 + st->hctsiz_copy.d32 = 0;
37531 + st->hcdma_copy.d32 = 0;
37532 + st->nr_errors = 0;
37533 + st->hub_addr = 0;
37534 + st->port_addr = 0;
37535 + st->expected_uframe = 0;
37536 + st->nrpackets = 0;
37537 + st->dma_info.index = 0;
37538 + for (i = 0; i < 6; i++)
37539 + st->dma_info.slot_len[i] = 255;
37540 + st->hs_isoc_info.index = 0;
37541 + st->hs_isoc_info.iso_desc = NULL;
37542 + st->hs_isoc_info.nrframes = 0;
37544 + DWC_MEMSET(&blob->channel[num].index[0], 0x6b, 1128);
37548 + * Frees secondary storage associated with the dwc_otg_hcd structure contained
37549 + * in the struct usb_hcd field.
37551 +static void dwc_otg_hcd_free(dwc_otg_hcd_t * dwc_otg_hcd)
37553 + struct device *dev = dwc_otg_hcd_to_dev(dwc_otg_hcd);
37556 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
37558 + del_timers(dwc_otg_hcd);
37560 + /* Free memory for QH/QTD lists */
37561 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
37562 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
37563 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
37564 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
37565 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
37566 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
37568 + /* Free memory for the host channels. */
37569 + for (i = 0; i < MAX_EPS_CHANNELS; i++) {
37570 + dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
37573 + if (dwc_otg_hcd->core_if->hc_xfer_timer[i]) {
37574 + DWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]);
37577 + if (hc != NULL) {
37578 + DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n",
37584 + if (dwc_otg_hcd->core_if->dma_enable) {
37585 + if (dwc_otg_hcd->status_buf_dma) {
37586 + DWC_DMA_FREE(dev, DWC_OTG_HCD_STATUS_BUF_SIZE,
37587 + dwc_otg_hcd->status_buf,
37588 + dwc_otg_hcd->status_buf_dma);
37590 + } else if (dwc_otg_hcd->status_buf != NULL) {
37591 + DWC_FREE(dwc_otg_hcd->status_buf);
37593 + DWC_SPINLOCK_FREE(dwc_otg_hcd->lock);
37594 + /* Set core_if's lock pointer to NULL */
37595 + dwc_otg_hcd->core_if->lock = NULL;
37597 + DWC_TIMER_FREE(dwc_otg_hcd->conn_timer);
37598 + DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet);
37599 + DWC_TASK_FREE(dwc_otg_hcd->completion_tasklet);
37600 + DWC_DMA_FREE(dev, 16, dwc_otg_hcd->fiq_state->dummy_send,
37601 + dwc_otg_hcd->fiq_state->dummy_send_dma);
37602 + DWC_FREE(dwc_otg_hcd->fiq_state);
37604 +#ifdef DWC_DEV_SRPCAP
37605 + if (dwc_otg_hcd->core_if->power_down == 2 &&
37606 + dwc_otg_hcd->core_if->pwron_timer) {
37607 + DWC_TIMER_FREE(dwc_otg_hcd->core_if->pwron_timer);
37610 + DWC_FREE(dwc_otg_hcd);
37613 +int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if)
37615 + struct device *dev = dwc_otg_hcd_to_dev(hcd);
37617 + int num_channels;
37619 + dwc_hc_t *channel;
37621 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK))
37622 + DWC_SPINLOCK_ALLOC_LINUX_DEBUG(hcd->lock);
37624 + hcd->lock = DWC_SPINLOCK_ALLOC();
37626 + DWC_DEBUGPL(DBG_HCDV, "init of HCD %p given core_if %p\n",
37628 + if (!hcd->lock) {
37629 + DWC_ERROR("Could not allocate lock for pcd");
37631 + retval = -DWC_E_NO_MEMORY;
37634 + hcd->core_if = core_if;
37636 + /* Register the HCD CIL Callbacks */
37637 + dwc_otg_cil_register_hcd_callbacks(hcd->core_if,
37638 + &hcd_cil_callbacks, hcd);
37640 + /* Initialize the non-periodic schedule. */
37641 + DWC_LIST_INIT(&hcd->non_periodic_sched_inactive);
37642 + DWC_LIST_INIT(&hcd->non_periodic_sched_active);
37644 + /* Initialize the periodic schedule. */
37645 + DWC_LIST_INIT(&hcd->periodic_sched_inactive);
37646 + DWC_LIST_INIT(&hcd->periodic_sched_ready);
37647 + DWC_LIST_INIT(&hcd->periodic_sched_assigned);
37648 + DWC_LIST_INIT(&hcd->periodic_sched_queued);
37649 + DWC_TAILQ_INIT(&hcd->completed_urb_list);
37651 + * Create a host channel descriptor for each host channel implemented
37652 + * in the controller. Initialize the channel descriptor array.
37654 + DWC_CIRCLEQ_INIT(&hcd->free_hc_list);
37655 + num_channels = hcd->core_if->core_params->host_channels;
37656 + DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array));
37657 + for (i = 0; i < num_channels; i++) {
37658 + channel = DWC_ALLOC(sizeof(dwc_hc_t));
37659 + if (channel == NULL) {
37660 + retval = -DWC_E_NO_MEMORY;
37661 + DWC_ERROR("%s: host channel allocation failed\n",
37663 + dwc_otg_hcd_free(hcd);
37666 + channel->hc_num = i;
37667 + hcd->hc_ptr_array[i] = channel;
37669 + hcd->core_if->hc_xfer_timer[i] =
37670 + DWC_TIMER_ALLOC("hc timer", hc_xfer_timeout,
37671 + &hcd->core_if->hc_xfer_info[i]);
37673 + DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i,
37677 + if (fiq_enable) {
37678 + hcd->fiq_state = DWC_ALLOC(sizeof(struct fiq_state) + (sizeof(struct fiq_channel_state) * num_channels));
37679 + if (!hcd->fiq_state) {
37680 + retval = -DWC_E_NO_MEMORY;
37681 + DWC_ERROR("%s: cannot allocate fiq_state structure\n", __func__);
37682 + dwc_otg_hcd_free(hcd);
37685 + DWC_MEMSET(hcd->fiq_state, 0, (sizeof(struct fiq_state) + (sizeof(struct fiq_channel_state) * num_channels)));
37687 +#ifdef CONFIG_ARM64
37688 + spin_lock_init(&hcd->fiq_state->lock);
37691 + for (i = 0; i < num_channels; i++) {
37692 + hcd->fiq_state->channel[i].fsm = FIQ_PASSTHROUGH;
37694 + hcd->fiq_state->dummy_send = DWC_DMA_ALLOC_ATOMIC(dev, 16,
37695 + &hcd->fiq_state->dummy_send_dma);
37697 + hcd->fiq_stack = DWC_ALLOC(sizeof(struct fiq_stack));
37698 + if (!hcd->fiq_stack) {
37699 + retval = -DWC_E_NO_MEMORY;
37700 + DWC_ERROR("%s: cannot allocate fiq_stack structure\n", __func__);
37701 + dwc_otg_hcd_free(hcd);
37704 + hcd->fiq_stack->magic1 = 0xDEADBEEF;
37705 + hcd->fiq_stack->magic2 = 0xD00DFEED;
37706 + hcd->fiq_state->gintmsk_saved.d32 = ~0;
37707 + hcd->fiq_state->haintmsk_saved.b2.chint = ~0;
37709 + /* This bit is terrible and uses no API, but necessary. The FIQ has no concept of DMA pools
37710 + * (and if it did, would be a lot slower). This allocates a chunk of memory (~9kiB for 8 host channels)
37711 + * for use as transaction bounce buffers in a 2-D array. Our access into this chunk is done by some
37712 + * moderately readable array casts.
37714 + hcd->fiq_dmab = DWC_DMA_ALLOC(dev, (sizeof(struct fiq_dma_channel) * num_channels), &hcd->fiq_state->dma_base);
37715 + DWC_WARN("FIQ DMA bounce buffers: virt = %px dma = %pad len=%zu",
37716 + hcd->fiq_dmab, &hcd->fiq_state->dma_base,
37717 + sizeof(struct fiq_dma_channel) * num_channels);
37719 + DWC_MEMSET(hcd->fiq_dmab, 0x6b, 9024);
37721 + /* pointer for debug in fiq_print */
37722 + hcd->fiq_state->fiq_dmab = hcd->fiq_dmab;
37723 + if (fiq_fsm_enable) {
37725 + for (i=0; i < hcd->core_if->core_params->host_channels; i++) {
37726 + dwc_otg_cleanup_fiq_channel(hcd, i);
37728 + DWC_PRINTF("FIQ FSM acceleration enabled for :\n%s%s%s%s",
37729 + (fiq_fsm_mask & 0x1) ? "Non-periodic Split Transactions\n" : "",
37730 + (fiq_fsm_mask & 0x2) ? "Periodic Split Transactions\n" : "",
37731 + (fiq_fsm_mask & 0x4) ? "High-Speed Isochronous Endpoints\n" : "",
37732 + (fiq_fsm_mask & 0x8) ? "Interrupt/Control Split Transaction hack enabled\n" : "");
37736 + /* Initialize the Connection timeout timer. */
37737 + hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer",
37738 + dwc_otg_hcd_connect_timeout, 0);
37740 + printk(KERN_DEBUG "dwc_otg: Microframe scheduler %s\n", microframe_schedule ? "enabled":"disabled");
37741 + if (microframe_schedule)
37742 + init_hcd_usecs(hcd);
37744 + /* Initialize reset tasklet. */
37745 + hcd->reset_tasklet = DWC_TASK_ALLOC("reset_tasklet", reset_tasklet_func, hcd);
37747 + hcd->completion_tasklet = DWC_TASK_ALLOC("completion_tasklet",
37748 + completion_tasklet_func, hcd);
37749 +#ifdef DWC_DEV_SRPCAP
37750 + if (hcd->core_if->power_down == 2) {
37751 + /* Initialize Power on timer for Host power up in case hibernation */
37752 + hcd->core_if->pwron_timer = DWC_TIMER_ALLOC("PWRON TIMER",
37753 + dwc_otg_hcd_power_up, core_if);
37758 + * Allocate space for storing data on status transactions. Normally no
37759 + * data is sent, but this space acts as a bit bucket. This must be
37760 + * done after usb_add_hcd since that function allocates the DMA buffer
37763 + if (hcd->core_if->dma_enable) {
37764 + hcd->status_buf =
37765 + DWC_DMA_ALLOC(dev, DWC_OTG_HCD_STATUS_BUF_SIZE,
37766 + &hcd->status_buf_dma);
37768 + hcd->status_buf = DWC_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE);
37770 + if (!hcd->status_buf) {
37771 + retval = -DWC_E_NO_MEMORY;
37772 + DWC_ERROR("%s: status_buf allocation failed\n", __func__);
37773 + dwc_otg_hcd_free(hcd);
37777 + hcd->otg_port = 1;
37778 + hcd->frame_list = NULL;
37779 + hcd->frame_list_dma = 0;
37780 + hcd->periodic_qh_count = 0;
37782 + DWC_MEMSET(hcd->hub_port, 0, sizeof(hcd->hub_port));
37784 + DWC_MEMSET(hcd->hub_port_alloc, -1, sizeof(hcd->hub_port_alloc));
37791 +void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd)
37793 + /* Turn off all host-specific interrupts. */
37794 + dwc_otg_disable_host_interrupts(hcd->core_if);
37796 + dwc_otg_hcd_free(hcd);
37800 + * Initializes dynamic portions of the DWC_otg HCD state.
37802 +static void dwc_otg_hcd_reinit(dwc_otg_hcd_t * hcd)
37804 + int num_channels;
37806 + dwc_hc_t *channel;
37807 + dwc_hc_t *channel_tmp;
37809 + hcd->flags.d32 = 0;
37811 + hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
37812 + if (!microframe_schedule) {
37813 + hcd->non_periodic_channels = 0;
37814 + hcd->periodic_channels = 0;
37816 + hcd->available_host_channels = hcd->core_if->core_params->host_channels;
37819 + * Put all channels in the free channel list and clean up channel
37822 + DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp,
37823 + &hcd->free_hc_list, hc_list_entry) {
37824 + DWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry);
37827 + num_channels = hcd->core_if->core_params->host_channels;
37828 + for (i = 0; i < num_channels; i++) {
37829 + channel = hcd->hc_ptr_array[i];
37830 + DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel,
37832 + dwc_otg_hc_cleanup(hcd->core_if, channel);
37835 + /* Initialize the DWC core for host mode operation. */
37836 + dwc_otg_core_host_init(hcd->core_if);
37838 + /* Set core_if's lock pointer to the hcd->lock */
37839 + hcd->core_if->lock = hcd->lock;
37843 + * Assigns transactions from a QTD to a free host channel and initializes the
37844 + * host channel to perform the transactions. The host channel is removed from
37847 + * @param hcd The HCD state structure.
37848 + * @param qh Transactions from the first QTD for this QH are selected and
37849 + * assigned to a free host channel.
37851 +static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
37854 + dwc_otg_qtd_t *qtd;
37855 + dwc_otg_hcd_urb_t *urb;
37856 + void* ptr = NULL;
37857 + uint16_t wLength;
37858 + uint32_t intr_enable;
37859 + unsigned long flags;
37860 + gintmsk_data_t gintmsk = { .d32 = 0, };
37861 + struct device *dev = dwc_otg_hcd_to_dev(hcd);
37863 + qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
37867 + DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p) - urb %x, actual_length %d\n", __func__, hcd, qh, (unsigned int)urb, urb->actual_length);
37869 + if (((urb->actual_length < 0) || (urb->actual_length > urb->length)) && !dwc_otg_hcd_is_pipe_in(&urb->pipe_info))
37870 + urb->actual_length = urb->length;
37873 + hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
37875 + /* Remove the host channel from the free list. */
37876 + DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
37878 + qh->channel = hc;
37880 + qtd->in_process = 1;
37883 + * Use usb_pipedevice to determine device address. This address is
37884 + * 0 before the SET_ADDRESS command and the correct address afterward.
37886 + hc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info);
37887 + hc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info);
37888 + hc->speed = qh->dev_speed;
37889 + hc->max_packet = dwc_max_packet(qh->maxp);
37891 + hc->xfer_started = 0;
37892 + hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
37893 + hc->error_state = (qtd->error_count > 0);
37894 + hc->halt_on_queue = 0;
37895 + hc->halt_pending = 0;
37896 + hc->requests = 0;
37899 + * The following values may be modified in the transfer type section
37900 + * below. The xfer_len value may be reduced when the transfer is
37901 + * started to accommodate the max widths of the XferSize and PktCnt
37902 + * fields in the HCTSIZn register.
37905 + hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0);
37906 + if (hc->ep_is_in) {
37909 + hc->do_ping = qh->ping_state;
37912 + hc->data_pid_start = qh->data_toggle;
37913 + hc->multi_count = 1;
37915 + if (hcd->core_if->dma_enable) {
37916 + hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length;
37918 + /* For non-dword aligned case */
37919 + if (((unsigned long)hc->xfer_buff & 0x3)
37920 + && !hcd->core_if->dma_desc_enable) {
37921 + ptr = (uint8_t *) urb->buf + urb->actual_length;
37924 + hc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length;
37926 + hc->xfer_len = urb->length - urb->actual_length;
37927 + hc->xfer_count = 0;
37930 + * Set the split attributes
37932 + hc->do_split = 0;
37933 + if (qh->do_split) {
37934 + uint32_t hub_addr, port_addr;
37935 + hc->do_split = 1;
37936 + hc->start_pkt_count = 1;
37937 + hc->xact_pos = qtd->isoc_split_pos;
37938 + /* We don't need to do complete splits anymore */
37939 +// if(fiq_fsm_enable)
37941 + hc->complete_split = qtd->complete_split = 0;
37943 + hc->complete_split = qtd->complete_split;
37945 + hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr);
37946 + hc->hub_addr = (uint8_t) hub_addr;
37947 + hc->port_addr = (uint8_t) port_addr;
37950 + switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
37952 + hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
37953 + switch (qtd->control_phase) {
37954 + case DWC_OTG_CONTROL_SETUP:
37955 + DWC_DEBUGPL(DBG_HCDV, " Control setup transaction\n");
37957 + hc->ep_is_in = 0;
37958 + hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
37959 + if (hcd->core_if->dma_enable) {
37960 + hc->xfer_buff = (uint8_t *) urb->setup_dma;
37962 + hc->xfer_buff = (uint8_t *) urb->setup_packet;
37964 + hc->xfer_len = 8;
37967 + case DWC_OTG_CONTROL_DATA:
37968 + DWC_DEBUGPL(DBG_HCDV, " Control data transaction\n");
37970 + * Hardware bug: small IN packets with length < 4
37971 + * cause a 4-byte write to memory. We can only catch
37972 + * the case where we know a short packet is going to be
37973 + * returned in a control transfer, as the length is
37974 + * specified in the setup packet. This is only an issue
37975 + * for drivers that insist on packing a device's various
37976 + * properties into a struct and querying them one at a
37977 + * time (uvcvideo).
37978 + * Force the use of align_buf so that the subsequent
37979 + * memcpy puts the right number of bytes in the URB's
37982 + wLength = ((uint16_t *)urb->setup_packet)[3];
37983 + if (hc->ep_is_in && wLength < 4)
37984 + ptr = hc->xfer_buff;
37986 + hc->data_pid_start = qtd->data_toggle;
37988 + case DWC_OTG_CONTROL_STATUS:
37990 + * Direction is opposite of data direction or IN if no
37993 + DWC_DEBUGPL(DBG_HCDV, " Control status transaction\n");
37994 + if (urb->length == 0) {
37995 + hc->ep_is_in = 1;
37998 + dwc_otg_hcd_is_pipe_out(&urb->pipe_info);
38000 + if (hc->ep_is_in) {
38004 + hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
38006 + hc->xfer_len = 0;
38007 + if (hcd->core_if->dma_enable) {
38008 + hc->xfer_buff = (uint8_t *) hcd->status_buf_dma;
38010 + hc->xfer_buff = (uint8_t *) hcd->status_buf;
38017 + hc->ep_type = DWC_OTG_EP_TYPE_BULK;
38019 + case UE_INTERRUPT:
38020 + hc->ep_type = DWC_OTG_EP_TYPE_INTR;
38022 + case UE_ISOCHRONOUS:
38024 + struct dwc_otg_hcd_iso_packet_desc *frame_desc;
38026 + hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
38028 + if (hcd->core_if->dma_desc_enable)
38031 + frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
38033 + frame_desc->status = 0;
38035 + if (hcd->core_if->dma_enable) {
38036 + hc->xfer_buff = (uint8_t *) urb->dma;
38038 + hc->xfer_buff = (uint8_t *) urb->buf;
38041 + frame_desc->offset + qtd->isoc_split_offset;
38043 + frame_desc->length - qtd->isoc_split_offset;
38045 + /* For non-dword aligned buffers */
38046 + if (((unsigned long)hc->xfer_buff & 0x3)
38047 + && hcd->core_if->dma_enable) {
38049 + (uint8_t *) urb->buf + frame_desc->offset +
38050 + qtd->isoc_split_offset;
38054 + if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
38055 + if (hc->xfer_len <= 188) {
38056 + hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
38059 + DWC_HCSPLIT_XACTPOS_BEGIN;
38065 + /* non DWORD-aligned buffer case */
38067 + uint32_t buf_size;
38068 + if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
38069 + buf_size = hcd->core_if->core_params->max_transfer_size;
38073 + if (!qh->dw_align_buf) {
38074 + qh->dw_align_buf = DWC_DMA_ALLOC_ATOMIC(dev, buf_size,
38075 + &qh->dw_align_buf_dma);
38076 + if (!qh->dw_align_buf) {
38078 + ("%s: Failed to allocate memory to handle "
38079 + "non-dword aligned buffer case\n",
38084 + if (!hc->ep_is_in) {
38085 + dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len);
38087 + hc->align_buff = qh->dw_align_buf_dma;
38089 + hc->align_buff = 0;
38092 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
38093 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
38095 + * This value may be modified when the transfer is started to
38096 + * reflect the actual transfer length.
38098 + hc->multi_count = dwc_hb_mult(qh->maxp);
38101 + if (hcd->core_if->dma_desc_enable)
38102 + hc->desc_list_addr = qh->desc_list_dma;
38104 + dwc_otg_hc_init(hcd->core_if, hc);
38106 + local_irq_save(flags);
38108 + if (fiq_enable) {
38109 + local_fiq_disable();
38110 + fiq_fsm_spin_lock(&hcd->fiq_state->lock);
38113 + /* Enable the top level host channel interrupt. */
38114 + intr_enable = (1 << hc->hc_num);
38115 + DWC_MODIFY_REG32(&hcd->core_if->host_if->host_global_regs->haintmsk, 0, intr_enable);
38117 + /* Make sure host channel interrupts are enabled. */
38118 + gintmsk.b.hcintr = 1;
38119 + DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
38121 + if (fiq_enable) {
38122 + fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
38123 + local_fiq_enable();
38126 + local_irq_restore(flags);
38132 + * fiq_fsm_transaction_suitable() - Test a QH for compatibility with the FIQ
38133 + * @hcd: Pointer to the dwc_otg_hcd struct
38134 + * @qh: pointer to the endpoint's queue head
38136 + * Transaction start/end control flow is grafted onto the existing dwc_otg
38137 + * mechanisms, to avoid spaghettifying the functions more than they already are.
38138 + * This function's eligibility check is altered by debug parameter.
38140 + * Returns: 0 for unsuitable, 1 implies the FIQ can be enabled for this transaction.
38143 +int fiq_fsm_transaction_suitable(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
38145 + if (qh->do_split) {
38146 + switch (qh->ep_type) {
38149 + if (fiq_fsm_mask & (1 << 0))
38152 + case UE_INTERRUPT:
38153 + case UE_ISOCHRONOUS:
38154 + if (fiq_fsm_mask & (1 << 1))
38160 + } else if (qh->ep_type == UE_ISOCHRONOUS) {
38161 + if (fiq_fsm_mask & (1 << 2)) {
38162 + /* ISOCH support. We test for compatibility:
38163 + * - DWORD aligned buffers
38164 + * - Must be at least 2 transfers (otherwise pointless to use the FIQ)
38165 + * If yes, then the fsm enqueue function will handle the state machine setup.
38167 + dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
38168 + dwc_otg_hcd_urb_t *urb = qtd->urb;
38172 + if (urb->packet_count < 2)
38174 + for (i = 0; i < urb->packet_count; i++) {
38175 + ptr = urb->dma + urb->iso_descs[i].offset;
38186 + * fiq_fsm_setup_periodic_dma() - Set up DMA bounce buffers
38187 + * @hcd: Pointer to the dwc_otg_hcd struct
38188 + * @qh: Pointer to the endpoint's queue head
38190 + * Periodic split transactions are transmitted modulo 188 bytes.
38191 + * This necessitates slicing data up into buckets for isochronous out
38192 + * and fixing up the DMA address for all IN transfers.
38194 + * Returns 1 if the DMA bounce buffers have been used, 0 if the default
38195 + * HC buffer has been used.
38197 +int fiq_fsm_setup_periodic_dma(dwc_otg_hcd_t *hcd, struct fiq_channel_state *st, dwc_otg_qh_t *qh)
38199 + int frame_length, i = 0;
38200 + uint8_t *ptr = NULL;
38201 + dwc_hc_t *hc = qh->channel;
38202 + struct fiq_dma_blob *blob;
38203 + struct dwc_otg_hcd_iso_packet_desc *frame_desc;
38205 + for (i = 0; i < 6; i++) {
38206 + st->dma_info.slot_len[i] = 255;
38208 + st->dma_info.index = 0;
38210 + if (hc->ep_is_in) {
38212 + * Set dma_regs to bounce buffer. FIQ will update the
38213 + * state depending on transaction progress.
38214 + * Pointer arithmetic on hcd->fiq_state->dma_base (a dma_addr_t)
38215 + * to point it to the correct offset in the allocated buffers.
38217 + blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;
38218 + st->hcdma_copy.d32 = (dma_addr_t) blob->channel[hc->hc_num].index[0].buf;
38220 + /* Calculate the max number of CSPLITS such that the FIQ can time out
38221 + * a transaction if it fails.
38223 + frame_length = st->hcchar_copy.b.mps;
38226 + frame_length -= 188;
38227 + } while (frame_length >= 0);
38228 + st->nrpackets = i;
38231 + if (qh->ep_type == UE_ISOCHRONOUS) {
38233 + dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
38235 + frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
38236 + frame_length = frame_desc->length;
38238 + /* Virtual address for bounce buffers */
38239 + blob = hcd->fiq_dmab;
38241 + ptr = qtd->urb->buf + frame_desc->offset;
38242 + if (frame_length == 0) {
38244 + * for isochronous transactions, we must still transmit a packet
38245 + * even if the length is zero.
38247 + st->dma_info.slot_len[0] = 0;
38248 + st->nrpackets = 1;
38251 + if (frame_length <= 188) {
38252 + dwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, frame_length);
38253 + st->dma_info.slot_len[i] = frame_length;
38254 + ptr += frame_length;
38256 + dwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, 188);
38257 + st->dma_info.slot_len[i] = 188;
38261 + frame_length -= 188;
38262 + } while (frame_length > 0);
38263 + st->nrpackets = i;
38265 + ptr = qtd->urb->buf + frame_desc->offset;
38267 + * Point the HC at the DMA address of the bounce buffers
38269 + * Pointer arithmetic on hcd->fiq_state->dma_base (a
38270 + * dma_addr_t) to point it to the correct offset in the
38271 + * allocated buffers.
38273 + blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;
38274 + st->hcdma_copy.d32 = (dma_addr_t) blob->channel[hc->hc_num].index[0].buf;
38276 + /* fixup xfersize to the actual packet size */
38277 + st->hctsiz_copy.b.pid = 0;
38278 + st->hctsiz_copy.b.xfersize = st->dma_info.slot_len[0];
38281 + /* For interrupt, single OUT packet required, goes in the SSPLIT from hc_buff. */
38288 + * fiq_fsm_np_tt_contended() - Avoid performing contended non-periodic transfers
38289 + * @hcd: Pointer to the dwc_otg_hcd struct
38290 + * @qh: Pointer to the endpoint's queue head
38292 + * Certain hub chips don't differentiate between IN and OUT non-periodic pipes
38293 + * with the same endpoint number. If transfers get completed out of order
38294 + * (disregarding the direction token) then the hub can lock up
38295 + * or return erroneous responses.
38297 + * Returns 1 if initiating the transfer would cause contention, 0 otherwise.
38299 +int fiq_fsm_np_tt_contended(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
38302 + struct fiq_channel_state *st;
38303 + int dev_addr = qh->channel->dev_addr;
38304 + int ep_num = qh->channel->ep_num;
38305 + for (i = 0; i < hcd->core_if->core_params->host_channels; i++) {
38306 + if (i == qh->channel->hc_num)
38308 + st = &hcd->fiq_state->channel[i];
38309 + switch (st->fsm) {
38310 + case FIQ_NP_SSPLIT_STARTED:
38311 + case FIQ_NP_SSPLIT_RETRY:
38312 + case FIQ_NP_SSPLIT_PENDING:
38313 + case FIQ_NP_OUT_CSPLIT_RETRY:
38314 + case FIQ_NP_IN_CSPLIT_RETRY:
38315 + if (st->hcchar_copy.b.devaddr == dev_addr &&
38316 + st->hcchar_copy.b.epnum == ep_num)
38327 + * Pushing a periodic request into the queue near the EOF1 point
38328 + * in a microframe causes erroneous behaviour (frmovrun) interrupt.
38329 + * Usually, the request goes out on the bus causing a transfer but
38330 + * the core does not transfer the data to memory.
38331 + * This guard interval (in number of 60MHz clocks) is required which
38332 + * must cater for CPU latency between reading the value and enabling
38335 +#define PERIODIC_FRREM_BACKOFF 1000
38337 +int fiq_fsm_queue_isoc_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
38339 + dwc_hc_t *hc = qh->channel;
38340 + dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
38341 + dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
38343 + struct fiq_channel_state *st = &hcd->fiq_state->channel[hc->hc_num];
38344 + int xfer_len, nrpackets;
38345 + hcdma_data_t hcdma;
38346 + hfnum_data_t hfnum;
38348 + if (st->fsm != FIQ_PASSTHROUGH)
38351 + st->nr_errors = 0;
38353 + st->hcchar_copy.d32 = 0;
38354 + st->hcchar_copy.b.mps = hc->max_packet;
38355 + st->hcchar_copy.b.epdir = hc->ep_is_in;
38356 + st->hcchar_copy.b.devaddr = hc->dev_addr;
38357 + st->hcchar_copy.b.epnum = hc->ep_num;
38358 + st->hcchar_copy.b.eptype = hc->ep_type;
38360 + st->hcintmsk_copy.b.chhltd = 1;
38362 + frame = dwc_otg_hcd_get_frame_number(hcd);
38363 + st->hcchar_copy.b.oddfrm = (frame & 0x1) ? 0 : 1;
38365 + st->hcchar_copy.b.lspddev = 0;
38366 + /* Enable the channel later as a final register write. */
38368 + st->hcsplt_copy.d32 = 0;
38370 + st->hs_isoc_info.iso_desc = (struct dwc_otg_hcd_iso_packet_desc *) &qtd->urb->iso_descs;
38371 + st->hs_isoc_info.nrframes = qtd->urb->packet_count;
38372 + /* grab the next DMA address offset from the array */
38373 + st->hcdma_copy.d32 = qtd->urb->dma;
38374 + hcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[0].offset;
38376 + /* We need to set multi_count. This is a bit tricky - has to be set per-transaction as
38377 + * the core needs to be told to send the correct number. Caution: for IN transfers,
38378 + * this is always set to the maximum size of the endpoint. */
38379 + xfer_len = st->hs_isoc_info.iso_desc[0].length;
38380 + nrpackets = (xfer_len + st->hcchar_copy.b.mps - 1) / st->hcchar_copy.b.mps;
38381 + if (nrpackets == 0)
38383 + st->hcchar_copy.b.multicnt = nrpackets;
38384 + st->hctsiz_copy.b.pktcnt = nrpackets;
38386 + /* Initial PID also needs to be set */
38387 + if (st->hcchar_copy.b.epdir == 0) {
38388 + st->hctsiz_copy.b.xfersize = xfer_len;
38389 + switch (st->hcchar_copy.b.multicnt) {
38391 + st->hctsiz_copy.b.pid = DWC_PID_DATA0;
38395 + st->hctsiz_copy.b.pid = DWC_PID_MDATA;
38400 + st->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps;
38401 + switch (st->hcchar_copy.b.multicnt) {
38403 + st->hctsiz_copy.b.pid = DWC_PID_DATA0;
38406 + st->hctsiz_copy.b.pid = DWC_PID_DATA1;
38409 + st->hctsiz_copy.b.pid = DWC_PID_DATA2;
38414 + st->hs_isoc_info.stride = qh->interval;
38415 + st->uframe_sleeps = 0;
38417 + fiq_print(FIQDBG_INT, hcd->fiq_state, "FSMQ %01d ", hc->hc_num);
38418 + fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcchar_copy.d32);
38419 + fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hctsiz_copy.d32);
38420 + fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcdma_copy.d32);
38421 + hfnum.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
38422 + local_fiq_disable();
38423 + fiq_fsm_spin_lock(&hcd->fiq_state->lock);
38424 + DWC_WRITE_REG32(&hc_regs->hctsiz, st->hctsiz_copy.d32);
38425 + DWC_WRITE_REG32(&hc_regs->hcsplt, st->hcsplt_copy.d32);
38426 + DWC_WRITE_REG32(&hc_regs->hcdma, st->hcdma_copy.d32);
38427 + DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);
38428 + DWC_WRITE_REG32(&hc_regs->hcintmsk, st->hcintmsk_copy.d32);
38429 + if (hfnum.b.frrem < PERIODIC_FRREM_BACKOFF) {
38430 + /* Prevent queueing near EOF1. Bad things happen if a periodic
38431 + * split transaction is queued very close to EOF. SOF interrupt handler
38432 + * will wake this channel at the next interrupt.
38434 + st->fsm = FIQ_HS_ISOC_SLEEPING;
38435 + st->uframe_sleeps = 1;
38437 + st->fsm = FIQ_HS_ISOC_TURBO;
38438 + st->hcchar_copy.b.chen = 1;
38439 + DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);
38442 + st->hcchar_copy.b.chen = 0;
38443 + fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
38444 + local_fiq_enable();
38450 + * fiq_fsm_queue_split_transaction() - Set up a host channel and FIQ state
38451 + * @hcd: Pointer to the dwc_otg_hcd struct
38452 + * @qh: Pointer to the endpoint's queue head
38454 + * This overrides the dwc_otg driver's normal method of queueing a transaction.
38455 + * Called from dwc_otg_hcd_queue_transactions(), this performs specific setup
38456 + * for the nominated host channel.
38458 + * For periodic transfers, it also peeks at the FIQ state to see if an immediate
38459 + * start is possible. If not, then the FIQ is left to start the transfer.
38461 +int fiq_fsm_queue_split_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
38463 + int start_immediate = 1, i;
38464 + hfnum_data_t hfnum;
38465 + dwc_hc_t *hc = qh->channel;
38466 + dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
38467 + /* Program HC registers, setup FIQ_state, examine FIQ if periodic, start transfer (not if uframe 5) */
38468 + int hub_addr, port_addr, frame, uframe;
38469 + struct fiq_channel_state *st = &hcd->fiq_state->channel[hc->hc_num];
38472 + * Non-periodic channel assignments stay in the non_periodic_active queue.
38473 + * Therefore we get repeatedly called until the FIQ's done processing this channel.
38475 + if (qh->channel->xfer_started == 1)
38478 + if (st->fsm != FIQ_PASSTHROUGH) {
38479 + pr_warn_ratelimited("%s:%d: Queue called for an active channel\n", __func__, __LINE__);
38483 + qh->channel->xfer_started = 1;
38485 + st->nr_errors = 0;
38487 + st->hcchar_copy.d32 = 0;
38488 + st->hcchar_copy.b.mps = hc->max_packet;
38489 + st->hcchar_copy.b.epdir = hc->ep_is_in;
38490 + st->hcchar_copy.b.devaddr = hc->dev_addr;
38491 + st->hcchar_copy.b.epnum = hc->ep_num;
38492 + st->hcchar_copy.b.eptype = hc->ep_type;
38493 + if (hc->ep_type & 0x1) {
38494 + if (hc->ep_is_in)
38495 + st->hcchar_copy.b.multicnt = 3;
38497 + /* Docs say set this to 1, but driver sets to 0! */
38498 + st->hcchar_copy.b.multicnt = 0;
38500 + st->hcchar_copy.b.multicnt = 1;
38501 + st->hcchar_copy.b.oddfrm = 0;
38503 + st->hcchar_copy.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW) ? 1 : 0;
38504 + /* Enable the channel later as a final register write. */
38506 + st->hcsplt_copy.d32 = 0;
38507 + if(qh->do_split) {
38508 + hcd->fops->hub_info(hcd, DWC_CIRCLEQ_FIRST(&qh->qtd_list)->urb->priv, &hub_addr, &port_addr);
38509 + st->hcsplt_copy.b.compsplt = 0;
38510 + st->hcsplt_copy.b.spltena = 1;
38511 + // XACTPOS is for isoc-out only but needs initialising anyway.
38512 + st->hcsplt_copy.b.xactpos = ISOC_XACTPOS_ALL;
38513 + if((qh->ep_type == DWC_OTG_EP_TYPE_ISOC) && (!qh->ep_is_in)) {
38514 + /* For packetsize 0 < L < 188, ISOC_XACTPOS_ALL.
38515 + * for longer than this, ISOC_XACTPOS_BEGIN and the FIQ
38516 + * will update as necessary.
38518 + if (hc->xfer_len > 188) {
38519 + st->hcsplt_copy.b.xactpos = ISOC_XACTPOS_BEGIN;
38522 + st->hcsplt_copy.b.hubaddr = (uint8_t) hub_addr;
38523 + st->hcsplt_copy.b.prtaddr = (uint8_t) port_addr;
38524 + st->hub_addr = hub_addr;
38525 + st->port_addr = port_addr;
38528 + st->hctsiz_copy.d32 = 0;
38529 + st->hctsiz_copy.b.dopng = 0;
38530 + st->hctsiz_copy.b.pid = hc->data_pid_start;
38532 + if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {
38533 + hc->xfer_len = hc->max_packet;
38534 + } else if (!hc->ep_is_in && (hc->xfer_len > 188)) {
38535 + hc->xfer_len = 188;
38537 + st->hctsiz_copy.b.xfersize = hc->xfer_len;
38539 + st->hctsiz_copy.b.pktcnt = 1;
38541 + if (hc->ep_type & 0x1) {
38543 + * For potentially multi-packet transfers, must use the DMA bounce buffers. For IN transfers,
38544 + * the DMA address is the address of the first 188byte slot buffer in the bounce buffer array.
38545 + * For multi-packet OUT transfers, we need to copy the data into the bounce buffer array so the FIQ can punt
38546 + * the right address out as necessary. hc->xfer_buff and hc->xfer_len have already been set
38547 + * in assign_and_init_hc(), but this is for the eventual transaction completion only. The FIQ
38548 + * must not touch internal driver state.
38550 + if(!fiq_fsm_setup_periodic_dma(hcd, st, qh)) {
38551 + if (hc->align_buff) {
38552 + st->hcdma_copy.d32 = hc->align_buff;
38554 + st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF);
38558 + if (hc->align_buff) {
38559 + st->hcdma_copy.d32 = hc->align_buff;
38561 + st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF);
38564 + /* The FIQ depends upon no other interrupts being enabled except channel halt.
38565 + * Fixup channel interrupt mask. */
38566 + st->hcintmsk_copy.d32 = 0;
38567 + st->hcintmsk_copy.b.chhltd = 1;
38568 + st->hcintmsk_copy.b.ahberr = 1;
38570 + /* Hack courtesy of FreeBSD: apparently forcing Interrupt Split transactions
38571 + * as Control puts the transfer into the non-periodic request queue and the
38572 + * non-periodic handler in the hub. Makes things lots easier.
38574 + if ((fiq_fsm_mask & 0x8) && hc->ep_type == UE_INTERRUPT) {
38575 + st->hcchar_copy.b.multicnt = 0;
38576 + st->hcchar_copy.b.oddfrm = 0;
38577 + st->hcchar_copy.b.eptype = UE_CONTROL;
38578 + if (hc->align_buff) {
38579 + st->hcdma_copy.d32 = hc->align_buff;
38581 + st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF);
38584 + DWC_WRITE_REG32(&hc_regs->hcdma, st->hcdma_copy.d32);
38585 + DWC_WRITE_REG32(&hc_regs->hctsiz, st->hctsiz_copy.d32);
38586 + DWC_WRITE_REG32(&hc_regs->hcsplt, st->hcsplt_copy.d32);
38587 + DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);
38588 + DWC_WRITE_REG32(&hc_regs->hcintmsk, st->hcintmsk_copy.d32);
38590 + local_fiq_disable();
38591 + fiq_fsm_spin_lock(&hcd->fiq_state->lock);
38593 + if (hc->ep_type & 0x1) {
38594 + hfnum.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
38595 + frame = (hfnum.b.frnum & ~0x7) >> 3;
38596 + uframe = hfnum.b.frnum & 0x7;
38597 + if (hfnum.b.frrem < PERIODIC_FRREM_BACKOFF) {
38598 + /* Prevent queueing near EOF1. Bad things happen if a periodic
38599 + * split transaction is queued very close to EOF.
38601 + start_immediate = 0;
38602 + } else if (uframe == 5) {
38603 + start_immediate = 0;
38604 + } else if (hc->ep_type == UE_ISOCHRONOUS && !hc->ep_is_in) {
38605 + start_immediate = 0;
38606 + } else if (hc->ep_is_in && fiq_fsm_too_late(hcd->fiq_state, hc->hc_num)) {
38607 + start_immediate = 0;
38609 + /* Search through all host channels to determine if a transaction
38610 + * is currently in progress */
38611 + for (i = 0; i < hcd->core_if->core_params->host_channels; i++) {
38612 + if (i == hc->hc_num || hcd->fiq_state->channel[i].fsm == FIQ_PASSTHROUGH)
38614 + switch (hcd->fiq_state->channel[i].fsm) {
38615 + /* TT is reserved for channels that are in the middle of a periodic
38616 + * split transaction.
38618 + case FIQ_PER_SSPLIT_STARTED:
38619 + case FIQ_PER_CSPLIT_WAIT:
38620 + case FIQ_PER_CSPLIT_NYET1:
38621 + case FIQ_PER_CSPLIT_POLL:
38622 + case FIQ_PER_ISO_OUT_ACTIVE:
38623 + case FIQ_PER_ISO_OUT_LAST:
38624 + if (hcd->fiq_state->channel[i].hub_addr == hub_addr &&
38625 + hcd->fiq_state->channel[i].port_addr == port_addr) {
38626 + start_immediate = 0;
38632 + if (!start_immediate)
38637 + if ((fiq_fsm_mask & 0x8) && hc->ep_type == UE_INTERRUPT)
38638 + start_immediate = 1;
38640 + fiq_print(FIQDBG_INT, hcd->fiq_state, "FSMQ %01d %01d", hc->hc_num, start_immediate);
38641 + fiq_print(FIQDBG_INT, hcd->fiq_state, "%08d", hfnum.b.frrem);
38642 + //fiq_print(FIQDBG_INT, hcd->fiq_state, "H:%02dP:%02d", hub_addr, port_addr);
38643 + //fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hctsiz_copy.d32);
38644 + //fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcdma_copy.d32);
38645 + switch (hc->ep_type) {
38648 + if (fiq_fsm_np_tt_contended(hcd, qh)) {
38649 + st->fsm = FIQ_NP_SSPLIT_PENDING;
38650 + start_immediate = 0;
38652 + st->fsm = FIQ_NP_SSPLIT_STARTED;
38655 + case UE_ISOCHRONOUS:
38656 + if (hc->ep_is_in) {
38657 + if (start_immediate) {
38658 + st->fsm = FIQ_PER_SSPLIT_STARTED;
38660 + st->fsm = FIQ_PER_SSPLIT_QUEUED;
38663 + if (start_immediate) {
38664 + /* Single-isoc OUT packets don't require FIQ involvement */
38665 + if (st->nrpackets == 1) {
38666 + st->fsm = FIQ_PER_ISO_OUT_LAST;
38668 + st->fsm = FIQ_PER_ISO_OUT_ACTIVE;
38671 + st->fsm = FIQ_PER_ISO_OUT_PENDING;
38675 + case UE_INTERRUPT:
38676 + if (fiq_fsm_mask & 0x8) {
38677 + if (fiq_fsm_np_tt_contended(hcd, qh)) {
38678 + st->fsm = FIQ_NP_SSPLIT_PENDING;
38679 + start_immediate = 0;
38681 + st->fsm = FIQ_NP_SSPLIT_STARTED;
38683 + } else if (start_immediate) {
38684 + st->fsm = FIQ_PER_SSPLIT_STARTED;
38686 + st->fsm = FIQ_PER_SSPLIT_QUEUED;
38691 + if (start_immediate) {
38692 + /* Set the oddfrm bit as close as possible to actual queueing */
38693 + frame = dwc_otg_hcd_get_frame_number(hcd);
38694 + st->expected_uframe = (frame + 1) & 0x3FFF;
38695 + st->hcchar_copy.b.oddfrm = (frame & 0x1) ? 0 : 1;
38696 + st->hcchar_copy.b.chen = 1;
38697 + DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);
38700 + fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
38701 + local_fiq_enable();
38707 + * This function selects transactions from the HCD transfer schedule and
38708 + * assigns them to available host channels. It is called from HCD interrupt
38709 + * handler functions.
38711 + * @param hcd The HCD state structure.
38713 + * @return The types of new transactions that were assigned to host channels.
38715 +dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd)
38717 + dwc_list_link_t *qh_ptr;
38718 + dwc_otg_qh_t *qh;
38719 + int num_channels;
38720 + dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
38722 +#ifdef DEBUG_HOST_CHANNELS
38723 + last_sel_trans_num_per_scheduled = 0;
38724 + last_sel_trans_num_nonper_scheduled = 0;
38725 + last_sel_trans_num_avail_hc_at_start = hcd->available_host_channels;
38726 +#endif /* DEBUG_HOST_CHANNELS */
38728 + /* Process entries in the periodic ready list. */
38729 + qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready);
38731 + while (qh_ptr != &hcd->periodic_sched_ready &&
38732 + !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
38734 + qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
38736 + if (microframe_schedule) {
38737 + // Make sure we leave one channel for non periodic transactions.
38738 + if (hcd->available_host_channels <= 1) {
38741 + hcd->available_host_channels--;
38742 +#ifdef DEBUG_HOST_CHANNELS
38743 + last_sel_trans_num_per_scheduled++;
38744 +#endif /* DEBUG_HOST_CHANNELS */
38746 + qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
38747 + assign_and_init_hc(hcd, qh);
38750 + * Move the QH from the periodic ready schedule to the
38751 + * periodic assigned schedule.
38753 + qh_ptr = DWC_LIST_NEXT(qh_ptr);
38754 + DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
38755 + &qh->qh_list_entry);
38759 + * Process entries in the inactive portion of the non-periodic
38760 + * schedule. Some free host channels may not be used if they are
38761 + * reserved for periodic transfers.
38763 + qh_ptr = hcd->non_periodic_sched_inactive.next;
38764 + num_channels = hcd->core_if->core_params->host_channels;
38765 + while (qh_ptr != &hcd->non_periodic_sched_inactive &&
38766 + (microframe_schedule || hcd->non_periodic_channels <
38767 + num_channels - hcd->periodic_channels) &&
38768 + !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
38770 + qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
38772 + * Check to see if this is a NAK'd retransmit, in which case ignore for retransmission
38773 + * we hold off on bulk retransmissions to reduce NAK interrupt overhead for full-speed
38774 + * cheeky devices that just hold off using NAKs
38776 + if (fiq_enable && nak_holdoff && qh->do_split) {
38777 + if (qh->nak_frame != 0xffff) {
38778 + uint16_t next_frame = dwc_frame_num_inc(qh->nak_frame, (qh->ep_type == UE_BULK) ? nak_holdoff : 8);
38779 + uint16_t frame = dwc_otg_hcd_get_frame_number(hcd);
38780 + if (dwc_frame_num_le(frame, next_frame)) {
38781 + if(dwc_frame_num_le(next_frame, hcd->fiq_state->next_sched_frame)) {
38782 + hcd->fiq_state->next_sched_frame = next_frame;
38784 + qh_ptr = DWC_LIST_NEXT(qh_ptr);
38787 + qh->nak_frame = 0xFFFF;
38792 + if (microframe_schedule) {
38793 + if (hcd->available_host_channels < 1) {
38796 + hcd->available_host_channels--;
38797 +#ifdef DEBUG_HOST_CHANNELS
38798 + last_sel_trans_num_nonper_scheduled++;
38799 +#endif /* DEBUG_HOST_CHANNELS */
38802 + assign_and_init_hc(hcd, qh);
38805 + * Move the QH from the non-periodic inactive schedule to the
38806 + * non-periodic active schedule.
38808 + qh_ptr = DWC_LIST_NEXT(qh_ptr);
38809 + DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active,
38810 + &qh->qh_list_entry);
38812 + if (!microframe_schedule)
38813 + hcd->non_periodic_channels++;
38815 + /* we moved a non-periodic QH to the active schedule. If the inactive queue is empty,
38816 + * stop the FIQ from kicking us. We could potentially still have elements here if we
38817 + * ran out of host channels.
38819 + if (fiq_enable) {
38820 + if (DWC_LIST_EMPTY(&hcd->non_periodic_sched_inactive)) {
38821 + hcd->fiq_state->kick_np_queues = 0;
38823 + /* For each entry remaining in the NP inactive queue,
38824 + * if this a NAK'd retransmit then don't set the kick flag.
38826 + if(nak_holdoff) {
38827 + DWC_LIST_FOREACH(qh_ptr, &hcd->non_periodic_sched_inactive) {
38828 + qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
38829 + if (qh->nak_frame == 0xFFFF) {
38830 + hcd->fiq_state->kick_np_queues = 1;
38836 + if(!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned))
38837 + ret_val |= DWC_OTG_TRANSACTION_PERIODIC;
38839 + if(!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active))
38840 + ret_val |= DWC_OTG_TRANSACTION_NON_PERIODIC;
38843 +#ifdef DEBUG_HOST_CHANNELS
38844 + last_sel_trans_num_avail_hc_at_end = hcd->available_host_channels;
38845 +#endif /* DEBUG_HOST_CHANNELS */
38850 + * Attempts to queue a single transaction request for a host channel
38851 + * associated with either a periodic or non-periodic transfer. This function
38852 + * assumes that there is space available in the appropriate request queue. For
38853 + * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
38854 + * is available in the appropriate Tx FIFO.
38856 + * @param hcd The HCD state structure.
38857 + * @param hc Host channel descriptor associated with either a periodic or
38858 + * non-periodic transfer.
38859 + * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx
38860 + * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
38863 + * @return 1 if a request is queued and more requests may be needed to
38864 + * complete the transfer, 0 if no more requests are required for this
38865 + * transfer, -1 if there is insufficient space in the Tx FIFO.
38867 +static int queue_transaction(dwc_otg_hcd_t * hcd,
38868 + dwc_hc_t * hc, uint16_t fifo_dwords_avail)
38872 + if (hcd->core_if->dma_enable) {
38873 + if (hcd->core_if->dma_desc_enable) {
38874 + if (!hc->xfer_started
38875 + || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) {
38876 + dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh);
38877 + hc->qh->ping_state = 0;
38879 + } else if (!hc->xfer_started) {
38880 + if (fiq_fsm_enable && hc->error_state) {
38881 + hcd->fiq_state->channel[hc->hc_num].nr_errors =
38882 + DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list)->error_count;
38883 + hcd->fiq_state->channel[hc->hc_num].fsm =
38884 + FIQ_PASSTHROUGH_ERRORSTATE;
38886 + dwc_otg_hc_start_transfer(hcd->core_if, hc);
38887 + hc->qh->ping_state = 0;
38890 + } else if (hc->halt_pending) {
38891 + /* Don't queue a request if the channel has been halted. */
38893 + } else if (hc->halt_on_queue) {
38894 + dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
38896 + } else if (hc->do_ping) {
38897 + if (!hc->xfer_started) {
38898 + dwc_otg_hc_start_transfer(hcd->core_if, hc);
38901 + } else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
38902 + if ((fifo_dwords_avail * 4) >= hc->max_packet) {
38903 + if (!hc->xfer_started) {
38904 + dwc_otg_hc_start_transfer(hcd->core_if, hc);
38908 + dwc_otg_hc_continue_transfer(hcd->core_if,
38915 + if (!hc->xfer_started) {
38916 + dwc_otg_hc_start_transfer(hcd->core_if, hc);
38919 + retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
38927 + * Processes periodic channels for the next frame and queues transactions for
38928 + * these channels to the DWC_otg controller. After queueing transactions, the
38929 + * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
38930 + * to queue as Periodic Tx FIFO or request queue space becomes available.
38931 + * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
38933 +static void process_periodic_channels(dwc_otg_hcd_t * hcd)
38935 + hptxsts_data_t tx_status;
38936 + dwc_list_link_t *qh_ptr;
38937 + dwc_otg_qh_t *qh;
38939 + int no_queue_space = 0;
38940 + int no_fifo_space = 0;
38942 + dwc_otg_host_global_regs_t *host_regs;
38943 + host_regs = hcd->core_if->host_if->host_global_regs;
38945 + DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
38947 + tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
38948 + DWC_DEBUGPL(DBG_HCDV,
38949 + " P Tx Req Queue Space Avail (before queue): %d\n",
38950 + tx_status.b.ptxqspcavail);
38951 + DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (before queue): %d\n",
38952 + tx_status.b.ptxfspcavail);
38955 + qh_ptr = hcd->periodic_sched_assigned.next;
38956 + while (qh_ptr != &hcd->periodic_sched_assigned) {
38957 + tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
38958 + if (tx_status.b.ptxqspcavail == 0) {
38959 + no_queue_space = 1;
38963 + qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
38965 + // Do not send a split start transaction any later than frame .6
38966 + // Note, we have to schedule a periodic in .5 to make it go in .6
38967 + if(fiq_fsm_enable && qh->do_split && ((dwc_otg_hcd_get_frame_number(hcd) + 1) & 7) > 6)
38969 + qh_ptr = qh_ptr->next;
38970 + hcd->fiq_state->next_sched_frame = dwc_otg_hcd_get_frame_number(hcd) | 7;
38974 + if (fiq_fsm_enable && fiq_fsm_transaction_suitable(hcd, qh)) {
38975 + if (qh->do_split)
38976 + fiq_fsm_queue_split_transaction(hcd, qh);
38978 + fiq_fsm_queue_isoc_transaction(hcd, qh);
38982 + * Set a flag if we're queueing high-bandwidth in slave mode.
38983 + * The flag prevents any halts to get into the request queue in
38984 + * the middle of multiple high-bandwidth packets getting queued.
38986 + if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) {
38987 + hcd->core_if->queuing_high_bandwidth = 1;
38989 + status = queue_transaction(hcd, qh->channel,
38990 + tx_status.b.ptxfspcavail);
38991 + if (status < 0) {
38992 + no_fifo_space = 1;
38998 + * In Slave mode, stay on the current transfer until there is
38999 + * nothing more to do or the high-bandwidth request count is
39000 + * reached. In DMA mode, only need to queue one request. The
39001 + * controller automatically handles multiple packets for
39002 + * high-bandwidth transfers.
39004 + if (hcd->core_if->dma_enable || status == 0 ||
39005 + qh->channel->requests == qh->channel->multi_count) {
39006 + qh_ptr = qh_ptr->next;
39008 + * Move the QH from the periodic assigned schedule to
39009 + * the periodic queued schedule.
39011 + DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued,
39012 + &qh->qh_list_entry);
39014 + /* done queuing high bandwidth */
39015 + hcd->core_if->queuing_high_bandwidth = 0;
39019 + if (!hcd->core_if->dma_enable) {
39020 + dwc_otg_core_global_regs_t *global_regs;
39021 + gintmsk_data_t intr_mask = {.d32 = 0 };
39023 + global_regs = hcd->core_if->core_global_regs;
39024 + intr_mask.b.ptxfempty = 1;
39026 + tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
39027 + DWC_DEBUGPL(DBG_HCDV,
39028 + " P Tx Req Queue Space Avail (after queue): %d\n",
39029 + tx_status.b.ptxqspcavail);
39030 + DWC_DEBUGPL(DBG_HCDV,
39031 + " P Tx FIFO Space Avail (after queue): %d\n",
39032 + tx_status.b.ptxfspcavail);
39034 + if (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) ||
39035 + no_queue_space || no_fifo_space) {
39037 + * May need to queue more transactions as the request
39038 + * queue or Tx FIFO empties. Enable the periodic Tx
39039 + * FIFO empty interrupt. (Always use the half-empty
39040 + * level to ensure that new requests are loaded as
39041 + * soon as possible.)
39043 + DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
39047 + * Disable the Tx FIFO empty interrupt since there are
39048 + * no more transactions that need to be queued right
39049 + * now. This function is called from interrupt
39050 + * handlers to queue more transactions as transfer
39053 + DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
39060 + * Processes active non-periodic channels and queues transactions for these
39061 + * channels to the DWC_otg controller. After queueing transactions, the NP Tx
39062 + * FIFO Empty interrupt is enabled if there are more transactions to queue as
39063 + * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
39064 + * FIFO Empty interrupt is disabled.
39066 +static void process_non_periodic_channels(dwc_otg_hcd_t * hcd)
39068 + gnptxsts_data_t tx_status;
39069 + dwc_list_link_t *orig_qh_ptr;
39070 + dwc_otg_qh_t *qh;
39072 + int no_queue_space = 0;
39073 + int no_fifo_space = 0;
39074 + int more_to_do = 0;
39076 + dwc_otg_core_global_regs_t *global_regs =
39077 + hcd->core_if->core_global_regs;
39079 + DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
39081 + tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
39082 + DWC_DEBUGPL(DBG_HCDV,
39083 + " NP Tx Req Queue Space Avail (before queue): %d\n",
39084 + tx_status.b.nptxqspcavail);
39085 + DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (before queue): %d\n",
39086 + tx_status.b.nptxfspcavail);
39089 + * Keep track of the starting point. Skip over the start-of-list
39092 + if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
39093 + hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
39095 + orig_qh_ptr = hcd->non_periodic_qh_ptr;
39098 + * Process once through the active list or until no more space is
39099 + * available in the request queue or the Tx FIFO.
39102 + tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
39103 + if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
39104 + no_queue_space = 1;
39108 + qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t,
39111 + if(fiq_fsm_enable && fiq_fsm_transaction_suitable(hcd, qh)) {
39112 + fiq_fsm_queue_split_transaction(hcd, qh);
39114 + status = queue_transaction(hcd, qh->channel,
39115 + tx_status.b.nptxfspcavail);
39117 + if (status > 0) {
39119 + } else if (status < 0) {
39120 + no_fifo_space = 1;
39124 + /* Advance to next QH, skipping start-of-list entry. */
39125 + hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
39126 + if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
39127 + hcd->non_periodic_qh_ptr =
39128 + hcd->non_periodic_qh_ptr->next;
39131 + } while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
39133 + if (!hcd->core_if->dma_enable) {
39134 + gintmsk_data_t intr_mask = {.d32 = 0 };
39135 + intr_mask.b.nptxfempty = 1;
39138 + tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
39139 + DWC_DEBUGPL(DBG_HCDV,
39140 + " NP Tx Req Queue Space Avail (after queue): %d\n",
39141 + tx_status.b.nptxqspcavail);
39142 + DWC_DEBUGPL(DBG_HCDV,
39143 + " NP Tx FIFO Space Avail (after queue): %d\n",
39144 + tx_status.b.nptxfspcavail);
39146 + if (more_to_do || no_queue_space || no_fifo_space) {
39148 + * May need to queue more transactions as the request
39149 + * queue or Tx FIFO empties. Enable the non-periodic
39150 + * Tx FIFO empty interrupt. (Always use the half-empty
39151 + * level to ensure that new requests are loaded as
39152 + * soon as possible.)
39154 + DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
39158 + * Disable the Tx FIFO empty interrupt since there are
39159 + * no more transactions that need to be queued right
39160 + * now. This function is called from interrupt
39161 + * handlers to queue more transactions as transfer
39164 + DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
39171 + * This function processes the currently active host channels and queues
39172 + * transactions for these channels to the DWC_otg controller. It is called
39173 + * from HCD interrupt handler functions.
39175 + * @param hcd The HCD state structure.
39176 + * @param tr_type The type(s) of transactions to queue (non-periodic,
39177 + * periodic, or both).
39179 +void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
39180 + dwc_otg_transaction_type_e tr_type)
39183 + DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
39185 + /* Process host channels associated with periodic transfers. */
39186 + if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
39187 + tr_type == DWC_OTG_TRANSACTION_ALL) &&
39188 + !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) {
39190 + process_periodic_channels(hcd);
39193 + /* Process host channels associated with non-periodic transfers. */
39194 + if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
39195 + tr_type == DWC_OTG_TRANSACTION_ALL) {
39196 + if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) {
39197 + process_non_periodic_channels(hcd);
39200 + * Ensure NP Tx FIFO empty interrupt is disabled when
39201 + * there are no non-periodic transfers to process.
39203 + gintmsk_data_t gintmsk = {.d32 = 0 };
39204 + gintmsk.b.nptxfempty = 1;
39206 + if (fiq_enable) {
39207 + local_fiq_disable();
39208 + fiq_fsm_spin_lock(&hcd->fiq_state->lock);
39209 + DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
39210 + fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
39211 + local_fiq_enable();
39213 + DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
39219 +#ifdef DWC_HS_ELECT_TST
39221 + * Quick and dirty hack to implement the HS Electrical Test
39222 + * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
39224 + * This code was copied from our userspace app "hset". It sends a
39225 + * Get Device Descriptor control sequence in two parts, first the
39226 + * Setup packet by itself, followed some time later by the In and
39227 + * Ack packets. Rather than trying to figure out how to add this
39228 + * functionality to the normal driver code, we just hijack the
39229 + * hardware, using these two function to drive the hardware
39233 +static dwc_otg_core_global_regs_t *global_regs;
39234 +static dwc_otg_host_global_regs_t *hc_global_regs;
39235 +static dwc_otg_hc_regs_t *hc_regs;
39236 +static uint32_t *data_fifo;
39238 +static void do_setup(void)
39240 + gintsts_data_t gintsts;
39241 + hctsiz_data_t hctsiz;
39242 + hcchar_data_t hcchar;
39243 + haint_data_t haint;
39244 + hcint_data_t hcint;
39246 + /* Enable HAINTs */
39247 + DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
39249 + /* Enable HCINTs */
39250 + DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
39252 + /* Read GINTSTS */
39253 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39256 + haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
39259 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
39261 + /* Read HCCHAR */
39262 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39264 + /* Clear HCINT */
39265 + DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
39267 + /* Clear HAINT */
39268 + DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
39270 + /* Clear GINTSTS */
39271 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
39273 + /* Read GINTSTS */
39274 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39277 + * Send Setup packet (Get Device Descriptor)
39280 + /* Make sure channel is disabled */
39281 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39282 + if (hcchar.b.chen) {
39283 + hcchar.b.chdis = 1;
39284 +// hcchar.b.chen = 1;
39285 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
39287 + dwc_mdelay(1000);
39289 + /* Read GINTSTS */
39290 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39293 + haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
39296 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
39298 + /* Read HCCHAR */
39299 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39301 + /* Clear HCINT */
39302 + DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
39304 + /* Clear HAINT */
39305 + DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
39307 + /* Clear GINTSTS */
39308 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
39310 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39315 + hctsiz.b.xfersize = 8;
39316 + hctsiz.b.pktcnt = 1;
39317 + hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
39318 + DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
39321 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39322 + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
39323 + hcchar.b.epdir = 0;
39324 + hcchar.b.epnum = 0;
39325 + hcchar.b.mps = 8;
39326 + hcchar.b.chen = 1;
39327 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
39329 + /* Fill FIFO with Setup data for Get Device Descriptor */
39330 + data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
39331 + DWC_WRITE_REG32(data_fifo++, 0x01000680);
39332 + DWC_WRITE_REG32(data_fifo++, 0x00080000);
39334 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39336 + /* Wait for host channel interrupt */
39338 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39339 + } while (gintsts.b.hcintr == 0);
39341 + /* Disable HCINTs */
39342 + DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
39344 + /* Disable HAINTs */
39345 + DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
39348 + haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
39351 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
39353 + /* Read HCCHAR */
39354 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39356 + /* Clear HCINT */
39357 + DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
39359 + /* Clear HAINT */
39360 + DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
39362 + /* Clear GINTSTS */
39363 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
39365 + /* Read GINTSTS */
39366 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39369 +static void do_in_ack(void)
39371 + gintsts_data_t gintsts;
39372 + hctsiz_data_t hctsiz;
39373 + hcchar_data_t hcchar;
39374 + haint_data_t haint;
39375 + hcint_data_t hcint;
39376 + host_grxsts_data_t grxsts;
39378 + /* Enable HAINTs */
39379 + DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
39381 + /* Enable HCINTs */
39382 + DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
39384 + /* Read GINTSTS */
39385 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39388 + haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
39391 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
39393 + /* Read HCCHAR */
39394 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39396 + /* Clear HCINT */
39397 + DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
39399 + /* Clear HAINT */
39400 + DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
39402 + /* Clear GINTSTS */
39403 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
39405 + /* Read GINTSTS */
39406 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39409 + * Receive Control In packet
39412 + /* Make sure channel is disabled */
39413 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39414 + if (hcchar.b.chen) {
39415 + hcchar.b.chdis = 1;
39416 + hcchar.b.chen = 1;
39417 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
39419 + dwc_mdelay(1000);
39421 + /* Read GINTSTS */
39422 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39425 + haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
39428 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
39430 + /* Read HCCHAR */
39431 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39433 + /* Clear HCINT */
39434 + DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
39436 + /* Clear HAINT */
39437 + DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
39439 + /* Clear GINTSTS */
39440 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
39442 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39447 + hctsiz.b.xfersize = 8;
39448 + hctsiz.b.pktcnt = 1;
39449 + hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
39450 + DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
39453 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39454 + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
39455 + hcchar.b.epdir = 1;
39456 + hcchar.b.epnum = 0;
39457 + hcchar.b.mps = 8;
39458 + hcchar.b.chen = 1;
39459 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
39461 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39463 + /* Wait for receive status queue interrupt */
39465 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39466 + } while (gintsts.b.rxstsqlvl == 0);
39469 + grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
39471 + /* Clear RXSTSQLVL in GINTSTS */
39473 + gintsts.b.rxstsqlvl = 1;
39474 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
39476 + switch (grxsts.b.pktsts) {
39477 + case DWC_GRXSTS_PKTSTS_IN:
39478 + /* Read the data into the host buffer */
39479 + if (grxsts.b.bcnt > 0) {
39481 + int word_count = (grxsts.b.bcnt + 3) / 4;
39483 + data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
39485 + for (i = 0; i < word_count; i++) {
39486 + (void)DWC_READ_REG32(data_fifo++);
39495 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39497 + /* Wait for receive status queue interrupt */
39499 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39500 + } while (gintsts.b.rxstsqlvl == 0);
39503 + grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
39505 + /* Clear RXSTSQLVL in GINTSTS */
39507 + gintsts.b.rxstsqlvl = 1;
39508 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
39510 + switch (grxsts.b.pktsts) {
39511 + case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
39518 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39520 + /* Wait for host channel interrupt */
39522 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39523 + } while (gintsts.b.hcintr == 0);
39526 + haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
39529 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
39531 + /* Read HCCHAR */
39532 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39534 + /* Clear HCINT */
39535 + DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
39537 + /* Clear HAINT */
39538 + DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
39540 + /* Clear GINTSTS */
39541 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
39543 + /* Read GINTSTS */
39544 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39546 +// usleep(100000);
39551 + * Send handshake packet
39555 + haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
39558 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
39560 + /* Read HCCHAR */
39561 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39563 + /* Clear HCINT */
39564 + DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
39566 + /* Clear HAINT */
39567 + DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
39569 + /* Clear GINTSTS */
39570 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
39572 + /* Read GINTSTS */
39573 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39575 + /* Make sure channel is disabled */
39576 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39577 + if (hcchar.b.chen) {
39578 + hcchar.b.chdis = 1;
39579 + hcchar.b.chen = 1;
39580 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
39582 + dwc_mdelay(1000);
39584 + /* Read GINTSTS */
39585 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39588 + haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
39591 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
39593 + /* Read HCCHAR */
39594 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39596 + /* Clear HCINT */
39597 + DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
39599 + /* Clear HAINT */
39600 + DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
39602 + /* Clear GINTSTS */
39603 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
39605 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39610 + hctsiz.b.xfersize = 0;
39611 + hctsiz.b.pktcnt = 1;
39612 + hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
39613 + DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
39616 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39617 + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
39618 + hcchar.b.epdir = 0;
39619 + hcchar.b.epnum = 0;
39620 + hcchar.b.mps = 8;
39621 + hcchar.b.chen = 1;
39622 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
39624 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39626 + /* Wait for host channel interrupt */
39628 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39629 + } while (gintsts.b.hcintr == 0);
39631 + /* Disable HCINTs */
39632 + DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
39634 + /* Disable HAINTs */
39635 + DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
39638 + haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
39641 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
39643 + /* Read HCCHAR */
39644 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39646 + /* Clear HCINT */
39647 + DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
39649 + /* Clear HAINT */
39650 + DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
39652 + /* Clear GINTSTS */
39653 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
39655 + /* Read GINTSTS */
39656 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39660 +/** Handles hub class-specific requests. */
39661 +int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
39662 + uint16_t typeReq,
39664 + uint16_t wIndex, uint8_t * buf, uint16_t wLength)
39668 + dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
39669 + usb_hub_descriptor_t *hub_desc;
39670 + hprt0_data_t hprt0 = {.d32 = 0 };
39672 + uint32_t port_status;
39674 + switch (typeReq) {
39675 + case UCR_CLEAR_HUB_FEATURE:
39676 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39677 + "ClearHubFeature 0x%x\n", wValue);
39678 + switch (wValue) {
39679 + case UHF_C_HUB_LOCAL_POWER:
39680 + case UHF_C_HUB_OVER_CURRENT:
39681 + /* Nothing required here */
39684 + retval = -DWC_E_INVALID;
39685 + DWC_ERROR("DWC OTG HCD - "
39686 + "ClearHubFeature request %xh unknown\n",
39690 + case UCR_CLEAR_PORT_FEATURE:
39691 +#ifdef CONFIG_USB_DWC_OTG_LPM
39692 + if (wValue != UHF_PORT_L1)
39694 + if (!wIndex || wIndex > 1)
39697 + switch (wValue) {
39698 + case UHF_PORT_ENABLE:
39699 + DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
39700 + "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
39701 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
39702 + hprt0.b.prtena = 1;
39703 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
39705 + case UHF_PORT_SUSPEND:
39706 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39707 + "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
39709 + if (core_if->power_down == 2) {
39710 + dwc_otg_host_hibernation_restore(core_if, 0, 0);
39712 + DWC_WRITE_REG32(core_if->pcgcctl, 0);
39715 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
39716 + hprt0.b.prtres = 1;
39717 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
39718 + hprt0.b.prtsusp = 0;
39719 + /* Clear Resume bit */
39721 + hprt0.b.prtres = 0;
39722 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
39725 +#ifdef CONFIG_USB_DWC_OTG_LPM
39726 + case UHF_PORT_L1:
39728 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
39729 + glpmcfg_data_t lpmcfg = {.d32 = 0 };
39732 + DWC_READ_REG32(&core_if->
39733 + core_global_regs->glpmcfg);
39734 + lpmcfg.b.en_utmi_sleep = 0;
39735 + lpmcfg.b.hird_thres &= (~(1 << 4));
39736 + lpmcfg.b.prt_sleep_sts = 1;
39737 + DWC_WRITE_REG32(&core_if->
39738 + core_global_regs->glpmcfg,
39741 + /* Clear Enbl_L1Gating bit. */
39742 + pcgcctl.b.enbl_sleep_gating = 1;
39743 + DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
39748 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
39749 + hprt0.b.prtres = 1;
39750 + DWC_WRITE_REG32(core_if->host_if->hprt0,
39752 + /* This bit will be cleared in wakeup interrupt handle */
39756 + case UHF_PORT_POWER:
39757 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39758 + "ClearPortFeature USB_PORT_FEAT_POWER\n");
39759 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
39760 + hprt0.b.prtpwr = 0;
39761 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
39763 + case UHF_PORT_INDICATOR:
39764 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39765 + "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
39766 + /* Port inidicator not supported */
39768 + case UHF_C_PORT_CONNECTION:
39769 + /* Clears drivers internal connect status change
39771 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39772 + "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
39773 + dwc_otg_hcd->flags.b.port_connect_status_change = 0;
39775 + case UHF_C_PORT_RESET:
39776 + /* Clears the driver's internal Port Reset Change
39778 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39779 + "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
39780 + dwc_otg_hcd->flags.b.port_reset_change = 0;
39782 + case UHF_C_PORT_ENABLE:
39783 + /* Clears the driver's internal Port
39784 + * Enable/Disable Change flag */
39785 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39786 + "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
39787 + dwc_otg_hcd->flags.b.port_enable_change = 0;
39789 + case UHF_C_PORT_SUSPEND:
39790 + /* Clears the driver's internal Port Suspend
39791 + * Change flag, which is set when resume signaling on
39792 + * the host port is complete */
39793 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39794 + "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
39795 + dwc_otg_hcd->flags.b.port_suspend_change = 0;
39797 +#ifdef CONFIG_USB_DWC_OTG_LPM
39798 + case UHF_C_PORT_L1:
39799 + dwc_otg_hcd->flags.b.port_l1_change = 0;
39802 + case UHF_C_PORT_OVER_CURRENT:
39803 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39804 + "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
39805 + dwc_otg_hcd->flags.b.port_over_current_change = 0;
39808 + retval = -DWC_E_INVALID;
39809 + DWC_ERROR("DWC OTG HCD - "
39810 + "ClearPortFeature request %xh "
39811 + "unknown or unsupported\n", wValue);
39814 + case UCR_GET_HUB_DESCRIPTOR:
39815 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39816 + "GetHubDescriptor\n");
39817 + hub_desc = (usb_hub_descriptor_t *) buf;
39818 + hub_desc->bDescLength = 9;
39819 + hub_desc->bDescriptorType = 0x29;
39820 + hub_desc->bNbrPorts = 1;
39821 + USETW(hub_desc->wHubCharacteristics, 0x08);
39822 + hub_desc->bPwrOn2PwrGood = 1;
39823 + hub_desc->bHubContrCurrent = 0;
39824 + hub_desc->DeviceRemovable[0] = 0;
39825 + hub_desc->DeviceRemovable[1] = 0xff;
39827 + case UCR_GET_HUB_STATUS:
39828 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39829 + "GetHubStatus\n");
39830 + DWC_MEMSET(buf, 0, 4);
39832 + case UCR_GET_PORT_STATUS:
39833 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39834 + "GetPortStatus wIndex = 0x%04x FLAGS=0x%08x\n",
39835 + wIndex, dwc_otg_hcd->flags.d32);
39836 + if (!wIndex || wIndex > 1)
39841 + if (dwc_otg_hcd->flags.b.port_connect_status_change)
39842 + port_status |= (1 << UHF_C_PORT_CONNECTION);
39844 + if (dwc_otg_hcd->flags.b.port_enable_change)
39845 + port_status |= (1 << UHF_C_PORT_ENABLE);
39847 + if (dwc_otg_hcd->flags.b.port_suspend_change)
39848 + port_status |= (1 << UHF_C_PORT_SUSPEND);
39850 + if (dwc_otg_hcd->flags.b.port_l1_change)
39851 + port_status |= (1 << UHF_C_PORT_L1);
39853 + if (dwc_otg_hcd->flags.b.port_reset_change) {
39854 + port_status |= (1 << UHF_C_PORT_RESET);
39857 + if (dwc_otg_hcd->flags.b.port_over_current_change) {
39858 + DWC_WARN("Overcurrent change detected\n");
39859 + port_status |= (1 << UHF_C_PORT_OVER_CURRENT);
39862 + if (!dwc_otg_hcd->flags.b.port_connect_status) {
39864 + * The port is disconnected, which means the core is
39865 + * either in device mode or it soon will be. Just
39866 + * return 0's for the remainder of the port status
39867 + * since the port register can't be read if the core
39868 + * is in device mode.
39870 + *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
39874 + hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
39875 + DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32);
39877 + if (hprt0.b.prtconnsts)
39878 + port_status |= (1 << UHF_PORT_CONNECTION);
39880 + if (hprt0.b.prtena)
39881 + port_status |= (1 << UHF_PORT_ENABLE);
39883 + if (hprt0.b.prtsusp)
39884 + port_status |= (1 << UHF_PORT_SUSPEND);
39886 + if (hprt0.b.prtovrcurract)
39887 + port_status |= (1 << UHF_PORT_OVER_CURRENT);
39889 + if (hprt0.b.prtrst)
39890 + port_status |= (1 << UHF_PORT_RESET);
39892 + if (hprt0.b.prtpwr)
39893 + port_status |= (1 << UHF_PORT_POWER);
39895 + if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
39896 + port_status |= (1 << UHF_PORT_HIGH_SPEED);
39897 + else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
39898 + port_status |= (1 << UHF_PORT_LOW_SPEED);
39900 + if (hprt0.b.prttstctl)
39901 + port_status |= (1 << UHF_PORT_TEST);
39902 + if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) {
39903 + port_status |= (1 << UHF_PORT_L1);
39906 + For Synopsys HW emulation of Power down wkup_control asserts the
39907 + hreset_n and prst_n on suspned. This causes the HPRT0 to be zero.
39908 + We intentionally tell the software that port is in L2Suspend state.
39911 + if ((core_if->power_down == 2)
39912 + && (core_if->hibernation_suspend == 1)) {
39913 + port_status |= (1 << UHF_PORT_SUSPEND);
39915 + /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
39917 + *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
39920 + case UCR_SET_HUB_FEATURE:
39921 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39922 + "SetHubFeature\n");
39923 + /* No HUB features supported */
39925 + case UCR_SET_PORT_FEATURE:
39926 + if (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1))
39929 + if (!dwc_otg_hcd->flags.b.port_connect_status) {
39931 + * The port is disconnected, which means the core is
39932 + * either in device mode or it soon will be. Just
39933 + * return without doing anything since the port
39934 + * register can't be written if the core is in device
39940 + switch (wValue) {
39941 + case UHF_PORT_SUSPEND:
39942 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39943 + "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
39944 + if (dwc_otg_hcd_otg_port(dwc_otg_hcd) != wIndex) {
39947 + if (core_if->power_down == 2) {
39948 + int timeout = 300;
39949 + dwc_irqflags_t flags;
39950 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
39951 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
39952 + gusbcfg_data_t gusbcfg = {.d32 = 0 };
39953 +#ifdef DWC_DEV_SRPCAP
39954 + int32_t otg_cap_param = core_if->core_params->otg_cap;
39956 + DWC_PRINTF("Preparing for complete power-off\n");
39958 + /* Save registers before hibernation */
39959 + dwc_otg_save_global_regs(core_if);
39960 + dwc_otg_save_host_regs(core_if);
39962 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
39963 + hprt0.b.prtsusp = 1;
39964 + hprt0.b.prtena = 0;
39965 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
39966 + /* Spin hprt0.b.prtsusp to became 1 */
39968 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
39969 + if (hprt0.b.prtsusp) {
39973 + } while (--timeout);
39975 + DWC_WARN("Suspend wasn't genereted\n");
39980 + * We need to disable interrupts to prevent servicing of any IRQ
39981 + * during going to hibernation
39983 + DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
39984 + core_if->lx_state = DWC_OTG_L2;
39985 +#ifdef DWC_DEV_SRPCAP
39986 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
39987 + hprt0.b.prtpwr = 0;
39988 + hprt0.b.prtena = 0;
39989 + DWC_WRITE_REG32(core_if->host_if->hprt0,
39993 + DWC_READ_REG32(&core_if->core_global_regs->
39995 + if (gusbcfg.b.ulpi_utmi_sel == 1) {
39996 + /* ULPI interface */
39997 + /* Suspend the Phy Clock */
39999 + pcgcctl.b.stoppclk = 1;
40000 + DWC_MODIFY_REG32(core_if->pcgcctl, 0,
40003 + gpwrdn.b.pmuactv = 1;
40004 + DWC_MODIFY_REG32(&core_if->
40005 + core_global_regs->
40006 + gpwrdn, 0, gpwrdn.d32);
40008 + /* UTMI+ Interface */
40009 + gpwrdn.b.pmuactv = 1;
40010 + DWC_MODIFY_REG32(&core_if->
40011 + core_global_regs->
40012 + gpwrdn, 0, gpwrdn.d32);
40014 + pcgcctl.b.stoppclk = 1;
40015 + DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
40018 +#ifdef DWC_DEV_SRPCAP
40020 + gpwrdn.b.dis_vbus = 1;
40021 + DWC_MODIFY_REG32(&core_if->core_global_regs->
40022 + gpwrdn, 0, gpwrdn.d32);
40025 + gpwrdn.b.pmuintsel = 1;
40026 + DWC_MODIFY_REG32(&core_if->core_global_regs->
40027 + gpwrdn, 0, gpwrdn.d32);
40031 +#ifdef DWC_DEV_SRPCAP
40032 + gpwrdn.b.srp_det_msk = 1;
40034 + gpwrdn.b.disconn_det_msk = 1;
40035 + gpwrdn.b.lnstchng_msk = 1;
40036 + gpwrdn.b.sts_chngint_msk = 1;
40037 + DWC_MODIFY_REG32(&core_if->core_global_regs->
40038 + gpwrdn, 0, gpwrdn.d32);
40041 + /* Enable Power Down Clamp and all interrupts in GPWRDN */
40043 + gpwrdn.b.pwrdnclmp = 1;
40044 + DWC_MODIFY_REG32(&core_if->core_global_regs->
40045 + gpwrdn, 0, gpwrdn.d32);
40048 + /* Switch off VDD */
40050 + gpwrdn.b.pwrdnswtch = 1;
40051 + DWC_MODIFY_REG32(&core_if->core_global_regs->
40052 + gpwrdn, 0, gpwrdn.d32);
40054 +#ifdef DWC_DEV_SRPCAP
40055 + if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE)
40057 + core_if->pwron_timer_started = 1;
40058 + DWC_TIMER_SCHEDULE(core_if->pwron_timer, 6000 /* 6 secs */ );
40061 + /* Save gpwrdn register for further usage if stschng interrupt */
40062 + core_if->gr_backup->gpwrdn_local =
40063 + DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
40065 + /* Set flag to indicate that we are in hibernation */
40066 + core_if->hibernation_suspend = 1;
40067 + DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,flags);
40069 + DWC_PRINTF("Host hibernation completed\n");
40070 + // Exit from case statement
40074 + if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex &&
40075 + dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
40076 + gotgctl_data_t gotgctl = {.d32 = 0 };
40077 + gotgctl.b.hstsethnpen = 1;
40078 + DWC_MODIFY_REG32(&core_if->core_global_regs->
40079 + gotgctl, 0, gotgctl.d32);
40080 + core_if->op_state = A_SUSPEND;
40082 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
40083 + hprt0.b.prtsusp = 1;
40084 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
40086 + dwc_irqflags_t flags;
40087 + /* Update lx_state */
40088 + DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
40089 + core_if->lx_state = DWC_OTG_L2;
40090 + DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
40092 + /* Suspend the Phy Clock */
40094 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
40095 + pcgcctl.b.stoppclk = 1;
40096 + DWC_MODIFY_REG32(core_if->pcgcctl, 0,
40101 + /* For HNP the bus must be suspended for at least 200ms. */
40102 + if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
40103 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
40104 + pcgcctl.b.stoppclk = 1;
40105 + DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
40109 + /** @todo - check how sw can wait for 1 sec to check asesvld??? */
40110 +#if 0 //vahrama !!!!!!!!!!!!!!!!!!
40111 + if (core_if->adp_enable) {
40112 + gotgctl_data_t gotgctl = {.d32 = 0 };
40113 + gpwrdn_data_t gpwrdn;
40115 + while (gotgctl.b.asesvld == 1) {
40117 + DWC_READ_REG32(&core_if->
40118 + core_global_regs->
40123 + /* Enable Power Down Logic */
40125 + gpwrdn.b.pmuactv = 1;
40126 + DWC_MODIFY_REG32(&core_if->core_global_regs->
40127 + gpwrdn, 0, gpwrdn.d32);
40129 + /* Unmask SRP detected interrupt from Power Down Logic */
40131 + gpwrdn.b.srp_det_msk = 1;
40132 + DWC_MODIFY_REG32(&core_if->core_global_regs->
40133 + gpwrdn, 0, gpwrdn.d32);
40135 + dwc_otg_adp_probe_start(core_if);
40139 + case UHF_PORT_POWER:
40140 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
40141 + "SetPortFeature - USB_PORT_FEAT_POWER\n");
40142 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
40143 + hprt0.b.prtpwr = 1;
40144 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
40146 + case UHF_PORT_RESET:
40147 + if ((core_if->power_down == 2)
40148 + && (core_if->hibernation_suspend == 1)) {
40149 + /* If we are going to exit from Hibernated
40150 + * state via USB RESET.
40152 + dwc_otg_host_hibernation_restore(core_if, 0, 1);
40154 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
40156 + DWC_DEBUGPL(DBG_HCD,
40157 + "DWC OTG HCD HUB CONTROL - "
40158 + "SetPortFeature - USB_PORT_FEAT_RESET\n");
40160 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
40161 + pcgcctl.b.enbl_sleep_gating = 1;
40162 + pcgcctl.b.stoppclk = 1;
40163 + DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
40164 + DWC_WRITE_REG32(core_if->pcgcctl, 0);
40166 +#ifdef CONFIG_USB_DWC_OTG_LPM
40168 + glpmcfg_data_t lpmcfg;
40170 + DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
40171 + if (lpmcfg.b.prt_sleep_sts) {
40172 + lpmcfg.b.en_utmi_sleep = 0;
40173 + lpmcfg.b.hird_thres &= (~(1 << 4));
40175 + (&core_if->core_global_regs->glpmcfg,
40181 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
40182 + /* Clear suspend bit if resetting from suspended state. */
40183 + hprt0.b.prtsusp = 0;
40184 + /* When B-Host the Port reset bit is set in
40185 + * the Start HCD Callback function, so that
40186 + * the reset is started within 1ms of the HNP
40187 + * success interrupt. */
40188 + if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) {
40189 + hprt0.b.prtpwr = 1;
40190 + hprt0.b.prtrst = 1;
40191 + DWC_PRINTF("Indeed it is in host mode hprt0 = %08x\n",hprt0.d32);
40192 + DWC_WRITE_REG32(core_if->host_if->hprt0,
40195 + /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
40197 + hprt0.b.prtrst = 0;
40198 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
40199 + core_if->lx_state = DWC_OTG_L0; /* Now back to the on state */
40202 +#ifdef DWC_HS_ELECT_TST
40203 + case UHF_PORT_TEST:
40206 + gintmsk_data_t gintmsk;
40208 + t = (wIndex >> 8); /* MSB wIndex USB */
40209 + DWC_DEBUGPL(DBG_HCD,
40210 + "DWC OTG HCD HUB CONTROL - "
40211 + "SetPortFeature - USB_PORT_FEAT_TEST %d\n",
40213 + DWC_WARN("USB_PORT_FEAT_TEST %d\n", t);
40215 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
40216 + hprt0.b.prttstctl = t;
40217 + DWC_WRITE_REG32(core_if->host_if->hprt0,
40220 + /* Setup global vars with reg addresses (quick and
40221 + * dirty hack, should be cleaned up)
40223 + global_regs = core_if->core_global_regs;
40225 + core_if->host_if->host_global_regs;
40227 + (dwc_otg_hc_regs_t *) ((char *)
40231 + (uint32_t *) ((char *)global_regs +
40234 + if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */
40235 + /* Save current interrupt mask */
40238 + (&global_regs->gintmsk);
40240 + /* Disable all interrupts while we muck with
40241 + * the hardware directly
40243 + DWC_WRITE_REG32(&global_regs->gintmsk, 0);
40245 + /* 15 second delay per the test spec */
40246 + dwc_mdelay(15000);
40248 + /* Drive suspend on the root port */
40250 + dwc_otg_read_hprt0(core_if);
40251 + hprt0.b.prtsusp = 1;
40252 + hprt0.b.prtres = 0;
40253 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
40255 + /* 15 second delay per the test spec */
40256 + dwc_mdelay(15000);
40258 + /* Drive resume on the root port */
40260 + dwc_otg_read_hprt0(core_if);
40261 + hprt0.b.prtsusp = 0;
40262 + hprt0.b.prtres = 1;
40263 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
40266 + /* Clear the resume bit */
40267 + hprt0.b.prtres = 0;
40268 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
40270 + /* Restore interrupts */
40271 + DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
40272 + } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
40273 + /* Save current interrupt mask */
40276 + (&global_regs->gintmsk);
40278 + /* Disable all interrupts while we muck with
40279 + * the hardware directly
40281 + DWC_WRITE_REG32(&global_regs->gintmsk, 0);
40283 + /* 15 second delay per the test spec */
40284 + dwc_mdelay(15000);
40286 + /* Send the Setup packet */
40289 + /* 15 second delay so nothing else happens for awhile */
40290 + dwc_mdelay(15000);
40292 + /* Restore interrupts */
40293 + DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
40294 + } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
40295 + /* Save current interrupt mask */
40298 + (&global_regs->gintmsk);
40300 + /* Disable all interrupts while we muck with
40301 + * the hardware directly
40303 + DWC_WRITE_REG32(&global_regs->gintmsk, 0);
40305 + /* Send the Setup packet */
40308 + /* 15 second delay so nothing else happens for awhile */
40309 + dwc_mdelay(15000);
40311 + /* Send the In and Ack packets */
40314 + /* 15 second delay so nothing else happens for awhile */
40315 + dwc_mdelay(15000);
40317 + /* Restore interrupts */
40318 + DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
40323 +#endif /* DWC_HS_ELECT_TST */
40325 + case UHF_PORT_INDICATOR:
40326 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
40327 + "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
40328 + /* Not supported */
40331 + retval = -DWC_E_INVALID;
40332 + DWC_ERROR("DWC OTG HCD - "
40333 + "SetPortFeature request %xh "
40334 + "unknown or unsupported\n", wValue);
40338 +#ifdef CONFIG_USB_DWC_OTG_LPM
40339 + case UCR_SET_AND_TEST_PORT_FEATURE:
40340 + if (wValue != UHF_PORT_L1) {
40344 + int portnum, hird, devaddr, remwake;
40345 + glpmcfg_data_t lpmcfg;
40346 + uint32_t time_usecs;
40347 + gintsts_data_t gintsts;
40348 + gintmsk_data_t gintmsk;
40350 + if (!dwc_otg_get_param_lpm_enable(core_if)) {
40353 + if (wValue != UHF_PORT_L1 || wLength != 1) {
40356 + /* Check if the port currently is in SLEEP state */
40358 + DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
40359 + if (lpmcfg.b.prt_sleep_sts) {
40360 + DWC_INFO("Port is already in sleep mode\n");
40361 + buf[0] = 0; /* Return success */
40365 + portnum = wIndex & 0xf;
40366 + hird = (wIndex >> 4) & 0xf;
40367 + devaddr = (wIndex >> 8) & 0x7f;
40368 + remwake = (wIndex >> 15);
40370 + if (portnum != 1) {
40371 + retval = -DWC_E_INVALID;
40373 + ("Wrong port number(%d) in SetandTestPortFeature request\n",
40379 + ("SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n",
40380 + portnum, hird, devaddr, remwake);
40381 + /* Disable LPM interrupt */
40383 + gintmsk.b.lpmtranrcvd = 1;
40384 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
40387 + if (dwc_otg_hcd_send_lpm
40388 + (dwc_otg_hcd, devaddr, hird, remwake)) {
40389 + retval = -DWC_E_INVALID;
40393 + time_usecs = 10 * (lpmcfg.b.retry_count + 1);
40394 + /* We will consider timeout if time_usecs microseconds pass,
40395 + * and we don't receive LPM transaction status.
40396 + * After receiving non-error responce(ACK/NYET/STALL) from device,
40397 + * core will set lpmtranrcvd bit.
40401 + DWC_READ_REG32(&core_if->core_global_regs->gintsts);
40402 + if (gintsts.b.lpmtranrcvd) {
40406 + } while (--time_usecs);
40407 + /* lpm_int bit will be cleared in LPM interrupt handler */
40409 + /* Now fill status
40414 + if (!gintsts.b.lpmtranrcvd) {
40415 + buf[0] = 0x3; /* Completion code is Timeout */
40416 + dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd);
40419 + DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
40420 + if (lpmcfg.b.lpm_resp == 0x3) {
40421 + /* ACK responce from the device */
40422 + buf[0] = 0x00; /* Success */
40423 + } else if (lpmcfg.b.lpm_resp == 0x2) {
40424 + /* NYET responce from the device */
40427 + /* Otherwise responce with Timeout */
40431 + DWC_PRINTF("Device responce to LPM trans is %x\n",
40432 + lpmcfg.b.lpm_resp);
40433 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0,
40438 +#endif /* CONFIG_USB_DWC_OTG_LPM */
40441 + retval = -DWC_E_INVALID;
40442 + DWC_WARN("DWC OTG HCD - "
40443 + "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
40444 + typeReq, wIndex, wValue);
40451 +#ifdef CONFIG_USB_DWC_OTG_LPM
40452 +/** Returns index of host channel to perform LPM transaction. */
40453 +int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd, uint8_t devaddr)
40455 + dwc_otg_core_if_t *core_if = hcd->core_if;
40457 + hcchar_data_t hcchar;
40458 + gintmsk_data_t gintmsk = {.d32 = 0 };
40460 + if (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
40461 + DWC_PRINTF("No free channel to select for LPM transaction\n");
40465 + hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
40467 + /* Mask host channel interrupts. */
40468 + gintmsk.b.hcintr = 1;
40469 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
40471 + /* Fill fields that core needs for LPM transaction */
40472 + hcchar.b.devaddr = devaddr;
40473 + hcchar.b.epnum = 0;
40474 + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
40475 + hcchar.b.mps = 64;
40476 + hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
40477 + hcchar.b.epdir = 0; /* OUT */
40478 + DWC_WRITE_REG32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar,
40481 + /* Remove the host channel from the free list. */
40482 + DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
40484 + DWC_PRINTF("hcnum = %d devaddr = %d\n", hc->hc_num, devaddr);
40486 + return hc->hc_num;
40489 +/** Release hc after performing LPM transaction */
40490 +void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd)
40493 + glpmcfg_data_t lpmcfg;
40496 + lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
40497 + hc_num = lpmcfg.b.lpm_chan_index;
40499 + hc = hcd->hc_ptr_array[hc_num];
40501 + DWC_PRINTF("Freeing channel %d after LPM\n", hc_num);
40502 + /* Return host channel to free list */
40503 + DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
40506 +int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr, uint8_t hird,
40507 + uint8_t bRemoteWake)
40509 + glpmcfg_data_t lpmcfg;
40510 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
40513 + channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr);
40514 + if (channel < 0) {
40518 + pcgcctl.b.enbl_sleep_gating = 1;
40519 + DWC_MODIFY_REG32(hcd->core_if->pcgcctl, 0, pcgcctl.d32);
40521 + /* Read LPM config register */
40522 + lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
40524 + /* Program LPM transaction fields */
40525 + lpmcfg.b.rem_wkup_en = bRemoteWake;
40526 + lpmcfg.b.hird = hird;
40527 + lpmcfg.b.hird_thres = 0x1c;
40528 + lpmcfg.b.lpm_chan_index = channel;
40529 + lpmcfg.b.en_utmi_sleep = 1;
40530 + /* Program LPM config register */
40531 + DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
40533 + /* Send LPM transaction */
40534 + lpmcfg.b.send_lpm = 1;
40535 + DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
40540 +#endif /* CONFIG_USB_DWC_OTG_LPM */
40542 +int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port)
40547 + return -DWC_E_INVALID;
40550 + retval = (hcd->flags.b.port_connect_status_change ||
40551 + hcd->flags.b.port_reset_change ||
40552 + hcd->flags.b.port_enable_change ||
40553 + hcd->flags.b.port_suspend_change ||
40554 + hcd->flags.b.port_over_current_change);
40557 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
40558 + " Root port status changed\n");
40559 + DWC_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n",
40560 + hcd->flags.b.port_connect_status_change);
40561 + DWC_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n",
40562 + hcd->flags.b.port_reset_change);
40563 + DWC_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n",
40564 + hcd->flags.b.port_enable_change);
40565 + DWC_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n",
40566 + hcd->flags.b.port_suspend_change);
40567 + DWC_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n",
40568 + hcd->flags.b.port_over_current_change);
40574 +int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * dwc_otg_hcd)
40576 + hfnum_data_t hfnum;
40578 + DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs->
40582 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n",
40585 + return hfnum.b.frnum;
40588 +int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
40589 + struct dwc_otg_hcd_function_ops *fops)
40593 + hcd->fops = fops;
40594 + if (!dwc_otg_is_device_mode(hcd->core_if) &&
40595 + (!hcd->core_if->adp_enable || hcd->core_if->adp.adp_started)) {
40596 + dwc_otg_hcd_reinit(hcd);
40598 + retval = -DWC_E_NO_DEVICE;
40604 +void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd)
40606 + return hcd->priv;
40609 +void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data)
40611 + hcd->priv = priv_data;
40614 +uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd)
40616 + return hcd->otg_port;
40619 +uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd)
40621 + uint32_t is_b_host;
40622 + if (hcd->core_if->op_state == B_HOST) {
40628 + return is_b_host;
40631 +dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
40632 + int iso_desc_count, int atomic_alloc)
40634 + dwc_otg_hcd_urb_t *dwc_otg_urb;
40638 + sizeof(*dwc_otg_urb) +
40639 + iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc);
40640 + if (atomic_alloc)
40641 + dwc_otg_urb = DWC_ALLOC_ATOMIC(size);
40643 + dwc_otg_urb = DWC_ALLOC(size);
40646 + dwc_otg_urb->packet_count = iso_desc_count;
40648 + DWC_ERROR("**** DWC OTG HCD URB alloc - "
40649 + "%salloc of %db failed\n",
40650 + atomic_alloc?"atomic ":"", size);
40652 + return dwc_otg_urb;
40655 +void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * dwc_otg_urb,
40656 + uint8_t dev_addr, uint8_t ep_num,
40657 + uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
40659 + dwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num,
40660 + ep_type, ep_dir, mps);
40663 + ("addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n",
40664 + dev_addr, ep_num, ep_dir, ep_type, mps);
40668 +void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
40669 + void *urb_handle, void *buf, dwc_dma_t dma,
40670 + uint32_t buflen, void *setup_packet,
40671 + dwc_dma_t setup_dma, uint32_t flags,
40672 + uint16_t interval)
40674 + dwc_otg_urb->priv = urb_handle;
40675 + dwc_otg_urb->buf = buf;
40676 + dwc_otg_urb->dma = dma;
40677 + dwc_otg_urb->length = buflen;
40678 + dwc_otg_urb->setup_packet = setup_packet;
40679 + dwc_otg_urb->setup_dma = setup_dma;
40680 + dwc_otg_urb->flags = flags;
40681 + dwc_otg_urb->interval = interval;
40682 + dwc_otg_urb->status = -DWC_E_IN_PROGRESS;
40685 +uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb)
40687 + return dwc_otg_urb->status;
40690 +uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t * dwc_otg_urb)
40692 + return dwc_otg_urb->actual_length;
40695 +uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t * dwc_otg_urb)
40697 + return dwc_otg_urb->error_count;
40700 +void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
40701 + int desc_num, uint32_t offset,
40704 + dwc_otg_urb->iso_descs[desc_num].offset = offset;
40705 + dwc_otg_urb->iso_descs[desc_num].length = length;
40708 +uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t * dwc_otg_urb,
40711 + return dwc_otg_urb->iso_descs[desc_num].status;
40714 +uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
40715 + dwc_otg_urb, int desc_num)
40717 + return dwc_otg_urb->iso_descs[desc_num].actual_length;
40720 +int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd, void *ep_handle)
40722 + int allocated = 0;
40723 + dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
40726 + if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
40730 + return allocated;
40733 +int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle)
40735 + dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
40737 + DWC_ASSERT(qh, "qh is not allocated\n");
40739 + if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
40746 +uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd, void *ep_handle)
40748 + dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
40749 + DWC_ASSERT(qh, "qh is not allocated\n");
40750 + return qh->usecs;
40753 +void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd)
40756 + int num_channels;
40758 + gnptxsts_data_t np_tx_status;
40759 + hptxsts_data_t p_tx_status;
40761 + num_channels = hcd->core_if->core_params->host_channels;
40762 + DWC_PRINTF("\n");
40764 + ("************************************************************\n");
40765 + DWC_PRINTF("HCD State:\n");
40766 + DWC_PRINTF(" Num channels: %d\n", num_channels);
40767 + for (i = 0; i < num_channels; i++) {
40768 + dwc_hc_t *hc = hcd->hc_ptr_array[i];
40769 + DWC_PRINTF(" Channel %d:\n", i);
40770 + DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
40771 + hc->dev_addr, hc->ep_num, hc->ep_is_in);
40772 + DWC_PRINTF(" speed: %d\n", hc->speed);
40773 + DWC_PRINTF(" ep_type: %d\n", hc->ep_type);
40774 + DWC_PRINTF(" max_packet: %d\n", hc->max_packet);
40775 + DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start);
40776 + DWC_PRINTF(" multi_count: %d\n", hc->multi_count);
40777 + DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started);
40778 + DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff);
40779 + DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len);
40780 + DWC_PRINTF(" xfer_count: %d\n", hc->xfer_count);
40781 + DWC_PRINTF(" halt_on_queue: %d\n", hc->halt_on_queue);
40782 + DWC_PRINTF(" halt_pending: %d\n", hc->halt_pending);
40783 + DWC_PRINTF(" halt_status: %d\n", hc->halt_status);
40784 + DWC_PRINTF(" do_split: %d\n", hc->do_split);
40785 + DWC_PRINTF(" complete_split: %d\n", hc->complete_split);
40786 + DWC_PRINTF(" hub_addr: %d\n", hc->hub_addr);
40787 + DWC_PRINTF(" port_addr: %d\n", hc->port_addr);
40788 + DWC_PRINTF(" xact_pos: %d\n", hc->xact_pos);
40789 + DWC_PRINTF(" requests: %d\n", hc->requests);
40790 + DWC_PRINTF(" qh: %p\n", hc->qh);
40791 + if (hc->xfer_started) {
40792 + hfnum_data_t hfnum;
40793 + hcchar_data_t hcchar;
40794 + hctsiz_data_t hctsiz;
40795 + hcint_data_t hcint;
40796 + hcintmsk_data_t hcintmsk;
40798 + DWC_READ_REG32(&hcd->core_if->
40799 + host_if->host_global_regs->hfnum);
40801 + DWC_READ_REG32(&hcd->core_if->host_if->
40802 + hc_regs[i]->hcchar);
40804 + DWC_READ_REG32(&hcd->core_if->host_if->
40805 + hc_regs[i]->hctsiz);
40807 + DWC_READ_REG32(&hcd->core_if->host_if->
40808 + hc_regs[i]->hcint);
40810 + DWC_READ_REG32(&hcd->core_if->host_if->
40811 + hc_regs[i]->hcintmsk);
40812 + DWC_PRINTF(" hfnum: 0x%08x\n", hfnum.d32);
40813 + DWC_PRINTF(" hcchar: 0x%08x\n", hcchar.d32);
40814 + DWC_PRINTF(" hctsiz: 0x%08x\n", hctsiz.d32);
40815 + DWC_PRINTF(" hcint: 0x%08x\n", hcint.d32);
40816 + DWC_PRINTF(" hcintmsk: 0x%08x\n", hcintmsk.d32);
40818 + if (hc->xfer_started && hc->qh) {
40819 + dwc_otg_qtd_t *qtd;
40820 + dwc_otg_hcd_urb_t *urb;
40822 + DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list, qtd_list_entry) {
40823 + if (!qtd->in_process)
40827 + DWC_PRINTF(" URB Info:\n");
40828 + DWC_PRINTF(" qtd: %p, urb: %p\n", qtd, urb);
40830 + DWC_PRINTF(" Dev: %d, EP: %d %s\n",
40831 + dwc_otg_hcd_get_dev_addr(&urb->
40833 + dwc_otg_hcd_get_ep_num(&urb->
40835 + dwc_otg_hcd_is_pipe_in(&urb->
40838 + DWC_PRINTF(" Max packet size: %d\n",
40839 + dwc_otg_hcd_get_mps(&urb->
40841 + DWC_PRINTF(" transfer_buffer: %p\n",
40843 + DWC_PRINTF(" transfer_dma: %p\n",
40844 + (void *)urb->dma);
40845 + DWC_PRINTF(" transfer_buffer_length: %d\n",
40847 + DWC_PRINTF(" actual_length: %d\n",
40848 + urb->actual_length);
40853 + DWC_PRINTF(" non_periodic_channels: %d\n", hcd->non_periodic_channels);
40854 + DWC_PRINTF(" periodic_channels: %d\n", hcd->periodic_channels);
40855 + DWC_PRINTF(" periodic_usecs: %d\n", hcd->periodic_usecs);
40856 + np_tx_status.d32 =
40857 + DWC_READ_REG32(&hcd->core_if->core_global_regs->gnptxsts);
40858 + DWC_PRINTF(" NP Tx Req Queue Space Avail: %d\n",
40859 + np_tx_status.b.nptxqspcavail);
40860 + DWC_PRINTF(" NP Tx FIFO Space Avail: %d\n",
40861 + np_tx_status.b.nptxfspcavail);
40862 + p_tx_status.d32 =
40863 + DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hptxsts);
40864 + DWC_PRINTF(" P Tx Req Queue Space Avail: %d\n",
40865 + p_tx_status.b.ptxqspcavail);
40866 + DWC_PRINTF(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
40867 + dwc_otg_hcd_dump_frrem(hcd);
40868 + dwc_otg_dump_global_registers(hcd->core_if);
40869 + dwc_otg_dump_host_registers(hcd->core_if);
40871 + ("************************************************************\n");
40872 + DWC_PRINTF("\n");
40877 +void dwc_print_setup_data(uint8_t * setup)
40880 + if (CHK_DEBUG_LEVEL(DBG_HCD)) {
40881 + DWC_PRINTF("Setup Data = MSB ");
40882 + for (i = 7; i >= 0; i--)
40883 + DWC_PRINTF("%02x ", setup[i]);
40884 + DWC_PRINTF("\n");
40885 + DWC_PRINTF(" bmRequestType Tranfer = %s\n",
40886 + (setup[0] & 0x80) ? "Device-to-Host" :
40887 + "Host-to-Device");
40888 + DWC_PRINTF(" bmRequestType Type = ");
40889 + switch ((setup[0] & 0x60) >> 5) {
40891 + DWC_PRINTF("Standard\n");
40894 + DWC_PRINTF("Class\n");
40897 + DWC_PRINTF("Vendor\n");
40900 + DWC_PRINTF("Reserved\n");
40903 + DWC_PRINTF(" bmRequestType Recipient = ");
40904 + switch (setup[0] & 0x1f) {
40906 + DWC_PRINTF("Device\n");
40909 + DWC_PRINTF("Interface\n");
40912 + DWC_PRINTF("Endpoint\n");
40915 + DWC_PRINTF("Other\n");
40918 + DWC_PRINTF("Reserved\n");
40921 + DWC_PRINTF(" bRequest = 0x%0x\n", setup[1]);
40922 + DWC_PRINTF(" wValue = 0x%0x\n", *((uint16_t *) & setup[2]));
40923 + DWC_PRINTF(" wIndex = 0x%0x\n", *((uint16_t *) & setup[4]));
40924 + DWC_PRINTF(" wLength = 0x%0x\n\n", *((uint16_t *) & setup[6]));
40929 +void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd)
40932 + DWC_PRINTF("Frame remaining at SOF:\n");
40933 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
40934 + hcd->frrem_samples, hcd->frrem_accum,
40935 + (hcd->frrem_samples > 0) ?
40936 + hcd->frrem_accum / hcd->frrem_samples : 0);
40938 + DWC_PRINTF("\n");
40939 + DWC_PRINTF("Frame remaining at start_transfer (uframe 7):\n");
40940 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
40941 + hcd->core_if->hfnum_7_samples,
40942 + hcd->core_if->hfnum_7_frrem_accum,
40943 + (hcd->core_if->hfnum_7_samples >
40944 + 0) ? hcd->core_if->hfnum_7_frrem_accum /
40945 + hcd->core_if->hfnum_7_samples : 0);
40946 + DWC_PRINTF("Frame remaining at start_transfer (uframe 0):\n");
40947 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
40948 + hcd->core_if->hfnum_0_samples,
40949 + hcd->core_if->hfnum_0_frrem_accum,
40950 + (hcd->core_if->hfnum_0_samples >
40951 + 0) ? hcd->core_if->hfnum_0_frrem_accum /
40952 + hcd->core_if->hfnum_0_samples : 0);
40953 + DWC_PRINTF("Frame remaining at start_transfer (uframe 1-6):\n");
40954 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
40955 + hcd->core_if->hfnum_other_samples,
40956 + hcd->core_if->hfnum_other_frrem_accum,
40957 + (hcd->core_if->hfnum_other_samples >
40958 + 0) ? hcd->core_if->hfnum_other_frrem_accum /
40959 + hcd->core_if->hfnum_other_samples : 0);
40961 + DWC_PRINTF("\n");
40962 + DWC_PRINTF("Frame remaining at sample point A (uframe 7):\n");
40963 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
40964 + hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a,
40965 + (hcd->hfnum_7_samples_a > 0) ?
40966 + hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0);
40967 + DWC_PRINTF("Frame remaining at sample point A (uframe 0):\n");
40968 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
40969 + hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a,
40970 + (hcd->hfnum_0_samples_a > 0) ?
40971 + hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0);
40972 + DWC_PRINTF("Frame remaining at sample point A (uframe 1-6):\n");
40973 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
40974 + hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a,
40975 + (hcd->hfnum_other_samples_a > 0) ?
40976 + hcd->hfnum_other_frrem_accum_a /
40977 + hcd->hfnum_other_samples_a : 0);
40979 + DWC_PRINTF("\n");
40980 + DWC_PRINTF("Frame remaining at sample point B (uframe 7):\n");
40981 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
40982 + hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b,
40983 + (hcd->hfnum_7_samples_b > 0) ?
40984 + hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0);
40985 + DWC_PRINTF("Frame remaining at sample point B (uframe 0):\n");
40986 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
40987 + hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b,
40988 + (hcd->hfnum_0_samples_b > 0) ?
40989 + hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0);
40990 + DWC_PRINTF("Frame remaining at sample point B (uframe 1-6):\n");
40991 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
40992 + hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b,
40993 + (hcd->hfnum_other_samples_b > 0) ?
40994 + hcd->hfnum_other_frrem_accum_b /
40995 + hcd->hfnum_other_samples_b : 0);
40999 +#endif /* DWC_DEVICE_ONLY */
41001 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.h
41003 +/* ==========================================================================
41004 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $
41005 + * $Revision: #58 $
41006 + * $Date: 2011/09/15 $
41007 + * $Change: 1846647 $
41009 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
41010 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
41011 + * otherwise expressly agreed to in writing between Synopsys and you.
41013 + * The Software IS NOT an item of Licensed Software or Licensed Product under
41014 + * any End User Software License Agreement or Agreement for Licensed Product
41015 + * with Synopsys or any supplement thereto. You are permitted to use and
41016 + * redistribute this Software in source and binary forms, with or without
41017 + * modification, provided that redistributions of source code must retain this
41018 + * notice. You may not view, use, disclose, copy or distribute this file or
41019 + * any information contained herein except pursuant to this license grant from
41020 + * Synopsys. If you do not agree with this notice, including the disclaimer
41021 + * below, then you are not authorized to use the Software.
41023 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
41024 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
41025 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
41026 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
41027 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
41028 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
41029 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
41030 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41031 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
41032 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
41034 + * ========================================================================== */
41035 +#ifndef DWC_DEVICE_ONLY
41036 +#ifndef __DWC_HCD_H__
41037 +#define __DWC_HCD_H__
41039 +#include "dwc_otg_os_dep.h"
41041 +#include "dwc_otg_hcd_if.h"
41042 +#include "dwc_otg_core_if.h"
41043 +#include "dwc_list.h"
41044 +#include "dwc_otg_cil.h"
41045 +#include "dwc_otg_fiq_fsm.h"
41046 +#include "dwc_otg_driver.h"
41052 + * This file contains the structures, constants, and interfaces for
41053 + * the Host Contoller Driver (HCD).
41055 + * The Host Controller Driver (HCD) is responsible for translating requests
41056 + * from the USB Driver into the appropriate actions on the DWC_otg controller.
41057 + * It isolates the USBD from the specifics of the controller by providing an
41058 + * API to the USBD.
41061 +struct dwc_otg_hcd_pipe_info {
41062 + uint8_t dev_addr;
41064 + uint8_t pipe_type;
41065 + uint8_t pipe_dir;
41069 +struct dwc_otg_hcd_iso_packet_desc {
41072 + uint32_t actual_length;
41076 +struct dwc_otg_qtd;
41078 +struct dwc_otg_hcd_urb {
41080 + struct dwc_otg_qtd *qtd;
41083 + void *setup_packet;
41084 + dwc_dma_t setup_dma;
41086 + uint32_t actual_length;
41088 + uint32_t error_count;
41089 + uint32_t packet_count;
41091 + uint16_t interval;
41092 + struct dwc_otg_hcd_pipe_info pipe_info;
41093 + struct dwc_otg_hcd_iso_packet_desc iso_descs[0];
41096 +static inline uint8_t dwc_otg_hcd_get_ep_num(struct dwc_otg_hcd_pipe_info *pipe)
41098 + return pipe->ep_num;
41101 +static inline uint8_t dwc_otg_hcd_get_pipe_type(struct dwc_otg_hcd_pipe_info
41104 + return pipe->pipe_type;
41107 +static inline uint16_t dwc_otg_hcd_get_mps(struct dwc_otg_hcd_pipe_info *pipe)
41109 + return pipe->mps;
41112 +static inline uint8_t dwc_otg_hcd_get_dev_addr(struct dwc_otg_hcd_pipe_info
41115 + return pipe->dev_addr;
41118 +static inline uint8_t dwc_otg_hcd_is_pipe_isoc(struct dwc_otg_hcd_pipe_info
41121 + return (pipe->pipe_type == UE_ISOCHRONOUS);
41124 +static inline uint8_t dwc_otg_hcd_is_pipe_int(struct dwc_otg_hcd_pipe_info
41127 + return (pipe->pipe_type == UE_INTERRUPT);
41130 +static inline uint8_t dwc_otg_hcd_is_pipe_bulk(struct dwc_otg_hcd_pipe_info
41133 + return (pipe->pipe_type == UE_BULK);
41136 +static inline uint8_t dwc_otg_hcd_is_pipe_control(struct dwc_otg_hcd_pipe_info
41139 + return (pipe->pipe_type == UE_CONTROL);
41142 +static inline uint8_t dwc_otg_hcd_is_pipe_in(struct dwc_otg_hcd_pipe_info *pipe)
41144 + return (pipe->pipe_dir == UE_DIR_IN);
41147 +static inline uint8_t dwc_otg_hcd_is_pipe_out(struct dwc_otg_hcd_pipe_info
41150 + return (!dwc_otg_hcd_is_pipe_in(pipe));
41153 +static inline void dwc_otg_hcd_fill_pipe(struct dwc_otg_hcd_pipe_info *pipe,
41154 + uint8_t devaddr, uint8_t ep_num,
41155 + uint8_t pipe_type, uint8_t pipe_dir,
41158 + pipe->dev_addr = devaddr;
41159 + pipe->ep_num = ep_num;
41160 + pipe->pipe_type = pipe_type;
41161 + pipe->pipe_dir = pipe_dir;
41166 + * Phases for control transfers.
41168 +typedef enum dwc_otg_control_phase {
41169 + DWC_OTG_CONTROL_SETUP,
41170 + DWC_OTG_CONTROL_DATA,
41171 + DWC_OTG_CONTROL_STATUS
41172 +} dwc_otg_control_phase_e;
41174 +/** Transaction types. */
41175 +typedef enum dwc_otg_transaction_type {
41176 + DWC_OTG_TRANSACTION_NONE = 0,
41177 + DWC_OTG_TRANSACTION_PERIODIC = 1,
41178 + DWC_OTG_TRANSACTION_NON_PERIODIC = 2,
41179 + DWC_OTG_TRANSACTION_ALL = DWC_OTG_TRANSACTION_PERIODIC + DWC_OTG_TRANSACTION_NON_PERIODIC
41180 +} dwc_otg_transaction_type_e;
41182 +struct dwc_otg_qh;
41185 + * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
41186 + * interrupt, or isochronous transfer. A single QTD is created for each URB
41187 + * (of one of these types) submitted to the HCD. The transfer associated with
41188 + * a QTD may require one or multiple transactions.
41190 + * A QTD is linked to a Queue Head, which is entered in either the
41191 + * non-periodic or periodic schedule for execution. When a QTD is chosen for
41192 + * execution, some or all of its transactions may be executed. After
41193 + * execution, the state of the QTD is updated. The QTD may be retired if all
41194 + * its transactions are complete or if an error occurred. Otherwise, it
41195 + * remains in the schedule so more transactions can be executed later.
41197 +typedef struct dwc_otg_qtd {
41199 + * Determines the PID of the next data packet for the data phase of
41200 + * control transfers. Ignored for other transfer types.<br>
41201 + * One of the following values:
41202 + * - DWC_OTG_HC_PID_DATA0
41203 + * - DWC_OTG_HC_PID_DATA1
41205 + uint8_t data_toggle;
41207 + /** Current phase for control transfers (Setup, Data, or Status). */
41208 + dwc_otg_control_phase_e control_phase;
41210 + /** Keep track of the current split type
41211 + * for FS/LS endpoints on a HS Hub */
41212 + uint8_t complete_split;
41214 + /** How many bytes transferred during SSPLIT OUT */
41215 + uint32_t ssplit_out_xfer_count;
41218 + * Holds the number of bus errors that have occurred for a transaction
41219 + * within this transfer.
41221 + uint8_t error_count;
41224 + * Index of the next frame descriptor for an isochronous transfer. A
41225 + * frame descriptor describes the buffer position and length of the
41226 + * data to be transferred in the next scheduled (micro)frame of an
41227 + * isochronous transfer. It also holds status for that transaction.
41228 + * The frame index starts at 0.
41230 + uint16_t isoc_frame_index;
41232 + /** Position of the ISOC split on full/low speed */
41233 + uint8_t isoc_split_pos;
41235 + /** Position of the ISOC split in the buffer for the current frame */
41236 + uint16_t isoc_split_offset;
41238 + /** URB for this transfer */
41239 + struct dwc_otg_hcd_urb *urb;
41241 + struct dwc_otg_qh *qh;
41243 + /** This list of QTDs */
41244 + DWC_CIRCLEQ_ENTRY(dwc_otg_qtd) qtd_list_entry;
41246 + /** Indicates if this QTD is currently processed by HW. */
41247 + uint8_t in_process;
41249 + /** Number of DMA descriptors for this QTD */
41253 + * Last activated frame(packet) index.
41254 + * Used in Descriptor DMA mode only.
41256 + uint16_t isoc_frame_index_last;
41260 +DWC_CIRCLEQ_HEAD(dwc_otg_qtd_list, dwc_otg_qtd);
41263 + * A Queue Head (QH) holds the static characteristics of an endpoint and
41264 + * maintains a list of transfers (QTDs) for that endpoint. A QH structure may
41265 + * be entered in either the non-periodic or periodic schedule.
41267 +typedef struct dwc_otg_qh {
41270 + * One of the following values:
41274 + * - UE_ISOCHRONOUS
41277 + uint8_t ep_is_in;
41279 + /** wMaxPacketSize Field of Endpoint Descriptor. */
41284 + * One of the following values:
41285 + * - DWC_OTG_EP_SPEED_LOW
41286 + * - DWC_OTG_EP_SPEED_FULL
41287 + * - DWC_OTG_EP_SPEED_HIGH
41289 + uint8_t dev_speed;
41292 + * Determines the PID of the next data packet for non-control
41293 + * transfers. Ignored for control transfers.<br>
41294 + * One of the following values:
41295 + * - DWC_OTG_HC_PID_DATA0
41296 + * - DWC_OTG_HC_PID_DATA1
41298 + uint8_t data_toggle;
41300 + /** Ping state if 1. */
41301 + uint8_t ping_state;
41304 + * List of QTDs for this QH.
41306 + struct dwc_otg_qtd_list qtd_list;
41308 + /** Host channel currently processing transfers for this QH. */
41309 + struct dwc_hc *channel;
41311 + /** Full/low speed endpoint on high-speed hub requires split. */
41312 + uint8_t do_split;
41314 + /** @name Periodic schedule information */
41317 + /** Bandwidth in microseconds per (micro)frame. */
41320 + /** Interval between transfers in (micro)frames. */
41321 + uint16_t interval;
41324 + * (micro)frame to initialize a periodic transfer. The transfer
41325 + * executes in the following (micro)frame.
41327 + uint16_t sched_frame;
41330 + ** Frame a NAK was received on this queue head, used to minimise NAK retransmission
41332 + uint16_t nak_frame;
41334 + /** (micro)frame at which last start split was initialized. */
41335 + uint16_t start_split_frame;
41340 + * Used instead of original buffer if
41341 + * it(physical address) is not dword-aligned.
41343 + uint8_t *dw_align_buf;
41344 + dwc_dma_t dw_align_buf_dma;
41346 + /** Entry for QH in either the periodic or non-periodic schedule. */
41347 + dwc_list_link_t qh_list_entry;
41349 + /** @name Descriptor DMA support */
41352 + /** Descriptor List. */
41353 + dwc_otg_host_dma_desc_t *desc_list;
41355 + /** Descriptor List physical address. */
41356 + dwc_dma_t desc_list_dma;
41359 + * Xfer Bytes array.
41360 + * Each element corresponds to a descriptor and indicates
41361 + * original XferSize size value for the descriptor.
41363 + uint32_t *n_bytes;
41365 + /** Actual number of transfer descriptors in a list. */
41368 + /** First activated isochronous transfer descriptor index. */
41369 + uint8_t td_first;
41370 + /** Last activated isochronous transfer descriptor index. */
41377 + uint16_t frame_usecs[8];
41379 + uint32_t skip_count;
41382 +DWC_CIRCLEQ_HEAD(hc_list, dwc_hc);
41384 +typedef struct urb_tq_entry {
41386 + DWC_TAILQ_ENTRY(urb_tq_entry) urb_tq_entries;
41389 +DWC_TAILQ_HEAD(urb_list, urb_tq_entry);
41392 + * This structure holds the state of the HCD, including the non-periodic and
41393 + * periodic schedules.
41395 +struct dwc_otg_hcd {
41396 + /** The DWC otg device pointer */
41397 + struct dwc_otg_device *otg_dev;
41398 + /** DWC OTG Core Interface Layer */
41399 + dwc_otg_core_if_t *core_if;
41401 + /** Function HCD driver callbacks */
41402 + struct dwc_otg_hcd_function_ops *fops;
41404 + /** Internal DWC HCD Flags */
41405 + volatile union dwc_otg_hcd_internal_flags {
41408 + unsigned port_connect_status_change:1;
41409 + unsigned port_connect_status:1;
41410 + unsigned port_reset_change:1;
41411 + unsigned port_enable_change:1;
41412 + unsigned port_suspend_change:1;
41413 + unsigned port_over_current_change:1;
41414 + unsigned port_l1_change:1;
41415 + unsigned port_speed:2;
41416 + unsigned reserved:24;
41421 + * Inactive items in the non-periodic schedule. This is a list of
41422 + * Queue Heads. Transfers associated with these Queue Heads are not
41423 + * currently assigned to a host channel.
41425 + dwc_list_link_t non_periodic_sched_inactive;
41428 + * Active items in the non-periodic schedule. This is a list of
41429 + * Queue Heads. Transfers associated with these Queue Heads are
41430 + * currently assigned to a host channel.
41432 + dwc_list_link_t non_periodic_sched_active;
41435 + * Pointer to the next Queue Head to process in the active
41436 + * non-periodic schedule.
41438 + dwc_list_link_t *non_periodic_qh_ptr;
41441 + * Inactive items in the periodic schedule. This is a list of QHs for
41442 + * periodic transfers that are _not_ scheduled for the next frame.
41443 + * Each QH in the list has an interval counter that determines when it
41444 + * needs to be scheduled for execution. This scheduling mechanism
41445 + * allows only a simple calculation for periodic bandwidth used (i.e.
41446 + * must assume that all periodic transfers may need to execute in the
41447 + * same frame). However, it greatly simplifies scheduling and should
41448 + * be sufficient for the vast majority of OTG hosts, which need to
41449 + * connect to a small number of peripherals at one time.
41451 + * Items move from this list to periodic_sched_ready when the QH
41452 + * interval counter is 0 at SOF.
41454 + dwc_list_link_t periodic_sched_inactive;
41457 + * List of periodic QHs that are ready for execution in the next
41458 + * frame, but have not yet been assigned to host channels.
41460 + * Items move from this list to periodic_sched_assigned as host
41461 + * channels become available during the current frame.
41463 + dwc_list_link_t periodic_sched_ready;
41466 + * List of periodic QHs to be executed in the next frame that are
41467 + * assigned to host channels.
41469 + * Items move from this list to periodic_sched_queued as the
41470 + * transactions for the QH are queued to the DWC_otg controller.
41472 + dwc_list_link_t periodic_sched_assigned;
41475 + * List of periodic QHs that have been queued for execution.
41477 + * Items move from this list to either periodic_sched_inactive or
41478 + * periodic_sched_ready when the channel associated with the transfer
41479 + * is released. If the interval for the QH is 1, the item moves to
41480 + * periodic_sched_ready because it must be rescheduled for the next
41481 + * frame. Otherwise, the item moves to periodic_sched_inactive.
41483 + dwc_list_link_t periodic_sched_queued;
41486 + * Total bandwidth claimed so far for periodic transfers. This value
41487 + * is in microseconds per (micro)frame. The assumption is that all
41488 + * periodic transfers may occur in the same (micro)frame.
41490 + uint16_t periodic_usecs;
41493 + * Total bandwidth claimed so far for all periodic transfers
41495 + * This will include a mixture of HS and FS transfers.
41496 + * Units are microseconds per (micro)frame.
41497 + * We have a budget per frame and have to schedule
41498 + * transactions accordingly.
41499 + * Watch out for the fact that things are actually scheduled for the
41502 + uint16_t frame_usecs[8];
41506 + * Frame number read from the core at SOF. The value ranges from 0 to
41507 + * DWC_HFNUM_MAX_FRNUM.
41509 + uint16_t frame_number;
41512 + * Count of periodic QHs, if using several eps. For SOF enable/disable.
41514 + uint16_t periodic_qh_count;
41517 + * Free host channels in the controller. This is a list of
41518 + * dwc_hc_t items.
41520 + struct hc_list free_hc_list;
41522 + * Number of host channels assigned to periodic transfers. Currently
41523 + * assuming that there is a dedicated host channel for each periodic
41524 + * transaction and at least one host channel available for
41525 + * non-periodic transactions.
41527 + int periodic_channels; /* microframe_schedule==0 */
41530 + * Number of host channels assigned to non-periodic transfers.
41532 + int non_periodic_channels; /* microframe_schedule==0 */
41535 + * Number of host channels assigned to non-periodic transfers.
41537 + int available_host_channels;
41540 + * Array of pointers to the host channel descriptors. Allows accessing
41541 + * a host channel descriptor given the host channel number. This is
41542 + * useful in interrupt handlers.
41544 + struct dwc_hc *hc_ptr_array[MAX_EPS_CHANNELS];
41547 + * Buffer to use for any data received during the status phase of a
41548 + * control transfer. Normally no data is transferred during the status
41549 + * phase. This buffer is used as a bit bucket.
41551 + uint8_t *status_buf;
41554 + * DMA address for status_buf.
41556 + dma_addr_t status_buf_dma;
41557 +#define DWC_OTG_HCD_STATUS_BUF_SIZE 64
41560 + * Connection timer. An OTG host must display a message if the device
41561 + * does not connect. Started when the VBus power is turned on via
41562 + * sysfs attribute "buspower".
41564 + dwc_timer_t *conn_timer;
41566 + /* Tasket to do a reset */
41567 + dwc_tasklet_t *reset_tasklet;
41569 + dwc_tasklet_t *completion_tasklet;
41570 + struct urb_list completed_urb_list;
41573 + dwc_spinlock_t *lock;
41575 + * Private data that could be used by OS wrapper.
41579 + uint8_t otg_port;
41581 + /** Frame List */
41582 + uint32_t *frame_list;
41584 + /** Hub - Port assignment */
41585 + int hub_port[128];
41587 + int hub_port_alloc[2048];
41590 + /** Frame List DMA address */
41591 + dma_addr_t frame_list_dma;
41593 + struct fiq_stack *fiq_stack;
41594 + struct fiq_state *fiq_state;
41596 + /** Virtual address for split transaction DMA bounce buffers */
41597 + struct fiq_dma_blob *fiq_dmab;
41600 + uint32_t frrem_samples;
41601 + uint64_t frrem_accum;
41603 + uint32_t hfnum_7_samples_a;
41604 + uint64_t hfnum_7_frrem_accum_a;
41605 + uint32_t hfnum_0_samples_a;
41606 + uint64_t hfnum_0_frrem_accum_a;
41607 + uint32_t hfnum_other_samples_a;
41608 + uint64_t hfnum_other_frrem_accum_a;
41610 + uint32_t hfnum_7_samples_b;
41611 + uint64_t hfnum_7_frrem_accum_b;
41612 + uint32_t hfnum_0_samples_b;
41613 + uint64_t hfnum_0_frrem_accum_b;
41614 + uint32_t hfnum_other_samples_b;
41615 + uint64_t hfnum_other_frrem_accum_b;
41619 +static inline struct device *dwc_otg_hcd_to_dev(struct dwc_otg_hcd *hcd)
41621 + return &hcd->otg_dev->os_dep.platformdev->dev;
41624 +/** @name Transaction Execution Functions */
41626 +extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t
41628 +extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
41629 + dwc_otg_transaction_type_e tr_type);
41631 +int dwc_otg_hcd_allocate_port(dwc_otg_hcd_t * hcd, dwc_otg_qh_t *qh);
41632 +void dwc_otg_hcd_release_port(dwc_otg_hcd_t * dwc_otg_hcd, dwc_otg_qh_t *qh);
41634 +extern int fiq_fsm_queue_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
41635 +extern int fiq_fsm_transaction_suitable(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
41636 +extern void dwc_otg_cleanup_fiq_channel(dwc_otg_hcd_t *hcd, uint32_t num);
41640 +/** @name Interrupt Handler Functions */
41642 +extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
41643 +extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * dwc_otg_hcd);
41644 +extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *
41646 +extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *
41648 +extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *
41650 +extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *
41652 +extern int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd);
41653 +extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t *
41655 +extern int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t * dwc_otg_hcd);
41656 +extern int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd);
41657 +extern int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd,
41659 +extern int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t * dwc_otg_hcd);
41660 +extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t *
41664 +/** @name Schedule Queue Functions */
41667 +/* Implemented in dwc_otg_hcd_queue.c */
41668 +extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,
41669 + dwc_otg_hcd_urb_t * urb, int atomic_alloc);
41670 +extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
41671 +extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
41672 +extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
41673 +extern void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
41674 + int sched_csplit);
41676 +/** Remove and free a QH */
41677 +static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t * hcd,
41678 + dwc_otg_qh_t * qh)
41680 + dwc_irqflags_t flags;
41681 + DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
41682 + dwc_otg_hcd_qh_remove(hcd, qh);
41683 + DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
41684 + dwc_otg_hcd_qh_free(hcd, qh);
41687 +/** Allocates memory for a QH structure.
41688 + * @return Returns the memory allocate or NULL on error. */
41689 +static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(int atomic_alloc)
41691 + if (atomic_alloc)
41692 + return (dwc_otg_qh_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qh_t));
41694 + return (dwc_otg_qh_t *) DWC_ALLOC(sizeof(dwc_otg_qh_t));
41697 +extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb,
41698 + int atomic_alloc);
41699 +extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb);
41700 +extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, dwc_otg_hcd_t * dwc_otg_hcd,
41701 + dwc_otg_qh_t ** qh, int atomic_alloc);
41703 +/** Allocates memory for a QTD structure.
41704 + * @return Returns the memory allocate or NULL on error. */
41705 +static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(int atomic_alloc)
41707 + if (atomic_alloc)
41708 + return (dwc_otg_qtd_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qtd_t));
41710 + return (dwc_otg_qtd_t *) DWC_ALLOC(sizeof(dwc_otg_qtd_t));
41713 +/** Frees the memory for a QTD structure. QTD should already be removed from
41715 + * @param qtd QTD to free.*/
41716 +static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t * qtd)
41721 +/** Removes a QTD from list.
41722 + * @param hcd HCD instance.
41723 + * @param qtd QTD to remove from list.
41724 + * @param qh QTD belongs to.
41726 +static inline void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t * hcd,
41727 + dwc_otg_qtd_t * qtd,
41728 + dwc_otg_qh_t * qh)
41730 + DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry);
41733 +/** Remove and free a QTD
41734 + * Need to disable IRQ and hold hcd lock while calling this function out of
41735 + * interrupt servicing chain */
41736 +static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t * hcd,
41737 + dwc_otg_qtd_t * qtd,
41738 + dwc_otg_qh_t * qh)
41740 + dwc_otg_hcd_qtd_remove(hcd, qtd, qh);
41741 + dwc_otg_hcd_qtd_free(qtd);
41746 +/** @name Descriptor DMA Supporting Functions */
41749 +extern void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
41750 +extern void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd,
41752 + dwc_otg_hc_regs_t * hc_regs,
41753 + dwc_otg_halt_status_e halt_status);
41755 +extern int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
41756 +extern void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
41760 +/** @name Internal Functions */
41762 +dwc_otg_qh_t *dwc_urb_to_qh(dwc_otg_hcd_urb_t * urb);
41765 +#ifdef CONFIG_USB_DWC_OTG_LPM
41766 +extern int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd,
41767 + uint8_t devaddr);
41768 +extern void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd);
41771 +/** Gets the QH that contains the list_head */
41772 +#define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry)
41774 +/** Gets the QTD that contains the list_head */
41775 +#define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry)
41777 +/** Check if QH is non-periodic */
41778 +#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == UE_BULK) || \
41779 + (_qh_ptr_->ep_type == UE_CONTROL))
41781 +/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */
41782 +#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
41784 +/** Packet size for any kind of endpoint descriptor */
41785 +#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
41788 + * Returns true if _frame1 is less than or equal to _frame2. The comparison is
41789 + * done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the
41790 + * frame number when the max frame number is reached.
41792 +static inline int dwc_frame_num_le(uint16_t frame1, uint16_t frame2)
41794 + return ((frame2 - frame1) & DWC_HFNUM_MAX_FRNUM) <=
41795 + (DWC_HFNUM_MAX_FRNUM >> 1);
41799 + * Returns true if _frame1 is greater than _frame2. The comparison is done
41800 + * modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
41801 + * number when the max frame number is reached.
41803 +static inline int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2)
41805 + return (frame1 != frame2) &&
41806 + (((frame1 - frame2) & DWC_HFNUM_MAX_FRNUM) <
41807 + (DWC_HFNUM_MAX_FRNUM >> 1));
41811 + * Increments _frame by the amount specified by _inc. The addition is done
41812 + * modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value.
41814 +static inline uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc)
41816 + return (frame + inc) & DWC_HFNUM_MAX_FRNUM;
41819 +static inline uint16_t dwc_full_frame_num(uint16_t frame)
41821 + return (frame & DWC_HFNUM_MAX_FRNUM) >> 3;
41824 +static inline uint16_t dwc_micro_frame_num(uint16_t frame)
41826 + return frame & 0x7;
41829 +extern void init_hcd_usecs(dwc_otg_hcd_t *_hcd);
41831 +void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
41832 + dwc_otg_hc_regs_t * hc_regs,
41833 + dwc_otg_qtd_t * qtd);
41837 + * Macro to sample the remaining PHY clocks left in the current frame. This
41838 + * may be used during debugging to determine the average time it takes to
41839 + * execute sections of code. There are two possible sample points, "a" and
41840 + * "b", so the _letter argument must be one of these values.
41842 + * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
41843 + * example, "cat /sys/devices/lm0/hcd_frrem".
41845 +#define dwc_sample_frrem(_hcd, _qh, _letter) \
41847 + hfnum_data_t hfnum; \
41848 + dwc_otg_qtd_t *qtd; \
41849 + qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \
41850 + if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \
41851 + hfnum.d32 = DWC_READ_REG32(&_hcd->core_if->host_if->host_global_regs->hfnum); \
41852 + switch (hfnum.b.frnum & 0x7) { \
41854 + _hcd->hfnum_7_samples_##_letter++; \
41855 + _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \
41858 + _hcd->hfnum_0_samples_##_letter++; \
41859 + _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \
41862 + _hcd->hfnum_other_samples_##_letter++; \
41863 + _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \
41869 +#define dwc_sample_frrem(_hcd, _qh, _letter)
41872 +#endif /* DWC_DEVICE_ONLY */
41874 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c
41876 +/*==========================================================================
41877 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_ddma.c $
41878 + * $Revision: #10 $
41879 + * $Date: 2011/10/20 $
41880 + * $Change: 1869464 $
41882 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
41883 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
41884 + * otherwise expressly agreed to in writing between Synopsys and you.
41886 + * The Software IS NOT an item of Licensed Software or Licensed Product under
41887 + * any End User Software License Agreement or Agreement for Licensed Product
41888 + * with Synopsys or any supplement thereto. You are permitted to use and
41889 + * redistribute this Software in source and binary forms, with or without
41890 + * modification, provided that redistributions of source code must retain this
41891 + * notice. You may not view, use, disclose, copy or distribute this file or
41892 + * any information contained herein except pursuant to this license grant from
41893 + * Synopsys. If you do not agree with this notice, including the disclaimer
41894 + * below, then you are not authorized to use the Software.
41896 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
41897 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
41898 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
41899 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
41900 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
41901 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
41902 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
41903 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41904 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
41905 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
41907 + * ========================================================================== */
41908 +#ifndef DWC_DEVICE_ONLY
41911 + * This file contains Descriptor DMA support implementation for host mode.
41914 +#include "dwc_otg_hcd.h"
41915 +#include "dwc_otg_regs.h"
41917 +extern bool microframe_schedule;
41919 +static inline uint8_t frame_list_idx(uint16_t frame)
41921 + return (frame & (MAX_FRLIST_EN_NUM - 1));
41924 +static inline uint16_t desclist_idx_inc(uint16_t idx, uint16_t inc, uint8_t speed)
41926 + return (idx + inc) &
41928 + DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC :
41929 + MAX_DMA_DESC_NUM_GENERIC) - 1);
41932 +static inline uint16_t desclist_idx_dec(uint16_t idx, uint16_t inc, uint8_t speed)
41934 + return (idx - inc) &
41936 + DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC :
41937 + MAX_DMA_DESC_NUM_GENERIC) - 1);
41940 +static inline uint16_t max_desc_num(dwc_otg_qh_t * qh)
41942 + return (((qh->ep_type == UE_ISOCHRONOUS)
41943 + && (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH))
41944 + ? MAX_DMA_DESC_NUM_HS_ISOC : MAX_DMA_DESC_NUM_GENERIC);
41946 +static inline uint16_t frame_incr_val(dwc_otg_qh_t * qh)
41948 + return ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH)
41949 + ? ((qh->interval + 8 - 1) / 8)
41953 +static int desc_list_alloc(struct device *dev, dwc_otg_qh_t * qh)
41957 + qh->desc_list = (dwc_otg_host_dma_desc_t *)
41958 + DWC_DMA_ALLOC(dev, sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh),
41959 + &qh->desc_list_dma);
41961 + if (!qh->desc_list) {
41962 + retval = -DWC_E_NO_MEMORY;
41963 + DWC_ERROR("%s: DMA descriptor list allocation failed\n", __func__);
41967 + dwc_memset(qh->desc_list, 0x00,
41968 + sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));
41971 + (uint32_t *) DWC_ALLOC(sizeof(uint32_t) * max_desc_num(qh));
41973 + if (!qh->n_bytes) {
41974 + retval = -DWC_E_NO_MEMORY;
41976 + ("%s: Failed to allocate array for descriptors' size actual values\n",
41984 +static void desc_list_free(struct device *dev, dwc_otg_qh_t * qh)
41986 + if (qh->desc_list) {
41987 + DWC_DMA_FREE(dev, max_desc_num(qh), qh->desc_list,
41988 + qh->desc_list_dma);
41989 + qh->desc_list = NULL;
41992 + if (qh->n_bytes) {
41993 + DWC_FREE(qh->n_bytes);
41994 + qh->n_bytes = NULL;
41998 +static int frame_list_alloc(dwc_otg_hcd_t * hcd)
42000 + struct device *dev = dwc_otg_hcd_to_dev(hcd);
42003 + if (hcd->frame_list)
42006 + hcd->frame_list = DWC_DMA_ALLOC(dev, 4 * MAX_FRLIST_EN_NUM,
42007 + &hcd->frame_list_dma);
42008 + if (!hcd->frame_list) {
42009 + retval = -DWC_E_NO_MEMORY;
42010 + DWC_ERROR("%s: Frame List allocation failed\n", __func__);
42013 + dwc_memset(hcd->frame_list, 0x00, 4 * MAX_FRLIST_EN_NUM);
42018 +static void frame_list_free(dwc_otg_hcd_t * hcd)
42020 + struct device *dev = dwc_otg_hcd_to_dev(hcd);
42022 + if (!hcd->frame_list)
42025 + DWC_DMA_FREE(dev, 4 * MAX_FRLIST_EN_NUM, hcd->frame_list, hcd->frame_list_dma);
42026 + hcd->frame_list = NULL;
42029 +static void per_sched_enable(dwc_otg_hcd_t * hcd, uint16_t fr_list_en)
42032 + hcfg_data_t hcfg;
42034 + hcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg);
42036 + if (hcfg.b.perschedena) {
42037 + /* already enabled */
42041 + DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hflbaddr,
42042 + hcd->frame_list_dma);
42044 + switch (fr_list_en) {
42046 + hcfg.b.frlisten = 3;
42049 + hcfg.b.frlisten = 2;
42052 + hcfg.b.frlisten = 1;
42055 + hcfg.b.frlisten = 0;
42061 + hcfg.b.perschedena = 1;
42063 + DWC_DEBUGPL(DBG_HCD, "Enabling Periodic schedule\n");
42064 + DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32);
42068 +static void per_sched_disable(dwc_otg_hcd_t * hcd)
42070 + hcfg_data_t hcfg;
42072 + hcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg);
42074 + if (!hcfg.b.perschedena) {
42075 + /* already disabled */
42078 + hcfg.b.perschedena = 0;
42080 + DWC_DEBUGPL(DBG_HCD, "Disabling Periodic schedule\n");
42081 + DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32);
42085 + * Activates/Deactivates FrameList entries for the channel
42086 + * based on endpoint servicing period.
42088 +void update_frame_list(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, uint8_t enable)
42090 + uint16_t i, j, inc;
42091 + dwc_hc_t *hc = NULL;
42093 + if (!qh->channel) {
42094 + DWC_ERROR("qh->channel = %p", qh->channel);
42099 + DWC_ERROR("------hcd = %p", hcd);
42103 + if (!hcd->frame_list) {
42104 + DWC_ERROR("-------hcd->frame_list = %p", hcd->frame_list);
42108 + hc = qh->channel;
42109 + inc = frame_incr_val(qh);
42110 + if (qh->ep_type == UE_ISOCHRONOUS)
42111 + i = frame_list_idx(qh->sched_frame);
42118 + hcd->frame_list[j] |= (1 << hc->hc_num);
42120 + hcd->frame_list[j] &= ~(1 << hc->hc_num);
42121 + j = (j + inc) & (MAX_FRLIST_EN_NUM - 1);
42127 + if (qh->channel->speed == DWC_OTG_EP_SPEED_HIGH) {
42129 + /* TODO - check this */
42130 + inc = (8 + qh->interval - 1) / qh->interval;
42131 + for (i = 0; i < inc; i++) {
42132 + hc->schinfo |= j;
42133 + j = j << qh->interval;
42136 + hc->schinfo = 0xff;
42141 +void dump_frame_list(dwc_otg_hcd_t * hcd)
42144 + DWC_PRINTF("--FRAME LIST (hex) --\n");
42145 + for (i = 0; i < MAX_FRLIST_EN_NUM; i++) {
42146 + DWC_PRINTF("%x\t", hcd->frame_list[i]);
42147 + if (!(i % 8) && i)
42148 + DWC_PRINTF("\n");
42150 + DWC_PRINTF("\n----\n");
42155 +static void release_channel_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
42157 + dwc_hc_t *hc = qh->channel;
42158 + if (dwc_qh_is_non_per(qh)) {
42159 + if (!microframe_schedule)
42160 + hcd->non_periodic_channels--;
42162 + hcd->available_host_channels++;
42164 + update_frame_list(hcd, qh, 0);
42167 + * The condition is added to prevent double cleanup try in case of device
42168 + * disconnect. See channel cleanup in dwc_otg_hcd_disconnect_cb().
42171 + dwc_otg_hc_cleanup(hcd->core_if, hc);
42172 + DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
42176 + qh->channel = NULL;
42179 + if (qh->desc_list) {
42180 + dwc_memset(qh->desc_list, 0x00,
42181 + sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));
42186 + * Initializes a QH structure's Descriptor DMA related members.
42187 + * Allocates memory for descriptor list.
42188 + * On first periodic QH, allocates memory for FrameList
42189 + * and enables periodic scheduling.
42191 + * @param hcd The HCD state structure for the DWC OTG controller.
42192 + * @param qh The QH to init.
42194 + * @return 0 if successful, negative error code otherwise.
42196 +int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
42198 + struct device *dev = dwc_otg_hcd_to_dev(hcd);
42201 + if (qh->do_split) {
42202 + DWC_ERROR("SPLIT Transfers are not supported in Descriptor DMA.\n");
42206 + retval = desc_list_alloc(dev, qh);
42208 + if ((retval == 0)
42209 + && (qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)) {
42210 + if (!hcd->frame_list) {
42211 + retval = frame_list_alloc(hcd);
42212 + /* Enable periodic schedule on first periodic QH */
42214 + per_sched_enable(hcd, MAX_FRLIST_EN_NUM);
42224 + * Frees descriptor list memory associated with the QH.
42225 + * If QH is periodic and the last, frees FrameList memory
42226 + * and disables periodic scheduling.
42228 + * @param hcd The HCD state structure for the DWC OTG controller.
42229 + * @param qh The QH to init.
42231 +void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
42233 + struct device *dev = dwc_otg_hcd_to_dev(hcd);
42235 + desc_list_free(dev, qh);
42238 + * Channel still assigned due to some reasons.
42239 + * Seen on Isoc URB dequeue. Channel halted but no subsequent
42240 + * ChHalted interrupt to release the channel. Afterwards
42241 + * when it comes here from endpoint disable routine
42242 + * channel remains assigned.
42245 + release_channel_ddma(hcd, qh);
42247 + if ((qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)
42248 + && (microframe_schedule || !hcd->periodic_channels) && hcd->frame_list) {
42250 + per_sched_disable(hcd);
42251 + frame_list_free(hcd);
42255 +static uint8_t frame_to_desc_idx(dwc_otg_qh_t * qh, uint16_t frame_idx)
42257 + if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {
42259 + * Descriptor set(8 descriptors) index
42260 + * which is 8-aligned.
42262 + return (frame_idx & ((MAX_DMA_DESC_NUM_HS_ISOC / 8) - 1)) * 8;
42264 + return (frame_idx & (MAX_DMA_DESC_NUM_GENERIC - 1));
42269 + * Determine starting frame for Isochronous transfer.
42270 + * Few frames skipped to prevent race condition with HC.
42272 +static uint8_t calc_starting_frame(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
42273 + uint8_t * skip_frames)
42275 + uint16_t frame = 0;
42276 + hcd->frame_number = dwc_otg_hcd_get_frame_number(hcd);
42278 + /* sched_frame is always frame number(not uFrame) both in FS and HS !! */
42281 + * skip_frames is used to limit activated descriptors number
42282 + * to avoid the situation when HC services the last activated
42283 + * descriptor firstly.
42284 + * Example for FS:
42285 + * Current frame is 1, scheduled frame is 3. Since HC always fetches the descriptor
42286 + * corresponding to curr_frame+1, the descriptor corresponding to frame 2
42287 + * will be fetched. If the number of descriptors is max=64 (or greather) the
42288 + * list will be fully programmed with Active descriptors and it is possible
42289 + * case(rare) that the latest descriptor(considering rollback) corresponding
42290 + * to frame 2 will be serviced first. HS case is more probable because, in fact,
42291 + * up to 11 uframes(16 in the code) may be skipped.
42293 + if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {
42295 + * Consider uframe counter also, to start xfer asap.
42296 + * If half of the frame elapsed skip 2 frames otherwise
42298 + * Starting descriptor index must be 8-aligned, so
42299 + * if the current frame is near to complete the next one
42300 + * is skipped as well.
42303 + if (dwc_micro_frame_num(hcd->frame_number) >= 5) {
42304 + *skip_frames = 2 * 8;
42305 + frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames);
42307 + *skip_frames = 1 * 8;
42308 + frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames);
42311 + frame = dwc_full_frame_num(frame);
42314 + * Two frames are skipped for FS - the current and the next.
42315 + * But for descriptor programming, 1 frame(descriptor) is enough,
42316 + * see example above.
42318 + *skip_frames = 1;
42319 + frame = dwc_frame_num_inc(hcd->frame_number, 2);
42326 + * Calculate initial descriptor index for isochronous transfer
42327 + * based on scheduled frame.
42329 +static uint8_t recalc_initial_desc_idx(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
42331 + uint16_t frame = 0, fr_idx, fr_idx_tmp;
42332 + uint8_t skip_frames = 0;
42334 + * With current ISOC processing algorithm the channel is being
42335 + * released when no more QTDs in the list(qh->ntd == 0).
42336 + * Thus this function is called only when qh->ntd == 0 and qh->channel == 0.
42338 + * So qh->channel != NULL branch is not used and just not removed from the
42339 + * source file. It is required for another possible approach which is,
42340 + * do not disable and release the channel when ISOC session completed,
42341 + * just move QH to inactive schedule until new QTD arrives.
42342 + * On new QTD, the QH moved back to 'ready' schedule,
42343 + * starting frame and therefore starting desc_index are recalculated.
42344 + * In this case channel is released only on ep_disable.
42347 + /* Calculate starting descriptor index. For INTERRUPT endpoint it is always 0. */
42348 + if (qh->channel) {
42349 + frame = calc_starting_frame(hcd, qh, &skip_frames);
42351 + * Calculate initial descriptor index based on FrameList current bitmap
42352 + * and servicing period.
42354 + fr_idx_tmp = frame_list_idx(frame);
42356 + (MAX_FRLIST_EN_NUM + frame_list_idx(qh->sched_frame) -
42358 + % frame_incr_val(qh);
42359 + fr_idx = (fr_idx + fr_idx_tmp) % MAX_FRLIST_EN_NUM;
42361 + qh->sched_frame = calc_starting_frame(hcd, qh, &skip_frames);
42362 + fr_idx = frame_list_idx(qh->sched_frame);
42365 + qh->td_first = qh->td_last = frame_to_desc_idx(qh, fr_idx);
42367 + return skip_frames;
42370 +#define ISOC_URB_GIVEBACK_ASAP
42372 +#define MAX_ISOC_XFER_SIZE_FS 1023
42373 +#define MAX_ISOC_XFER_SIZE_HS 3072
42374 +#define DESCNUM_THRESHOLD 4
42376 +static void init_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
42377 + uint8_t skip_frames)
42379 + struct dwc_otg_hcd_iso_packet_desc *frame_desc;
42380 + dwc_otg_qtd_t *qtd;
42381 + dwc_otg_host_dma_desc_t *dma_desc;
42382 + uint16_t idx, inc, n_desc, ntd_max, max_xfer_size;
42384 + idx = qh->td_last;
42385 + inc = qh->interval;
42388 + ntd_max = (max_desc_num(qh) + qh->interval - 1) / qh->interval;
42389 + if (skip_frames && !qh->channel)
42390 + ntd_max = ntd_max - skip_frames / qh->interval;
42393 + (qh->dev_speed ==
42394 + DWC_OTG_EP_SPEED_HIGH) ? MAX_ISOC_XFER_SIZE_HS :
42395 + MAX_ISOC_XFER_SIZE_FS;
42397 + DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {
42398 + while ((qh->ntd < ntd_max)
42399 + && (qtd->isoc_frame_index_last <
42400 + qtd->urb->packet_count)) {
42402 + dma_desc = &qh->desc_list[idx];
42403 + dwc_memset(dma_desc, 0x00, sizeof(dwc_otg_host_dma_desc_t));
42405 + frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index_last];
42407 + if (frame_desc->length > max_xfer_size)
42408 + qh->n_bytes[idx] = max_xfer_size;
42410 + qh->n_bytes[idx] = frame_desc->length;
42411 + dma_desc->status.b_isoc.n_bytes = qh->n_bytes[idx];
42412 + dma_desc->status.b_isoc.a = 1;
42413 + dma_desc->status.b_isoc.sts = 0;
42415 + dma_desc->buf = qtd->urb->dma + frame_desc->offset;
42419 + qtd->isoc_frame_index_last++;
42421 +#ifdef ISOC_URB_GIVEBACK_ASAP
42423 + * Set IOC for each descriptor corresponding to the
42424 + * last frame of the URB.
42426 + if (qtd->isoc_frame_index_last ==
42427 + qtd->urb->packet_count)
42428 + dma_desc->status.b_isoc.ioc = 1;
42431 + idx = desclist_idx_inc(idx, inc, qh->dev_speed);
42435 + qtd->in_process = 1;
42438 + qh->td_last = idx;
42440 +#ifdef ISOC_URB_GIVEBACK_ASAP
42441 + /* Set IOC for the last descriptor if descriptor list is full */
42442 + if (qh->ntd == ntd_max) {
42443 + idx = desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
42444 + qh->desc_list[idx].status.b_isoc.ioc = 1;
42448 + * Set IOC bit only for one descriptor.
42449 + * Always try to be ahead of HW processing,
42450 + * i.e. on IOC generation driver activates next descriptors but
42451 + * core continues to process descriptors followed the one with IOC set.
42454 + if (n_desc > DESCNUM_THRESHOLD) {
42456 + * Move IOC "up". Required even if there is only one QTD
42457 + * in the list, cause QTDs migth continue to be queued,
42458 + * but during the activation it was only one queued.
42459 + * Actually more than one QTD might be in the list if this function called
42460 + * from XferCompletion - QTDs was queued during HW processing of the previous
42461 + * descriptor chunk.
42463 + idx = dwc_desclist_idx_dec(idx, inc * ((qh->ntd + 1) / 2), qh->dev_speed);
42466 + * Set the IOC for the latest descriptor
42467 + * if either number of descriptor is not greather than threshold
42468 + * or no more new descriptors activated.
42470 + idx = dwc_desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
42473 + qh->desc_list[idx].status.b_isoc.ioc = 1;
42477 +static void init_non_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
42481 + dwc_otg_host_dma_desc_t *dma_desc;
42482 + dwc_otg_qtd_t *qtd;
42483 + int num_packets, len, n_desc = 0;
42485 + hc = qh->channel;
42488 + * Start with hc->xfer_buff initialized in
42489 + * assign_and_init_hc(), then if SG transfer consists of multiple URBs,
42490 + * this pointer re-assigned to the buffer of the currently processed QTD.
42491 + * For non-SG request there is always one QTD active.
42494 + DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {
42497 + /* SG request - more than 1 QTDs */
42498 + hc->xfer_buff = (uint8_t *)qtd->urb->dma + qtd->urb->actual_length;
42499 + hc->xfer_len = qtd->urb->length - qtd->urb->actual_length;
42505 + dma_desc = &qh->desc_list[n_desc];
42506 + len = hc->xfer_len;
42508 + if (len > MAX_DMA_DESC_SIZE)
42509 + len = MAX_DMA_DESC_SIZE - hc->max_packet + 1;
42511 + if (hc->ep_is_in) {
42513 + num_packets = (len + hc->max_packet - 1) / hc->max_packet;
42515 + /* Need 1 packet for transfer length of 0. */
42518 + /* Always program an integral # of max packets for IN transfers. */
42519 + len = num_packets * hc->max_packet;
42522 + dma_desc->status.b.n_bytes = len;
42524 + qh->n_bytes[n_desc] = len;
42526 + if ((qh->ep_type == UE_CONTROL)
42527 + && (qtd->control_phase == DWC_OTG_CONTROL_SETUP))
42528 + dma_desc->status.b.sup = 1; /* Setup Packet */
42530 + dma_desc->status.b.a = 1; /* Active descriptor */
42531 + dma_desc->status.b.sts = 0;
42534 + ((unsigned long)hc->xfer_buff & 0xffffffff);
42537 + * Last descriptor(or single) of IN transfer
42538 + * with actual size less than MaxPacket.
42540 + if (len > hc->xfer_len) {
42541 + hc->xfer_len = 0;
42543 + hc->xfer_buff += len;
42544 + hc->xfer_len -= len;
42550 + while ((hc->xfer_len > 0) && (n_desc != MAX_DMA_DESC_NUM_GENERIC));
42553 + qtd->in_process = 1;
42555 + if (qh->ep_type == UE_CONTROL)
42558 + if (n_desc == MAX_DMA_DESC_NUM_GENERIC)
42563 + /* Request Transfer Complete interrupt for the last descriptor */
42564 + qh->desc_list[n_desc - 1].status.b.ioc = 1;
42565 + /* End of List indicator */
42566 + qh->desc_list[n_desc - 1].status.b.eol = 1;
42568 + hc->ntd = n_desc;
42573 + * For Control and Bulk endpoints initializes descriptor list
42574 + * and starts the transfer.
42576 + * For Interrupt and Isochronous endpoints initializes descriptor list
42577 + * then updates FrameList, marking appropriate entries as active.
42578 + * In case of Isochronous, the starting descriptor index is calculated based
42579 + * on the scheduled frame, but only on the first transfer descriptor within a session.
42580 + * Then starts the transfer via enabling the channel.
42581 + * For Isochronous endpoint the channel is not halted on XferComplete
42582 + * interrupt so remains assigned to the endpoint(QH) until session is done.
42584 + * @param hcd The HCD state structure for the DWC OTG controller.
42585 + * @param qh The QH to init.
42587 + * @return 0 if successful, negative error code otherwise.
42589 +void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
42591 + /* Channel is already assigned */
42592 + dwc_hc_t *hc = qh->channel;
42593 + uint8_t skip_frames = 0;
42595 + switch (hc->ep_type) {
42596 + case DWC_OTG_EP_TYPE_CONTROL:
42597 + case DWC_OTG_EP_TYPE_BULK:
42598 + init_non_isoc_dma_desc(hcd, qh);
42600 + dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
42602 + case DWC_OTG_EP_TYPE_INTR:
42603 + init_non_isoc_dma_desc(hcd, qh);
42605 + update_frame_list(hcd, qh, 1);
42607 + dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
42609 + case DWC_OTG_EP_TYPE_ISOC:
42612 + skip_frames = recalc_initial_desc_idx(hcd, qh);
42614 + init_isoc_dma_desc(hcd, qh, skip_frames);
42616 + if (!hc->xfer_started) {
42618 + update_frame_list(hcd, qh, 1);
42621 + * Always set to max, instead of actual size.
42622 + * Otherwise ntd will be changed with
42623 + * channel being enabled. Not recommended.
42626 + hc->ntd = max_desc_num(qh);
42627 + /* Enable channel only once for ISOC */
42628 + dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
42638 +static void complete_isoc_xfer_ddma(dwc_otg_hcd_t * hcd,
42640 + dwc_otg_hc_regs_t * hc_regs,
42641 + dwc_otg_halt_status_e halt_status)
42643 + struct dwc_otg_hcd_iso_packet_desc *frame_desc;
42644 + dwc_otg_qtd_t *qtd, *qtd_tmp;
42645 + dwc_otg_qh_t *qh;
42646 + dwc_otg_host_dma_desc_t *dma_desc;
42647 + uint16_t idx, remain;
42648 + uint8_t urb_compl;
42651 + idx = qh->td_first;
42653 + if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
42654 + DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry)
42655 + qtd->in_process = 0;
42657 + } else if ((halt_status == DWC_OTG_HC_XFER_AHB_ERR) ||
42658 + (halt_status == DWC_OTG_HC_XFER_BABBLE_ERR)) {
42660 + * Channel is halted in these error cases.
42661 + * Considered as serious issues.
42662 + * Complete all URBs marking all frames as failed,
42663 + * irrespective whether some of the descriptors(frames) succeeded or no.
42664 + * Pass error code to completion routine as well, to
42665 + * update urb->status, some of class drivers might use it to stop
42666 + * queing transfer requests.
42668 + int err = (halt_status == DWC_OTG_HC_XFER_AHB_ERR)
42670 + : (-DWC_E_OVERFLOW);
42672 + DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
42673 + for (idx = 0; idx < qtd->urb->packet_count; idx++) {
42674 + frame_desc = &qtd->urb->iso_descs[idx];
42675 + frame_desc->status = err;
42677 + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, err);
42678 + dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
42683 + DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
42685 + if (!qtd->in_process)
42692 + dma_desc = &qh->desc_list[idx];
42694 + frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
42695 + remain = hc->ep_is_in ? dma_desc->status.b_isoc.n_bytes : 0;
42697 + if (dma_desc->status.b_isoc.sts == DMA_DESC_STS_PKTERR) {
42699 + * XactError or, unable to complete all the transactions
42700 + * in the scheduled micro-frame/frame,
42701 + * both indicated by DMA_DESC_STS_PKTERR.
42703 + qtd->urb->error_count++;
42704 + frame_desc->actual_length = qh->n_bytes[idx] - remain;
42705 + frame_desc->status = -DWC_E_PROTOCOL;
42709 + frame_desc->actual_length = qh->n_bytes[idx] - remain;
42710 + frame_desc->status = 0;
42713 + if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
42715 + * urb->status is not used for isoc transfers here.
42716 + * The individual frame_desc status are used instead.
42719 + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
42720 + dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
42723 + * This check is necessary because urb_dequeue can be called
42724 + * from urb complete callback(sound driver example).
42725 + * All pending URBs are dequeued there, so no need for
42726 + * further processing.
42728 + if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
42738 + /* Stop if IOC requested descriptor reached */
42739 + if (dma_desc->status.b_isoc.ioc) {
42740 + idx = desclist_idx_inc(idx, qh->interval, hc->speed);
42744 + idx = desclist_idx_inc(idx, qh->interval, hc->speed);
42749 + while (idx != qh->td_first);
42752 + qh->td_first = idx;
42755 +uint8_t update_non_isoc_urb_state_ddma(dwc_otg_hcd_t * hcd,
42757 + dwc_otg_qtd_t * qtd,
42758 + dwc_otg_host_dma_desc_t * dma_desc,
42759 + dwc_otg_halt_status_e halt_status,
42760 + uint32_t n_bytes, uint8_t * xfer_done)
42763 + uint16_t remain = hc->ep_is_in ? dma_desc->status.b.n_bytes : 0;
42764 + dwc_otg_hcd_urb_t *urb = qtd->urb;
42766 + if (halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
42767 + urb->status = -DWC_E_IO;
42770 + if (dma_desc->status.b.sts == DMA_DESC_STS_PKTERR) {
42771 + switch (halt_status) {
42772 + case DWC_OTG_HC_XFER_STALL:
42773 + urb->status = -DWC_E_PIPE;
42775 + case DWC_OTG_HC_XFER_BABBLE_ERR:
42776 + urb->status = -DWC_E_OVERFLOW;
42778 + case DWC_OTG_HC_XFER_XACT_ERR:
42779 + urb->status = -DWC_E_PROTOCOL;
42782 + DWC_ERROR("%s: Unhandled descriptor error status (%d)\n", __func__,
42789 + if (dma_desc->status.b.a == 1) {
42790 + DWC_DEBUGPL(DBG_HCDV,
42791 + "Active descriptor encountered on channel %d\n",
42796 + if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL) {
42797 + if (qtd->control_phase == DWC_OTG_CONTROL_DATA) {
42798 + urb->actual_length += n_bytes - remain;
42799 + if (remain || urb->actual_length == urb->length) {
42801 + * For Control Data stage do not set urb->status=0 to prevent
42802 + * URB callback. Set it when Status phase done. See below.
42807 + } else if (qtd->control_phase == DWC_OTG_CONTROL_STATUS) {
42811 + /* No handling for SETUP stage */
42813 + /* BULK and INTR */
42814 + urb->actual_length += n_bytes - remain;
42815 + if (remain || urb->actual_length == urb->length) {
42824 +static void complete_non_isoc_xfer_ddma(dwc_otg_hcd_t * hcd,
42826 + dwc_otg_hc_regs_t * hc_regs,
42827 + dwc_otg_halt_status_e halt_status)
42829 + dwc_otg_hcd_urb_t *urb = NULL;
42830 + dwc_otg_qtd_t *qtd, *qtd_tmp;
42831 + dwc_otg_qh_t *qh;
42832 + dwc_otg_host_dma_desc_t *dma_desc;
42833 + uint32_t n_bytes, n_desc, i;
42834 + uint8_t failed = 0, xfer_done;
42840 + if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
42841 + DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
42842 + qtd->in_process = 0;
42847 + DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {
42854 + for (i = 0; i < qtd->n_desc; i++) {
42855 + dma_desc = &qh->desc_list[n_desc];
42857 + n_bytes = qh->n_bytes[n_desc];
42860 + update_non_isoc_urb_state_ddma(hcd, hc, qtd,
42862 + halt_status, n_bytes,
42867 + && (urb->status != -DWC_E_IN_PROGRESS))) {
42869 + hcd->fops->complete(hcd, urb->priv, urb,
42871 + dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
42875 + } else if (qh->ep_type == UE_CONTROL) {
42876 + if (qtd->control_phase == DWC_OTG_CONTROL_SETUP) {
42877 + if (urb->length > 0) {
42878 + qtd->control_phase = DWC_OTG_CONTROL_DATA;
42880 + qtd->control_phase = DWC_OTG_CONTROL_STATUS;
42882 + DWC_DEBUGPL(DBG_HCDV, " Control setup transaction done\n");
42883 + } else if (qtd->control_phase == DWC_OTG_CONTROL_DATA) {
42885 + qtd->control_phase = DWC_OTG_CONTROL_STATUS;
42886 + DWC_DEBUGPL(DBG_HCDV, " Control data transfer done\n");
42887 + } else if (i + 1 == qtd->n_desc) {
42889 + * Last descriptor for Control data stage which is
42890 + * not completed yet.
42892 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
42904 + if (qh->ep_type != UE_CONTROL) {
42906 + * Resetting the data toggle for bulk
42907 + * and interrupt endpoints in case of stall. See handle_hc_stall_intr()
42909 + if (halt_status == DWC_OTG_HC_XFER_STALL)
42910 + qh->data_toggle = DWC_OTG_HC_PID_DATA0;
42912 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
42915 + if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
42916 + hcint_data_t hcint;
42917 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
42918 + if (hcint.b.nyet) {
42920 + * Got a NYET on the last transaction of the transfer. It
42921 + * means that the endpoint should be in the PING state at the
42922 + * beginning of the next transfer.
42924 + qh->ping_state = 1;
42925 + clear_hc_int(hc_regs, nyet);
42933 + * This function is called from interrupt handlers.
42934 + * Scans the descriptor list, updates URB's status and
42935 + * calls completion routine for the URB if it's done.
42936 + * Releases the channel to be used by other transfers.
42937 + * In case of Isochronous endpoint the channel is not halted until
42938 + * the end of the session, i.e. QTD list is empty.
42939 + * If periodic channel released the FrameList is updated accordingly.
42941 + * Calls transaction selection routines to activate pending transfers.
42943 + * @param hcd The HCD state structure for the DWC OTG controller.
42944 + * @param hc Host channel, the transfer is completed on.
42945 + * @param hc_regs Host channel registers.
42946 + * @param halt_status Reason the channel is being halted,
42947 + * or just XferComplete for isochronous transfer
42949 +void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd,
42951 + dwc_otg_hc_regs_t * hc_regs,
42952 + dwc_otg_halt_status_e halt_status)
42954 + uint8_t continue_isoc_xfer = 0;
42955 + dwc_otg_transaction_type_e tr_type;
42956 + dwc_otg_qh_t *qh = hc->qh;
42958 + if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
42960 + complete_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);
42962 + /* Release the channel if halted or session completed */
42963 + if (halt_status != DWC_OTG_HC_XFER_COMPLETE ||
42964 + DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
42966 + /* Halt the channel if session completed */
42967 + if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
42968 + dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
42971 + release_channel_ddma(hcd, qh);
42972 + dwc_otg_hcd_qh_remove(hcd, qh);
42974 + /* Keep in assigned schedule to continue transfer */
42975 + DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
42976 + &qh->qh_list_entry);
42977 + continue_isoc_xfer = 1;
42980 + /** @todo Consider the case when period exceeds FrameList size.
42981 + * Frame Rollover interrupt should be used.
42984 + /* Scan descriptor list to complete the URB(s), then release the channel */
42985 + complete_non_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);
42987 + release_channel_ddma(hcd, qh);
42988 + dwc_otg_hcd_qh_remove(hcd, qh);
42990 + if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
42991 + /* Add back to inactive non-periodic schedule on normal completion */
42992 + dwc_otg_hcd_qh_add(hcd, qh);
42996 + tr_type = dwc_otg_hcd_select_transactions(hcd);
42997 + if (tr_type != DWC_OTG_TRANSACTION_NONE || continue_isoc_xfer) {
42998 + if (continue_isoc_xfer) {
42999 + if (tr_type == DWC_OTG_TRANSACTION_NONE) {
43000 + tr_type = DWC_OTG_TRANSACTION_PERIODIC;
43001 + } else if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC) {
43002 + tr_type = DWC_OTG_TRANSACTION_ALL;
43005 + dwc_otg_hcd_queue_transactions(hcd, tr_type);
43009 +#endif /* DWC_DEVICE_ONLY */
43011 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h
43013 +/* ==========================================================================
43014 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_if.h $
43015 + * $Revision: #12 $
43016 + * $Date: 2011/10/26 $
43017 + * $Change: 1873028 $
43019 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
43020 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
43021 + * otherwise expressly agreed to in writing between Synopsys and you.
43023 + * The Software IS NOT an item of Licensed Software or Licensed Product under
43024 + * any End User Software License Agreement or Agreement for Licensed Product
43025 + * with Synopsys or any supplement thereto. You are permitted to use and
43026 + * redistribute this Software in source and binary forms, with or without
43027 + * modification, provided that redistributions of source code must retain this
43028 + * notice. You may not view, use, disclose, copy or distribute this file or
43029 + * any information contained herein except pursuant to this license grant from
43030 + * Synopsys. If you do not agree with this notice, including the disclaimer
43031 + * below, then you are not authorized to use the Software.
43033 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
43034 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43035 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43036 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
43037 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
43038 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
43039 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
43040 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43041 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
43042 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
43044 + * ========================================================================== */
43045 +#ifndef DWC_DEVICE_ONLY
43046 +#ifndef __DWC_HCD_IF_H__
43047 +#define __DWC_HCD_IF_H__
43049 +#include "dwc_otg_core_if.h"
43052 + * This file defines DWC_OTG HCD Core API.
43055 +struct dwc_otg_hcd;
43056 +typedef struct dwc_otg_hcd dwc_otg_hcd_t;
43058 +struct dwc_otg_hcd_urb;
43059 +typedef struct dwc_otg_hcd_urb dwc_otg_hcd_urb_t;
43061 +/** @name HCD Function Driver Callbacks */
43064 +/** This function is called whenever core switches to host mode. */
43065 +typedef int (*dwc_otg_hcd_start_cb_t) (dwc_otg_hcd_t * hcd);
43067 +/** This function is called when device has been disconnected */
43068 +typedef int (*dwc_otg_hcd_disconnect_cb_t) (dwc_otg_hcd_t * hcd);
43070 +/** Wrapper provides this function to HCD to core, so it can get hub information to which device is connected */
43071 +typedef int (*dwc_otg_hcd_hub_info_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
43072 + void *urb_handle,
43073 + uint32_t * hub_addr,
43074 + uint32_t * port_addr);
43075 +/** Via this function HCD core gets device speed */
43076 +typedef int (*dwc_otg_hcd_speed_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
43077 + void *urb_handle);
43079 +/** This function is called when urb is completed */
43080 +typedef int (*dwc_otg_hcd_complete_urb_cb_t) (dwc_otg_hcd_t * hcd,
43081 + void *urb_handle,
43082 + dwc_otg_hcd_urb_t * dwc_otg_urb,
43085 +/** Via this function HCD core gets b_hnp_enable parameter */
43086 +typedef int (*dwc_otg_hcd_get_b_hnp_enable) (dwc_otg_hcd_t * hcd);
43088 +struct dwc_otg_hcd_function_ops {
43089 + dwc_otg_hcd_start_cb_t start;
43090 + dwc_otg_hcd_disconnect_cb_t disconnect;
43091 + dwc_otg_hcd_hub_info_from_urb_cb_t hub_info;
43092 + dwc_otg_hcd_speed_from_urb_cb_t speed;
43093 + dwc_otg_hcd_complete_urb_cb_t complete;
43094 + dwc_otg_hcd_get_b_hnp_enable get_b_hnp_enable;
43098 +/** @name HCD Core API */
43100 +/** This function allocates dwc_otg_hcd structure and returns pointer on it. */
43101 +extern dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void);
43103 +/** This function should be called to initiate HCD Core.
43105 + * @param hcd The HCD
43106 + * @param core_if The DWC_OTG Core
43108 + * Returns -DWC_E_NO_MEMORY if no enough memory.
43109 + * Returns 0 on success
43111 +extern int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if);
43115 + * @param hcd The HCD
43117 +extern void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd);
43119 +/** This function should be called on every hardware interrupt.
43121 + * @param dwc_otg_hcd The HCD
43123 + * Returns non zero if interrupt is handled
43124 + * Return 0 if interrupt is not handled
43126 +extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
43128 +/** This function is used to handle the fast interrupt
43131 +#ifdef CONFIG_ARM64
43132 +extern void dwc_otg_hcd_handle_fiq(void);
43134 +extern void __attribute__ ((naked)) dwc_otg_hcd_handle_fiq(void);
43138 + * Returns private data set by
43139 + * dwc_otg_hcd_set_priv_data function.
43141 + * @param hcd The HCD
43143 +extern void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd);
43146 + * Set private data.
43148 + * @param hcd The HCD
43149 + * @param priv_data pointer to be stored in private data
43151 +extern void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data);
43154 + * This function initializes the HCD Core.
43156 + * @param hcd The HCD
43157 + * @param fops The Function Driver Operations data structure containing pointers to all callbacks.
43159 + * Returns -DWC_E_NO_DEVICE if Core is currently is in device mode.
43160 + * Returns 0 on success
43162 +extern int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
43163 + struct dwc_otg_hcd_function_ops *fops);
43166 + * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
43169 + * @param hcd The HCD
43171 +extern void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd);
43174 + * Handles hub class-specific requests.
43176 + * @param dwc_otg_hcd The HCD
43177 + * @param typeReq Request Type
43178 + * @param wValue wValue from control request
43179 + * @param wIndex wIndex from control request
43180 + * @param buf data buffer
43181 + * @param wLength data buffer length
43183 + * Returns -DWC_E_INVALID if invalid argument is passed
43184 + * Returns 0 on success
43186 +extern int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
43187 + uint16_t typeReq, uint16_t wValue,
43188 + uint16_t wIndex, uint8_t * buf,
43189 + uint16_t wLength);
43192 + * Returns otg port number.
43194 + * @param hcd The HCD
43196 +extern uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd);
43199 + * Returns OTG version - either 1.3 or 2.0.
43201 + * @param core_if The core_if structure pointer
43203 +extern uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if);
43206 + * Returns 1 if currently core is acting as B host, and 0 otherwise.
43208 + * @param hcd The HCD
43210 +extern uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd);
43213 + * Returns current frame number.
43215 + * @param hcd The HCD
43217 +extern int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * hcd);
43220 + * Dumps hcd state.
43222 + * @param hcd The HCD
43224 +extern void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd);
43227 + * Dump the average frame remaining at SOF. This can be used to
43228 + * determine average interrupt latency. Frame remaining is also shown for
43229 + * start transfer and two additional sample points.
43230 + * Currently this function is not implemented.
43232 + * @param hcd The HCD
43234 +extern void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd);
43237 + * Sends LPM transaction to the local device.
43239 + * @param hcd The HCD
43240 + * @param devaddr Device Address
43241 + * @param hird Host initiated resume duration
43242 + * @param bRemoteWake Value of bRemoteWake field in LPM transaction
43244 + * Returns negative value if sending LPM transaction was not succeeded.
43245 + * Returns 0 on success.
43247 +extern int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr,
43248 + uint8_t hird, uint8_t bRemoteWake);
43250 +/* URB interface */
43253 + * Allocates memory for dwc_otg_hcd_urb structure.
43254 + * Allocated memory should be freed by call of DWC_FREE.
43256 + * @param hcd The HCD
43257 + * @param iso_desc_count Count of ISOC descriptors
43258 + * @param atomic_alloc Specefies whether to perform atomic allocation.
43260 +extern dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
43261 + int iso_desc_count,
43262 + int atomic_alloc);
43265 + * Set pipe information in URB.
43267 + * @param hcd_urb DWC_OTG URB
43268 + * @param devaddr Device Address
43269 + * @param ep_num Endpoint Number
43270 + * @param ep_type Endpoint Type
43271 + * @param ep_dir Endpoint Direction
43272 + * @param mps Max Packet Size
43274 +extern void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * hcd_urb,
43275 + uint8_t devaddr, uint8_t ep_num,
43276 + uint8_t ep_type, uint8_t ep_dir,
43279 +/* Transfer flags */
43280 +#define URB_GIVEBACK_ASAP 0x1
43281 +#define URB_SEND_ZERO_PACKET 0x2
43284 + * Sets dwc_otg_hcd_urb parameters.
43286 + * @param urb DWC_OTG URB allocated by dwc_otg_hcd_urb_alloc function.
43287 + * @param urb_handle Unique handle for request, this will be passed back
43288 + * to function driver in completion callback.
43289 + * @param buf The buffer for the data
43290 + * @param dma The DMA buffer for the data
43291 + * @param buflen Transfer length
43292 + * @param sp Buffer for setup data
43293 + * @param sp_dma DMA address of setup data buffer
43294 + * @param flags Transfer flags
43295 + * @param interval Polling interval for interrupt or isochronous transfers.
43297 +extern void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * urb,
43298 + void *urb_handle, void *buf,
43299 + dwc_dma_t dma, uint32_t buflen, void *sp,
43300 + dwc_dma_t sp_dma, uint32_t flags,
43301 + uint16_t interval);
43303 +/** Gets status from dwc_otg_hcd_urb
43305 + * @param dwc_otg_urb DWC_OTG URB
43307 +extern uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb);
43309 +/** Gets actual length from dwc_otg_hcd_urb
43311 + * @param dwc_otg_urb DWC_OTG URB
43313 +extern uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t *
43316 +/** Gets error count from dwc_otg_hcd_urb. Only for ISOC URBs
43318 + * @param dwc_otg_urb DWC_OTG URB
43320 +extern uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t *
43323 +/** Set ISOC descriptor offset and length
43325 + * @param dwc_otg_urb DWC_OTG URB
43326 + * @param desc_num ISOC descriptor number
43327 + * @param offset Offset from beginig of buffer.
43328 + * @param length Transaction length
43330 +extern void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
43331 + int desc_num, uint32_t offset,
43332 + uint32_t length);
43334 +/** Get status of ISOC descriptor, specified by desc_num
43336 + * @param dwc_otg_urb DWC_OTG URB
43337 + * @param desc_num ISOC descriptor number
43339 +extern uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t *
43340 + dwc_otg_urb, int desc_num);
43342 +/** Get actual length of ISOC descriptor, specified by desc_num
43344 + * @param dwc_otg_urb DWC_OTG URB
43345 + * @param desc_num ISOC descriptor number
43347 +extern uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
43351 +/** Queue URB. After transfer is completes, the complete callback will be called with the URB status
43353 + * @param dwc_otg_hcd The HCD
43354 + * @param dwc_otg_urb DWC_OTG URB
43355 + * @param ep_handle Out parameter for returning endpoint handle
43356 + * @param atomic_alloc Flag to do atomic allocation if needed
43358 + * Returns -DWC_E_NO_DEVICE if no device is connected.
43359 + * Returns -DWC_E_NO_MEMORY if there is no enough memory.
43360 + * Returns 0 on success.
43362 +extern int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * dwc_otg_hcd,
43363 + dwc_otg_hcd_urb_t * dwc_otg_urb,
43364 + void **ep_handle, int atomic_alloc);
43366 +/** De-queue the specified URB
43368 + * @param dwc_otg_hcd The HCD
43369 + * @param dwc_otg_urb DWC_OTG URB
43371 +extern int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * dwc_otg_hcd,
43372 + dwc_otg_hcd_urb_t * dwc_otg_urb);
43374 +/** Frees resources in the DWC_otg controller related to a given endpoint.
43375 + * Any URBs for the endpoint must already be dequeued.
43377 + * @param hcd The HCD
43378 + * @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
43379 + * @param retry Number of retries if there are queued transfers.
43381 + * Returns -DWC_E_INVALID if invalid arguments are passed.
43382 + * Returns 0 on success
43384 +extern int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
43387 +/* Resets the data toggle in qh structure. This function can be called from
43388 + * usb_clear_halt routine.
43390 + * @param hcd The HCD
43391 + * @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
43393 + * Returns -DWC_E_INVALID if invalid arguments are passed.
43394 + * Returns 0 on success
43396 +extern int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle);
43398 +/** Returns 1 if status of specified port is changed and 0 otherwise.
43400 + * @param hcd The HCD
43401 + * @param port Port number
43403 +extern int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port);
43405 +/** Call this function to check if bandwidth was allocated for specified endpoint.
43406 + * Only for ISOC and INTERRUPT endpoints.
43408 + * @param hcd The HCD
43409 + * @param ep_handle Endpoint handle
43411 +extern int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd,
43412 + void *ep_handle);
43414 +/** Call this function to check if bandwidth was freed for specified endpoint.
43416 + * @param hcd The HCD
43417 + * @param ep_handle Endpoint handle
43419 +extern int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle);
43421 +/** Returns bandwidth allocated for specified endpoint in microseconds.
43422 + * Only for ISOC and INTERRUPT endpoints.
43424 + * @param hcd The HCD
43425 + * @param ep_handle Endpoint handle
43427 +extern uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd,
43428 + void *ep_handle);
43432 +#endif /* __DWC_HCD_IF_H__ */
43433 +#endif /* DWC_DEVICE_ONLY */
43435 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
43437 +/* ==========================================================================
43438 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $
43439 + * $Revision: #89 $
43440 + * $Date: 2011/10/20 $
43441 + * $Change: 1869487 $
43443 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
43444 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
43445 + * otherwise expressly agreed to in writing between Synopsys and you.
43447 + * The Software IS NOT an item of Licensed Software or Licensed Product under
43448 + * any End User Software License Agreement or Agreement for Licensed Product
43449 + * with Synopsys or any supplement thereto. You are permitted to use and
43450 + * redistribute this Software in source and binary forms, with or without
43451 + * modification, provided that redistributions of source code must retain this
43452 + * notice. You may not view, use, disclose, copy or distribute this file or
43453 + * any information contained herein except pursuant to this license grant from
43454 + * Synopsys. If you do not agree with this notice, including the disclaimer
43455 + * below, then you are not authorized to use the Software.
43457 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
43458 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43459 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43460 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
43461 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
43462 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
43463 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
43464 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43465 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
43466 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
43468 + * ========================================================================== */
43469 +#ifndef DWC_DEVICE_ONLY
43471 +#include "dwc_otg_hcd.h"
43472 +#include "dwc_otg_regs.h"
43474 +#include <linux/jiffies.h>
43476 +#include <asm/fiq.h>
43479 +extern bool microframe_schedule;
43482 + * This file contains the implementation of the HCD Interrupt handlers.
43485 +int fiq_done, int_done;
43488 +char buffer[1000*16];
43490 +void notrace _fiq_print(FIQDBG_T dbg_lvl, char *fmt, ...)
43492 + FIQDBG_T dbg_lvl_req = FIQDBG_PORTHUB;
43495 + hfnum_data_t hfnum = { .d32 = FIQ_READ(dwc_regs_base + 0x408) };
43497 + if(dbg_lvl & dbg_lvl_req || dbg_lvl == FIQDBG_ERR)
43499 + local_fiq_disable();
43500 + snprintf(text, 9, "%4d%d:%d ", hfnum.b.frnum/8, hfnum.b.frnum%8, 8 - hfnum.b.frrem/937);
43501 + va_start(args, fmt);
43502 + vsnprintf(text+8, 9, fmt, args);
43505 + memcpy(buffer + wptr, text, 16);
43506 + wptr = (wptr + 16) % sizeof(buffer);
43507 + local_fiq_enable();
43512 +/** This function handles interrupts for the HCD. */
43513 +int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd)
43516 + static int last_time;
43517 + dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
43518 + gintsts_data_t gintsts;
43519 + gintmsk_data_t gintmsk;
43520 + hfnum_data_t hfnum;
43521 + haintmsk_data_t haintmsk;
43524 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
43528 + gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
43529 + gintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
43531 + /* Exit from ISR if core is hibernated */
43532 + if (core_if->hibernation_suspend == 1) {
43533 + goto exit_handler_routine;
43535 + DWC_SPINLOCK(dwc_otg_hcd->lock);
43536 + /* Check if HOST Mode */
43537 + if (dwc_otg_is_host_mode(core_if)) {
43538 + if (fiq_enable) {
43539 + local_fiq_disable();
43540 + fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);
43541 + /* Pull in from the FIQ's disabled mask */
43542 + gintmsk.d32 = gintmsk.d32 | ~(dwc_otg_hcd->fiq_state->gintmsk_saved.d32);
43543 + dwc_otg_hcd->fiq_state->gintmsk_saved.d32 = ~0;
43546 + if (fiq_fsm_enable && ( 0x0000FFFF & ~(dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint))) {
43547 + gintsts.b.hcintr = 1;
43550 + /* Danger will robinson: fake a SOF if necessary */
43551 + if (fiq_fsm_enable && (dwc_otg_hcd->fiq_state->gintmsk_saved.b.sofintr == 1)) {
43552 + gintsts.b.sofintr = 1;
43554 + gintsts.d32 &= gintmsk.d32;
43556 + if (fiq_enable) {
43557 + fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);
43558 + local_fiq_enable();
43561 + if (!gintsts.d32) {
43562 + goto exit_handler_routine;
43566 + // We should be OK doing this because the common interrupts should already have been serviced
43567 + /* Don't print debug message in the interrupt handler on SOF */
43569 + if (gintsts.d32 != DWC_SOF_INTR_MASK)
43571 + DWC_DEBUGPL(DBG_HCDI, "\n");
43576 + if (gintsts.d32 != DWC_SOF_INTR_MASK)
43578 + DWC_DEBUGPL(DBG_HCDI,
43579 + "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x core_if=%p\n",
43580 + gintsts.d32, core_if);
43582 + hfnum.d32 = DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs->hfnum);
43583 + if (gintsts.b.sofintr) {
43584 + retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd);
43587 + if (gintsts.b.rxstsqlvl) {
43589 + dwc_otg_hcd_handle_rx_status_q_level_intr
43592 + if (gintsts.b.nptxfempty) {
43594 + dwc_otg_hcd_handle_np_tx_fifo_empty_intr
43597 + if (gintsts.b.i2cintr) {
43598 + /** @todo Implement i2cintr handler. */
43600 + if (gintsts.b.portintr) {
43602 + gintmsk_data_t gintmsk = { .b.portintr = 1};
43603 + retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
43604 + if (fiq_enable) {
43605 + local_fiq_disable();
43606 + fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);
43607 + DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
43608 + fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);
43609 + local_fiq_enable();
43611 + DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
43614 + if (gintsts.b.hcintr) {
43615 + retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
43617 + if (gintsts.b.ptxfempty) {
43619 + dwc_otg_hcd_handle_perio_tx_fifo_empty_intr
43624 + if (gintsts.d32 != DWC_SOF_INTR_MASK)
43627 + DWC_DEBUGPL(DBG_HCDI,
43628 + "DWC OTG HCD Finished Servicing Interrupts\n");
43629 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
43630 + DWC_READ_REG32(&global_regs->gintsts));
43631 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
43632 + DWC_READ_REG32(&global_regs->gintmsk));
43638 + if (gintsts.d32 != DWC_SOF_INTR_MASK)
43640 + DWC_DEBUGPL(DBG_HCDI, "\n");
43645 +exit_handler_routine:
43646 + if (fiq_enable) {
43647 + gintmsk_data_t gintmsk_new;
43648 + haintmsk_data_t haintmsk_new;
43649 + local_fiq_disable();
43650 + fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);
43651 + gintmsk_new.d32 = *(volatile uint32_t *)&dwc_otg_hcd->fiq_state->gintmsk_saved.d32;
43652 + if(fiq_fsm_enable)
43653 + haintmsk_new.d32 = *(volatile uint32_t *)&dwc_otg_hcd->fiq_state->haintmsk_saved.d32;
43655 + haintmsk_new.d32 = 0x0000FFFF;
43657 + /* The FIQ could have sneaked another interrupt in. If so, don't clear MPHI */
43658 + if ((gintmsk_new.d32 == ~0) && (haintmsk_new.d32 == 0x0000FFFF)) {
43659 + if (dwc_otg_hcd->fiq_state->mphi_regs.swirq_clr) {
43660 + DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.swirq_clr, 1);
43662 + DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.intstat, (1<<16));
43664 + if (dwc_otg_hcd->fiq_state->mphi_int_count >= 50) {
43665 + fiq_print(FIQDBG_INT, dwc_otg_hcd->fiq_state, "MPHI CLR");
43666 + DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl, ((1<<31) + (1<<16)));
43667 + while (!(DWC_READ_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & (1 << 17)))
43669 + DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl, (1<<31));
43670 + dwc_otg_hcd->fiq_state->mphi_int_count = 0;
43674 + haintmsk.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk);
43675 + /* Re-enable interrupts that the FIQ masked (first time round) */
43676 + FIQ_WRITE(dwc_otg_hcd->fiq_state->dwc_regs_base + GINTMSK, gintmsk.d32);
43677 + fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);
43678 + local_fiq_enable();
43680 + if ((jiffies / HZ) > last_time) {
43681 + //dwc_otg_qh_t *qh;
43682 + //dwc_list_link_t *cur;
43683 + /* Once a second output the fiq and irq numbers, useful for debug */
43684 + last_time = jiffies / HZ;
43685 + // DWC_WARN("np_kick=%d AHC=%d sched_frame=%d cur_frame=%d int_done=%d fiq_done=%d",
43686 + // dwc_otg_hcd->fiq_state->kick_np_queues, dwc_otg_hcd->available_host_channels,
43687 + // dwc_otg_hcd->fiq_state->next_sched_frame, hfnum.b.frnum, int_done, dwc_otg_hcd->fiq_state->fiq_done);
43688 + //printk(KERN_WARNING "Periodic queues:\n");
43692 + DWC_SPINUNLOCK(dwc_otg_hcd->lock);
43696 +#ifdef DWC_TRACK_MISSED_SOFS
43698 +#warning Compiling code to track missed SOFs
43699 +#define FRAME_NUM_ARRAY_SIZE 1000
43701 + * This function is for debug only.
43703 +static inline void track_missed_sofs(uint16_t curr_frame_number)
43705 + static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];
43706 + static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
43707 + static int frame_num_idx = 0;
43708 + static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM;
43709 + static int dumped_frame_num_array = 0;
43711 + if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
43712 + if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) !=
43713 + curr_frame_number) {
43714 + frame_num_array[frame_num_idx] = curr_frame_number;
43715 + last_frame_num_array[frame_num_idx++] = last_frame_num;
43717 + } else if (!dumped_frame_num_array) {
43719 + DWC_PRINTF("Frame Last Frame\n");
43720 + DWC_PRINTF("----- ----------\n");
43721 + for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
43722 + DWC_PRINTF("0x%04x 0x%04x\n",
43723 + frame_num_array[i], last_frame_num_array[i]);
43725 + dumped_frame_num_array = 1;
43727 + last_frame_num = curr_frame_number;
43732 + * Handles the start-of-frame interrupt in host mode. Non-periodic
43733 + * transactions may be queued to the DWC_otg controller for the current
43734 + * (micro)frame. Periodic transactions may be queued to the controller for the
43735 + * next (micro)frame.
43737 +int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd)
43739 + hfnum_data_t hfnum;
43740 + gintsts_data_t gintsts = { .d32 = 0 };
43741 + dwc_list_link_t *qh_entry;
43742 + dwc_otg_qh_t *qh;
43743 + dwc_otg_transaction_type_e tr_type;
43744 + int did_something = 0;
43745 + int32_t next_sched_frame = -1;
43748 + DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
43751 + DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
43753 + hcd->frame_number = hfnum.b.frnum;
43756 + hcd->frrem_accum += hfnum.b.frrem;
43757 + hcd->frrem_samples++;
43760 +#ifdef DWC_TRACK_MISSED_SOFS
43761 + track_missed_sofs(hcd->frame_number);
43763 + /* Determine whether any periodic QHs should be executed. */
43764 + qh_entry = DWC_LIST_FIRST(&hcd->periodic_sched_inactive);
43765 + while (qh_entry != &hcd->periodic_sched_inactive) {
43766 + qh = DWC_LIST_ENTRY(qh_entry, dwc_otg_qh_t, qh_list_entry);
43767 + qh_entry = qh_entry->next;
43768 + if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) {
43771 + * Move QH to the ready list to be executed next
43774 + DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
43775 + &qh->qh_list_entry);
43777 + did_something = 1;
43781 + if(next_sched_frame < 0 || dwc_frame_num_le(qh->sched_frame, next_sched_frame))
43783 + next_sched_frame = qh->sched_frame;
43788 + hcd->fiq_state->next_sched_frame = next_sched_frame;
43790 + tr_type = dwc_otg_hcd_select_transactions(hcd);
43791 + if (tr_type != DWC_OTG_TRANSACTION_NONE) {
43792 + dwc_otg_hcd_queue_transactions(hcd, tr_type);
43793 + did_something = 1;
43796 + /* Clear interrupt - but do not trample on the FIQ sof */
43797 + if (!fiq_fsm_enable) {
43798 + gintsts.b.sofintr = 1;
43799 + DWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32);
43804 +/** Handles the Rx Status Queue Level Interrupt, which indicates that there is at
43805 + * least one packet in the Rx FIFO. The packets are moved from the FIFO to
43806 + * memory if the DWC_otg controller is operating in Slave mode. */
43807 +int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t * dwc_otg_hcd)
43809 + host_grxsts_data_t grxsts;
43810 + dwc_hc_t *hc = NULL;
43812 + DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
43815 + DWC_READ_REG32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp);
43817 + hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
43819 + DWC_ERROR("Unable to get corresponding channel\n");
43823 + /* Packet Status */
43824 + DWC_DEBUGPL(DBG_HCDV, " Ch num = %d\n", grxsts.b.chnum);
43825 + DWC_DEBUGPL(DBG_HCDV, " Count = %d\n", grxsts.b.bcnt);
43826 + DWC_DEBUGPL(DBG_HCDV, " DPID = %d, hc.dpid = %d\n", grxsts.b.dpid,
43827 + hc->data_pid_start);
43828 + DWC_DEBUGPL(DBG_HCDV, " PStatus = %d\n", grxsts.b.pktsts);
43830 + switch (grxsts.b.pktsts) {
43831 + case DWC_GRXSTS_PKTSTS_IN:
43832 + /* Read the data into the host buffer. */
43833 + if (grxsts.b.bcnt > 0) {
43834 + dwc_otg_read_packet(dwc_otg_hcd->core_if,
43835 + hc->xfer_buff, grxsts.b.bcnt);
43837 + /* Update the HC fields for the next packet received. */
43838 + hc->xfer_count += grxsts.b.bcnt;
43839 + hc->xfer_buff += grxsts.b.bcnt;
43842 + case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
43843 + case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
43844 + case DWC_GRXSTS_PKTSTS_CH_HALTED:
43845 + /* Handled in interrupt, just ignore data */
43848 + DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n",
43849 + grxsts.b.pktsts);
43856 +/** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
43857 + * data packets may be written to the FIFO for OUT transfers. More requests
43858 + * may be written to the non-periodic request queue for IN transfers. This
43859 + * interrupt is enabled only in Slave mode. */
43860 +int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
43862 + DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
43863 + dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
43864 + DWC_OTG_TRANSACTION_NON_PERIODIC);
43868 +/** This interrupt occurs when the periodic Tx FIFO is half-empty. More data
43869 + * packets may be written to the FIFO for OUT transfers. More requests may be
43870 + * written to the periodic request queue for IN transfers. This interrupt is
43871 + * enabled only in Slave mode. */
43872 +int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
43874 + DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
43875 + dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
43876 + DWC_OTG_TRANSACTION_PERIODIC);
43880 +/** There are multiple conditions that can cause a port interrupt. This function
43881 + * determines which interrupt conditions have occurred and handles them
43882 + * appropriately. */
43883 +int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd)
43886 + hprt0_data_t hprt0;
43887 + hprt0_data_t hprt0_modify;
43889 + hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
43890 + hprt0_modify.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
43892 + /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
43895 + hprt0_modify.b.prtena = 0;
43896 + hprt0_modify.b.prtconndet = 0;
43897 + hprt0_modify.b.prtenchng = 0;
43898 + hprt0_modify.b.prtovrcurrchng = 0;
43900 + /* Port Connect Detected
43901 + * Set flag and clear if detected */
43902 + if (dwc_otg_hcd->core_if->hibernation_suspend == 1) {
43903 + // Dont modify port status if we are in hibernation state
43904 + hprt0_modify.b.prtconndet = 1;
43905 + hprt0_modify.b.prtenchng = 1;
43906 + DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
43907 + hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
43911 + if (hprt0.b.prtconndet) {
43912 + /** @todo - check if steps performed in 'else' block should be perfromed regardles adp */
43913 + if (dwc_otg_hcd->core_if->adp_enable &&
43914 + dwc_otg_hcd->core_if->adp.vbuson_timer_started == 1) {
43915 + DWC_PRINTF("PORT CONNECT DETECTED ----------------\n");
43916 + DWC_TIMER_CANCEL(dwc_otg_hcd->core_if->adp.vbuson_timer);
43917 + dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
43918 + /* TODO - check if this is required, as
43919 + * host initialization was already performed
43920 + * after initial ADP probing
43922 + /*dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
43923 + dwc_otg_core_init(dwc_otg_hcd->core_if);
43924 + dwc_otg_enable_global_interrupts(dwc_otg_hcd->core_if);
43925 + cil_hcd_start(dwc_otg_hcd->core_if);*/
43928 + DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
43929 + "Port Connect Detected--\n", hprt0.d32);
43930 + dwc_otg_hcd->flags.b.port_connect_status_change = 1;
43931 + dwc_otg_hcd->flags.b.port_connect_status = 1;
43932 + hprt0_modify.b.prtconndet = 1;
43934 + /* B-Device has connected, Delete the connection timer. */
43935 + DWC_TIMER_CANCEL(dwc_otg_hcd->conn_timer);
43937 + /* The Hub driver asserts a reset when it sees port connect
43938 + * status change flag */
43942 + /* Port Enable Changed
43943 + * Clear if detected - Set internal flag if disabled */
43944 + if (hprt0.b.prtenchng) {
43945 + DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x "
43946 + "Port Enable Changed--\n", hprt0.d32);
43947 + hprt0_modify.b.prtenchng = 1;
43948 + if (hprt0.b.prtena == 1) {
43949 + hfir_data_t hfir;
43950 + int do_reset = 0;
43951 + dwc_otg_core_params_t *params =
43952 + dwc_otg_hcd->core_if->core_params;
43953 + dwc_otg_core_global_regs_t *global_regs =
43954 + dwc_otg_hcd->core_if->core_global_regs;
43955 + dwc_otg_host_if_t *host_if =
43956 + dwc_otg_hcd->core_if->host_if;
43958 + dwc_otg_hcd->flags.b.port_speed = hprt0.b.prtspd;
43959 + if (microframe_schedule)
43960 + init_hcd_usecs(dwc_otg_hcd);
43962 + /* Every time when port enables calculate
43963 + * HFIR.FrInterval
43965 + hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);
43966 + hfir.b.frint = calc_frame_interval(dwc_otg_hcd->core_if);
43967 + DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);
43969 + /* Check if we need to adjust the PHY clock speed for
43970 + * low power and adjust it */
43971 + if (params->host_support_fs_ls_low_power) {
43972 + gusbcfg_data_t usbcfg;
43975 + DWC_READ_REG32(&global_regs->gusbcfg);
43977 + if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED
43978 + || hprt0.b.prtspd ==
43979 + DWC_HPRT0_PRTSPD_FULL_SPEED) {
43983 + hcfg_data_t hcfg;
43984 + if (usbcfg.b.phylpwrclksel == 0) {
43985 + /* Set PHY low power clock select for FS/LS devices */
43986 + usbcfg.b.phylpwrclksel = 1;
43988 + (&global_regs->gusbcfg,
43995 + (&host_if->host_global_regs->hcfg);
43997 + if (hprt0.b.prtspd ==
43998 + DWC_HPRT0_PRTSPD_LOW_SPEED
43999 + && params->host_ls_low_power_phy_clk
44001 + DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)
44004 + DWC_DEBUGPL(DBG_CIL,
44005 + "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
44006 + if (hcfg.b.fslspclksel !=
44007 + DWC_HCFG_6_MHZ) {
44008 + hcfg.b.fslspclksel =
44011 + (&host_if->host_global_regs->hcfg,
44017 + DWC_DEBUGPL(DBG_CIL,
44018 + "FS_PHY programming HCFG to 48 MHz ()\n");
44019 + if (hcfg.b.fslspclksel !=
44020 + DWC_HCFG_48_MHZ) {
44021 + hcfg.b.fslspclksel =
44024 + (&host_if->host_global_regs->hcfg,
44033 + if (usbcfg.b.phylpwrclksel == 1) {
44034 + usbcfg.b.phylpwrclksel = 0;
44036 + (&global_regs->gusbcfg,
44043 + DWC_TASK_SCHEDULE(dwc_otg_hcd->reset_tasklet);
44048 + /* Port has been enabled set the reset change flag */
44049 + dwc_otg_hcd->flags.b.port_reset_change = 1;
44052 + dwc_otg_hcd->flags.b.port_enable_change = 1;
44057 + /** Overcurrent Change Interrupt */
44058 + if (hprt0.b.prtovrcurrchng) {
44059 + DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x "
44060 + "Port Overcurrent Changed--\n", hprt0.d32);
44061 + dwc_otg_hcd->flags.b.port_over_current_change = 1;
44062 + hprt0_modify.b.prtovrcurrchng = 1;
44066 + /* Clear Port Interrupts */
44067 + DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
44072 +/** This interrupt indicates that one or more host channels has a pending
44073 + * interrupt. There are multiple conditions that can cause each host channel
44074 + * interrupt. This function determines which conditions have occurred for each
44075 + * host channel interrupt and handles them appropriately. */
44076 +int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd)
44080 + haint_data_t haint = { .d32 = 0 } ;
44082 + /* Clear appropriate bits in HCINTn to clear the interrupt bit in
44085 + if (!fiq_fsm_enable)
44086 + haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if);
44088 + // Overwrite with saved interrupts from fiq handler
44089 + if(fiq_fsm_enable)
44091 + /* check the mask? */
44092 + local_fiq_disable();
44093 + fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);
44094 + haint.b2.chint |= ~(dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint);
44095 + dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint = ~0;
44096 + fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);
44097 + local_fiq_enable();
44100 + for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) {
44101 + if (haint.b2.chint & (1 << i)) {
44102 + retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i);
44110 + * Gets the actual length of a transfer after the transfer halts. _halt_status
44111 + * holds the reason for the halt.
44113 + * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE,
44114 + * *short_read is set to 1 upon return if less than the requested
44115 + * number of bytes were transferred. Otherwise, *short_read is set to 0 upon
44116 + * return. short_read may also be NULL on entry, in which case it remains
44119 +static uint32_t get_actual_xfer_length(dwc_hc_t * hc,
44120 + dwc_otg_hc_regs_t * hc_regs,
44121 + dwc_otg_qtd_t * qtd,
44122 + dwc_otg_halt_status_e halt_status,
44125 + hctsiz_data_t hctsiz;
44128 + if (short_read != NULL) {
44131 + hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
44133 + if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
44134 + if (hc->ep_is_in) {
44135 + length = hc->xfer_len - hctsiz.b.xfersize;
44136 + if (short_read != NULL) {
44137 + *short_read = (hctsiz.b.xfersize != 0);
44139 + } else if (hc->qh->do_split) {
44140 + //length = split_out_xfersize[hc->hc_num];
44141 + length = qtd->ssplit_out_xfer_count;
44143 + length = hc->xfer_len;
44147 + * Must use the hctsiz.pktcnt field to determine how much data
44148 + * has been transferred. This field reflects the number of
44149 + * packets that have been transferred via the USB. This is
44150 + * always an integral number of packets if the transfer was
44151 + * halted before its normal completion. (Can't use the
44152 + * hctsiz.xfersize field because that reflects the number of
44153 + * bytes transferred via the AHB, not the USB).
44156 + (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet;
44163 + * Updates the state of the URB after a Transfer Complete interrupt on the
44164 + * host channel. Updates the actual_length field of the URB based on the
44165 + * number of bytes transferred via the host channel. Sets the URB status
44166 + * if the data transfer is finished.
44168 + * @return 1 if the data transfer specified by the URB is completely finished,
44171 +static int update_urb_state_xfer_comp(dwc_hc_t * hc,
44172 + dwc_otg_hc_regs_t * hc_regs,
44173 + dwc_otg_hcd_urb_t * urb,
44174 + dwc_otg_qtd_t * qtd)
44176 + int xfer_done = 0;
44177 + int short_read = 0;
44181 + xfer_length = get_actual_xfer_length(hc, hc_regs, qtd,
44182 + DWC_OTG_HC_XFER_COMPLETE,
44185 + if (urb->actual_length + xfer_length > urb->length) {
44186 + printk_once(KERN_DEBUG "dwc_otg: DEVICE:%03d : %s:%d:trimming xfer length\n",
44187 + hc->dev_addr, __func__, __LINE__);
44188 + xfer_length = urb->length - urb->actual_length;
44191 + /* non DWORD-aligned buffer case handling. */
44192 + if (hc->align_buff && xfer_length && hc->ep_is_in) {
44193 + dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
44197 + urb->actual_length += xfer_length;
44199 + if (xfer_length && (hc->ep_type == DWC_OTG_EP_TYPE_BULK) &&
44200 + (urb->flags & URB_SEND_ZERO_PACKET)
44201 + && (urb->actual_length == urb->length)
44202 + && !(urb->length % hc->max_packet)) {
44204 + } else if (short_read || urb->actual_length >= urb->length) {
44211 + hctsiz_data_t hctsiz;
44212 + hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
44213 + DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
44214 + __func__, (hc->ep_is_in ? "IN" : "OUT"),
44216 + DWC_DEBUGPL(DBG_HCDV, " hc->xfer_len %d\n", hc->xfer_len);
44217 + DWC_DEBUGPL(DBG_HCDV, " hctsiz.xfersize %d\n",
44218 + hctsiz.b.xfersize);
44219 + DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n",
44221 + DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n",
44222 + urb->actual_length);
44223 + DWC_DEBUGPL(DBG_HCDV, " short_read %d, xfer_done %d\n",
44224 + short_read, xfer_done);
44228 + return xfer_done;
44232 + * Save the starting data toggle for the next transfer. The data toggle is
44233 + * saved in the QH for non-control transfers and it's saved in the QTD for
44234 + * control transfers.
44236 +void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
44237 + dwc_otg_hc_regs_t * hc_regs, dwc_otg_qtd_t * qtd)
44239 + hctsiz_data_t hctsiz;
44240 + hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
44242 + if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
44243 + dwc_otg_qh_t *qh = hc->qh;
44244 + if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
44245 + qh->data_toggle = DWC_OTG_HC_PID_DATA0;
44247 + qh->data_toggle = DWC_OTG_HC_PID_DATA1;
44250 + if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
44251 + qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
44253 + qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
44259 + * Updates the state of an Isochronous URB when the transfer is stopped for
44260 + * any reason. The fields of the current entry in the frame descriptor array
44261 + * are set based on the transfer state and the input _halt_status. Completes
44262 + * the Isochronous URB if all the URB frames have been completed.
44264 + * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be
44265 + * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
44267 +static dwc_otg_halt_status_e
44268 +update_isoc_urb_state(dwc_otg_hcd_t * hcd,
44270 + dwc_otg_hc_regs_t * hc_regs,
44271 + dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
44273 + dwc_otg_hcd_urb_t *urb = qtd->urb;
44274 + dwc_otg_halt_status_e ret_val = halt_status;
44275 + struct dwc_otg_hcd_iso_packet_desc *frame_desc;
44277 + frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
44278 + switch (halt_status) {
44279 + case DWC_OTG_HC_XFER_COMPLETE:
44280 + frame_desc->status = 0;
44281 + frame_desc->actual_length =
44282 + get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
44284 + /* non DWORD-aligned buffer case handling. */
44285 + if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
44286 + dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
44287 + hc->qh->dw_align_buf, frame_desc->actual_length);
44291 + case DWC_OTG_HC_XFER_FRAME_OVERRUN:
44292 + urb->error_count++;
44293 + if (hc->ep_is_in) {
44294 + frame_desc->status = -DWC_E_NO_STREAM_RES;
44296 + frame_desc->status = -DWC_E_COMMUNICATION;
44298 + frame_desc->actual_length = 0;
44300 + case DWC_OTG_HC_XFER_BABBLE_ERR:
44301 + urb->error_count++;
44302 + frame_desc->status = -DWC_E_OVERFLOW;
44303 + /* Don't need to update actual_length in this case. */
44305 + case DWC_OTG_HC_XFER_XACT_ERR:
44306 + urb->error_count++;
44307 + frame_desc->status = -DWC_E_PROTOCOL;
44308 + frame_desc->actual_length =
44309 + get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
44311 + /* non DWORD-aligned buffer case handling. */
44312 + if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
44313 + dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
44314 + hc->qh->dw_align_buf, frame_desc->actual_length);
44316 + /* Skip whole frame */
44317 + if (hc->qh->do_split && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) &&
44318 + hc->ep_is_in && hcd->core_if->dma_enable) {
44319 + qtd->complete_split = 0;
44320 + qtd->isoc_split_offset = 0;
44325 + DWC_ASSERT(1, "Unhandled _halt_status (%d)\n", halt_status);
44328 + if (++qtd->isoc_frame_index == urb->packet_count) {
44330 + * urb->status is not used for isoc transfers.
44331 + * The individual frame_desc statuses are used instead.
44333 + hcd->fops->complete(hcd, urb->priv, urb, 0);
44334 + ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
44336 + ret_val = DWC_OTG_HC_XFER_COMPLETE;
44342 + * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
44343 + * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
44344 + * still linked to the QH, the QH is added to the end of the inactive
44345 + * non-periodic schedule. For periodic QHs, removes the QH from the periodic
44346 + * schedule if no more QTDs are linked to the QH.
44348 +static void deactivate_qh(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, int free_qtd)
44350 + int continue_split = 0;
44351 + dwc_otg_qtd_t *qtd;
44353 + DWC_DEBUGPL(DBG_HCDV, " %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd);
44355 + qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
44357 + if (qtd->complete_split) {
44358 + continue_split = 1;
44359 + } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID ||
44360 + qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) {
44361 + continue_split = 1;
44365 + dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
44366 + continue_split = 0;
44369 + qh->channel = NULL;
44370 + dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);
44374 + * Releases a host channel for use by other transfers. Attempts to select and
44375 + * queue more transactions since at least one host channel is available.
44377 + * @param hcd The HCD state structure.
44378 + * @param hc The host channel to release.
44379 + * @param qtd The QTD associated with the host channel. This QTD may be freed
44380 + * if the transfer is complete or an error has occurred.
44381 + * @param halt_status Reason the channel is being released. This status
44382 + * determines the actions taken by this function.
44384 +static void release_channel(dwc_otg_hcd_t * hcd,
44386 + dwc_otg_qtd_t * qtd,
44387 + dwc_otg_halt_status_e halt_status)
44389 + dwc_otg_transaction_type_e tr_type;
44392 + int hog_port = 0;
44394 + DWC_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d, xfer_len %d\n",
44395 + __func__, hc->hc_num, halt_status, hc->xfer_len);
44397 + if(fiq_fsm_enable && hc->do_split) {
44398 + if(!hc->ep_is_in && hc->ep_type == UE_ISOCHRONOUS) {
44399 + if(hc->xact_pos == DWC_HCSPLIT_XACTPOS_MID ||
44400 + hc->xact_pos == DWC_HCSPLIT_XACTPOS_BEGIN) {
44406 + switch (halt_status) {
44407 + case DWC_OTG_HC_XFER_URB_COMPLETE:
44410 + case DWC_OTG_HC_XFER_AHB_ERR:
44411 + case DWC_OTG_HC_XFER_STALL:
44412 + case DWC_OTG_HC_XFER_BABBLE_ERR:
44415 + case DWC_OTG_HC_XFER_XACT_ERR:
44416 + if (qtd->error_count >= 3) {
44417 + DWC_DEBUGPL(DBG_HCDV,
44418 + " Complete URB with transaction error\n");
44420 + qtd->urb->status = -DWC_E_PROTOCOL;
44421 + hcd->fops->complete(hcd, qtd->urb->priv,
44422 + qtd->urb, -DWC_E_PROTOCOL);
44427 + case DWC_OTG_HC_XFER_URB_DEQUEUE:
44429 + * The QTD has already been removed and the QH has been
44430 + * deactivated. Don't want to do anything except release the
44431 + * host channel and try to queue more transfers.
44434 + case DWC_OTG_HC_XFER_NO_HALT_STATUS:
44437 + case DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE:
44438 + DWC_DEBUGPL(DBG_HCDV,
44439 + " Complete URB with I/O error\n");
44441 + qtd->urb->status = -DWC_E_IO;
44442 + hcd->fops->complete(hcd, qtd->urb->priv,
44443 + qtd->urb, -DWC_E_IO);
44450 + deactivate_qh(hcd, hc->qh, free_qtd);
44454 + * Release the host channel for use by other transfers. The cleanup
44455 + * function clears the channel interrupt enables and conditions, so
44456 + * there's no need to clear the Channel Halted interrupt separately.
44458 + if (fiq_fsm_enable && hcd->fiq_state->channel[hc->hc_num].fsm != FIQ_PASSTHROUGH)
44459 + dwc_otg_cleanup_fiq_channel(hcd, hc->hc_num);
44460 + dwc_otg_hc_cleanup(hcd->core_if, hc);
44461 + DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
44463 + if (!microframe_schedule) {
44464 + switch (hc->ep_type) {
44465 + case DWC_OTG_EP_TYPE_CONTROL:
44466 + case DWC_OTG_EP_TYPE_BULK:
44467 + hcd->non_periodic_channels--;
44472 + * Don't release reservations for periodic channels here.
44473 + * That's done when a periodic transfer is descheduled (i.e.
44474 + * when the QH is removed from the periodic schedule).
44479 + hcd->available_host_channels++;
44480 + fiq_print(FIQDBG_INT, hcd->fiq_state, "AHC = %d ", hcd->available_host_channels);
44483 + /* Try to queue more transfers now that there's a free channel. */
44484 + tr_type = dwc_otg_hcd_select_transactions(hcd);
44485 + if (tr_type != DWC_OTG_TRANSACTION_NONE) {
44486 + dwc_otg_hcd_queue_transactions(hcd, tr_type);
44491 + * Halts a host channel. If the channel cannot be halted immediately because
44492 + * the request queue is full, this function ensures that the FIFO empty
44493 + * interrupt for the appropriate queue is enabled so that the halt request can
44494 + * be queued when there is space in the request queue.
44496 + * This function may also be called in DMA mode. In that case, the channel is
44497 + * simply released since the core always halts the channel automatically in
44500 +static void halt_channel(dwc_otg_hcd_t * hcd,
44502 + dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
44504 + if (hcd->core_if->dma_enable) {
44505 + release_channel(hcd, hc, qtd, halt_status);
44509 + /* Slave mode processing... */
44510 + dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
44512 + if (hc->halt_on_queue) {
44513 + gintmsk_data_t gintmsk = {.d32 = 0 };
44514 + dwc_otg_core_global_regs_t *global_regs;
44515 + global_regs = hcd->core_if->core_global_regs;
44517 + if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
44518 + hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
44520 + * Make sure the Non-periodic Tx FIFO empty interrupt
44521 + * is enabled so that the non-periodic schedule will
44524 + gintmsk.b.nptxfempty = 1;
44525 + if (fiq_enable) {
44526 + local_fiq_disable();
44527 + fiq_fsm_spin_lock(&hcd->fiq_state->lock);
44528 + DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
44529 + fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
44530 + local_fiq_enable();
44532 + DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
44536 + * Move the QH from the periodic queued schedule to
44537 + * the periodic assigned schedule. This allows the
44538 + * halt to be queued when the periodic schedule is
44541 + DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
44542 + &hc->qh->qh_list_entry);
44545 + * Make sure the Periodic Tx FIFO Empty interrupt is
44546 + * enabled so that the periodic schedule will be
44549 + gintmsk.b.ptxfempty = 1;
44550 + if (fiq_enable) {
44551 + local_fiq_disable();
44552 + fiq_fsm_spin_lock(&hcd->fiq_state->lock);
44553 + DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
44554 + fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
44555 + local_fiq_enable();
44557 + DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
44564 + * Performs common cleanup for non-periodic transfers after a Transfer
44565 + * Complete interrupt. This function should be called after any endpoint type
44566 + * specific handling is finished to release the host channel.
44568 +static void complete_non_periodic_xfer(dwc_otg_hcd_t * hcd,
44570 + dwc_otg_hc_regs_t * hc_regs,
44571 + dwc_otg_qtd_t * qtd,
44572 + dwc_otg_halt_status_e halt_status)
44574 + hcint_data_t hcint;
44576 + qtd->error_count = 0;
44578 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
44579 + if (hcint.b.nyet) {
44581 + * Got a NYET on the last transaction of the transfer. This
44582 + * means that the endpoint should be in the PING state at the
44583 + * beginning of the next transfer.
44585 + hc->qh->ping_state = 1;
44586 + clear_hc_int(hc_regs, nyet);
44590 + * Always halt and release the host channel to make it available for
44591 + * more transfers. There may still be more phases for a control
44592 + * transfer or more data packets for a bulk transfer at this point,
44593 + * but the host channel is still halted. A channel will be reassigned
44594 + * to the transfer when the non-periodic schedule is processed after
44595 + * the channel is released. This allows transactions to be queued
44596 + * properly via dwc_otg_hcd_queue_transactions, which also enables the
44597 + * Tx FIFO Empty interrupt if necessary.
44599 + if (hc->ep_is_in) {
44601 + * IN transfers in Slave mode require an explicit disable to
44602 + * halt the channel. (In DMA mode, this call simply releases
44605 + halt_channel(hcd, hc, qtd, halt_status);
44608 + * The channel is automatically disabled by the core for OUT
44609 + * transfers in Slave mode.
44611 + release_channel(hcd, hc, qtd, halt_status);
44616 + * Performs common cleanup for periodic transfers after a Transfer Complete
44617 + * interrupt. This function should be called after any endpoint type specific
44618 + * handling is finished to release the host channel.
44620 +static void complete_periodic_xfer(dwc_otg_hcd_t * hcd,
44622 + dwc_otg_hc_regs_t * hc_regs,
44623 + dwc_otg_qtd_t * qtd,
44624 + dwc_otg_halt_status_e halt_status)
44626 + hctsiz_data_t hctsiz;
44627 + qtd->error_count = 0;
44629 + hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
44630 + if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) {
44631 + /* Core halts channel in these cases. */
44632 + release_channel(hcd, hc, qtd, halt_status);
44634 + /* Flush any outstanding requests from the Tx queue. */
44635 + halt_channel(hcd, hc, qtd, halt_status);
44639 +static int32_t handle_xfercomp_isoc_split_in(dwc_otg_hcd_t * hcd,
44641 + dwc_otg_hc_regs_t * hc_regs,
44642 + dwc_otg_qtd_t * qtd)
44645 + struct dwc_otg_hcd_iso_packet_desc *frame_desc;
44646 + frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
44648 + len = get_actual_xfer_length(hc, hc_regs, qtd,
44649 + DWC_OTG_HC_XFER_COMPLETE, NULL);
44652 + qtd->complete_split = 0;
44653 + qtd->isoc_split_offset = 0;
44656 + frame_desc->actual_length += len;
44658 + if (hc->align_buff && len)
44659 + dwc_memcpy(qtd->urb->buf + frame_desc->offset +
44660 + qtd->isoc_split_offset, hc->qh->dw_align_buf, len);
44661 + qtd->isoc_split_offset += len;
44663 + if (frame_desc->length == frame_desc->actual_length) {
44664 + frame_desc->status = 0;
44665 + qtd->isoc_frame_index++;
44666 + qtd->complete_split = 0;
44667 + qtd->isoc_split_offset = 0;
44670 + if (qtd->isoc_frame_index == qtd->urb->packet_count) {
44671 + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
44672 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
44674 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
44677 + return 1; /* Indicates that channel released */
44681 + * Handles a host channel Transfer Complete interrupt. This handler may be
44682 + * called in either DMA mode or Slave mode.
44684 +static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t * hcd,
44686 + dwc_otg_hc_regs_t * hc_regs,
44687 + dwc_otg_qtd_t * qtd)
44689 + int urb_xfer_done;
44690 + dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE;
44691 + dwc_otg_hcd_urb_t *urb = qtd->urb;
44692 + int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
44694 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
44695 + "Transfer Complete--\n", hc->hc_num);
44697 + if (hcd->core_if->dma_desc_enable) {
44698 + dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, halt_status);
44699 + if (pipe_type == UE_ISOCHRONOUS) {
44700 + /* Do not disable the interrupt, just clear it */
44701 + clear_hc_int(hc_regs, xfercomp);
44704 + goto handle_xfercomp_done;
44708 + * Handle xfer complete on CSPLIT.
44711 + if (hc->qh->do_split) {
44712 + if ((hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hc->ep_is_in
44713 + && hcd->core_if->dma_enable) {
44714 + if (qtd->complete_split
44715 + && handle_xfercomp_isoc_split_in(hcd, hc, hc_regs,
44717 + goto handle_xfercomp_done;
44719 + qtd->complete_split = 0;
44723 + /* Update the QTD and URB states. */
44724 + switch (pipe_type) {
44726 + switch (qtd->control_phase) {
44727 + case DWC_OTG_CONTROL_SETUP:
44728 + if (urb->length > 0) {
44729 + qtd->control_phase = DWC_OTG_CONTROL_DATA;
44731 + qtd->control_phase = DWC_OTG_CONTROL_STATUS;
44733 + DWC_DEBUGPL(DBG_HCDV,
44734 + " Control setup transaction done\n");
44735 + halt_status = DWC_OTG_HC_XFER_COMPLETE;
44737 + case DWC_OTG_CONTROL_DATA:{
44739 + update_urb_state_xfer_comp(hc, hc_regs, urb,
44741 + if (urb_xfer_done) {
44742 + qtd->control_phase =
44743 + DWC_OTG_CONTROL_STATUS;
44744 + DWC_DEBUGPL(DBG_HCDV,
44745 + " Control data transfer done\n");
44747 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
44749 + halt_status = DWC_OTG_HC_XFER_COMPLETE;
44752 + case DWC_OTG_CONTROL_STATUS:
44753 + DWC_DEBUGPL(DBG_HCDV, " Control transfer complete\n");
44754 + if (urb->status == -DWC_E_IN_PROGRESS) {
44757 + hcd->fops->complete(hcd, urb->priv, urb, urb->status);
44758 + halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
44762 + complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
44765 + DWC_DEBUGPL(DBG_HCDV, " Bulk transfer complete\n");
44767 + update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
44768 + if (urb_xfer_done) {
44769 + hcd->fops->complete(hcd, urb->priv, urb, urb->status);
44770 + halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
44772 + halt_status = DWC_OTG_HC_XFER_COMPLETE;
44775 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
44776 + complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
44778 + case UE_INTERRUPT:
44779 + DWC_DEBUGPL(DBG_HCDV, " Interrupt transfer complete\n");
44781 + update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
44784 + * Interrupt URB is done on the first transfer complete
44787 + if (urb_xfer_done) {
44788 + hcd->fops->complete(hcd, urb->priv, urb, urb->status);
44789 + halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
44791 + halt_status = DWC_OTG_HC_XFER_COMPLETE;
44794 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
44795 + complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
44797 + case UE_ISOCHRONOUS:
44798 + DWC_DEBUGPL(DBG_HCDV, " Isochronous transfer complete\n");
44799 + if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) {
44801 + update_isoc_urb_state(hcd, hc, hc_regs, qtd,
44802 + DWC_OTG_HC_XFER_COMPLETE);
44804 + complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
44808 +handle_xfercomp_done:
44809 + disable_hc_int(hc_regs, xfercompl);
44815 + * Handles a host channel STALL interrupt. This handler may be called in
44816 + * either DMA mode or Slave mode.
44818 +static int32_t handle_hc_stall_intr(dwc_otg_hcd_t * hcd,
44820 + dwc_otg_hc_regs_t * hc_regs,
44821 + dwc_otg_qtd_t * qtd)
44823 + dwc_otg_hcd_urb_t *urb = qtd->urb;
44824 + int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
44826 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
44827 + "STALL Received--\n", hc->hc_num);
44829 + if (hcd->core_if->dma_desc_enable) {
44830 + dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_STALL);
44831 + goto handle_stall_done;
44834 + if (pipe_type == UE_CONTROL) {
44835 + hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
44838 + if (pipe_type == UE_BULK || pipe_type == UE_INTERRUPT) {
44839 + hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
44841 + * USB protocol requires resetting the data toggle for bulk
44842 + * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
44843 + * setup command is issued to the endpoint. Anticipate the
44844 + * CLEAR_FEATURE command since a STALL has occurred and reset
44845 + * the data toggle now.
44847 + hc->qh->data_toggle = 0;
44850 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL);
44852 +handle_stall_done:
44853 + disable_hc_int(hc_regs, stall);
44859 + * Updates the state of the URB when a transfer has been stopped due to an
44860 + * abnormal condition before the transfer completes. Modifies the
44861 + * actual_length field of the URB to reflect the number of bytes that have
44862 + * actually been transferred via the host channel.
44864 +static void update_urb_state_xfer_intr(dwc_hc_t * hc,
44865 + dwc_otg_hc_regs_t * hc_regs,
44866 + dwc_otg_hcd_urb_t * urb,
44867 + dwc_otg_qtd_t * qtd,
44868 + dwc_otg_halt_status_e halt_status)
44870 + uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd,
44871 + halt_status, NULL);
44873 + if (urb->actual_length + bytes_transferred > urb->length) {
44874 + printk_once(KERN_DEBUG "dwc_otg: DEVICE:%03d : %s:%d:trimming xfer length\n",
44875 + hc->dev_addr, __func__, __LINE__);
44876 + bytes_transferred = urb->length - urb->actual_length;
44879 + /* non DWORD-aligned buffer case handling. */
44880 + if (hc->align_buff && bytes_transferred && hc->ep_is_in) {
44881 + dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
44882 + bytes_transferred);
44885 + urb->actual_length += bytes_transferred;
44889 + hctsiz_data_t hctsiz;
44890 + hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
44891 + DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
44892 + __func__, (hc->ep_is_in ? "IN" : "OUT"),
44894 + DWC_DEBUGPL(DBG_HCDV, " hc->start_pkt_count %d\n",
44895 + hc->start_pkt_count);
44896 + DWC_DEBUGPL(DBG_HCDV, " hctsiz.pktcnt %d\n", hctsiz.b.pktcnt);
44897 + DWC_DEBUGPL(DBG_HCDV, " hc->max_packet %d\n", hc->max_packet);
44898 + DWC_DEBUGPL(DBG_HCDV, " bytes_transferred %d\n",
44899 + bytes_transferred);
44900 + DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n",
44901 + urb->actual_length);
44902 + DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n",
44909 + * Handles a host channel NAK interrupt. This handler may be called in either
44910 + * DMA mode or Slave mode.
44912 +static int32_t handle_hc_nak_intr(dwc_otg_hcd_t * hcd,
44914 + dwc_otg_hc_regs_t * hc_regs,
44915 + dwc_otg_qtd_t * qtd)
44917 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
44918 + "NAK Received--\n", hc->hc_num);
44921 + * When we get bulk NAKs then remember this so we holdoff on this qh until
44922 + * the beginning of the next frame
44924 + switch(dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
44927 + if (nak_holdoff && qtd->qh->do_split)
44928 + hc->qh->nak_frame = dwc_otg_hcd_get_frame_number(hcd);
44932 + * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
44933 + * interrupt. Re-start the SSPLIT transfer.
44935 + if (hc->do_split) {
44936 + if (hc->complete_split) {
44937 + qtd->error_count = 0;
44939 + qtd->complete_split = 0;
44940 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
44941 + goto handle_nak_done;
44944 + switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
44947 + if (hcd->core_if->dma_enable && hc->ep_is_in) {
44949 + * NAK interrupts are enabled on bulk/control IN
44950 + * transfers in DMA mode for the sole purpose of
44951 + * resetting the error count after a transaction error
44952 + * occurs. The core will continue transferring data.
44953 + * Disable other interrupts unmasked for the same
44956 + disable_hc_int(hc_regs, datatglerr);
44957 + disable_hc_int(hc_regs, ack);
44958 + qtd->error_count = 0;
44959 + goto handle_nak_done;
44963 + * NAK interrupts normally occur during OUT transfers in DMA
44964 + * or Slave mode. For IN transfers, more requests will be
44965 + * queued as request queue space is available.
44967 + qtd->error_count = 0;
44969 + if (!hc->qh->ping_state) {
44970 + update_urb_state_xfer_intr(hc, hc_regs,
44972 + DWC_OTG_HC_XFER_NAK);
44973 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
44975 + if (hc->speed == DWC_OTG_EP_SPEED_HIGH)
44976 + hc->qh->ping_state = 1;
44980 + * Halt the channel so the transfer can be re-started from
44981 + * the appropriate point or the PING protocol will
44982 + * start/continue.
44984 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
44986 + case UE_INTERRUPT:
44987 + qtd->error_count = 0;
44988 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
44990 + case UE_ISOCHRONOUS:
44991 + /* Should never get called for isochronous transfers. */
44992 + DWC_ASSERT(1, "NACK interrupt for ISOC transfer\n");
44997 + disable_hc_int(hc_regs, nak);
45003 + * Handles a host channel ACK interrupt. This interrupt is enabled when
45004 + * performing the PING protocol in Slave mode, when errors occur during
45005 + * either Slave mode or DMA mode, and during Start Split transactions.
45007 +static int32_t handle_hc_ack_intr(dwc_otg_hcd_t * hcd,
45009 + dwc_otg_hc_regs_t * hc_regs,
45010 + dwc_otg_qtd_t * qtd)
45012 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
45013 + "ACK Received--\n", hc->hc_num);
45015 + if (hc->do_split) {
45017 + * Handle ACK on SSPLIT.
45018 + * ACK should not occur in CSPLIT.
45020 + if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) {
45021 + qtd->ssplit_out_xfer_count = hc->xfer_len;
45023 + if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) {
45024 + /* Don't need complete for isochronous out transfers. */
45025 + qtd->complete_split = 1;
45029 + if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
45030 + switch (hc->xact_pos) {
45031 + case DWC_HCSPLIT_XACTPOS_ALL:
45033 + case DWC_HCSPLIT_XACTPOS_END:
45034 + qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
45035 + qtd->isoc_split_offset = 0;
45037 + case DWC_HCSPLIT_XACTPOS_BEGIN:
45038 + case DWC_HCSPLIT_XACTPOS_MID:
45040 + * For BEGIN or MID, calculate the length for
45041 + * the next microframe to determine the correct
45042 + * SSPLIT token, either MID or END.
45045 + struct dwc_otg_hcd_iso_packet_desc
45050 + iso_descs[qtd->isoc_frame_index];
45051 + qtd->isoc_split_offset += 188;
45053 + if ((frame_desc->length -
45054 + qtd->isoc_split_offset) <= 188) {
45055 + qtd->isoc_split_pos =
45056 + DWC_HCSPLIT_XACTPOS_END;
45058 + qtd->isoc_split_pos =
45059 + DWC_HCSPLIT_XACTPOS_MID;
45066 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
45070 + * An unmasked ACK on a non-split DMA transaction is
45071 + * for the sole purpose of resetting error counts. Disable other
45072 + * interrupts unmasked for the same reason.
45074 + if(hcd->core_if->dma_enable) {
45075 + disable_hc_int(hc_regs, datatglerr);
45076 + disable_hc_int(hc_regs, nak);
45078 + qtd->error_count = 0;
45080 + if (hc->qh->ping_state) {
45081 + hc->qh->ping_state = 0;
45083 + * Halt the channel so the transfer can be re-started
45084 + * from the appropriate point. This only happens in
45085 + * Slave mode. In DMA mode, the ping_state is cleared
45086 + * when the transfer is started because the core
45087 + * automatically executes the PING, then the transfer.
45089 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
45094 + * If the ACK occurred when _not_ in the PING state, let the channel
45095 + * continue transferring data after clearing the error count.
45098 + disable_hc_int(hc_regs, ack);
45104 + * Handles a host channel NYET interrupt. This interrupt should only occur on
45105 + * Bulk and Control OUT endpoints and for complete split transactions. If a
45106 + * NYET occurs at the same time as a Transfer Complete interrupt, it is
45107 + * handled in the xfercomp interrupt handler, not here. This handler may be
45108 + * called in either DMA mode or Slave mode.
45110 +static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t * hcd,
45112 + dwc_otg_hc_regs_t * hc_regs,
45113 + dwc_otg_qtd_t * qtd)
45115 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
45116 + "NYET Received--\n", hc->hc_num);
45120 + * re-do the CSPLIT immediately on non-periodic
45122 + if (hc->do_split && hc->complete_split) {
45123 + if (hc->ep_is_in && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
45124 + && hcd->core_if->dma_enable) {
45125 + qtd->complete_split = 0;
45126 + qtd->isoc_split_offset = 0;
45127 + if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
45128 + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
45129 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
45132 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
45133 + goto handle_nyet_done;
45136 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
45137 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
45138 + int frnum = dwc_otg_hcd_get_frame_number(hcd);
45140 + // With the FIQ running we only ever see the failed NYET
45141 + if (dwc_full_frame_num(frnum) !=
45142 + dwc_full_frame_num(hc->qh->sched_frame) ||
45143 + fiq_fsm_enable) {
45145 + * No longer in the same full speed frame.
45146 + * Treat this as a transaction error.
45149 + /** @todo Fix system performance so this can
45150 + * be treated as an error. Right now complete
45151 + * splits cannot be scheduled precisely enough
45152 + * due to other system activity, so this error
45153 + * occurs regularly in Slave mode.
45155 + qtd->error_count++;
45157 + qtd->complete_split = 0;
45158 + halt_channel(hcd, hc, qtd,
45159 + DWC_OTG_HC_XFER_XACT_ERR);
45160 + /** @todo add support for isoc release */
45161 + goto handle_nyet_done;
45165 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
45166 + goto handle_nyet_done;
45169 + hc->qh->ping_state = 1;
45170 + qtd->error_count = 0;
45172 + update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd,
45173 + DWC_OTG_HC_XFER_NYET);
45174 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
45177 + * Halt the channel and re-start the transfer so the PING
45178 + * protocol will start.
45180 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
45183 + disable_hc_int(hc_regs, nyet);
45188 + * Handles a host channel babble interrupt. This handler may be called in
45189 + * either DMA mode or Slave mode.
45191 +static int32_t handle_hc_babble_intr(dwc_otg_hcd_t * hcd,
45193 + dwc_otg_hc_regs_t * hc_regs,
45194 + dwc_otg_qtd_t * qtd)
45196 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
45197 + "Babble Error--\n", hc->hc_num);
45199 + if (hcd->core_if->dma_desc_enable) {
45200 + dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
45201 + DWC_OTG_HC_XFER_BABBLE_ERR);
45202 + goto handle_babble_done;
45205 + if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
45206 + hcd->fops->complete(hcd, qtd->urb->priv,
45207 + qtd->urb, -DWC_E_OVERFLOW);
45208 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR);
45210 + dwc_otg_halt_status_e halt_status;
45211 + halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
45212 + DWC_OTG_HC_XFER_BABBLE_ERR);
45213 + halt_channel(hcd, hc, qtd, halt_status);
45216 +handle_babble_done:
45217 + disable_hc_int(hc_regs, bblerr);
45222 + * Handles a host channel AHB error interrupt. This handler is only called in
45225 +static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t * hcd,
45227 + dwc_otg_hc_regs_t * hc_regs,
45228 + dwc_otg_qtd_t * qtd)
45230 + hcchar_data_t hcchar;
45231 + hcsplt_data_t hcsplt;
45232 + hctsiz_data_t hctsiz;
45234 + char *pipetype, *speed;
45236 + dwc_otg_hcd_urb_t *urb = qtd->urb;
45238 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
45239 + "AHB Error--\n", hc->hc_num);
45241 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
45242 + hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
45243 + hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
45244 + hcdma = DWC_READ_REG32(&hc_regs->hcdma);
45246 + DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num);
45247 + DWC_ERROR(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
45248 + DWC_ERROR(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
45249 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n");
45250 + DWC_ERROR(" Device address: %d\n",
45251 + dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
45252 + DWC_ERROR(" Endpoint: %d, %s\n",
45253 + dwc_otg_hcd_get_ep_num(&urb->pipe_info),
45254 + (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"));
45256 + switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
45258 + pipetype = "CONTROL";
45261 + pipetype = "BULK";
45263 + case UE_INTERRUPT:
45264 + pipetype = "INTERRUPT";
45266 + case UE_ISOCHRONOUS:
45267 + pipetype = "ISOCHRONOUS";
45270 + pipetype = "UNKNOWN";
45274 + DWC_ERROR(" Endpoint type: %s\n", pipetype);
45276 + switch (hc->speed) {
45277 + case DWC_OTG_EP_SPEED_HIGH:
45280 + case DWC_OTG_EP_SPEED_FULL:
45283 + case DWC_OTG_EP_SPEED_LOW:
45287 + speed = "UNKNOWN";
45291 + DWC_ERROR(" Speed: %s\n", speed);
45293 + DWC_ERROR(" Max packet size: %d\n",
45294 + dwc_otg_hcd_get_mps(&urb->pipe_info));
45295 + DWC_ERROR(" Data buffer length: %d\n", urb->length);
45296 + DWC_ERROR(" Transfer buffer: %p, Transfer DMA: %p\n",
45297 + urb->buf, (void *)urb->dma);
45298 + DWC_ERROR(" Setup buffer: %p, Setup DMA: %p\n",
45299 + urb->setup_packet, (void *)urb->setup_dma);
45300 + DWC_ERROR(" Interval: %d\n", urb->interval);
45302 + /* Core haltes the channel for Descriptor DMA mode */
45303 + if (hcd->core_if->dma_desc_enable) {
45304 + dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
45305 + DWC_OTG_HC_XFER_AHB_ERR);
45306 + goto handle_ahberr_done;
45309 + hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_IO);
45312 + * Force a channel halt. Don't call halt_channel because that won't
45313 + * write to the HCCHARn register in DMA mode to force the halt.
45315 + dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR);
45316 +handle_ahberr_done:
45317 + disable_hc_int(hc_regs, ahberr);
45322 + * Handles a host channel transaction error interrupt. This handler may be
45323 + * called in either DMA mode or Slave mode.
45325 +static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t * hcd,
45327 + dwc_otg_hc_regs_t * hc_regs,
45328 + dwc_otg_qtd_t * qtd)
45330 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
45331 + "Transaction Error--\n", hc->hc_num);
45333 + if (hcd->core_if->dma_desc_enable) {
45334 + dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
45335 + DWC_OTG_HC_XFER_XACT_ERR);
45336 + goto handle_xacterr_done;
45339 + switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
45342 + qtd->error_count++;
45343 + if (!hc->qh->ping_state) {
45345 + update_urb_state_xfer_intr(hc, hc_regs,
45347 + DWC_OTG_HC_XFER_XACT_ERR);
45348 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
45349 + if (!hc->ep_is_in && hc->speed == DWC_OTG_EP_SPEED_HIGH) {
45350 + hc->qh->ping_state = 1;
45355 + * Halt the channel so the transfer can be re-started from
45356 + * the appropriate point or the PING protocol will start.
45358 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
45360 + case UE_INTERRUPT:
45361 + qtd->error_count++;
45362 + if (hc->do_split && hc->complete_split) {
45363 + qtd->complete_split = 0;
45365 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
45367 + case UE_ISOCHRONOUS:
45369 + dwc_otg_halt_status_e halt_status;
45371 + update_isoc_urb_state(hcd, hc, hc_regs, qtd,
45372 + DWC_OTG_HC_XFER_XACT_ERR);
45374 + halt_channel(hcd, hc, qtd, halt_status);
45378 +handle_xacterr_done:
45379 + disable_hc_int(hc_regs, xacterr);
45385 + * Handles a host channel frame overrun interrupt. This handler may be called
45386 + * in either DMA mode or Slave mode.
45388 +static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t * hcd,
45390 + dwc_otg_hc_regs_t * hc_regs,
45391 + dwc_otg_qtd_t * qtd)
45393 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
45394 + "Frame Overrun--\n", hc->hc_num);
45396 + switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
45400 + case UE_INTERRUPT:
45401 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN);
45403 + case UE_ISOCHRONOUS:
45405 + dwc_otg_halt_status_e halt_status;
45407 + update_isoc_urb_state(hcd, hc, hc_regs, qtd,
45408 + DWC_OTG_HC_XFER_FRAME_OVERRUN);
45410 + halt_channel(hcd, hc, qtd, halt_status);
45415 + disable_hc_int(hc_regs, frmovrun);
45421 + * Handles a host channel data toggle error interrupt. This handler may be
45422 + * called in either DMA mode or Slave mode.
45424 +static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t * hcd,
45426 + dwc_otg_hc_regs_t * hc_regs,
45427 + dwc_otg_qtd_t * qtd)
45429 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
45430 + "Data Toggle Error on %s transfer--\n",
45431 + hc->hc_num, (hc->ep_is_in ? "IN" : "OUT"));
45433 + /* Data toggles on split transactions cause the hc to halt.
45434 + * restart transfer */
45435 + if(hc->qh->do_split)
45437 + qtd->error_count++;
45438 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
45439 + update_urb_state_xfer_intr(hc, hc_regs,
45440 + qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR);
45441 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
45442 + } else if (hc->ep_is_in) {
45443 + /* An unmasked data toggle error on a non-split DMA transaction is
45444 + * for the sole purpose of resetting error counts. Disable other
45445 + * interrupts unmasked for the same reason.
45447 + if(hcd->core_if->dma_enable) {
45448 + disable_hc_int(hc_regs, ack);
45449 + disable_hc_int(hc_regs, nak);
45451 + qtd->error_count = 0;
45454 + disable_hc_int(hc_regs, datatglerr);
45461 + * This function is for debug only. It checks that a valid halt status is set
45462 + * and that HCCHARn.chdis is clear. If there's a problem, corrective action is
45463 + * taken and a warning is issued.
45464 + * @return 1 if halt status is ok, 0 otherwise.
45466 +static inline int halt_status_ok(dwc_otg_hcd_t * hcd,
45468 + dwc_otg_hc_regs_t * hc_regs,
45469 + dwc_otg_qtd_t * qtd)
45471 + hcchar_data_t hcchar;
45472 + hctsiz_data_t hctsiz;
45473 + hcint_data_t hcint;
45474 + hcintmsk_data_t hcintmsk;
45475 + hcsplt_data_t hcsplt;
45477 + if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
45479 + * This code is here only as a check. This condition should
45480 + * never happen. Ignore the halt if it does occur.
45482 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
45483 + hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
45484 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
45485 + hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
45486 + hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
45488 + ("%s: hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, "
45489 + "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
45490 + "hcint 0x%08x, hcintmsk 0x%08x, "
45491 + "hcsplt 0x%08x, qtd->complete_split %d\n", __func__,
45492 + hc->hc_num, hcchar.d32, hctsiz.d32, hcint.d32,
45493 + hcintmsk.d32, hcsplt.d32, qtd->complete_split);
45495 + DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
45496 + __func__, hc->hc_num);
45498 + clear_hc_int(hc_regs, chhltd);
45503 + * This code is here only as a check. hcchar.chdis should
45504 + * never be set when the halt interrupt occurs. Halt the
45505 + * channel again if it does occur.
45507 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
45508 + if (hcchar.b.chdis) {
45509 + DWC_WARN("%s: hcchar.chdis set unexpectedly, "
45510 + "hcchar 0x%08x, trying to halt again\n",
45511 + __func__, hcchar.d32);
45512 + clear_hc_int(hc_regs, chhltd);
45513 + hc->halt_pending = 0;
45514 + halt_channel(hcd, hc, qtd, hc->halt_status);
45523 + * Handles a host Channel Halted interrupt in DMA mode. This handler
45524 + * determines the reason the channel halted and proceeds accordingly.
45526 +static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t * hcd,
45528 + dwc_otg_hc_regs_t * hc_regs,
45529 + dwc_otg_qtd_t * qtd)
45531 + int out_nak_enh = 0;
45532 + hcint_data_t hcint;
45533 + hcintmsk_data_t hcintmsk;
45534 + /* For core with OUT NAK enhancement, the flow for high-
45535 + * speed CONTROL/BULK OUT is handled a little differently.
45537 + if (hcd->core_if->snpsid >= OTG_CORE_REV_2_71a) {
45538 + if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
45539 + (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
45540 + hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
45545 + if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
45546 + (hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR
45547 + && !hcd->core_if->dma_desc_enable)) {
45549 + * Just release the channel. A dequeue can happen on a
45550 + * transfer timeout. In the case of an AHB Error, the channel
45551 + * was forced to halt because there's no way to gracefully
45554 + if (hcd->core_if->dma_desc_enable)
45555 + dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
45556 + hc->halt_status);
45558 + release_channel(hcd, hc, qtd, hc->halt_status);
45562 + /* Read the HCINTn register to determine the cause for the halt. */
45564 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
45565 + hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
45567 + if (hcint.b.xfercomp) {
45568 + /** @todo This is here because of a possible hardware bug. Spec
45569 + * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
45570 + * interrupt w/ACK bit set should occur, but I only see the
45571 + * XFERCOMP bit, even with it masked out. This is a workaround
45572 + * for that behavior. Should fix this when hardware is fixed.
45574 + if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
45575 + handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
45577 + handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
45578 + } else if (hcint.b.stall) {
45579 + handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
45580 + } else if (hcint.b.xacterr && !hcd->core_if->dma_desc_enable) {
45581 + if (out_nak_enh) {
45582 + if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
45583 + DWC_DEBUGPL(DBG_HCD, "XactErr with NYET/NAK/ACK\n");
45584 + qtd->error_count = 0;
45586 + DWC_DEBUGPL(DBG_HCD, "XactErr without NYET/NAK/ACK\n");
45591 + * Must handle xacterr before nak or ack. Could get a xacterr
45592 + * at the same time as either of these on a BULK/CONTROL OUT
45593 + * that started with a PING. The xacterr takes precedence.
45595 + handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
45596 + } else if (hcint.b.xcs_xact && hcd->core_if->dma_desc_enable) {
45597 + handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
45598 + } else if (hcint.b.ahberr && hcd->core_if->dma_desc_enable) {
45599 + handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
45600 + } else if (hcint.b.bblerr) {
45601 + handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
45602 + } else if (hcint.b.frmovrun) {
45603 + handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
45604 + } else if (hcint.b.datatglerr) {
45605 + handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd);
45606 + } else if (!out_nak_enh) {
45607 + if (hcint.b.nyet) {
45609 + * Must handle nyet before nak or ack. Could get a nyet at the
45610 + * same time as either of those on a BULK/CONTROL OUT that
45611 + * started with a PING. The nyet takes precedence.
45613 + handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
45614 + } else if (hcint.b.nak && !hcintmsk.b.nak) {
45616 + * If nak is not masked, it's because a non-split IN transfer
45617 + * is in an error state. In that case, the nak is handled by
45618 + * the nak interrupt handler, not here. Handle nak here for
45619 + * BULK/CONTROL OUT transfers, which halt on a NAK to allow
45620 + * rewinding the buffer pointer.
45622 + handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
45623 + } else if (hcint.b.ack && !hcintmsk.b.ack) {
45625 + * If ack is not masked, it's because a non-split IN transfer
45626 + * is in an error state. In that case, the ack is handled by
45627 + * the ack interrupt handler, not here. Handle ack here for
45628 + * split transfers. Start splits halt on ACK.
45630 + handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
45632 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
45633 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
45635 + * A periodic transfer halted with no other channel
45636 + * interrupts set. Assume it was halted by the core
45637 + * because it could not be completed in its scheduled
45642 + ("%s: Halt channel %d (assume incomplete periodic transfer)\n",
45643 + __func__, hc->hc_num);
45645 + halt_channel(hcd, hc, qtd,
45646 + DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
45649 + ("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
45650 + "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
45651 + __func__, hc->hc_num, hcint.d32,
45652 + DWC_READ_REG32(&hcd->
45653 + core_if->core_global_regs->
45655 + /* Failthrough: use 3-strikes rule */
45656 + qtd->error_count++;
45657 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
45658 + update_urb_state_xfer_intr(hc, hc_regs,
45659 + qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR);
45660 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
45665 + DWC_PRINTF("NYET/NAK/ACK/other in non-error case, 0x%08x\n",
45667 + /* Failthrough: use 3-strikes rule */
45668 + qtd->error_count++;
45669 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
45670 + update_urb_state_xfer_intr(hc, hc_regs,
45671 + qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR);
45672 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
45677 + * Handles a host channel Channel Halted interrupt.
45679 + * In slave mode, this handler is called only when the driver specifically
45680 + * requests a halt. This occurs during handling other host channel interrupts
45681 + * (e.g. nak, xacterr, stall, nyet, etc.).
45683 + * In DMA mode, this is the interrupt that occurs when the core has finished
45684 + * processing a transfer on a channel. Other host channel interrupts (except
45685 + * ahberr) are disabled in DMA mode.
45687 +static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t * hcd,
45689 + dwc_otg_hc_regs_t * hc_regs,
45690 + dwc_otg_qtd_t * qtd)
45692 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
45693 + "Channel Halted--\n", hc->hc_num);
45695 + if (hcd->core_if->dma_enable) {
45696 + handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd);
45699 + if (!halt_status_ok(hcd, hc, hc_regs, qtd)) {
45703 + release_channel(hcd, hc, qtd, hc->halt_status);
45711 + * dwc_otg_fiq_unmangle_isoc() - Update the iso_frame_desc structure on
45712 + * FIQ transfer completion
45713 + * @hcd: Pointer to dwc_otg_hcd struct
45714 + * @num: Host channel number
45716 + * 1. Un-mangle the status as recorded in each iso_frame_desc status
45717 + * 2. Copy it from the dwc_otg_urb into the real URB
45719 +void dwc_otg_fiq_unmangle_isoc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_qtd_t *qtd, uint32_t num)
45721 + struct dwc_otg_hcd_urb *dwc_urb = qtd->urb;
45722 + int nr_frames = dwc_urb->packet_count;
45724 + hcint_data_t frame_hcint;
45726 + for (i = 0; i < nr_frames; i++) {
45727 + frame_hcint.d32 = dwc_urb->iso_descs[i].status;
45728 + if (frame_hcint.b.xfercomp) {
45729 + dwc_urb->iso_descs[i].status = 0;
45730 + dwc_urb->actual_length += dwc_urb->iso_descs[i].actual_length;
45731 + } else if (frame_hcint.b.frmovrun) {
45732 + if (qh->ep_is_in)
45733 + dwc_urb->iso_descs[i].status = -DWC_E_NO_STREAM_RES;
45735 + dwc_urb->iso_descs[i].status = -DWC_E_COMMUNICATION;
45736 + dwc_urb->error_count++;
45737 + dwc_urb->iso_descs[i].actual_length = 0;
45738 + } else if (frame_hcint.b.xacterr) {
45739 + dwc_urb->iso_descs[i].status = -DWC_E_PROTOCOL;
45740 + dwc_urb->error_count++;
45741 + dwc_urb->iso_descs[i].actual_length = 0;
45742 + } else if (frame_hcint.b.bblerr) {
45743 + dwc_urb->iso_descs[i].status = -DWC_E_OVERFLOW;
45744 + dwc_urb->error_count++;
45745 + dwc_urb->iso_descs[i].actual_length = 0;
45747 + /* Something went wrong */
45748 + dwc_urb->iso_descs[i].status = -1;
45749 + dwc_urb->iso_descs[i].actual_length = 0;
45750 + dwc_urb->error_count++;
45753 + qh->sched_frame = dwc_frame_num_inc(qh->sched_frame, qh->interval * (nr_frames - 1));
45755 + //printk_ratelimited(KERN_INFO "%s: HS isochronous of %d/%d frames with %d errors complete\n",
45756 + // __FUNCTION__, i, dwc_urb->packet_count, dwc_urb->error_count);
45760 + * dwc_otg_fiq_unsetup_per_dma() - Remove data from bounce buffers for split transactions
45761 + * @hcd: Pointer to dwc_otg_hcd struct
45762 + * @num: Host channel number
45764 + * Copies data from the FIQ bounce buffers into the URB's transfer buffer. Does not modify URB state.
45765 + * Returns total length of data or -1 if the buffers were not used.
45768 +int dwc_otg_fiq_unsetup_per_dma(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_qtd_t *qtd, uint32_t num)
45770 + dwc_hc_t *hc = qh->channel;
45771 + struct fiq_dma_blob *blob = hcd->fiq_dmab;
45772 + struct fiq_channel_state *st = &hcd->fiq_state->channel[num];
45773 + uint8_t *ptr = NULL;
45774 + int index = 0, len = 0;
45776 + if (hc->ep_is_in) {
45777 + /* Copy data out of the DMA bounce buffers to the URB's buffer.
45778 + * The align_buf is ignored as this is ignored on FSM enqueue. */
45779 + ptr = qtd->urb->buf;
45780 + if (qh->ep_type == UE_ISOCHRONOUS) {
45781 + /* Isoc IN transactions - grab the offset of the iso_frame_desc into the URB transfer buffer */
45782 + index = qtd->isoc_frame_index;
45783 + ptr += qtd->urb->iso_descs[index].offset;
45785 + /* Need to increment by actual_length for interrupt IN */
45786 + ptr += qtd->urb->actual_length;
45789 + for (i = 0; i < st->dma_info.index; i++) {
45790 + len += st->dma_info.slot_len[i];
45791 + dwc_memcpy(ptr, &blob->channel[num].index[i].buf[0], st->dma_info.slot_len[i]);
45792 + ptr += st->dma_info.slot_len[i];
45796 + /* OUT endpoints - nothing to do. */
45802 + * dwc_otg_hcd_handle_hc_fsm() - handle an unmasked channel interrupt
45803 + * from a channel handled in the FIQ
45804 + * @hcd: Pointer to dwc_otg_hcd struct
45805 + * @num: Host channel number
45807 + * If a host channel interrupt was received by the IRQ and this was a channel
45808 + * used by the FIQ, the execution flow for transfer completion is substantially
45809 + * different from the normal (messy) path. This function and its friends handles
45810 + * channel cleanup and transaction completion from a FIQ transaction.
45812 +void dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd_t *hcd, uint32_t num)
45814 + struct fiq_channel_state *st = &hcd->fiq_state->channel[num];
45815 + dwc_hc_t *hc = hcd->hc_ptr_array[num];
45816 + dwc_otg_qtd_t *qtd;
45817 + dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[num];
45818 + hcint_data_t hcint = hcd->fiq_state->channel[num].hcint_copy;
45819 + hctsiz_data_t hctsiz = hcd->fiq_state->channel[num].hctsiz_copy;
45820 + int hostchannels = 0;
45821 + fiq_print(FIQDBG_INT, hcd->fiq_state, "OUT %01d %01d ", num , st->fsm);
45823 + hostchannels = hcd->available_host_channels;
45824 + if (hc->halt_pending) {
45825 + /* Dequeue: The FIQ was allowed to complete the transfer but state has been cleared. */
45826 + if (hc->qh && st->fsm == FIQ_NP_SPLIT_DONE &&
45827 + hcint.b.xfercomp && hc->qh->ep_type == UE_BULK) {
45828 + if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
45829 + hc->qh->data_toggle = DWC_OTG_HC_PID_DATA1;
45831 + hc->qh->data_toggle = DWC_OTG_HC_PID_DATA0;
45834 + release_channel(hcd, hc, NULL, hc->halt_status);
45838 + qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);
45839 + switch (st->fsm) {
45843 + case FIQ_DEQUEUE_ISSUED:
45844 + /* Handled above, but keep for posterity */
45845 + release_channel(hcd, hc, NULL, hc->halt_status);
45848 + case FIQ_NP_SPLIT_DONE:
45849 + /* Nonperiodic transaction complete. */
45850 + if (!hc->ep_is_in) {
45851 + qtd->ssplit_out_xfer_count = hc->xfer_len;
45853 + if (hcint.b.xfercomp) {
45854 + handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
45855 + } else if (hcint.b.nak) {
45856 + handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
45858 + DWC_WARN("Unexpected IRQ state on FSM transaction:"
45859 + "dev_addr=%d ep=%d fsm=%d, hcint=0x%08x\n",
45860 + hc->dev_addr, hc->ep_num, st->fsm, hcint.d32);
45861 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
45865 + case FIQ_NP_SPLIT_HS_ABORTED:
45866 + /* A HS abort is a 3-strikes on the HS bus at any point in the transaction.
45867 + * Normally a CLEAR_TT_BUFFER hub command would be required: we can't do that
45868 + * because there's no guarantee which order a non-periodic split happened in.
45869 + * We could end up clearing a perfectly good transaction out of the buffer.
45871 + if (hcint.b.xacterr) {
45872 + qtd->error_count += st->nr_errors;
45873 + handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
45874 + } else if (hcint.b.ahberr) {
45875 + handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
45877 + DWC_WARN("Unexpected IRQ state on FSM transaction:"
45878 + "dev_addr=%d ep=%d fsm=%d, hcint=0x%08x\n",
45879 + hc->dev_addr, hc->ep_num, st->fsm, hcint.d32);
45880 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
45884 + case FIQ_NP_SPLIT_LS_ABORTED:
45885 + /* A few cases can cause this - either an unknown state on a SSPLIT or
45886 + * STALL/data toggle error response on a CSPLIT */
45887 + if (hcint.b.stall) {
45888 + handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
45889 + } else if (hcint.b.datatglerr) {
45890 + handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd);
45891 + } else if (hcint.b.bblerr) {
45892 + handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
45893 + } else if (hcint.b.ahberr) {
45894 + handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
45896 + DWC_WARN("Unexpected IRQ state on FSM transaction:"
45897 + "dev_addr=%d ep=%d fsm=%d, hcint=0x%08x\n",
45898 + hc->dev_addr, hc->ep_num, st->fsm, hcint.d32);
45899 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
45903 + case FIQ_PER_SPLIT_DONE:
45904 + /* Isoc IN or Interrupt IN/OUT */
45906 + /* Flow control here is different from the normal execution by the driver.
45907 + * We need to completely ignore most of the driver's method of handling
45908 + * split transactions and do it ourselves.
45910 + if (hc->ep_type == UE_INTERRUPT) {
45911 + if (hcint.b.nak) {
45912 + handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
45913 + } else if (hc->ep_is_in) {
45915 + len = dwc_otg_fiq_unsetup_per_dma(hcd, hc->qh, qtd, num);
45916 + //printk(KERN_NOTICE "FIQ Transaction: hc=%d len=%d urb_len = %d\n", num, len, qtd->urb->length);
45917 + qtd->urb->actual_length += len;
45918 + if (qtd->urb->actual_length >= qtd->urb->length) {
45919 + qtd->urb->status = 0;
45920 + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status);
45921 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
45923 + /* Interrupt transfer not complete yet - is it a short read? */
45924 + if (len < hc->max_packet) {
45925 + /* Interrupt transaction complete */
45926 + qtd->urb->status = 0;
45927 + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status);
45928 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
45930 + /* Further transactions required */
45931 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
45935 + /* Interrupt OUT complete. */
45936 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
45937 + qtd->urb->actual_length += hc->xfer_len;
45938 + if (qtd->urb->actual_length >= qtd->urb->length) {
45939 + qtd->urb->status = 0;
45940 + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status);
45941 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
45943 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
45947 + /* ISOC IN complete. */
45948 + struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
45950 + /* Record errors, update qtd. */
45951 + if (st->nr_errors) {
45952 + frame_desc->actual_length = 0;
45953 + frame_desc->status = -DWC_E_PROTOCOL;
45955 + frame_desc->status = 0;
45956 + /* Unswizzle dma */
45957 + len = dwc_otg_fiq_unsetup_per_dma(hcd, hc->qh, qtd, num);
45958 + frame_desc->actual_length = len;
45960 + qtd->isoc_frame_index++;
45961 + if (qtd->isoc_frame_index == qtd->urb->packet_count) {
45962 + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
45963 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
45965 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
45970 + case FIQ_PER_ISO_OUT_DONE: {
45971 + struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
45972 + /* Record errors, update qtd. */
45973 + if (st->nr_errors) {
45974 + frame_desc->actual_length = 0;
45975 + frame_desc->status = -DWC_E_PROTOCOL;
45977 + frame_desc->status = 0;
45978 + frame_desc->actual_length = frame_desc->length;
45980 + qtd->isoc_frame_index++;
45981 + qtd->isoc_split_offset = 0;
45982 + if (qtd->isoc_frame_index == qtd->urb->packet_count) {
45983 + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
45984 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
45986 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
45991 + case FIQ_PER_SPLIT_NYET_ABORTED:
45992 + /* Doh. lost the data. */
45993 + printk_ratelimited(KERN_INFO "Transfer to device %d endpoint 0x%x frame %d failed "
45994 + "- FIQ reported NYET. Data may have been lost.\n",
45995 + hc->dev_addr, hc->ep_num, dwc_otg_hcd_get_frame_number(hcd) >> 3);
45996 + if (hc->ep_type == UE_ISOCHRONOUS) {
45997 + struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
45998 + /* Record errors, update qtd. */
45999 + frame_desc->actual_length = 0;
46000 + frame_desc->status = -DWC_E_PROTOCOL;
46001 + qtd->isoc_frame_index++;
46002 + qtd->isoc_split_offset = 0;
46003 + if (qtd->isoc_frame_index == qtd->urb->packet_count) {
46004 + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
46005 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
46007 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
46010 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
46014 + case FIQ_HS_ISOC_DONE:
46015 + /* The FIQ has performed a whole pile of isochronous transactions.
46016 + * The status is recorded as the interrupt state should the transaction
46019 + dwc_otg_fiq_unmangle_isoc(hcd, hc->qh, qtd, num);
46020 + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
46021 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
46024 + case FIQ_PER_SPLIT_LS_ABORTED:
46025 + if (hcint.b.xacterr) {
46026 + /* Hub has responded with an ERR packet. Device
46027 + * has been unplugged or the port has been disabled.
46028 + * TODO: need to issue a reset to the hub port. */
46029 + qtd->error_count += 3;
46030 + handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
46031 + } else if (hcint.b.stall) {
46032 + handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
46033 + } else if (hcint.b.bblerr) {
46034 + handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
46036 + printk_ratelimited(KERN_INFO "Transfer to device %d endpoint 0x%x failed "
46037 + "- FIQ reported FSM=%d. Data may have been lost.\n",
46038 + st->fsm, hc->dev_addr, hc->ep_num);
46039 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
46043 + case FIQ_PER_SPLIT_HS_ABORTED:
46044 + /* Either the SSPLIT phase suffered transaction errors or something
46045 + * unexpected happened.
46047 + qtd->error_count += 3;
46048 + handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
46049 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
46052 + case FIQ_PER_SPLIT_TIMEOUT:
46053 + /* Couldn't complete in the nominated frame */
46054 + printk(KERN_INFO "Transfer to device %d endpoint 0x%x frame %d failed "
46055 + "- FIQ timed out. Data may have been lost.\n",
46056 + hc->dev_addr, hc->ep_num, dwc_otg_hcd_get_frame_number(hcd) >> 3);
46057 + if (hc->ep_type == UE_ISOCHRONOUS) {
46058 + struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
46059 + /* Record errors, update qtd. */
46060 + frame_desc->actual_length = 0;
46061 + if (hc->ep_is_in) {
46062 + frame_desc->status = -DWC_E_NO_STREAM_RES;
46064 + frame_desc->status = -DWC_E_COMMUNICATION;
46066 + qtd->isoc_frame_index++;
46067 + if (qtd->isoc_frame_index == qtd->urb->packet_count) {
46068 + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
46069 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
46071 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
46074 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
46079 + DWC_WARN("Unexpected state received on hc=%d fsm=%d on transfer to device %d ep 0x%x",
46080 + hc->hc_num, st->fsm, hc->dev_addr, hc->ep_num);
46081 + qtd->error_count++;
46082 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
46087 +/** Handles interrupt for a specific Host Channel */
46088 +int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num)
46091 + hcint_data_t hcint;
46092 + hcintmsk_data_t hcintmsk;
46094 + dwc_otg_hc_regs_t *hc_regs;
46095 + dwc_otg_qtd_t *qtd;
46097 + DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num);
46099 + hc = dwc_otg_hcd->hc_ptr_array[num];
46100 + hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num];
46101 + if(hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
46102 + /* A dequeue was issued for this transfer. Our QTD has gone away
46103 + * but in the case of a FIQ transfer, the transfer would have run
46106 + if (fiq_fsm_enable && dwc_otg_hcd->fiq_state->channel[num].fsm != FIQ_PASSTHROUGH) {
46107 + dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd, num);
46109 + release_channel(dwc_otg_hcd, hc, NULL, hc->halt_status);
46113 + qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);
46116 + * FSM mode: Check to see if this is a HC interrupt from a channel handled by the FIQ.
46117 + * Execution path is fundamentally different for the channels after a FIQ has completed
46118 + * a split transaction.
46120 + if (fiq_fsm_enable) {
46121 + switch (dwc_otg_hcd->fiq_state->channel[num].fsm) {
46122 + case FIQ_PASSTHROUGH:
46124 + case FIQ_PASSTHROUGH_ERRORSTATE:
46125 + /* Hook into the error count */
46126 + fiq_print(FIQDBG_ERR, dwc_otg_hcd->fiq_state, "HCDERR%02d", num);
46127 + if (!dwc_otg_hcd->fiq_state->channel[num].nr_errors) {
46128 + qtd->error_count = 0;
46129 + fiq_print(FIQDBG_ERR, dwc_otg_hcd->fiq_state, "RESET ");
46133 + dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd, num);
46138 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
46139 + hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
46140 + hcint.d32 = hcint.d32 & hcintmsk.d32;
46141 + if (!dwc_otg_hcd->core_if->dma_enable) {
46142 + if (hcint.b.chhltd && hcint.d32 != 0x2) {
46143 + hcint.b.chhltd = 0;
46147 + if (hcint.b.xfercomp) {
46149 + handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd);
46151 + * If NYET occurred at same time as Xfer Complete, the NYET is
46152 + * handled by the Xfer Complete interrupt handler. Don't want
46153 + * to call the NYET interrupt handler in this case.
46155 + hcint.b.nyet = 0;
46157 + if (hcint.b.chhltd) {
46158 + retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd);
46160 + if (hcint.b.ahberr) {
46161 + retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
46163 + if (hcint.b.stall) {
46164 + retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd);
46166 + if (hcint.b.nak) {
46167 + retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd);
46169 + if (hcint.b.ack) {
46170 + if(!hcint.b.chhltd)
46171 + retval |= handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd);
46173 + if (hcint.b.nyet) {
46174 + retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd);
46176 + if (hcint.b.xacterr) {
46177 + retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
46179 + if (hcint.b.bblerr) {
46180 + retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd);
46182 + if (hcint.b.frmovrun) {
46184 + handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd);
46186 + if (hcint.b.datatglerr) {
46188 + handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
46193 +#endif /* DWC_DEVICE_ONLY */
46195 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
46198 +/* ==========================================================================
46199 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_linux.c $
46200 + * $Revision: #20 $
46201 + * $Date: 2011/10/26 $
46202 + * $Change: 1872981 $
46204 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
46205 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
46206 + * otherwise expressly agreed to in writing between Synopsys and you.
46208 + * The Software IS NOT an item of Licensed Software or Licensed Product under
46209 + * any End User Software License Agreement or Agreement for Licensed Product
46210 + * with Synopsys or any supplement thereto. You are permitted to use and
46211 + * redistribute this Software in source and binary forms, with or without
46212 + * modification, provided that redistributions of source code must retain this
46213 + * notice. You may not view, use, disclose, copy or distribute this file or
46214 + * any information contained herein except pursuant to this license grant from
46215 + * Synopsys. If you do not agree with this notice, including the disclaimer
46216 + * below, then you are not authorized to use the Software.
46218 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
46219 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
46220 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
46221 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
46222 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
46223 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
46224 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
46225 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
46226 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
46227 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
46229 + * ========================================================================== */
46230 +#ifndef DWC_DEVICE_ONLY
46235 + * This file contains the implementation of the HCD. In Linux, the HCD
46236 + * implements the hc_driver API.
46238 +#include <linux/kernel.h>
46239 +#include <linux/module.h>
46240 +#include <linux/moduleparam.h>
46241 +#include <linux/init.h>
46242 +#include <linux/device.h>
46243 +#include <linux/errno.h>
46244 +#include <linux/list.h>
46245 +#include <linux/interrupt.h>
46246 +#include <linux/string.h>
46247 +#include <linux/dma-mapping.h>
46248 +#include <linux/version.h>
46249 +#include <asm/io.h>
46251 +#include <asm/fiq.h>
46253 +#include <linux/usb.h>
46254 +#include <linux/usb/hcd.h>
46255 +#include <asm/bug.h>
46257 +#define USB_URB_EP_LINKING 1
46259 +#include "dwc_otg_hcd_if.h"
46260 +#include "dwc_otg_dbg.h"
46261 +#include "dwc_otg_driver.h"
46262 +#include "dwc_otg_hcd.h"
46264 +#ifndef __virt_to_bus
46265 +#define __virt_to_bus __virt_to_phys
46266 +#define __bus_to_virt __phys_to_virt
46267 +#define __pfn_to_bus(x) __pfn_to_phys(x)
46268 +#define __bus_to_pfn(x) __phys_to_pfn(x)
46271 +extern unsigned char _dwc_otg_fiq_stub, _dwc_otg_fiq_stub_end;
46274 + * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is
46275 + * qualified with its direction (possible 32 endpoints per device).
46277 +#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
46278 + ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
46280 +static const char dwc_otg_hcd_name[] = "dwc_otg_hcd";
46282 +extern bool fiq_enable;
46284 +/** @name Linux HC Driver API Functions */
46286 +/* manage i/o requests, device state */
46287 +static int dwc_otg_urb_enqueue(struct usb_hcd *hcd,
46288 + struct urb *urb, gfp_t mem_flags);
46290 +static int dwc_otg_urb_dequeue(struct usb_hcd *hcd,
46291 + struct urb *urb, int status);
46293 +static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
46294 +static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
46295 +static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd);
46296 +extern int hcd_start(struct usb_hcd *hcd);
46297 +extern void hcd_stop(struct usb_hcd *hcd);
46298 +static int get_frame_number(struct usb_hcd *hcd);
46299 +extern int hub_status_data(struct usb_hcd *hcd, char *buf);
46300 +extern int hub_control(struct usb_hcd *hcd,
46302 + u16 wValue, u16 wIndex, char *buf, u16 wLength);
46304 +struct wrapper_priv_data {
46305 + dwc_otg_hcd_t *dwc_otg_hcd;
46310 +static struct hc_driver dwc_otg_hc_driver = {
46312 + .description = dwc_otg_hcd_name,
46313 + .product_desc = "DWC OTG Controller",
46314 + .hcd_priv_size = sizeof(struct wrapper_priv_data),
46316 + .irq = dwc_otg_hcd_irq,
46318 + .flags = HCD_MEMORY | HCD_USB2,
46321 + .start = hcd_start,
46324 + .stop = hcd_stop,
46326 + .urb_enqueue = dwc_otg_urb_enqueue,
46327 + .urb_dequeue = dwc_otg_urb_dequeue,
46328 + .endpoint_disable = endpoint_disable,
46329 + .endpoint_reset = endpoint_reset,
46330 + .get_frame_number = get_frame_number,
46332 + .hub_status_data = hub_status_data,
46333 + .hub_control = hub_control,
46338 +/** Gets the dwc_otg_hcd from a struct usb_hcd */
46339 +static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd)
46341 + struct wrapper_priv_data *p;
46342 + p = (struct wrapper_priv_data *)(hcd->hcd_priv);
46343 + return p->dwc_otg_hcd;
46346 +/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */
46347 +static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t * dwc_otg_hcd)
46349 + return dwc_otg_hcd_get_priv_data(dwc_otg_hcd);
46352 +/** Gets the usb_host_endpoint associated with an URB. */
46353 +inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *urb)
46355 + struct usb_device *dev = urb->dev;
46356 + int ep_num = usb_pipeendpoint(urb->pipe);
46358 + if (usb_pipein(urb->pipe))
46359 + return dev->ep_in[ep_num];
46361 + return dev->ep_out[ep_num];
46364 +static int _disconnect(dwc_otg_hcd_t * hcd)
46366 + struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
46368 + usb_hcd->self.is_b_host = 0;
46372 +static int _start(dwc_otg_hcd_t * hcd)
46374 + struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
46376 + usb_hcd->self.is_b_host = dwc_otg_hcd_is_b_host(hcd);
46377 + hcd_start(usb_hcd);
46382 +static int _hub_info(dwc_otg_hcd_t * hcd, void *urb_handle, uint32_t * hub_addr,
46383 + uint32_t * port_addr)
46385 + struct urb *urb = (struct urb *)urb_handle;
46386 + struct usb_bus *bus;
46387 +#if 1 //GRAYG - temporary
46388 + if (NULL == urb_handle)
46389 + DWC_ERROR("**** %s - NULL URB handle\n", __func__);//GRAYG
46390 + if (NULL == urb->dev)
46391 + DWC_ERROR("**** %s - URB has no device\n", __func__);//GRAYG
46392 + if (NULL == port_addr)
46393 + DWC_ERROR("**** %s - NULL port_address\n", __func__);//GRAYG
46395 + if (urb->dev->tt) {
46396 + if (NULL == urb->dev->tt->hub) {
46397 + DWC_ERROR("**** %s - (URB's transactor has no TT - giving no hub)\n",
46398 + __func__); //GRAYG
46399 + //*hub_addr = (u8)usb_pipedevice(urb->pipe); //GRAYG
46400 + *hub_addr = 0; //GRAYG
46401 + // we probably shouldn't have a transaction translator if
46402 + // there's no associated hub?
46404 + bus = hcd_to_bus(dwc_otg_hcd_to_hcd(hcd));
46405 + if (urb->dev->tt->hub == bus->root_hub)
46408 + *hub_addr = urb->dev->tt->hub->devnum;
46410 + *port_addr = urb->dev->ttport;
46413 + *port_addr = urb->dev->ttport;
46418 +static int _speed(dwc_otg_hcd_t * hcd, void *urb_handle)
46420 + struct urb *urb = (struct urb *)urb_handle;
46421 + return urb->dev->speed;
46424 +static int _get_b_hnp_enable(dwc_otg_hcd_t * hcd)
46426 + struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
46427 + return usb_hcd->self.b_hnp_enable;
46430 +static void allocate_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw,
46433 + hcd_to_bus(hcd)->bandwidth_allocated += bw / urb->interval;
46434 + if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
46435 + hcd_to_bus(hcd)->bandwidth_isoc_reqs++;
46437 + hcd_to_bus(hcd)->bandwidth_int_reqs++;
46441 +static void free_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw,
46444 + hcd_to_bus(hcd)->bandwidth_allocated -= bw / urb->interval;
46445 + if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
46446 + hcd_to_bus(hcd)->bandwidth_isoc_reqs--;
46448 + hcd_to_bus(hcd)->bandwidth_int_reqs--;
46453 + * Sets the final status of an URB and returns it to the device driver. Any
46454 + * required cleanup of the URB is performed. The HCD lock should be held on
46457 +static int _complete(dwc_otg_hcd_t * hcd, void *urb_handle,
46458 + dwc_otg_hcd_urb_t * dwc_otg_urb, int32_t status)
46460 + struct urb *urb = (struct urb *)urb_handle;
46461 + urb_tq_entry_t *new_entry;
46463 + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
46464 + DWC_PRINTF("%s: urb %p, device %d, ep %d %s, status=%d\n",
46465 + __func__, urb, usb_pipedevice(urb->pipe),
46466 + usb_pipeendpoint(urb->pipe),
46467 + usb_pipein(urb->pipe) ? "IN" : "OUT", status);
46468 + if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
46470 + for (i = 0; i < urb->number_of_packets; i++) {
46471 + DWC_PRINTF(" ISO Desc %d status: %d\n",
46472 + i, urb->iso_frame_desc[i].status);
46476 + new_entry = DWC_ALLOC_ATOMIC(sizeof(urb_tq_entry_t));
46477 + urb->actual_length = dwc_otg_hcd_urb_get_actual_length(dwc_otg_urb);
46478 + /* Convert status value. */
46479 + switch (status) {
46480 + case -DWC_E_PROTOCOL:
46481 + status = -EPROTO;
46483 + case -DWC_E_IN_PROGRESS:
46484 + status = -EINPROGRESS;
46486 + case -DWC_E_PIPE:
46492 + case -DWC_E_TIMEOUT:
46493 + status = -ETIMEDOUT;
46495 + case -DWC_E_OVERFLOW:
46496 + status = -EOVERFLOW;
46498 + case -DWC_E_SHUTDOWN:
46499 + status = -ESHUTDOWN;
46503 + DWC_PRINTF("Uknown urb status %d\n", status);
46508 + if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
46511 + urb->error_count = dwc_otg_hcd_urb_get_error_count(dwc_otg_urb);
46512 + urb->actual_length = 0;
46513 + for (i = 0; i < urb->number_of_packets; ++i) {
46514 + urb->iso_frame_desc[i].actual_length =
46515 + dwc_otg_hcd_urb_get_iso_desc_actual_length
46516 + (dwc_otg_urb, i);
46517 + urb->actual_length += urb->iso_frame_desc[i].actual_length;
46518 + urb->iso_frame_desc[i].status =
46519 + dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_urb, i);
46523 + urb->status = status;
46524 + urb->hcpriv = NULL;
46526 + if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
46527 + (urb->actual_length < urb->transfer_buffer_length)) {
46528 + urb->status = -EREMOTEIO;
46532 + if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) ||
46533 + (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) {
46534 + struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb);
46536 + free_bus_bandwidth(dwc_otg_hcd_to_hcd(hcd),
46537 + dwc_otg_hcd_get_ep_bandwidth(hcd,
46542 + DWC_FREE(dwc_otg_urb);
46543 + if (!new_entry) {
46544 + DWC_ERROR("dwc_otg_hcd: complete: cannot allocate URB TQ entry\n");
46545 + urb->status = -EPROTO;
46546 + /* don't schedule the tasklet -
46547 + * directly return the packet here with error. */
46548 +#if USB_URB_EP_LINKING
46549 + usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(hcd), urb);
46551 + usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, urb->status);
46553 + new_entry->urb = urb;
46554 +#if USB_URB_EP_LINKING
46555 + rc = usb_hcd_check_unlink_urb(dwc_otg_hcd_to_hcd(hcd), urb, urb->status);
46557 + usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(hcd), urb);
46561 + DWC_TAILQ_INSERT_TAIL(&hcd->completed_urb_list, new_entry,
46563 + DWC_TASK_HI_SCHEDULE(hcd->completion_tasklet);
46569 +static struct dwc_otg_hcd_function_ops hcd_fops = {
46571 + .disconnect = _disconnect,
46572 + .hub_info = _hub_info,
46574 + .complete = _complete,
46575 + .get_b_hnp_enable = _get_b_hnp_enable,
46578 +#ifdef CONFIG_ARM64
46580 +static int simfiq_irq = -1;
46582 +void local_fiq_enable(void)
46584 + if (simfiq_irq >= 0)
46585 + enable_irq(simfiq_irq);
46588 +void local_fiq_disable(void)
46590 + if (simfiq_irq >= 0)
46591 + disable_irq(simfiq_irq);
46594 +irqreturn_t fiq_irq_handler(int irq, void *dev_id)
46596 + dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *)dev_id;
46598 + if (fiq_fsm_enable)
46599 + dwc_otg_fiq_fsm(dwc_otg_hcd->fiq_state, dwc_otg_hcd->core_if->core_params->host_channels);
46601 + dwc_otg_fiq_nop(dwc_otg_hcd->fiq_state);
46603 + return IRQ_HANDLED;
46607 +static struct fiq_handler fh = {
46608 + .name = "usb_fiq",
46613 +static void hcd_init_fiq(void *cookie)
46615 + dwc_otg_device_t *otg_dev = cookie;
46616 + dwc_otg_hcd_t *dwc_otg_hcd = otg_dev->hcd;
46617 +#ifdef CONFIG_ARM64
46621 + struct pt_regs regs;
46624 + if (claim_fiq(&fh)) {
46625 + DWC_ERROR("Can't claim FIQ");
46628 + DWC_WARN("FIQ on core %d", smp_processor_id());
46629 + DWC_WARN("FIQ ASM at %px length %d", &_dwc_otg_fiq_stub, (int)(&_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub));
46630 + set_fiq_handler((void *) &_dwc_otg_fiq_stub, &_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub);
46631 + memset(®s,0,sizeof(regs));
46633 + regs.ARM_r8 = (long) dwc_otg_hcd->fiq_state;
46634 + if (fiq_fsm_enable) {
46635 + regs.ARM_r9 = dwc_otg_hcd->core_if->core_params->host_channels;
46636 + //regs.ARM_r10 = dwc_otg_hcd->dma;
46637 + regs.ARM_fp = (long) dwc_otg_fiq_fsm;
46639 + regs.ARM_fp = (long) dwc_otg_fiq_nop;
46642 + regs.ARM_sp = (long) dwc_otg_hcd->fiq_stack + (sizeof(struct fiq_stack) - 4);
46644 +// __show_regs(®s);
46645 + set_fiq_regs(®s);
46648 + dwc_otg_hcd->fiq_state->dwc_regs_base = otg_dev->os_dep.base;
46649 + //Set the mphi periph to the required registers
46650 + dwc_otg_hcd->fiq_state->mphi_regs.base = otg_dev->os_dep.mphi_base;
46651 + if (otg_dev->os_dep.use_swirq) {
46652 + dwc_otg_hcd->fiq_state->mphi_regs.swirq_set =
46653 + otg_dev->os_dep.mphi_base + 0x1f0;
46654 + dwc_otg_hcd->fiq_state->mphi_regs.swirq_clr =
46655 + otg_dev->os_dep.mphi_base + 0x1f4;
46656 + DWC_WARN("Fake MPHI regs_base at 0x%08x",
46657 + (int)dwc_otg_hcd->fiq_state->mphi_regs.base);
46659 + dwc_otg_hcd->fiq_state->mphi_regs.ctrl =
46660 + otg_dev->os_dep.mphi_base + 0x4c;
46661 + dwc_otg_hcd->fiq_state->mphi_regs.outdda
46662 + = otg_dev->os_dep.mphi_base + 0x28;
46663 + dwc_otg_hcd->fiq_state->mphi_regs.outddb
46664 + = otg_dev->os_dep.mphi_base + 0x2c;
46665 + dwc_otg_hcd->fiq_state->mphi_regs.intstat
46666 + = otg_dev->os_dep.mphi_base + 0x50;
46667 + DWC_WARN("MPHI regs_base at %px",
46668 + dwc_otg_hcd->fiq_state->mphi_regs.base);
46670 + //Enable mphi peripheral
46671 + writel((1<<31),dwc_otg_hcd->fiq_state->mphi_regs.ctrl);
46673 + if (readl(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & 0x80000000)
46674 + DWC_WARN("MPHI periph has been enabled");
46676 + DWC_WARN("MPHI periph has NOT been enabled");
46679 + // Enable FIQ interrupt from USB peripheral
46680 +#ifdef CONFIG_ARM64
46681 + irq = otg_dev->os_dep.fiq_num;
46684 + DWC_ERROR("Can't get SIM-FIQ irq");
46688 + retval = request_irq(irq, fiq_irq_handler, 0, "dwc_otg_sim-fiq", dwc_otg_hcd);
46690 + if (retval < 0) {
46691 + DWC_ERROR("Unable to request SIM-FIQ irq\n");
46695 + simfiq_irq = irq;
46697 +#ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER
46698 + irq = otg_dev->os_dep.fiq_num;
46700 + irq = INTERRUPT_VC_USB;
46703 + DWC_ERROR("Can't get FIQ irq");
46707 + * We could take an interrupt immediately after enabling the FIQ.
46708 + * Ensure coherency of hcd->fiq_state.
46712 + local_fiq_enable();
46718 + * Initializes the HCD. This function allocates memory for and initializes the
46719 + * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the
46720 + * USB bus with the core and calls the hc_driver->start() function. It returns
46721 + * a negative error on failure.
46723 +int hcd_init(dwc_bus_dev_t *_dev)
46725 + struct usb_hcd *hcd = NULL;
46726 + dwc_otg_hcd_t *dwc_otg_hcd = NULL;
46727 + dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
46731 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT otg_dev=%p\n", otg_dev);
46733 + /* Set device flags indicating whether the HCD supports DMA. */
46734 + if (dwc_otg_is_dma_enable(otg_dev->core_if))
46735 + dmamask = DMA_BIT_MASK(32);
46739 +#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)
46740 + dma_set_mask(&_dev->dev, dmamask);
46741 + dma_set_coherent_mask(&_dev->dev, dmamask);
46742 +#elif defined(PCI_INTERFACE)
46743 + pci_set_dma_mask(_dev, dmamask);
46744 + pci_set_consistent_dma_mask(_dev, dmamask);
46748 + * Allocate memory for the base HCD plus the DWC OTG HCD.
46749 + * Initialize the base HCD.
46751 + hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, dev_name(&_dev->dev));
46753 +// hcd->uses_new_polling = 1;
46754 +// hcd->poll_rh = 0;
46756 + retval = -ENOMEM;
46760 + hcd->regs = otg_dev->os_dep.base;
46763 + /* Initialize the DWC OTG HCD. */
46764 + dwc_otg_hcd = dwc_otg_hcd_alloc_hcd();
46765 + if (!dwc_otg_hcd) {
46768 + ((struct wrapper_priv_data *)(hcd->hcd_priv))->dwc_otg_hcd =
46770 + otg_dev->hcd = dwc_otg_hcd;
46771 + otg_dev->hcd->otg_dev = otg_dev;
46773 +#ifdef CONFIG_ARM64
46774 + if (dwc_otg_hcd_init(dwc_otg_hcd, otg_dev->core_if))
46778 + hcd_init_fiq(otg_dev);
46780 + if (dwc_otg_hcd_init(dwc_otg_hcd, otg_dev->core_if)) {
46784 + if (fiq_enable) {
46785 + if (num_online_cpus() > 1) {
46787 + * bcm2709: can run the FIQ on a separate core to IRQs.
46788 + * Ensure driver state is visible to other cores before setting up the FIQ.
46791 + smp_call_function_single(1, hcd_init_fiq, otg_dev, 1);
46793 + smp_call_function_single(0, hcd_init_fiq, otg_dev, 1);
46798 + hcd->self.otg_port = dwc_otg_hcd_otg_port(dwc_otg_hcd);
46799 + /* Don't support SG list at this point */
46800 + hcd->self.sg_tablesize = 0;
46802 + * Finish generic HCD initialization and start the HCD. This function
46803 + * allocates the DMA buffer pool, registers the USB bus, requests the
46804 + * IRQ line, and calls hcd_start method.
46806 + retval = usb_add_hcd(hcd, otg_dev->os_dep.irq_num, IRQF_SHARED);
46807 + if (retval < 0) {
46811 + dwc_otg_hcd_set_priv_data(dwc_otg_hcd, hcd);
46815 + usb_put_hcd(hcd);
46821 + * Removes the HCD.
46822 + * Frees memory and resources associated with the HCD and deregisters the bus.
46824 +void hcd_remove(dwc_bus_dev_t *_dev)
46826 + dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
46827 + dwc_otg_hcd_t *dwc_otg_hcd;
46828 + struct usb_hcd *hcd;
46830 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE otg_dev=%p\n", otg_dev);
46833 + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
46837 + dwc_otg_hcd = otg_dev->hcd;
46839 + if (!dwc_otg_hcd) {
46840 + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
46844 + hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
46847 + DWC_DEBUGPL(DBG_ANY,
46848 + "%s: dwc_otg_hcd_to_hcd(dwc_otg_hcd) NULL!\n",
46852 + usb_remove_hcd(hcd);
46853 + dwc_otg_hcd_set_priv_data(dwc_otg_hcd, NULL);
46854 + dwc_otg_hcd_remove(dwc_otg_hcd);
46855 + usb_put_hcd(hcd);
46858 +/* =========================================================================
46859 + * Linux HC Driver Functions
46860 + * ========================================================================= */
46862 +/** Initializes the DWC_otg controller and its root hub and prepares it for host
46863 + * mode operation. Activates the root port. Returns 0 on success and a negative
46864 + * error code on failure. */
46865 +int hcd_start(struct usb_hcd *hcd)
46867 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
46868 + struct usb_bus *bus;
46870 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
46871 + bus = hcd_to_bus(hcd);
46873 + hcd->state = HC_STATE_RUNNING;
46874 + if (dwc_otg_hcd_start(dwc_otg_hcd, &hcd_fops)) {
46878 + /* Initialize and connect root hub if one is not already attached */
46879 + if (bus->root_hub) {
46880 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n");
46881 + /* Inform the HUB driver to resume. */
46882 + usb_hcd_resume_root_hub(hcd);
46889 + * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
46892 +void hcd_stop(struct usb_hcd *hcd)
46894 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
46896 + dwc_otg_hcd_stop(dwc_otg_hcd);
46899 +/** Returns the current frame number. */
46900 +static int get_frame_number(struct usb_hcd *hcd)
46902 + hprt0_data_t hprt0;
46903 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
46904 + hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
46905 + if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
46906 + return dwc_otg_hcd_get_frame_number(dwc_otg_hcd) >> 3;
46908 + return dwc_otg_hcd_get_frame_number(dwc_otg_hcd);
46912 +static void dump_urb_info(struct urb *urb, char *fn_name)
46914 + DWC_PRINTF("%s, urb %p\n", fn_name, urb);
46915 + DWC_PRINTF(" Device address: %d\n", usb_pipedevice(urb->pipe));
46916 + DWC_PRINTF(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
46917 + (usb_pipein(urb->pipe) ? "IN" : "OUT"));
46918 + DWC_PRINTF(" Endpoint type: %s\n", ( {
46920 + switch (usb_pipetype(urb->pipe)) {
46921 +case PIPE_CONTROL:
46922 +pipetype = "CONTROL"; break; case PIPE_BULK:
46923 +pipetype = "BULK"; break; case PIPE_INTERRUPT:
46924 +pipetype = "INTERRUPT"; break; case PIPE_ISOCHRONOUS:
46925 +pipetype = "ISOCHRONOUS"; break; default:
46926 + pipetype = "UNKNOWN"; break;};
46929 + DWC_PRINTF(" Speed: %s\n", ( {
46930 + char *speed; switch (urb->dev->speed) {
46931 +case USB_SPEED_HIGH:
46932 +speed = "HIGH"; break; case USB_SPEED_FULL:
46933 +speed = "FULL"; break; case USB_SPEED_LOW:
46934 +speed = "LOW"; break; default:
46935 + speed = "UNKNOWN"; break;};
46938 + DWC_PRINTF(" Max packet size: %d\n",
46939 + usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
46940 + DWC_PRINTF(" Data buffer length: %d\n", urb->transfer_buffer_length);
46941 + DWC_PRINTF(" Transfer buffer: %p, Transfer DMA: %p\n",
46942 + urb->transfer_buffer, (void *)urb->transfer_dma);
46943 + DWC_PRINTF(" Setup buffer: %p, Setup DMA: %p\n",
46944 + urb->setup_packet, (void *)urb->setup_dma);
46945 + DWC_PRINTF(" Interval: %d\n", urb->interval);
46946 + if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
46948 + for (i = 0; i < urb->number_of_packets; i++) {
46949 + DWC_PRINTF(" ISO Desc %d:\n", i);
46950 + DWC_PRINTF(" offset: %d, length %d\n",
46951 + urb->iso_frame_desc[i].offset,
46952 + urb->iso_frame_desc[i].length);
46958 +/** Starts processing a USB transfer request specified by a USB Request Block
46959 + * (URB). mem_flags indicates the type of memory allocation to use while
46960 + * processing this URB. */
46961 +static int dwc_otg_urb_enqueue(struct usb_hcd *hcd,
46962 + struct urb *urb, gfp_t mem_flags)
46965 + struct usb_host_endpoint *ep = urb->ep;
46966 + dwc_irqflags_t irqflags;
46967 + void **ref_ep_hcpriv = &ep->hcpriv;
46968 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
46969 + dwc_otg_hcd_urb_t *dwc_otg_urb;
46971 + int alloc_bandwidth = 0;
46972 + uint8_t ep_type = 0;
46973 + uint32_t flags = 0;
46977 + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
46978 + dump_urb_info(urb, "dwc_otg_urb_enqueue");
46982 + if (!urb->transfer_buffer && urb->transfer_buffer_length)
46985 + if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
46986 + || (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) {
46987 + if (!dwc_otg_hcd_is_bandwidth_allocated
46988 + (dwc_otg_hcd, ref_ep_hcpriv)) {
46989 + alloc_bandwidth = 1;
46993 + switch (usb_pipetype(urb->pipe)) {
46994 + case PIPE_CONTROL:
46995 + ep_type = USB_ENDPOINT_XFER_CONTROL;
46997 + case PIPE_ISOCHRONOUS:
46998 + ep_type = USB_ENDPOINT_XFER_ISOC;
47001 + ep_type = USB_ENDPOINT_XFER_BULK;
47003 + case PIPE_INTERRUPT:
47004 + ep_type = USB_ENDPOINT_XFER_INT;
47007 + DWC_WARN("Wrong EP type - %d\n", usb_pipetype(urb->pipe));
47010 + /* # of packets is often 0 - do we really need to call this then? */
47011 + dwc_otg_urb = dwc_otg_hcd_urb_alloc(dwc_otg_hcd,
47012 + urb->number_of_packets,
47013 + mem_flags == GFP_ATOMIC ? 1 : 0);
47015 + if(dwc_otg_urb == NULL)
47018 + if (!dwc_otg_urb && urb->number_of_packets)
47021 + dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_urb, usb_pipedevice(urb->pipe),
47022 + usb_pipeendpoint(urb->pipe), ep_type,
47023 + usb_pipein(urb->pipe),
47024 + usb_maxpacket(urb->dev, urb->pipe,
47025 + !(usb_pipein(urb->pipe))));
47027 + buf = urb->transfer_buffer;
47028 + if (hcd_uses_dma(hcd) && !buf && urb->transfer_buffer_length) {
47030 + * Calculate virtual address from physical address,
47031 + * because some class driver may not fill transfer_buffer.
47032 + * In Buffer DMA mode virual address is used,
47033 + * when handling non DWORD aligned buffers.
47035 + buf = (void *)__bus_to_virt((unsigned long)urb->transfer_dma);
47036 + dev_warn_once(&urb->dev->dev,
47037 + "USB transfer_buffer was NULL, will use __bus_to_virt(%pad)=%p\n",
47038 + &urb->transfer_dma, buf);
47041 + if (!(urb->transfer_flags & URB_NO_INTERRUPT))
47042 + flags |= URB_GIVEBACK_ASAP;
47043 + if (urb->transfer_flags & URB_ZERO_PACKET)
47044 + flags |= URB_SEND_ZERO_PACKET;
47046 + dwc_otg_hcd_urb_set_params(dwc_otg_urb, urb, buf,
47047 + urb->transfer_dma,
47048 + urb->transfer_buffer_length,
47049 + urb->setup_packet,
47050 + urb->setup_dma, flags, urb->interval);
47052 + for (i = 0; i < urb->number_of_packets; ++i) {
47053 + dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_urb, i,
47055 + iso_frame_desc[i].offset,
47057 + iso_frame_desc[i].length);
47060 + DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &irqflags);
47061 + urb->hcpriv = dwc_otg_urb;
47062 +#if USB_URB_EP_LINKING
47063 + retval = usb_hcd_link_urb_to_ep(hcd, urb);
47067 + retval = dwc_otg_hcd_urb_enqueue(dwc_otg_hcd, dwc_otg_urb,
47068 + /*(dwc_otg_qh_t **)*/
47069 + ref_ep_hcpriv, 1);
47070 + if (0 == retval) {
47071 + if (alloc_bandwidth) {
47072 + allocate_bus_bandwidth(hcd,
47073 + dwc_otg_hcd_get_ep_bandwidth(
47074 + dwc_otg_hcd, *ref_ep_hcpriv),
47078 + DWC_DEBUGPL(DBG_HCD, "DWC OTG dwc_otg_hcd_urb_enqueue failed rc %d\n", retval);
47079 +#if USB_URB_EP_LINKING
47080 + usb_hcd_unlink_urb_from_ep(hcd, urb);
47082 + DWC_FREE(dwc_otg_urb);
47083 + urb->hcpriv = NULL;
47084 + if (retval == -DWC_E_NO_DEVICE)
47085 + retval = -ENODEV;
47088 +#if USB_URB_EP_LINKING
47091 + DWC_FREE(dwc_otg_urb);
47092 + urb->hcpriv = NULL;
47095 + DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, irqflags);
47099 +/** Aborts/cancels a USB transfer request. Always returns 0 to indicate
47101 +static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
47103 + dwc_irqflags_t flags;
47104 + dwc_otg_hcd_t *dwc_otg_hcd;
47107 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
47109 + dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
47112 + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
47113 + dump_urb_info(urb, "dwc_otg_urb_dequeue");
47117 + DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
47118 + rc = usb_hcd_check_unlink_urb(hcd, urb, status);
47120 + if(urb->hcpriv != NULL) {
47121 + dwc_otg_hcd_urb_dequeue(dwc_otg_hcd,
47122 + (dwc_otg_hcd_urb_t *)urb->hcpriv);
47124 + DWC_FREE(urb->hcpriv);
47125 + urb->hcpriv = NULL;
47130 + /* Higher layer software sets URB status. */
47131 +#if USB_URB_EP_LINKING
47132 + usb_hcd_unlink_urb_from_ep(hcd, urb);
47134 + DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
47137 + usb_hcd_giveback_urb(hcd, urb, status);
47138 + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
47139 + DWC_PRINTF("Called usb_hcd_giveback_urb() \n");
47140 + DWC_PRINTF(" 1urb->status = %d\n", urb->status);
47142 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue OK\n");
47144 + DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
47145 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue failed - rc %d\n",
47152 +/* Frees resources in the DWC_otg controller related to a given endpoint. Also
47153 + * clears state in the HCD related to the endpoint. Any URBs for the endpoint
47154 + * must already be dequeued. */
47155 +static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
47157 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
47159 + DWC_DEBUGPL(DBG_HCD,
47160 + "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "
47161 + "endpoint=%d\n", ep->desc.bEndpointAddress,
47162 + dwc_ep_addr_to_endpoint(ep->desc.bEndpointAddress));
47163 + dwc_otg_hcd_endpoint_disable(dwc_otg_hcd, ep->hcpriv, 250);
47164 + ep->hcpriv = NULL;
47167 +/* Resets endpoint specific parameter values, in current version used to reset
47168 + * the data toggle(as a WA). This function can be called from usb_clear_halt routine */
47169 +static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
47171 + dwc_irqflags_t flags;
47172 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
47174 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP RESET: Endpoint Num=0x%02d\n", epnum);
47176 + DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
47177 + if (ep->hcpriv) {
47178 + dwc_otg_hcd_endpoint_reset(dwc_otg_hcd, ep->hcpriv);
47180 + DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
47183 +/** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
47184 + * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
47187 + * This function is called by the USB core when an interrupt occurs */
47188 +static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd)
47190 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
47191 + int32_t retval = dwc_otg_hcd_handle_intr(dwc_otg_hcd);
47192 + if (retval != 0) {
47193 + S3C2410X_CLEAR_EINTPEND();
47195 + return IRQ_RETVAL(retval);
47198 +/** Creates Status Change bitmap for the root hub and root port. The bitmap is
47199 + * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
47200 + * is the status change indicator for the single root port. Returns 1 if either
47201 + * change indicator is 1, otherwise returns 0. */
47202 +int hub_status_data(struct usb_hcd *hcd, char *buf)
47204 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
47207 + buf[0] |= (dwc_otg_hcd_is_status_changed(dwc_otg_hcd, 1)) << 1;
47209 + return (buf[0] != 0);
47212 +/** Handles hub class-specific requests. */
47213 +int hub_control(struct usb_hcd *hcd,
47214 + u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength)
47218 + retval = dwc_otg_hcd_hub_control(hcd_to_dwc_otg_hcd(hcd),
47219 + typeReq, wValue, wIndex, buf, wLength);
47221 + switch (retval) {
47222 + case -DWC_E_INVALID:
47223 + retval = -EINVAL;
47230 +#endif /* DWC_DEVICE_ONLY */
47232 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c
47234 +/* ==========================================================================
47235 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_queue.c $
47236 + * $Revision: #44 $
47237 + * $Date: 2011/10/26 $
47238 + * $Change: 1873028 $
47240 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
47241 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
47242 + * otherwise expressly agreed to in writing between Synopsys and you.
47244 + * The Software IS NOT an item of Licensed Software or Licensed Product under
47245 + * any End User Software License Agreement or Agreement for Licensed Product
47246 + * with Synopsys or any supplement thereto. You are permitted to use and
47247 + * redistribute this Software in source and binary forms, with or without
47248 + * modification, provided that redistributions of source code must retain this
47249 + * notice. You may not view, use, disclose, copy or distribute this file or
47250 + * any information contained herein except pursuant to this license grant from
47251 + * Synopsys. If you do not agree with this notice, including the disclaimer
47252 + * below, then you are not authorized to use the Software.
47254 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
47255 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
47256 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
47257 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
47258 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
47259 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
47260 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
47261 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
47262 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
47263 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
47265 + * ========================================================================== */
47266 +#ifndef DWC_DEVICE_ONLY
47271 + * This file contains the functions to manage Queue Heads and Queue
47272 + * Transfer Descriptors.
47275 +#include "dwc_otg_hcd.h"
47276 +#include "dwc_otg_regs.h"
47278 +extern bool microframe_schedule;
47279 +extern unsigned short int_ep_interval_min;
47282 + * Free each QTD in the QH's QTD-list then free the QH. QH should already be
47283 + * removed from a list. QTD list should already be empty if called from URB
47286 + * @param hcd HCD instance.
47287 + * @param qh The QH to free.
47289 +void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
47291 + dwc_otg_qtd_t *qtd, *qtd_tmp;
47292 + dwc_irqflags_t flags;
47293 + uint32_t buf_size = 0;
47294 + uint8_t *align_buf_virt = NULL;
47295 + dwc_dma_t align_buf_dma;
47296 + struct device *dev = dwc_otg_hcd_to_dev(hcd);
47298 + /* Free each QTD in the QTD list */
47299 + DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
47300 + DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {
47301 + DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry);
47302 + dwc_otg_hcd_qtd_free(qtd);
47305 + if (hcd->core_if->dma_desc_enable) {
47306 + dwc_otg_hcd_qh_free_ddma(hcd, qh);
47307 + } else if (qh->dw_align_buf) {
47308 + if (qh->ep_type == UE_ISOCHRONOUS) {
47311 + buf_size = hcd->core_if->core_params->max_transfer_size;
47313 + align_buf_virt = qh->dw_align_buf;
47314 + align_buf_dma = qh->dw_align_buf_dma;
47318 + DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
47319 + if (align_buf_virt)
47320 + DWC_DMA_FREE(dev, buf_size, align_buf_virt, align_buf_dma);
47324 +#define BitStuffTime(bytecount) ((8 * 7* bytecount) / 6)
47325 +#define HS_HOST_DELAY 5 /* nanoseconds */
47326 +#define FS_LS_HOST_DELAY 1000 /* nanoseconds */
47327 +#define HUB_LS_SETUP 333 /* nanoseconds */
47328 +#define NS_TO_US(ns) ((ns + 500) / 1000)
47329 + /* convert & round nanoseconds to microseconds */
47331 +static uint32_t calc_bus_time(int speed, int is_in, int is_isoc, int bytecount)
47333 + unsigned long retval;
47336 + case USB_SPEED_HIGH:
47339 + ((38 * 8 * 2083) +
47340 + (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +
47344 + ((55 * 8 * 2083) +
47345 + (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +
47349 + case USB_SPEED_FULL:
47352 + (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;
47354 + retval = 7268 + FS_LS_HOST_DELAY + retval;
47356 + retval = 6265 + FS_LS_HOST_DELAY + retval;
47360 + (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;
47361 + retval = 9107 + FS_LS_HOST_DELAY + retval;
47364 + case USB_SPEED_LOW:
47367 + (67667 * (31 + 10 * BitStuffTime(bytecount))) /
47370 + 64060 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
47374 + (66700 * (31 + 10 * BitStuffTime(bytecount))) /
47377 + 64107 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
47382 + DWC_WARN("Unknown device speed\n");
47386 + return NS_TO_US(retval);
47390 + * Initializes a QH structure.
47392 + * @param hcd The HCD state structure for the DWC OTG controller.
47393 + * @param qh The QH to init.
47394 + * @param urb Holds the information about the device/endpoint that we need
47395 + * to initialize the QH.
47397 +#define SCHEDULE_SLOP 10
47398 +void qh_init(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, dwc_otg_hcd_urb_t * urb)
47400 + char *speed, *type;
47402 + uint32_t hub_addr, hub_port;
47403 + hprt0_data_t hprt;
47405 + dwc_memset(qh, 0, sizeof(dwc_otg_qh_t));
47406 + hprt.d32 = DWC_READ_REG32(hcd->core_if->host_if->hprt0);
47408 + /* Initialize QH */
47409 + qh->ep_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
47410 + qh->ep_is_in = dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0;
47412 + qh->data_toggle = DWC_OTG_HC_PID_DATA0;
47413 + qh->maxp = dwc_otg_hcd_get_mps(&urb->pipe_info);
47414 + DWC_CIRCLEQ_INIT(&qh->qtd_list);
47415 + DWC_LIST_INIT(&qh->qh_list_entry);
47416 + qh->channel = NULL;
47418 + /* FS/LS Enpoint on HS Hub
47419 + * NOT virtual root hub */
47420 + dev_speed = hcd->fops->speed(hcd, urb->priv);
47422 + hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &hub_port);
47423 + qh->do_split = 0;
47424 + if (microframe_schedule)
47425 + qh->speed = dev_speed;
47427 + qh->nak_frame = 0xffff;
47429 + if (hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED &&
47430 + dev_speed != USB_SPEED_HIGH) {
47431 + DWC_DEBUGPL(DBG_HCD,
47432 + "QH init: EP %d: TT found at hub addr %d, for port %d\n",
47433 + dwc_otg_hcd_get_ep_num(&urb->pipe_info), hub_addr,
47435 + qh->do_split = 1;
47436 + qh->skip_count = 0;
47439 + if (qh->ep_type == UE_INTERRUPT || qh->ep_type == UE_ISOCHRONOUS) {
47440 + /* Compute scheduling parameters once and save them. */
47442 + /** @todo Account for split transfers in the bus time. */
47444 + dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp);
47447 + calc_bus_time((qh->do_split ? USB_SPEED_HIGH : dev_speed),
47448 + qh->ep_is_in, (qh->ep_type == UE_ISOCHRONOUS),
47450 + /* Start in a slightly future (micro)frame. */
47451 + qh->sched_frame = dwc_frame_num_inc(hcd->frame_number,
47453 + qh->interval = urb->interval;
47455 + if (hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) {
47456 + if (dev_speed == USB_SPEED_LOW ||
47457 + dev_speed == USB_SPEED_FULL) {
47458 + qh->interval *= 8;
47459 + qh->sched_frame |= 0x7;
47460 + qh->start_split_frame = qh->sched_frame;
47461 + } else if (int_ep_interval_min >= 2 &&
47462 + qh->interval < int_ep_interval_min &&
47463 + qh->ep_type == UE_INTERRUPT) {
47464 + qh->interval = int_ep_interval_min;
47469 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
47470 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", qh);
47471 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n",
47472 + dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
47473 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n",
47474 + dwc_otg_hcd_get_ep_num(&urb->pipe_info),
47475 + dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
47476 + switch (dev_speed) {
47477 + case USB_SPEED_LOW:
47478 + qh->dev_speed = DWC_OTG_EP_SPEED_LOW;
47481 + case USB_SPEED_FULL:
47482 + qh->dev_speed = DWC_OTG_EP_SPEED_FULL;
47485 + case USB_SPEED_HIGH:
47486 + qh->dev_speed = DWC_OTG_EP_SPEED_HIGH;
47493 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n", speed);
47495 + switch (qh->ep_type) {
47496 + case UE_ISOCHRONOUS:
47497 + type = "isochronous";
47499 + case UE_INTERRUPT:
47500 + type = "interrupt";
47503 + type = "control";
47513 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n", type);
47516 + if (qh->ep_type == UE_INTERRUPT) {
47517 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
47519 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
47527 + * This function allocates and initializes a QH.
47529 + * @param hcd The HCD state structure for the DWC OTG controller.
47530 + * @param urb Holds the information about the device/endpoint that we need
47531 + * to initialize the QH.
47532 + * @param atomic_alloc Flag to do atomic allocation if needed
47534 + * @return Returns pointer to the newly allocated QH, or NULL on error. */
47535 +dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,
47536 + dwc_otg_hcd_urb_t * urb, int atomic_alloc)
47538 + dwc_otg_qh_t *qh;
47540 + /* Allocate memory */
47541 + /** @todo add memflags argument */
47542 + qh = dwc_otg_hcd_qh_alloc(atomic_alloc);
47543 + if (qh == NULL) {
47544 + DWC_ERROR("qh allocation failed");
47548 + qh_init(hcd, qh, urb);
47550 + if (hcd->core_if->dma_desc_enable
47551 + && (dwc_otg_hcd_qh_init_ddma(hcd, qh) < 0)) {
47552 + dwc_otg_hcd_qh_free(hcd, qh);
47559 +/* microframe_schedule=0 start */
47562 + * Checks that a channel is available for a periodic transfer.
47564 + * @return 0 if successful, negative error code otherise.
47566 +static int periodic_channel_available(dwc_otg_hcd_t * hcd)
47569 + * Currently assuming that there is a dedicated host channnel for each
47570 + * periodic transaction plus at least one host channel for
47571 + * non-periodic transactions.
47574 + int num_channels;
47576 + num_channels = hcd->core_if->core_params->host_channels;
47577 + if ((hcd->periodic_channels + hcd->non_periodic_channels < num_channels)
47578 + && (hcd->periodic_channels < num_channels - 1)) {
47581 + DWC_INFO("%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n",
47582 + __func__, num_channels, hcd->periodic_channels, hcd->non_periodic_channels); //NOTICE
47583 + status = -DWC_E_NO_SPACE;
47590 + * Checks that there is sufficient bandwidth for the specified QH in the
47591 + * periodic schedule. For simplicity, this calculation assumes that all the
47592 + * transfers in the periodic schedule may occur in the same (micro)frame.
47594 + * @param hcd The HCD state structure for the DWC OTG controller.
47595 + * @param qh QH containing periodic bandwidth required.
47597 + * @return 0 if successful, negative error code otherwise.
47599 +static int check_periodic_bandwidth(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
47602 + int16_t max_claimed_usecs;
47606 + if ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) || qh->do_split) {
47608 + * High speed mode.
47609 + * Max periodic usecs is 80% x 125 usec = 100 usec.
47612 + max_claimed_usecs = 100 - qh->usecs;
47615 + * Full speed mode.
47616 + * Max periodic usecs is 90% x 1000 usec = 900 usec.
47618 + max_claimed_usecs = 900 - qh->usecs;
47621 + if (hcd->periodic_usecs > max_claimed_usecs) {
47622 + DWC_INFO("%s: already claimed usecs %d, required usecs %d\n", __func__, hcd->periodic_usecs, qh->usecs); //NOTICE
47623 + status = -DWC_E_NO_SPACE;
47629 +/* microframe_schedule=0 end */
47632 + * Microframe scheduler
47633 + * track the total use in hcd->frame_usecs
47634 + * keep each qh use in qh->frame_usecs
47635 + * when surrendering the qh then donate the time back
47637 +const unsigned short max_uframe_usecs[]={ 100, 100, 100, 100, 100, 100, 30, 0 };
47640 + * called from dwc_otg_hcd.c:dwc_otg_hcd_init
47642 +void init_hcd_usecs(dwc_otg_hcd_t *_hcd)
47645 + if (_hcd->flags.b.port_speed == DWC_HPRT0_PRTSPD_FULL_SPEED) {
47646 + _hcd->frame_usecs[0] = 900;
47647 + for (i = 1; i < 8; i++)
47648 + _hcd->frame_usecs[i] = 0;
47650 + for (i = 0; i < 8; i++)
47651 + _hcd->frame_usecs[i] = max_uframe_usecs[i];
47655 +static int find_single_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
47658 + unsigned short utime;
47664 + utime = _qh->usecs;
47668 + while (done == 0) {
47669 + /* At the start _hcd->frame_usecs[i] = max_uframe_usecs[i]; */
47670 + if (utime <= _hcd->frame_usecs[i]) {
47671 + _hcd->frame_usecs[i] -= utime;
47672 + _qh->frame_usecs[i] += utime;
47689 + * use this for FS apps that can span multiple uframes
47691 +static int find_multi_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
47695 + unsigned short utime;
47699 + unsigned short xtime;
47702 + utime = _qh->usecs;
47707 + while (done == 0) {
47708 + if(_hcd->frame_usecs[i] <= 0) {
47718 + * we need n consecutive slots
47719 + * so use j as a start slot j plus j+1 must be enough time (for now)
47721 + xtime= _hcd->frame_usecs[i];
47722 + for (j = i+1 ; j < 8 ; j++ ) {
47724 + * if we add this frame remaining time to xtime we may
47725 + * be OK, if not we need to test j for a complete frame
47727 + if ((xtime+_hcd->frame_usecs[j]) < utime) {
47728 + if (_hcd->frame_usecs[j] < max_uframe_usecs[j]) {
47734 + if (xtime >= utime) {
47736 + j = 8; /* stop loop with a good value ret */
47739 + /* add the frame time to x time */
47740 + xtime += _hcd->frame_usecs[j];
47741 + /* we must have a fully available next frame or break */
47742 + if ((xtime < utime)
47743 + && (_hcd->frame_usecs[j] == max_uframe_usecs[j])) {
47745 + j = 8; /* stop loop with a bad value ret */
47751 + for (j = i; (t_left>0) && (j < 8); j++ ) {
47752 + t_left -= _hcd->frame_usecs[j];
47753 + if ( t_left <= 0 ) {
47754 + _qh->frame_usecs[j] += _hcd->frame_usecs[j] + t_left;
47755 + _hcd->frame_usecs[j]= -t_left;
47759 + _qh->frame_usecs[j] += _hcd->frame_usecs[j];
47760 + _hcd->frame_usecs[j] = 0;
47774 +static int find_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
47779 + if (_qh->speed == USB_SPEED_HIGH ||
47780 + _hcd->flags.b.port_speed == DWC_HPRT0_PRTSPD_FULL_SPEED) {
47781 + /* if this is a hs transaction we need a full frame - or account for FS usecs */
47782 + ret = find_single_uframe(_hcd, _qh);
47784 + /* if this is a fs transaction we may need a sequence of frames */
47785 + ret = find_multi_uframe(_hcd, _qh);
47791 + * Checks that the max transfer size allowed in a host channel is large enough
47792 + * to handle the maximum data transfer in a single (micro)frame for a periodic
47795 + * @param hcd The HCD state structure for the DWC OTG controller.
47796 + * @param qh QH for a periodic endpoint.
47798 + * @return 0 if successful, negative error code otherwise.
47800 +static int check_max_xfer_size(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
47803 + uint32_t max_xfer_size;
47804 + uint32_t max_channel_xfer_size;
47808 + max_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp);
47809 + max_channel_xfer_size = hcd->core_if->core_params->max_transfer_size;
47811 + if (max_xfer_size > max_channel_xfer_size) {
47812 + DWC_INFO("%s: Periodic xfer length %d > " "max xfer length for channel %d\n",
47813 + __func__, max_xfer_size, max_channel_xfer_size); //NOTICE
47814 + status = -DWC_E_NO_SPACE;
47823 + * Schedules an interrupt or isochronous transfer in the periodic schedule.
47825 + * @param hcd The HCD state structure for the DWC OTG controller.
47826 + * @param qh QH for the periodic transfer. The QH should already contain the
47827 + * scheduling information.
47829 + * @return 0 if successful, negative error code otherwise.
47831 +static int schedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
47835 + if (microframe_schedule) {
47837 + status = find_uframe(hcd, qh);
47839 + if (status == 0) {
47843 + frame = status-1;
47846 + /* Set the new frame up */
47847 + if (frame > -1) {
47848 + qh->sched_frame &= ~0x7;
47849 + qh->sched_frame |= (frame & 7);
47852 + if (status != -1)
47855 + status = periodic_channel_available(hcd);
47857 + DWC_INFO("%s: No host channel available for periodic " "transfer.\n", __func__); //NOTICE
47861 + status = check_periodic_bandwidth(hcd, qh);
47864 + DWC_INFO("%s: Insufficient periodic bandwidth for "
47865 + "periodic transfer.\n", __func__);
47866 + return -DWC_E_NO_SPACE;
47868 + status = check_max_xfer_size(hcd, qh);
47870 + DWC_INFO("%s: Channel max transfer size too small "
47871 + "for periodic transfer.\n", __func__);
47875 + if (hcd->core_if->dma_desc_enable) {
47876 + /* Don't rely on SOF and start in ready schedule */
47877 + DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_ready, &qh->qh_list_entry);
47880 + if(fiq_enable && (DWC_LIST_EMPTY(&hcd->periodic_sched_inactive) || dwc_frame_num_le(qh->sched_frame, hcd->fiq_state->next_sched_frame)))
47882 + hcd->fiq_state->next_sched_frame = qh->sched_frame;
47885 + /* Always start in the inactive schedule. */
47886 + DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_inactive, &qh->qh_list_entry);
47889 + if (!microframe_schedule) {
47890 + /* Reserve the periodic channel. */
47891 + hcd->periodic_channels++;
47894 + /* Update claimed usecs per (micro)frame. */
47895 + hcd->periodic_usecs += qh->usecs;
47902 + * This function adds a QH to either the non periodic or periodic schedule if
47903 + * it is not already in the schedule. If the QH is already in the schedule, no
47904 + * action is taken.
47906 + * @return 0 if successful, negative error code otherwise.
47908 +int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
47911 + gintmsk_data_t intr_mask = {.d32 = 0 };
47913 + if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
47914 + /* QH already in a schedule. */
47918 + /* Add the new QH to the appropriate schedule */
47919 + if (dwc_qh_is_non_per(qh)) {
47920 + /* Always start in the inactive schedule. */
47921 + DWC_LIST_INSERT_TAIL(&hcd->non_periodic_sched_inactive,
47922 + &qh->qh_list_entry);
47923 + //hcd->fiq_state->kick_np_queues = 1;
47925 + status = schedule_periodic(hcd, qh);
47926 + if ( !hcd->periodic_qh_count ) {
47927 + intr_mask.b.sofintr = 1;
47928 + if (fiq_enable) {
47929 + local_fiq_disable();
47930 + fiq_fsm_spin_lock(&hcd->fiq_state->lock);
47931 + DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
47932 + fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
47933 + local_fiq_enable();
47935 + DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
47938 + hcd->periodic_qh_count++;
47945 + * Removes an interrupt or isochronous transfer from the periodic schedule.
47947 + * @param hcd The HCD state structure for the DWC OTG controller.
47948 + * @param qh QH for the periodic transfer.
47950 +static void deschedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
47953 + DWC_LIST_REMOVE_INIT(&qh->qh_list_entry);
47955 + /* Update claimed usecs per (micro)frame. */
47956 + hcd->periodic_usecs -= qh->usecs;
47958 + if (!microframe_schedule) {
47959 + /* Release the periodic channel reservation. */
47960 + hcd->periodic_channels--;
47962 + for (i = 0; i < 8; i++) {
47963 + hcd->frame_usecs[i] += qh->frame_usecs[i];
47964 + qh->frame_usecs[i] = 0;
47970 + * Removes a QH from either the non-periodic or periodic schedule. Memory is
47973 + * @param hcd The HCD state structure.
47974 + * @param qh QH to remove from schedule. */
47975 +void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
47977 + gintmsk_data_t intr_mask = {.d32 = 0 };
47979 + if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
47980 + /* QH is not in a schedule. */
47984 + if (dwc_qh_is_non_per(qh)) {
47985 + if (hcd->non_periodic_qh_ptr == &qh->qh_list_entry) {
47986 + hcd->non_periodic_qh_ptr =
47987 + hcd->non_periodic_qh_ptr->next;
47989 + DWC_LIST_REMOVE_INIT(&qh->qh_list_entry);
47990 + //if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_inactive))
47991 + // hcd->fiq_state->kick_np_queues = 1;
47993 + deschedule_periodic(hcd, qh);
47994 + hcd->periodic_qh_count--;
47995 + if( !hcd->periodic_qh_count && !fiq_fsm_enable ) {
47996 + intr_mask.b.sofintr = 1;
47997 + if (fiq_enable) {
47998 + local_fiq_disable();
47999 + fiq_fsm_spin_lock(&hcd->fiq_state->lock);
48000 + DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
48001 + fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
48002 + local_fiq_enable();
48004 + DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
48011 + * Deactivates a QH. For non-periodic QHs, removes the QH from the active
48012 + * non-periodic schedule. The QH is added to the inactive non-periodic
48013 + * schedule if any QTDs are still attached to the QH.
48015 + * For periodic QHs, the QH is removed from the periodic queued schedule. If
48016 + * there are any QTDs still attached to the QH, the QH is added to either the
48017 + * periodic inactive schedule or the periodic ready schedule and its next
48018 + * scheduled frame is calculated. The QH is placed in the ready schedule if
48019 + * the scheduled frame has been reached already. Otherwise it's placed in the
48020 + * inactive schedule. If there are no QTDs attached to the QH, the QH is
48021 + * completely removed from the periodic schedule.
48023 +void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
48024 + int sched_next_periodic_split)
48026 + if (dwc_qh_is_non_per(qh)) {
48027 + dwc_otg_hcd_qh_remove(hcd, qh);
48028 + if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
48029 + /* Add back to inactive non-periodic schedule. */
48030 + dwc_otg_hcd_qh_add(hcd, qh);
48031 + //hcd->fiq_state->kick_np_queues = 1;
48033 + if(nak_holdoff && qh->do_split) {
48034 + qh->nak_frame = 0xFFFF;
48038 + uint16_t frame_number = dwc_otg_hcd_get_frame_number(hcd);
48040 + if (qh->do_split) {
48041 + /* Schedule the next continuing periodic split transfer */
48042 + if (sched_next_periodic_split) {
48044 + qh->sched_frame = frame_number;
48046 + if (dwc_frame_num_le(frame_number,
48047 + dwc_frame_num_inc
48048 + (qh->start_split_frame,
48051 + * Allow one frame to elapse after start
48052 + * split microframe before scheduling
48053 + * complete split, but DONT if we are
48054 + * doing the next start split in the
48055 + * same frame for an ISOC out.
48057 + if ((qh->ep_type != UE_ISOCHRONOUS) ||
48058 + (qh->ep_is_in != 0)) {
48059 + qh->sched_frame =
48060 + dwc_frame_num_inc(qh->sched_frame, 1);
48064 + qh->sched_frame =
48065 + dwc_frame_num_inc(qh->start_split_frame,
48067 + if (dwc_frame_num_le
48068 + (qh->sched_frame, frame_number)) {
48069 + qh->sched_frame = frame_number;
48071 + qh->sched_frame |= 0x7;
48072 + qh->start_split_frame = qh->sched_frame;
48075 + qh->sched_frame =
48076 + dwc_frame_num_inc(qh->sched_frame, qh->interval);
48077 + if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
48078 + qh->sched_frame = frame_number;
48082 + if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
48083 + dwc_otg_hcd_qh_remove(hcd, qh);
48086 + * Remove from periodic_sched_queued and move to
48087 + * appropriate queue.
48089 + if ((microframe_schedule && dwc_frame_num_le(qh->sched_frame, frame_number)) ||
48090 + (!microframe_schedule && qh->sched_frame == frame_number)) {
48091 + DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
48092 + &qh->qh_list_entry);
48094 + if(fiq_enable && !dwc_frame_num_le(hcd->fiq_state->next_sched_frame, qh->sched_frame))
48096 + hcd->fiq_state->next_sched_frame = qh->sched_frame;
48099 + DWC_LIST_MOVE_HEAD
48100 + (&hcd->periodic_sched_inactive,
48101 + &qh->qh_list_entry);
48108 + * This function allocates and initializes a QTD.
48110 + * @param urb The URB to create a QTD from. Each URB-QTD pair will end up
48111 + * pointing to each other so each pair should have a unique correlation.
48112 + * @param atomic_alloc Flag to do atomic alloc if needed
48114 + * @return Returns pointer to the newly allocated QTD, or NULL on error. */
48115 +dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb, int atomic_alloc)
48117 + dwc_otg_qtd_t *qtd;
48119 + qtd = dwc_otg_hcd_qtd_alloc(atomic_alloc);
48120 + if (qtd == NULL) {
48124 + dwc_otg_hcd_qtd_init(qtd, urb);
48129 + * Initializes a QTD structure.
48131 + * @param qtd The QTD to initialize.
48132 + * @param urb The URB to use for initialization. */
48133 +void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb)
48135 + dwc_memset(qtd, 0, sizeof(dwc_otg_qtd_t));
48137 + if (dwc_otg_hcd_get_pipe_type(&urb->pipe_info) == UE_CONTROL) {
48139 + * The only time the QTD data toggle is used is on the data
48140 + * phase of control transfers. This phase always starts with
48143 + qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
48144 + qtd->control_phase = DWC_OTG_CONTROL_SETUP;
48147 + /* start split */
48148 + qtd->complete_split = 0;
48149 + qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
48150 + qtd->isoc_split_offset = 0;
48151 + qtd->in_process = 0;
48153 + /* Store the qtd ptr in the urb to reference what QTD. */
48159 + * This function adds a QTD to the QTD-list of a QH. It will find the correct
48160 + * QH to place the QTD into. If it does not find a QH, then it will create a
48161 + * new QH. If the QH to which the QTD is added is not currently scheduled, it
48162 + * is placed into the proper schedule based on its EP type.
48163 + * HCD lock must be held and interrupts must be disabled on entry
48165 + * @param[in] qtd The QTD to add
48166 + * @param[in] hcd The DWC HCD structure
48167 + * @param[out] qh out parameter to return queue head
48168 + * @param atomic_alloc Flag to do atomic alloc if needed
48170 + * @return 0 if successful, negative error code otherwise.
48172 +int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd,
48173 + dwc_otg_hcd_t * hcd, dwc_otg_qh_t ** qh, int atomic_alloc)
48176 + dwc_otg_hcd_urb_t *urb = qtd->urb;
48179 + * Get the QH which holds the QTD-list to insert to. Create QH if it
48182 + if (*qh == NULL) {
48183 + *qh = dwc_otg_hcd_qh_create(hcd, urb, atomic_alloc);
48184 + if (*qh == NULL) {
48185 + retval = -DWC_E_NO_MEMORY;
48189 + hcd->fiq_state->kick_np_queues = 1;
48192 + retval = dwc_otg_hcd_qh_add(hcd, *qh);
48193 + if (retval == 0) {
48194 + DWC_CIRCLEQ_INSERT_TAIL(&((*qh)->qtd_list), qtd,
48203 +#endif /* DWC_DEVICE_ONLY */
48205 +++ b/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h
48207 +#ifndef _DWC_OS_DEP_H_
48208 +#define _DWC_OS_DEP_H_
48213 + * This file contains OS dependent structures.
48217 +#include <linux/kernel.h>
48218 +#include <linux/module.h>
48219 +#include <linux/moduleparam.h>
48220 +#include <linux/init.h>
48221 +#include <linux/device.h>
48222 +#include <linux/errno.h>
48223 +#include <linux/types.h>
48224 +#include <linux/slab.h>
48225 +#include <linux/list.h>
48226 +#include <linux/interrupt.h>
48227 +#include <linux/ctype.h>
48228 +#include <linux/string.h>
48229 +#include <linux/dma-mapping.h>
48230 +#include <linux/jiffies.h>
48231 +#include <linux/delay.h>
48232 +#include <linux/timer.h>
48233 +#include <linux/workqueue.h>
48234 +#include <linux/stat.h>
48235 +#include <linux/pci.h>
48237 +#include <linux/version.h>
48239 +# include <linux/irq.h>
48241 +# include <linux/usb/ch9.h>
48243 +# include <linux/usb/gadget.h>
48245 +#ifdef PCI_INTERFACE
48246 +# include <asm/io.h>
48249 +#ifdef LM_INTERFACE
48250 +# include <asm/unaligned.h>
48251 +# include <asm/sizes.h>
48252 +# include <asm/param.h>
48253 +# include <asm/io.h>
48254 +/* in 2.6.31, at least, we seem to have lost the generic LM infrastructure -
48255 + here we assume that the machine architecture provides definitions
48256 + in its own header
48258 +# include <mach/lm.h>
48259 +# include <mach/hardware.h>
48262 +#ifdef PLATFORM_INTERFACE
48263 +#include <linux/platform_device.h>
48265 +#include <asm/mach/map.h>
48269 +/** The OS page size */
48270 +#define DWC_OS_PAGE_SIZE PAGE_SIZE
48272 +typedef struct os_dependent {
48273 + /** Base address returned from ioremap() */
48276 + /** Register offset for Diagnostic API */
48277 + uint32_t reg_offset;
48279 + /** Base address for MPHI peripheral */
48282 + /** mphi_base actually points to the SWIRQ block */
48285 + /** IRQ number (<0 if not valid) */
48288 + /** FIQ number (<0 if not valid) */
48291 +#ifdef LM_INTERFACE
48292 + struct lm_device *lmdev;
48293 +#elif defined(PCI_INTERFACE)
48294 + struct pci_dev *pcidev;
48296 + /** Start address of a PCI region */
48297 + resource_size_t rsrc_start;
48299 + /** Length address of a PCI region */
48300 + resource_size_t rsrc_len;
48301 +#elif defined(PLATFORM_INTERFACE)
48302 + struct platform_device *platformdev;
48307 +#ifdef __cplusplus
48313 +/* Type for the our device on the chosen bus */
48314 +#if defined(LM_INTERFACE)
48315 +typedef struct lm_device dwc_bus_dev_t;
48316 +#elif defined(PCI_INTERFACE)
48317 +typedef struct pci_dev dwc_bus_dev_t;
48318 +#elif defined(PLATFORM_INTERFACE)
48319 +typedef struct platform_device dwc_bus_dev_t;
48322 +/* Helper macro to retrieve drvdata from the device on the chosen bus */
48323 +#if defined(LM_INTERFACE)
48324 +#define DWC_OTG_BUSDRVDATA(_dev) lm_get_drvdata(_dev)
48325 +#elif defined(PCI_INTERFACE)
48326 +#define DWC_OTG_BUSDRVDATA(_dev) pci_get_drvdata(_dev)
48327 +#elif defined(PLATFORM_INTERFACE)
48328 +#define DWC_OTG_BUSDRVDATA(_dev) platform_get_drvdata(_dev)
48332 + * Helper macro returning the otg_device structure of a given struct device
48334 + * c.f. static dwc_otg_device_t *dwc_otg_drvdev(struct device *_dev)
48336 +#ifdef LM_INTERFACE
48337 +#define DWC_OTG_GETDRVDEV(_var, _dev) do { \
48338 + struct lm_device *lm_dev = \
48339 + container_of(_dev, struct lm_device, dev); \
48340 + _var = lm_get_drvdata(lm_dev); \
48343 +#elif defined(PCI_INTERFACE)
48344 +#define DWC_OTG_GETDRVDEV(_var, _dev) do { \
48345 + _var = dev_get_drvdata(_dev); \
48348 +#elif defined(PLATFORM_INTERFACE)
48349 +#define DWC_OTG_GETDRVDEV(_var, _dev) do { \
48350 + struct platform_device *platform_dev = \
48351 + container_of(_dev, struct platform_device, dev); \
48352 + _var = platform_get_drvdata(platform_dev); \
48358 + * Helper macro returning the struct dev of the given struct os_dependent
48360 + * c.f. static struct device *dwc_otg_getdev(struct os_dependent *osdep)
48362 +#ifdef LM_INTERFACE
48363 +#define DWC_OTG_OS_GETDEV(_osdep) \
48364 + ((_osdep).lmdev == NULL? NULL: &(_osdep).lmdev->dev)
48365 +#elif defined(PCI_INTERFACE)
48366 +#define DWC_OTG_OS_GETDEV(_osdep) \
48367 + ((_osdep).pci_dev == NULL? NULL: &(_osdep).pci_dev->dev)
48368 +#elif defined(PLATFORM_INTERFACE)
48369 +#define DWC_OTG_OS_GETDEV(_osdep) \
48370 + ((_osdep).platformdev == NULL? NULL: &(_osdep).platformdev->dev)
48376 +#endif /* _DWC_OS_DEP_H_ */
48378 +++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd.c
48380 +/* ==========================================================================
48381 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $
48382 + * $Revision: #101 $
48383 + * $Date: 2012/08/10 $
48384 + * $Change: 2047372 $
48386 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
48387 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
48388 + * otherwise expressly agreed to in writing between Synopsys and you.
48390 + * The Software IS NOT an item of Licensed Software or Licensed Product under
48391 + * any End User Software License Agreement or Agreement for Licensed Product
48392 + * with Synopsys or any supplement thereto. You are permitted to use and
48393 + * redistribute this Software in source and binary forms, with or without
48394 + * modification, provided that redistributions of source code must retain this
48395 + * notice. You may not view, use, disclose, copy or distribute this file or
48396 + * any information contained herein except pursuant to this license grant from
48397 + * Synopsys. If you do not agree with this notice, including the disclaimer
48398 + * below, then you are not authorized to use the Software.
48400 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
48401 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
48402 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
48403 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
48404 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
48405 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
48406 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
48407 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48408 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
48409 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
48411 + * ========================================================================== */
48412 +#ifndef DWC_HOST_ONLY
48415 + * This file implements PCD Core. All code in this file is portable and doesn't
48416 + * use any OS specific functions.
48417 + * PCD Core provides Interface, defined in <code><dwc_otg_pcd_if.h></code>
48418 + * header file, which can be used to implement OS specific PCD interface.
48420 + * An important function of the PCD is managing interrupts generated
48421 + * by the DWC_otg controller. The implementation of the DWC_otg device
48422 + * mode interrupt service routines is in dwc_otg_pcd_intr.c.
48424 + * @todo Add Device Mode test modes (Test J mode, Test K mode, etc).
48425 + * @todo Does it work when the request size is greater than DEPTSIZ
48430 +#include "dwc_otg_pcd.h"
48432 +#ifdef DWC_UTE_CFI
48433 +#include "dwc_otg_cfi.h"
48435 +extern int init_cfi(cfiobject_t * cfiobj);
48439 + * Choose endpoint from ep arrays using usb_ep structure.
48441 +static dwc_otg_pcd_ep_t *get_ep_from_handle(dwc_otg_pcd_t * pcd, void *handle)
48444 + if (pcd->ep0.priv == handle) {
48445 + return &pcd->ep0;
48447 + for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) {
48448 + if (pcd->in_ep[i].priv == handle)
48449 + return &pcd->in_ep[i];
48450 + if (pcd->out_ep[i].priv == handle)
48451 + return &pcd->out_ep[i];
48458 + * This function completes a request. It call's the request call back.
48460 +void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req,
48463 + unsigned stopped = ep->stopped;
48465 + DWC_DEBUGPL(DBG_PCDV, "%s(ep %p req %p)\n", __func__, ep, req);
48466 + DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry);
48468 + /* don't modify queue heads during completion callback */
48470 + /* spin_unlock/spin_lock now done in fops->complete() */
48471 + ep->pcd->fops->complete(ep->pcd, ep->priv, req->priv, status,
48474 + if (ep->pcd->request_pending > 0) {
48475 + --ep->pcd->request_pending;
48478 + ep->stopped = stopped;
48483 + * This function terminates all the requsts in the EP request queue.
48485 +void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep)
48487 + dwc_otg_pcd_request_t *req;
48491 + /* called with irqs blocked?? */
48492 + while (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
48493 + req = DWC_CIRCLEQ_FIRST(&ep->queue);
48494 + dwc_otg_request_done(ep, req, -DWC_E_SHUTDOWN);
48498 +void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
48499 + const struct dwc_otg_pcd_function_ops *fops)
48501 + pcd->fops = fops;
48505 + * PCD Callback function for initializing the PCD when switching to
48508 + * @param p void pointer to the <code>dwc_otg_pcd_t</code>
48510 +static int32_t dwc_otg_pcd_start_cb(void *p)
48512 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
48513 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
48516 + * Initialized the Core for Device mode.
48518 + if (dwc_otg_is_device_mode(core_if)) {
48519 + dwc_otg_core_dev_init(core_if);
48520 + /* Set core_if's lock pointer to the pcd->lock */
48521 + core_if->lock = pcd->lock;
48526 +/** CFI-specific buffer allocation function for EP */
48527 +#ifdef DWC_UTE_CFI
48528 +uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,
48529 + size_t buflen, int flags)
48531 + dwc_otg_pcd_ep_t *ep;
48532 + ep = get_ep_from_handle(pcd, pep);
48534 + DWC_WARN("bad ep\n");
48535 + return -DWC_E_INVALID;
48538 + return pcd->cfi->ops.ep_alloc_buf(pcd->cfi, pcd, ep, addr, buflen,
48542 +uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,
48543 + size_t buflen, int flags);
48547 + * PCD Callback function for notifying the PCD when resuming from
48550 + * @param p void pointer to the <code>dwc_otg_pcd_t</code>
48552 +static int32_t dwc_otg_pcd_resume_cb(void *p)
48554 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
48556 + if (pcd->fops->resume) {
48557 + pcd->fops->resume(pcd);
48560 + /* Stop the SRP timeout timer. */
48561 + if ((GET_CORE_IF(pcd)->core_params->phy_type != DWC_PHY_TYPE_PARAM_FS)
48562 + || (!GET_CORE_IF(pcd)->core_params->i2c_enable)) {
48563 + if (GET_CORE_IF(pcd)->srp_timer_started) {
48564 + GET_CORE_IF(pcd)->srp_timer_started = 0;
48565 + DWC_TIMER_CANCEL(GET_CORE_IF(pcd)->srp_timer);
48572 + * PCD Callback function for notifying the PCD device is suspended.
48574 + * @param p void pointer to the <code>dwc_otg_pcd_t</code>
48576 +static int32_t dwc_otg_pcd_suspend_cb(void *p)
48578 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
48580 + if (pcd->fops->suspend) {
48581 + DWC_SPINUNLOCK(pcd->lock);
48582 + pcd->fops->suspend(pcd);
48583 + DWC_SPINLOCK(pcd->lock);
48590 + * PCD Callback function for stopping the PCD when switching to Host
48593 + * @param p void pointer to the <code>dwc_otg_pcd_t</code>
48595 +static int32_t dwc_otg_pcd_stop_cb(void *p)
48597 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
48598 + extern void dwc_otg_pcd_stop(dwc_otg_pcd_t * _pcd);
48600 + dwc_otg_pcd_stop(pcd);
48605 + * PCD Callback structure for handling mode switching.
48607 +static dwc_otg_cil_callbacks_t pcd_callbacks = {
48608 + .start = dwc_otg_pcd_start_cb,
48609 + .stop = dwc_otg_pcd_stop_cb,
48610 + .suspend = dwc_otg_pcd_suspend_cb,
48611 + .resume_wakeup = dwc_otg_pcd_resume_cb,
48612 + .p = 0, /* Set at registration */
48616 + * This function allocates a DMA Descriptor chain for the Endpoint
48617 + * buffer to be used for a transfer to/from the specified endpoint.
48619 +dwc_otg_dev_dma_desc_t *dwc_otg_ep_alloc_desc_chain(struct device *dev,
48620 + dwc_dma_t * dma_desc_addr,
48623 + return DWC_DMA_ALLOC_ATOMIC(dev, count * sizeof(dwc_otg_dev_dma_desc_t),
48628 + * This function frees a DMA Descriptor chain that was allocated by ep_alloc_desc.
48630 +void dwc_otg_ep_free_desc_chain(struct device *dev,
48631 + dwc_otg_dev_dma_desc_t * desc_addr,
48632 + uint32_t dma_desc_addr, uint32_t count)
48634 + DWC_DMA_FREE(dev, count * sizeof(dwc_otg_dev_dma_desc_t), desc_addr,
48638 +#ifdef DWC_EN_ISOC
48641 + * This function initializes a descriptor chain for Isochronous transfer
48643 + * @param core_if Programming view of DWC_otg controller.
48644 + * @param dwc_ep The EP to start the transfer on.
48647 +void dwc_otg_iso_ep_start_ddma_transfer(dwc_otg_core_if_t * core_if,
48648 + dwc_ep_t * dwc_ep)
48651 + dsts_data_t dsts = {.d32 = 0 };
48652 + depctl_data_t depctl = {.d32 = 0 };
48653 + volatile uint32_t *addr;
48657 + if (dwc_ep->is_in)
48658 + dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl / dwc_ep->bInterval;
48660 + dwc_ep->desc_cnt =
48661 + dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
48662 + dwc_ep->bInterval;
48664 + /** Allocate descriptors for double buffering */
48665 + dwc_ep->iso_desc_addr =
48666 + dwc_otg_ep_alloc_desc_chain(&dwc_ep->iso_dma_desc_addr,
48667 + dwc_ep->desc_cnt * 2);
48668 + if (dwc_ep->desc_addr) {
48669 + DWC_WARN("%s, can't allocate DMA descriptor chain\n", __func__);
48673 + dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
48675 + /** ISO OUT EP */
48676 + if (dwc_ep->is_in == 0) {
48677 + dev_dma_desc_sts_t sts = {.d32 = 0 };
48678 + dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;
48679 + dma_addr_t dma_ad;
48680 + uint32_t data_per_desc;
48681 + dwc_otg_dev_out_ep_regs_t *out_regs =
48682 + core_if->dev_if->out_ep_regs[dwc_ep->num];
48685 + addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
48686 + dma_ad = (dma_addr_t) DWC_READ_REG32(&(out_regs->doepdma));
48688 + /** Buffer 0 descriptors setup */
48689 + dma_ad = dwc_ep->dma_addr0;
48691 + sts.b_iso_out.bs = BS_HOST_READY;
48692 + sts.b_iso_out.rxsts = 0;
48693 + sts.b_iso_out.l = 0;
48694 + sts.b_iso_out.sp = 0;
48695 + sts.b_iso_out.ioc = 0;
48696 + sts.b_iso_out.pid = 0;
48697 + sts.b_iso_out.framenum = 0;
48700 + for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
48701 + i += dwc_ep->pkt_per_frm) {
48703 + for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
48704 + uint32_t len = (j + 1) * dwc_ep->maxpacket;
48705 + if (len > dwc_ep->data_per_frame)
48707 + dwc_ep->data_per_frame -
48708 + j * dwc_ep->maxpacket;
48710 + data_per_desc = dwc_ep->maxpacket;
48711 + len = data_per_desc % 4;
48713 + data_per_desc += 4 - len;
48715 + sts.b_iso_out.rxbytes = data_per_desc;
48716 + dma_desc->buf = dma_ad;
48717 + dma_desc->status.d32 = sts.d32;
48719 + offset += data_per_desc;
48721 + dma_ad += data_per_desc;
48725 + for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
48726 + uint32_t len = (j + 1) * dwc_ep->maxpacket;
48727 + if (len > dwc_ep->data_per_frame)
48729 + dwc_ep->data_per_frame -
48730 + j * dwc_ep->maxpacket;
48732 + data_per_desc = dwc_ep->maxpacket;
48733 + len = data_per_desc % 4;
48735 + data_per_desc += 4 - len;
48736 + sts.b_iso_out.rxbytes = data_per_desc;
48737 + dma_desc->buf = dma_ad;
48738 + dma_desc->status.d32 = sts.d32;
48740 + offset += data_per_desc;
48742 + dma_ad += data_per_desc;
48745 + sts.b_iso_out.ioc = 1;
48746 + len = (j + 1) * dwc_ep->maxpacket;
48747 + if (len > dwc_ep->data_per_frame)
48749 + dwc_ep->data_per_frame - j * dwc_ep->maxpacket;
48751 + data_per_desc = dwc_ep->maxpacket;
48752 + len = data_per_desc % 4;
48754 + data_per_desc += 4 - len;
48755 + sts.b_iso_out.rxbytes = data_per_desc;
48757 + dma_desc->buf = dma_ad;
48758 + dma_desc->status.d32 = sts.d32;
48761 + /** Buffer 1 descriptors setup */
48762 + sts.b_iso_out.ioc = 0;
48763 + dma_ad = dwc_ep->dma_addr1;
48766 + for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
48767 + i += dwc_ep->pkt_per_frm) {
48768 + for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
48769 + uint32_t len = (j + 1) * dwc_ep->maxpacket;
48770 + if (len > dwc_ep->data_per_frame)
48772 + dwc_ep->data_per_frame -
48773 + j * dwc_ep->maxpacket;
48775 + data_per_desc = dwc_ep->maxpacket;
48776 + len = data_per_desc % 4;
48778 + data_per_desc += 4 - len;
48781 + sts.b_iso_out.rxbytes = data_per_desc;
48782 + dma_desc->buf = dma_ad;
48783 + dma_desc->status.d32 = sts.d32;
48785 + offset += data_per_desc;
48787 + dma_ad += data_per_desc;
48790 + for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
48792 + ((j + 1) * dwc_ep->maxpacket >
48793 + dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
48794 + j * dwc_ep->maxpacket : dwc_ep->maxpacket;
48796 + (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
48797 + sts.b_iso_out.rxbytes = data_per_desc;
48798 + dma_desc->buf = dma_ad;
48799 + dma_desc->status.d32 = sts.d32;
48801 + offset += data_per_desc;
48803 + dma_ad += data_per_desc;
48806 + sts.b_iso_out.ioc = 1;
48807 + sts.b_iso_out.l = 1;
48809 + ((j + 1) * dwc_ep->maxpacket >
48810 + dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
48811 + j * dwc_ep->maxpacket : dwc_ep->maxpacket;
48813 + (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
48814 + sts.b_iso_out.rxbytes = data_per_desc;
48816 + dma_desc->buf = dma_ad;
48817 + dma_desc->status.d32 = sts.d32;
48819 + dwc_ep->next_frame = 0;
48821 + /** Write dma_ad into DOEPDMA register */
48822 + DWC_WRITE_REG32(&(out_regs->doepdma),
48823 + (uint32_t) dwc_ep->iso_dma_desc_addr);
48828 + dev_dma_desc_sts_t sts = {.d32 = 0 };
48829 + dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;
48830 + dma_addr_t dma_ad;
48831 + dwc_otg_dev_in_ep_regs_t *in_regs =
48832 + core_if->dev_if->in_ep_regs[dwc_ep->num];
48833 + unsigned int frmnumber;
48834 + fifosize_data_t txfifosize, rxfifosize;
48837 + DWC_READ_REG32(&core_if->dev_if->in_ep_regs[dwc_ep->num]->
48840 + DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
48842 + addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
48844 + dma_ad = dwc_ep->dma_addr0;
48847 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
48849 + sts.b_iso_in.bs = BS_HOST_READY;
48850 + sts.b_iso_in.txsts = 0;
48851 + sts.b_iso_in.sp =
48852 + (dwc_ep->data_per_frame % dwc_ep->maxpacket) ? 1 : 0;
48853 + sts.b_iso_in.ioc = 0;
48854 + sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
48856 + frmnumber = dwc_ep->next_frame;
48858 + sts.b_iso_in.framenum = frmnumber;
48859 + sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
48860 + sts.b_iso_in.l = 0;
48862 + /** Buffer 0 descriptors setup */
48863 + for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
48864 + dma_desc->buf = dma_ad;
48865 + dma_desc->status.d32 = sts.d32;
48868 + dma_ad += dwc_ep->data_per_frame;
48869 + sts.b_iso_in.framenum += dwc_ep->bInterval;
48872 + sts.b_iso_in.ioc = 1;
48873 + dma_desc->buf = dma_ad;
48874 + dma_desc->status.d32 = sts.d32;
48877 + /** Buffer 1 descriptors setup */
48878 + sts.b_iso_in.ioc = 0;
48879 + dma_ad = dwc_ep->dma_addr1;
48881 + for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
48882 + i += dwc_ep->pkt_per_frm) {
48883 + dma_desc->buf = dma_ad;
48884 + dma_desc->status.d32 = sts.d32;
48887 + dma_ad += dwc_ep->data_per_frame;
48888 + sts.b_iso_in.framenum += dwc_ep->bInterval;
48890 + sts.b_iso_in.ioc = 0;
48892 + sts.b_iso_in.ioc = 1;
48893 + sts.b_iso_in.l = 1;
48895 + dma_desc->buf = dma_ad;
48896 + dma_desc->status.d32 = sts.d32;
48898 + dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval;
48900 + /** Write dma_ad into diepdma register */
48901 + DWC_WRITE_REG32(&(in_regs->diepdma),
48902 + (uint32_t) dwc_ep->iso_dma_desc_addr);
48904 + /** Enable endpoint, clear nak */
48906 + depctl.b.epena = 1;
48907 + depctl.b.usbactep = 1;
48908 + depctl.b.cnak = 1;
48910 + DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
48911 + depctl.d32 = DWC_READ_REG32(addr);
48915 + * This function initializes a descriptor chain for Isochronous transfer
48917 + * @param core_if Programming view of DWC_otg controller.
48918 + * @param ep The EP to start the transfer on.
48921 +void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
48924 + depctl_data_t depctl = {.d32 = 0 };
48925 + volatile uint32_t *addr;
48928 + addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
48930 + addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
48933 + if (core_if->dma_enable == 0 || core_if->dma_desc_enable != 0) {
48936 + deptsiz_data_t deptsiz = {.d32 = 0 };
48939 + ep->data_per_frame * ep->buf_proc_intrvl / ep->bInterval;
48941 + (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
48942 + ep->xfer_count = 0;
48944 + (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
48946 + (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
48949 + /* Program the transfer size and packet count
48950 + * as follows: xfersize = N * maxpacket +
48951 + * short_packet pktcnt = N + (short_packet
48954 + deptsiz.b.mc = ep->pkt_per_frm;
48955 + deptsiz.b.xfersize = ep->xfer_len;
48956 + deptsiz.b.pktcnt =
48957 + (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
48958 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
48959 + dieptsiz, deptsiz.d32);
48961 + /* Write the DMA register */
48962 + DWC_WRITE_REG32(&
48963 + (core_if->dev_if->in_ep_regs[ep->num]->
48964 + diepdma), (uint32_t) ep->dma_addr);
48967 + deptsiz.b.pktcnt =
48968 + (ep->xfer_len + (ep->maxpacket - 1)) /
48970 + deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
48972 + DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->
48973 + doeptsiz, deptsiz.d32);
48975 + /* Write the DMA register */
48976 + DWC_WRITE_REG32(&
48977 + (core_if->dev_if->out_ep_regs[ep->num]->
48978 + doepdma), (uint32_t) ep->dma_addr);
48981 + /** Enable endpoint, clear nak */
48983 + depctl.b.epena = 1;
48984 + depctl.b.cnak = 1;
48986 + DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
48991 + * This function does the setup for a data transfer for an EP and
48992 + * starts the transfer. For an IN transfer, the packets will be
48993 + * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
48994 + * the packets are unloaded from the Rx FIFO in the ISR.
48996 + * @param core_if Programming view of DWC_otg controller.
48997 + * @param ep The EP to start the transfer on.
49000 +static void dwc_otg_iso_ep_start_transfer(dwc_otg_core_if_t * core_if,
49003 + if (core_if->dma_enable) {
49004 + if (core_if->dma_desc_enable) {
49006 + ep->desc_cnt = ep->pkt_cnt / ep->pkt_per_frm;
49008 + ep->desc_cnt = ep->pkt_cnt;
49010 + dwc_otg_iso_ep_start_ddma_transfer(core_if, ep);
49012 + if (core_if->pti_enh_enable) {
49013 + dwc_otg_iso_ep_start_buf_transfer(core_if, ep);
49015 + ep->cur_pkt_addr =
49016 + (ep->proc_buf_num) ? ep->xfer_buff1 : ep->
49018 + ep->cur_pkt_dma_addr =
49019 + (ep->proc_buf_num) ? ep->dma_addr1 : ep->
49021 + dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
49025 + ep->cur_pkt_addr =
49026 + (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
49027 + ep->cur_pkt_dma_addr =
49028 + (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
49029 + dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
49034 + * This function stops transfer for an EP and
49035 + * resets the ep's variables.
49037 + * @param core_if Programming view of DWC_otg controller.
49038 + * @param ep The EP to start the transfer on.
49041 +void dwc_otg_iso_ep_stop_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
49043 + depctl_data_t depctl = {.d32 = 0 };
49044 + volatile uint32_t *addr;
49046 + if (ep->is_in == 1) {
49047 + addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
49049 + addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
49052 + /* disable the ep */
49053 + depctl.d32 = DWC_READ_REG32(addr);
49055 + depctl.b.epdis = 1;
49056 + depctl.b.snak = 1;
49058 + DWC_WRITE_REG32(addr, depctl.d32);
49060 + if (core_if->dma_desc_enable &&
49061 + ep->iso_desc_addr && ep->iso_dma_desc_addr) {
49062 + dwc_otg_ep_free_desc_chain(ep->iso_desc_addr,
49063 + ep->iso_dma_desc_addr,
49064 + ep->desc_cnt * 2);
49067 + /* reset varibales */
49068 + ep->dma_addr0 = 0;
49069 + ep->dma_addr1 = 0;
49070 + ep->xfer_buff0 = 0;
49071 + ep->xfer_buff1 = 0;
49072 + ep->data_per_frame = 0;
49073 + ep->data_pattern_frame = 0;
49074 + ep->sync_frame = 0;
49075 + ep->buf_proc_intrvl = 0;
49076 + ep->bInterval = 0;
49077 + ep->proc_buf_num = 0;
49078 + ep->pkt_per_frm = 0;
49079 + ep->pkt_per_frm = 0;
49080 + ep->desc_cnt = 0;
49081 + ep->iso_desc_addr = 0;
49082 + ep->iso_dma_desc_addr = 0;
49085 +int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
49086 + uint8_t * buf0, uint8_t * buf1, dwc_dma_t dma0,
49087 + dwc_dma_t dma1, int sync_frame, int dp_frame,
49088 + int data_per_frame, int start_frame,
49089 + int buf_proc_intrvl, void *req_handle,
49090 + int atomic_alloc)
49092 + dwc_otg_pcd_ep_t *ep;
49093 + dwc_irqflags_t flags = 0;
49094 + dwc_ep_t *dwc_ep;
49095 + int32_t frm_data;
49096 + dsts_data_t dsts;
49097 + dwc_otg_core_if_t *core_if;
49099 + ep = get_ep_from_handle(pcd, ep_handle);
49101 + if (!ep || !ep->desc || ep->dwc_ep.num == 0) {
49102 + DWC_WARN("bad ep\n");
49103 + return -DWC_E_INVALID;
49106 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
49107 + core_if = GET_CORE_IF(pcd);
49108 + dwc_ep = &ep->dwc_ep;
49110 + if (ep->iso_req_handle) {
49111 + DWC_WARN("ISO request in progress\n");
49114 + dwc_ep->dma_addr0 = dma0;
49115 + dwc_ep->dma_addr1 = dma1;
49117 + dwc_ep->xfer_buff0 = buf0;
49118 + dwc_ep->xfer_buff1 = buf1;
49120 + dwc_ep->data_per_frame = data_per_frame;
49122 + /** @todo - pattern data support is to be implemented in the future */
49123 + dwc_ep->data_pattern_frame = dp_frame;
49124 + dwc_ep->sync_frame = sync_frame;
49126 + dwc_ep->buf_proc_intrvl = buf_proc_intrvl;
49128 + dwc_ep->bInterval = 1 << (ep->desc->bInterval - 1);
49130 + dwc_ep->proc_buf_num = 0;
49132 + dwc_ep->pkt_per_frm = 0;
49133 + frm_data = ep->dwc_ep.data_per_frame;
49134 + while (frm_data > 0) {
49135 + dwc_ep->pkt_per_frm++;
49136 + frm_data -= ep->dwc_ep.maxpacket;
49139 + dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
49141 + if (start_frame == -1) {
49142 + dwc_ep->next_frame = dsts.b.soffn + 1;
49143 + if (dwc_ep->bInterval != 1) {
49144 + dwc_ep->next_frame =
49145 + dwc_ep->next_frame + (dwc_ep->bInterval - 1 -
49146 + dwc_ep->next_frame %
49147 + dwc_ep->bInterval);
49150 + dwc_ep->next_frame = start_frame;
49153 + if (!core_if->pti_enh_enable) {
49154 + dwc_ep->pkt_cnt =
49155 + dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
49156 + dwc_ep->bInterval;
49158 + dwc_ep->pkt_cnt =
49159 + (dwc_ep->data_per_frame *
49160 + (dwc_ep->buf_proc_intrvl / dwc_ep->bInterval)
49161 + - 1 + dwc_ep->maxpacket) / dwc_ep->maxpacket;
49164 + if (core_if->dma_desc_enable) {
49165 + dwc_ep->desc_cnt =
49166 + dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
49167 + dwc_ep->bInterval;
49170 + if (atomic_alloc) {
49171 + dwc_ep->pkt_info =
49172 + DWC_ALLOC_ATOMIC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
49174 + dwc_ep->pkt_info =
49175 + DWC_ALLOC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
49177 + if (!dwc_ep->pkt_info) {
49178 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
49179 + return -DWC_E_NO_MEMORY;
49181 + if (core_if->pti_enh_enable) {
49182 + dwc_memset(dwc_ep->pkt_info, 0,
49183 + sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
49186 + dwc_ep->cur_pkt = 0;
49187 + ep->iso_req_handle = req_handle;
49189 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
49190 + dwc_otg_iso_ep_start_transfer(core_if, dwc_ep);
49194 +int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
49195 + void *req_handle)
49197 + dwc_irqflags_t flags = 0;
49198 + dwc_otg_pcd_ep_t *ep;
49199 + dwc_ep_t *dwc_ep;
49201 + ep = get_ep_from_handle(pcd, ep_handle);
49202 + if (!ep || !ep->desc || ep->dwc_ep.num == 0) {
49203 + DWC_WARN("bad ep\n");
49204 + return -DWC_E_INVALID;
49206 + dwc_ep = &ep->dwc_ep;
49208 + dwc_otg_iso_ep_stop_transfer(GET_CORE_IF(pcd), dwc_ep);
49210 + DWC_FREE(dwc_ep->pkt_info);
49211 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
49212 + if (ep->iso_req_handle != req_handle) {
49213 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
49214 + return -DWC_E_INVALID;
49217 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
49219 + ep->iso_req_handle = 0;
49224 + * This function is used for perodical data exchnage between PCD and gadget drivers.
49225 + * for Isochronous EPs
49227 + * - Every time a sync period completes this function is called to
49228 + * perform data exchange between PCD and gadget
49230 +void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
49231 + void *req_handle)
49234 + dwc_ep_t *dwc_ep;
49236 + dwc_ep = &ep->dwc_ep;
49238 + DWC_SPINUNLOCK(ep->pcd->lock);
49239 + pcd->fops->isoc_complete(pcd, ep->priv, ep->iso_req_handle,
49240 + dwc_ep->proc_buf_num ^ 0x1);
49241 + DWC_SPINLOCK(ep->pcd->lock);
49243 + for (i = 0; i < dwc_ep->pkt_cnt; ++i) {
49244 + dwc_ep->pkt_info[i].status = 0;
49245 + dwc_ep->pkt_info[i].offset = 0;
49246 + dwc_ep->pkt_info[i].length = 0;
49250 +int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd, void *ep_handle,
49251 + void *iso_req_handle)
49253 + dwc_otg_pcd_ep_t *ep;
49254 + dwc_ep_t *dwc_ep;
49256 + ep = get_ep_from_handle(pcd, ep_handle);
49257 + if (!ep->desc || ep->dwc_ep.num == 0) {
49258 + DWC_WARN("bad ep\n");
49259 + return -DWC_E_INVALID;
49261 + dwc_ep = &ep->dwc_ep;
49263 + return dwc_ep->pkt_cnt;
49266 +void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd, void *ep_handle,
49267 + void *iso_req_handle, int packet,
49268 + int *status, int *actual, int *offset)
49270 + dwc_otg_pcd_ep_t *ep;
49271 + dwc_ep_t *dwc_ep;
49273 + ep = get_ep_from_handle(pcd, ep_handle);
49275 + DWC_WARN("bad ep\n");
49277 + dwc_ep = &ep->dwc_ep;
49279 + *status = dwc_ep->pkt_info[packet].status;
49280 + *actual = dwc_ep->pkt_info[packet].length;
49281 + *offset = dwc_ep->pkt_info[packet].offset;
49284 +#endif /* DWC_EN_ISOC */
49286 +static void dwc_otg_pcd_init_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * pcd_ep,
49287 + uint32_t is_in, uint32_t ep_num)
49289 + /* Init EP structure */
49290 + pcd_ep->desc = 0;
49291 + pcd_ep->pcd = pcd;
49292 + pcd_ep->stopped = 1;
49293 + pcd_ep->queue_sof = 0;
49295 + /* Init DWC ep structure */
49296 + pcd_ep->dwc_ep.is_in = is_in;
49297 + pcd_ep->dwc_ep.num = ep_num;
49298 + pcd_ep->dwc_ep.active = 0;
49299 + pcd_ep->dwc_ep.tx_fifo_num = 0;
49300 + /* Control until ep is actvated */
49301 + pcd_ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
49302 + pcd_ep->dwc_ep.maxpacket = MAX_PACKET_SIZE;
49303 + pcd_ep->dwc_ep.dma_addr = 0;
49304 + pcd_ep->dwc_ep.start_xfer_buff = 0;
49305 + pcd_ep->dwc_ep.xfer_buff = 0;
49306 + pcd_ep->dwc_ep.xfer_len = 0;
49307 + pcd_ep->dwc_ep.xfer_count = 0;
49308 + pcd_ep->dwc_ep.sent_zlp = 0;
49309 + pcd_ep->dwc_ep.total_len = 0;
49310 + pcd_ep->dwc_ep.desc_addr = 0;
49311 + pcd_ep->dwc_ep.dma_desc_addr = 0;
49312 + DWC_CIRCLEQ_INIT(&pcd_ep->queue);
49316 + * Initialize ep's
49318 +static void dwc_otg_pcd_reinit(dwc_otg_pcd_t * pcd)
49322 + dwc_otg_pcd_ep_t *ep;
49323 + int in_ep_cntr, out_ep_cntr;
49324 + uint32_t num_in_eps = (GET_CORE_IF(pcd))->dev_if->num_in_eps;
49325 + uint32_t num_out_eps = (GET_CORE_IF(pcd))->dev_if->num_out_eps;
49328 + * Initialize the EP0 structure.
49331 + dwc_otg_pcd_init_ep(pcd, ep, 0, 0);
49334 + hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 3;
49335 + for (i = 1; in_ep_cntr < num_in_eps; i++) {
49336 + if ((hwcfg1 & 0x1) == 0) {
49337 + dwc_otg_pcd_ep_t *ep = &pcd->in_ep[in_ep_cntr];
49340 + * @todo NGS: Add direction to EP, based on contents
49341 + * of HWCFG1. Need a copy of HWCFG1 in pcd structure?
49344 + dwc_otg_pcd_init_ep(pcd, ep, 1 /* IN */ , i);
49346 + DWC_CIRCLEQ_INIT(&ep->queue);
49352 + hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 2;
49353 + for (i = 1; out_ep_cntr < num_out_eps; i++) {
49354 + if ((hwcfg1 & 0x1) == 0) {
49355 + dwc_otg_pcd_ep_t *ep = &pcd->out_ep[out_ep_cntr];
49358 + * @todo NGS: Add direction to EP, based on contents
49359 + * of HWCFG1. Need a copy of HWCFG1 in pcd structure?
49362 + dwc_otg_pcd_init_ep(pcd, ep, 0 /* OUT */ , i);
49363 + DWC_CIRCLEQ_INIT(&ep->queue);
49368 + pcd->ep0state = EP0_DISCONNECT;
49369 + pcd->ep0.dwc_ep.maxpacket = MAX_EP0_SIZE;
49370 + pcd->ep0.dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
49374 + * This function is called when the SRP timer expires. The SRP should
49375 + * complete within 6 seconds.
49377 +static void srp_timeout(void *ptr)
49379 + gotgctl_data_t gotgctl;
49380 + dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
49381 + volatile uint32_t *addr = &core_if->core_global_regs->gotgctl;
49383 + gotgctl.d32 = DWC_READ_REG32(addr);
49385 + core_if->srp_timer_started = 0;
49387 + if (core_if->adp_enable) {
49388 + if (gotgctl.b.bsesvld == 0) {
49389 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
49390 + DWC_PRINTF("SRP Timeout BSESSVLD = 0\n");
49391 + /* Power off the core */
49392 + if (core_if->power_down == 2) {
49393 + gpwrdn.b.pwrdnswtch = 1;
49394 + DWC_MODIFY_REG32(&core_if->
49395 + core_global_regs->gpwrdn,
49400 + gpwrdn.b.pmuintsel = 1;
49401 + gpwrdn.b.pmuactv = 1;
49402 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
49404 + dwc_otg_adp_probe_start(core_if);
49406 + DWC_PRINTF("SRP Timeout BSESSVLD = 1\n");
49407 + core_if->op_state = B_PERIPHERAL;
49408 + dwc_otg_core_init(core_if);
49409 + dwc_otg_enable_global_interrupts(core_if);
49410 + cil_pcd_start(core_if);
49414 + if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
49415 + (core_if->core_params->i2c_enable)) {
49416 + DWC_PRINTF("SRP Timeout\n");
49418 + if ((core_if->srp_success) && (gotgctl.b.bsesvld)) {
49419 + if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
49420 + core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
49423 + /* Clear Session Request */
49425 + gotgctl.b.sesreq = 1;
49426 + DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl,
49429 + core_if->srp_success = 0;
49431 + __DWC_ERROR("Device not connected/responding\n");
49432 + gotgctl.b.sesreq = 0;
49433 + DWC_WRITE_REG32(addr, gotgctl.d32);
49435 + } else if (gotgctl.b.sesreq) {
49436 + DWC_PRINTF("SRP Timeout\n");
49438 + __DWC_ERROR("Device not connected/responding\n");
49439 + gotgctl.b.sesreq = 0;
49440 + DWC_WRITE_REG32(addr, gotgctl.d32);
49442 + DWC_PRINTF(" SRP GOTGCTL=%0x\n", gotgctl.d32);
49450 +extern void start_next_request(dwc_otg_pcd_ep_t * ep);
49452 +static void start_xfer_tasklet_func(void *data)
49454 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data;
49455 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
49458 + depctl_data_t diepctl;
49460 + DWC_DEBUGPL(DBG_PCDV, "Start xfer tasklet\n");
49462 + diepctl.d32 = DWC_READ_REG32(&core_if->dev_if->in_ep_regs[0]->diepctl);
49464 + if (pcd->ep0.queue_sof) {
49465 + pcd->ep0.queue_sof = 0;
49466 + start_next_request(&pcd->ep0);
49470 + for (i = 0; i < core_if->dev_if->num_in_eps; i++) {
49471 + depctl_data_t diepctl;
49473 + DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl);
49475 + if (pcd->in_ep[i].queue_sof) {
49476 + pcd->in_ep[i].queue_sof = 0;
49477 + start_next_request(&pcd->in_ep[i]);
49486 + * This function initialized the PCD portion of the driver.
49489 +dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_device_t *otg_dev)
49491 + struct device *dev = &otg_dev->os_dep.platformdev->dev;
49492 + dwc_otg_core_if_t *core_if = otg_dev->core_if;
49493 + dwc_otg_pcd_t *pcd = NULL;
49494 + dwc_otg_dev_if_t *dev_if;
49498 + * Allocate PCD structure
49500 + pcd = DWC_ALLOC(sizeof(dwc_otg_pcd_t));
49502 + if (pcd == NULL) {
49506 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK))
49507 + DWC_SPINLOCK_ALLOC_LINUX_DEBUG(pcd->lock);
49509 + pcd->lock = DWC_SPINLOCK_ALLOC();
49511 + DWC_DEBUGPL(DBG_HCDV, "Init of PCD %p given core_if %p\n",
49512 + pcd, core_if);//GRAYG
49513 + if (!pcd->lock) {
49514 + DWC_ERROR("Could not allocate lock for pcd");
49518 + /* Set core_if's lock pointer to hcd->lock */
49519 + core_if->lock = pcd->lock;
49520 + pcd->core_if = core_if;
49522 + dev_if = core_if->dev_if;
49523 + dev_if->isoc_ep = NULL;
49525 + if (core_if->hwcfg4.b.ded_fifo_en) {
49526 + DWC_PRINTF("Dedicated Tx FIFOs mode\n");
49528 + DWC_PRINTF("Shared Tx FIFO mode\n");
49532 + * Initialized the Core for Device mode here if there is nod ADP support.
49533 + * Otherwise it will be done later in dwc_otg_adp_start routine.
49535 + if (dwc_otg_is_device_mode(core_if) /*&& !core_if->adp_enable*/) {
49536 + dwc_otg_core_dev_init(core_if);
49540 + * Register the PCD Callbacks.
49542 + dwc_otg_cil_register_pcd_callbacks(core_if, &pcd_callbacks, pcd);
49545 + * Initialize the DMA buffer for SETUP packets
49547 + if (GET_CORE_IF(pcd)->dma_enable) {
49549 + DWC_DMA_ALLOC(dev, sizeof(*pcd->setup_pkt) * 5,
49550 + &pcd->setup_pkt_dma_handle);
49551 + if (pcd->setup_pkt == NULL) {
49556 + pcd->status_buf =
49557 + DWC_DMA_ALLOC(dev, sizeof(uint16_t),
49558 + &pcd->status_buf_dma_handle);
49559 + if (pcd->status_buf == NULL) {
49560 + DWC_DMA_FREE(dev, sizeof(*pcd->setup_pkt) * 5,
49561 + pcd->setup_pkt, pcd->setup_pkt_dma_handle);
49566 + if (GET_CORE_IF(pcd)->dma_desc_enable) {
49567 + dev_if->setup_desc_addr[0] =
49568 + dwc_otg_ep_alloc_desc_chain(dev,
49569 + &dev_if->dma_setup_desc_addr[0], 1);
49570 + dev_if->setup_desc_addr[1] =
49571 + dwc_otg_ep_alloc_desc_chain(dev,
49572 + &dev_if->dma_setup_desc_addr[1], 1);
49573 + dev_if->in_desc_addr =
49574 + dwc_otg_ep_alloc_desc_chain(dev,
49575 + &dev_if->dma_in_desc_addr, 1);
49576 + dev_if->out_desc_addr =
49577 + dwc_otg_ep_alloc_desc_chain(dev,
49578 + &dev_if->dma_out_desc_addr, 1);
49579 + pcd->data_terminated = 0;
49581 + if (dev_if->setup_desc_addr[0] == 0
49582 + || dev_if->setup_desc_addr[1] == 0
49583 + || dev_if->in_desc_addr == 0
49584 + || dev_if->out_desc_addr == 0) {
49586 + if (dev_if->out_desc_addr)
49587 + dwc_otg_ep_free_desc_chain(dev,
49588 + dev_if->out_desc_addr,
49589 + dev_if->dma_out_desc_addr, 1);
49590 + if (dev_if->in_desc_addr)
49591 + dwc_otg_ep_free_desc_chain(dev,
49592 + dev_if->in_desc_addr,
49593 + dev_if->dma_in_desc_addr, 1);
49594 + if (dev_if->setup_desc_addr[1])
49595 + dwc_otg_ep_free_desc_chain(dev,
49596 + dev_if->setup_desc_addr[1],
49597 + dev_if->dma_setup_desc_addr[1], 1);
49598 + if (dev_if->setup_desc_addr[0])
49599 + dwc_otg_ep_free_desc_chain(dev,
49600 + dev_if->setup_desc_addr[0],
49601 + dev_if->dma_setup_desc_addr[0], 1);
49603 + DWC_DMA_FREE(dev, sizeof(*pcd->setup_pkt) * 5,
49605 + pcd->setup_pkt_dma_handle);
49606 + DWC_DMA_FREE(dev, sizeof(*pcd->status_buf),
49608 + pcd->status_buf_dma_handle);
49616 + pcd->setup_pkt = DWC_ALLOC(sizeof(*pcd->setup_pkt) * 5);
49617 + if (pcd->setup_pkt == NULL) {
49622 + pcd->status_buf = DWC_ALLOC(sizeof(uint16_t));
49623 + if (pcd->status_buf == NULL) {
49624 + DWC_FREE(pcd->setup_pkt);
49630 + dwc_otg_pcd_reinit(pcd);
49632 + /* Allocate the cfi object for the PCD */
49633 +#ifdef DWC_UTE_CFI
49634 + pcd->cfi = DWC_ALLOC(sizeof(cfiobject_t));
49635 + if (NULL == pcd->cfi)
49637 + if (init_cfi(pcd->cfi)) {
49638 + CFI_INFO("%s: Failed to init the CFI object\n", __func__);
49643 + /* Initialize tasklets */
49644 + pcd->start_xfer_tasklet = DWC_TASK_ALLOC("xfer_tasklet",
49645 + start_xfer_tasklet_func, pcd);
49646 + pcd->test_mode_tasklet = DWC_TASK_ALLOC("test_mode_tasklet",
49647 + do_test_mode, pcd);
49649 + /* Initialize SRP timer */
49650 + core_if->srp_timer = DWC_TIMER_ALLOC("SRP TIMER", srp_timeout, core_if);
49652 + if (core_if->core_params->dev_out_nak) {
49654 + * Initialize xfer timeout timer. Implemented for
49655 + * 2.93a feature "Device DDMA OUT NAK Enhancement"
49657 + for(i = 0; i < MAX_EPS_CHANNELS; i++) {
49658 + pcd->core_if->ep_xfer_timer[i] =
49659 + DWC_TIMER_ALLOC("ep timer", ep_xfer_timeout,
49660 + &pcd->core_if->ep_xfer_info[i]);
49665 +#ifdef DWC_UTE_CFI
49668 + if (pcd->setup_pkt)
49669 + DWC_FREE(pcd->setup_pkt);
49670 + if (pcd->status_buf)
49671 + DWC_FREE(pcd->status_buf);
49672 +#ifdef DWC_UTE_CFI
49674 + DWC_FREE(pcd->cfi);
49683 + * Remove PCD specific data
49685 +void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd)
49687 + dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
49688 + struct device *dev = dwc_otg_pcd_to_dev(pcd);
49691 + if (pcd->core_if->core_params->dev_out_nak) {
49692 + for (i = 0; i < MAX_EPS_CHANNELS; i++) {
49693 + DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[i]);
49694 + pcd->core_if->ep_xfer_info[i].state = 0;
49698 + if (GET_CORE_IF(pcd)->dma_enable) {
49699 + DWC_DMA_FREE(dev, sizeof(*pcd->setup_pkt) * 5, pcd->setup_pkt,
49700 + pcd->setup_pkt_dma_handle);
49701 + DWC_DMA_FREE(dev, sizeof(uint16_t), pcd->status_buf,
49702 + pcd->status_buf_dma_handle);
49703 + if (GET_CORE_IF(pcd)->dma_desc_enable) {
49704 + dwc_otg_ep_free_desc_chain(dev,
49705 + dev_if->setup_desc_addr[0],
49706 + dev_if->dma_setup_desc_addr
49708 + dwc_otg_ep_free_desc_chain(dev,
49709 + dev_if->setup_desc_addr[1],
49710 + dev_if->dma_setup_desc_addr
49712 + dwc_otg_ep_free_desc_chain(dev,
49713 + dev_if->in_desc_addr,
49714 + dev_if->dma_in_desc_addr, 1);
49715 + dwc_otg_ep_free_desc_chain(dev,
49716 + dev_if->out_desc_addr,
49717 + dev_if->dma_out_desc_addr,
49721 + DWC_FREE(pcd->setup_pkt);
49722 + DWC_FREE(pcd->status_buf);
49724 + DWC_SPINLOCK_FREE(pcd->lock);
49725 + /* Set core_if's lock pointer to NULL */
49726 + pcd->core_if->lock = NULL;
49728 + DWC_TASK_FREE(pcd->start_xfer_tasklet);
49729 + DWC_TASK_FREE(pcd->test_mode_tasklet);
49730 + if (pcd->core_if->core_params->dev_out_nak) {
49731 + for (i = 0; i < MAX_EPS_CHANNELS; i++) {
49732 + if (pcd->core_if->ep_xfer_timer[i]) {
49733 + DWC_TIMER_FREE(pcd->core_if->ep_xfer_timer[i]);
49738 +/* Release the CFI object's dynamic memory */
49739 +#ifdef DWC_UTE_CFI
49740 + if (pcd->cfi->ops.release) {
49741 + pcd->cfi->ops.release(pcd->cfi);
49749 + * Returns whether registered pcd is dual speed or not
49751 +uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd)
49753 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
49755 + if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) ||
49756 + ((core_if->hwcfg2.b.hs_phy_type == 2) &&
49757 + (core_if->hwcfg2.b.fs_phy_type == 1) &&
49758 + (core_if->core_params->ulpi_fs_ls))) {
49766 + * Returns whether registered pcd is OTG capable or not
49768 +uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd)
49770 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
49771 + gusbcfg_data_t usbcfg = {.d32 = 0 };
49773 + usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
49774 + if (!usbcfg.b.srpcap || !usbcfg.b.hnpcap) {
49782 + * This function assigns periodic Tx FIFO to an periodic EP
49783 + * in shared Tx FIFO mode
49785 +static uint32_t assign_tx_fifo(dwc_otg_core_if_t * core_if)
49787 + uint32_t TxMsk = 1;
49790 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; ++i) {
49791 + if ((TxMsk & core_if->tx_msk) == 0) {
49792 + core_if->tx_msk |= TxMsk;
49801 + * This function assigns periodic Tx FIFO to an periodic EP
49802 + * in shared Tx FIFO mode
49804 +static uint32_t assign_perio_tx_fifo(dwc_otg_core_if_t * core_if)
49806 + uint32_t PerTxMsk = 1;
49808 + for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; ++i) {
49809 + if ((PerTxMsk & core_if->p_tx_msk) == 0) {
49810 + core_if->p_tx_msk |= PerTxMsk;
49819 + * This function releases periodic Tx FIFO
49820 + * in shared Tx FIFO mode
49822 +static void release_perio_tx_fifo(dwc_otg_core_if_t * core_if,
49823 + uint32_t fifo_num)
49825 + core_if->p_tx_msk =
49826 + (core_if->p_tx_msk & (1 << (fifo_num - 1))) ^ core_if->p_tx_msk;
49830 + * This function releases periodic Tx FIFO
49831 + * in shared Tx FIFO mode
49833 +static void release_tx_fifo(dwc_otg_core_if_t * core_if, uint32_t fifo_num)
49835 + core_if->tx_msk =
49836 + (core_if->tx_msk & (1 << (fifo_num - 1))) ^ core_if->tx_msk;
49840 + * This function is being called from gadget
49841 + * to enable PCD endpoint.
49843 +int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
49844 + const uint8_t * ep_desc, void *usb_ep)
49847 + dwc_otg_pcd_ep_t *ep = NULL;
49848 + const usb_endpoint_descriptor_t *desc;
49849 + dwc_irqflags_t flags;
49850 + fifosize_data_t dptxfsiz = {.d32 = 0 };
49851 + gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
49852 + gdfifocfg_data_t gdfifocfgbase = {.d32 = 0 };
49855 + struct device *dev = dwc_otg_pcd_to_dev(pcd);
49857 + desc = (const usb_endpoint_descriptor_t *)ep_desc;
49860 + pcd->ep0.priv = usb_ep;
49862 + retval = -DWC_E_INVALID;
49866 + num = UE_GET_ADDR(desc->bEndpointAddress);
49867 + dir = UE_GET_DIR(desc->bEndpointAddress);
49869 + if (!desc->wMaxPacketSize) {
49870 + DWC_WARN("bad maxpacketsize\n");
49871 + retval = -DWC_E_INVALID;
49875 + if (dir == UE_DIR_IN) {
49876 + epcount = pcd->core_if->dev_if->num_in_eps;
49877 + for (i = 0; i < epcount; i++) {
49878 + if (num == pcd->in_ep[i].dwc_ep.num) {
49879 + ep = &pcd->in_ep[i];
49884 + epcount = pcd->core_if->dev_if->num_out_eps;
49885 + for (i = 0; i < epcount; i++) {
49886 + if (num == pcd->out_ep[i].dwc_ep.num) {
49887 + ep = &pcd->out_ep[i];
49894 + DWC_WARN("bad address\n");
49895 + retval = -DWC_E_INVALID;
49899 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
49902 + ep->priv = usb_ep;
49905 + * Activate the EP
49909 + ep->dwc_ep.is_in = (dir == UE_DIR_IN);
49910 + ep->dwc_ep.maxpacket = UGETW(desc->wMaxPacketSize);
49912 + ep->dwc_ep.type = desc->bmAttributes & UE_XFERTYPE;
49914 + if (ep->dwc_ep.is_in) {
49915 + if (!GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
49916 + ep->dwc_ep.tx_fifo_num = 0;
49918 + if (ep->dwc_ep.type == UE_ISOCHRONOUS) {
49920 + * if ISOC EP then assign a Periodic Tx FIFO.
49922 + ep->dwc_ep.tx_fifo_num =
49923 + assign_perio_tx_fifo(GET_CORE_IF(pcd));
49927 + * if Dedicated FIFOs mode is on then assign a Tx FIFO.
49929 + ep->dwc_ep.tx_fifo_num =
49930 + assign_tx_fifo(GET_CORE_IF(pcd));
49933 + /* Calculating EP info controller base address */
49934 + if (ep->dwc_ep.tx_fifo_num
49935 + && GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
49937 + DWC_READ_REG32(&GET_CORE_IF(pcd)->
49938 + core_global_regs->gdfifocfg);
49939 + gdfifocfgbase.d32 = gdfifocfg.d32 >> 16;
49942 + (&GET_CORE_IF(pcd)->core_global_regs->
49943 + dtxfsiz[ep->dwc_ep.tx_fifo_num - 1]) >> 16);
49944 + gdfifocfg.b.epinfobase =
49945 + gdfifocfgbase.d32 + dptxfsiz.d32;
49946 + if (GET_CORE_IF(pcd)->snpsid <= OTG_CORE_REV_2_94a) {
49947 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->
49948 + core_global_regs->gdfifocfg,
49953 + /* Set initial data PID. */
49954 + if (ep->dwc_ep.type == UE_BULK) {
49955 + ep->dwc_ep.data_pid_start = 0;
49958 + /* Alloc DMA Descriptors */
49959 + if (GET_CORE_IF(pcd)->dma_desc_enable) {
49960 +#ifndef DWC_UTE_PER_IO
49961 + if (ep->dwc_ep.type != UE_ISOCHRONOUS) {
49963 + ep->dwc_ep.desc_addr =
49964 + dwc_otg_ep_alloc_desc_chain(dev,
49965 + &ep->dwc_ep.dma_desc_addr,
49966 + MAX_DMA_DESC_CNT);
49967 + if (!ep->dwc_ep.desc_addr) {
49968 + DWC_WARN("%s, can't allocate DMA descriptor\n",
49970 + retval = -DWC_E_SHUTDOWN;
49971 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
49974 +#ifndef DWC_UTE_PER_IO
49979 + DWC_DEBUGPL(DBG_PCD, "Activate %s: type=%d, mps=%d desc=%p\n",
49980 + (ep->dwc_ep.is_in ? "IN" : "OUT"),
49981 + ep->dwc_ep.type, ep->dwc_ep.maxpacket, ep->desc);
49982 +#ifdef DWC_UTE_PER_IO
49983 + ep->dwc_ep.xiso_bInterval = 1 << (ep->desc->bInterval - 1);
49985 + if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
49986 + ep->dwc_ep.bInterval = 1 << (ep->desc->bInterval - 1);
49987 + ep->dwc_ep.frame_num = 0xFFFFFFFF;
49990 + dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
49992 +#ifdef DWC_UTE_CFI
49993 + if (pcd->cfi->ops.ep_enable) {
49994 + pcd->cfi->ops.ep_enable(pcd->cfi, pcd, ep);
49998 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50005 + * This function is being called from gadget
50006 + * to disable PCD endpoint.
50008 +int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle)
50010 + dwc_otg_pcd_ep_t *ep;
50011 + dwc_irqflags_t flags;
50012 + dwc_otg_dev_dma_desc_t *desc_addr;
50013 + dwc_dma_t dma_desc_addr;
50014 + gdfifocfg_data_t gdfifocfgbase = {.d32 = 0 };
50015 + gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
50016 + fifosize_data_t dptxfsiz = {.d32 = 0 };
50017 + struct device *dev = dwc_otg_pcd_to_dev(pcd);
50019 + ep = get_ep_from_handle(pcd, ep_handle);
50021 + if (!ep || !ep->desc) {
50022 + DWC_DEBUGPL(DBG_PCD, "bad ep address\n");
50023 + return -DWC_E_INVALID;
50026 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
50028 + dwc_otg_request_nuke(ep);
50030 + dwc_otg_ep_deactivate(GET_CORE_IF(pcd), &ep->dwc_ep);
50031 + if (pcd->core_if->core_params->dev_out_nak) {
50032 + DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[ep->dwc_ep.num]);
50033 + pcd->core_if->ep_xfer_info[ep->dwc_ep.num].state = 0;
50039 + DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg);
50040 + gdfifocfgbase.d32 = gdfifocfg.d32 >> 16;
50042 + if (ep->dwc_ep.is_in) {
50043 + if (GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
50044 + /* Flush the Tx FIFO */
50045 + dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd),
50046 + ep->dwc_ep.tx_fifo_num);
50048 + release_perio_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
50049 + release_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
50050 + if (GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
50051 + /* Decreasing EPinfo Base Addr */
50054 + (&GET_CORE_IF(pcd)->
50055 + core_global_regs->dtxfsiz[ep->dwc_ep.tx_fifo_num-1]) >> 16);
50056 + gdfifocfg.b.epinfobase = gdfifocfgbase.d32 - dptxfsiz.d32;
50057 + if (GET_CORE_IF(pcd)->snpsid <= OTG_CORE_REV_2_94a) {
50058 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg,
50064 + /* Free DMA Descriptors */
50065 + if (GET_CORE_IF(pcd)->dma_desc_enable) {
50066 + if (ep->dwc_ep.type != UE_ISOCHRONOUS) {
50067 + desc_addr = ep->dwc_ep.desc_addr;
50068 + dma_desc_addr = ep->dwc_ep.dma_desc_addr;
50070 + /* Cannot call dma_free_coherent() with IRQs disabled */
50071 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50072 + dwc_otg_ep_free_desc_chain(dev, desc_addr, dma_desc_addr,
50073 + MAX_DMA_DESC_CNT);
50075 + goto out_unlocked;
50078 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50081 + DWC_DEBUGPL(DBG_PCD, "%d %s disabled\n", ep->dwc_ep.num,
50082 + ep->dwc_ep.is_in ? "IN" : "OUT");
50087 +/******************************************************************************/
50088 +#ifdef DWC_UTE_PER_IO
50091 + * Free the request and its extended parts
50094 +void dwc_pcd_xiso_ereq_free(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req)
50096 + DWC_FREE(req->ext_req.per_io_frame_descs);
50101 + * Start the next request in the endpoint's queue.
50104 +int dwc_otg_pcd_xiso_start_next_request(dwc_otg_pcd_t * pcd,
50105 + dwc_otg_pcd_ep_t * ep)
50108 + dwc_otg_pcd_request_t *req = NULL;
50109 + dwc_ep_t *dwcep = NULL;
50110 + struct dwc_iso_xreq_port *ereq = NULL;
50111 + struct dwc_iso_pkt_desc_port *ddesc_iso;
50113 + depctl_data_t diepctl;
50115 + dwcep = &ep->dwc_ep;
50117 + if (dwcep->xiso_active_xfers > 0) {
50118 +#if 0 //Disable this to decrease s/w overhead that is crucial for Isoc transfers
50119 + DWC_WARN("There are currently active transfers for EP%d \
50120 + (active=%d; queued=%d)", dwcep->num, dwcep->xiso_active_xfers,
50121 + dwcep->xiso_queued_xfers);
50126 + nat = UGETW(ep->desc->wMaxPacketSize);
50127 + nat = (nat >> 11) & 0x03;
50129 + if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
50130 + req = DWC_CIRCLEQ_FIRST(&ep->queue);
50131 + ereq = &req->ext_req;
50134 + /* Get the frame number */
50135 + dwcep->xiso_frame_num =
50136 + dwc_otg_get_frame_number(GET_CORE_IF(pcd));
50137 + DWC_DEBUG("FRM_NUM=%d", dwcep->xiso_frame_num);
50139 + ddesc_iso = ereq->per_io_frame_descs;
50141 + if (dwcep->is_in) {
50142 + /* Setup DMA Descriptor chain for IN Isoc request */
50143 + for (i = 0; i < ereq->pio_pkt_count; i++) {
50144 + //if ((i % (nat + 1)) == 0)
50146 + dwcep->xiso_frame_num =
50147 + (dwcep->xiso_bInterval +
50148 + dwcep->xiso_frame_num) & 0x3FFF;
50149 + dwcep->desc_addr[i].buf =
50150 + req->dma + ddesc_iso[i].offset;
50151 + dwcep->desc_addr[i].status.b_iso_in.txbytes =
50152 + ddesc_iso[i].length;
50153 + dwcep->desc_addr[i].status.b_iso_in.framenum =
50154 + dwcep->xiso_frame_num;
50155 + dwcep->desc_addr[i].status.b_iso_in.bs =
50157 + dwcep->desc_addr[i].status.b_iso_in.txsts = 0;
50158 + dwcep->desc_addr[i].status.b_iso_in.sp =
50159 + (ddesc_iso[i].length %
50160 + dwcep->maxpacket) ? 1 : 0;
50161 + dwcep->desc_addr[i].status.b_iso_in.ioc = 0;
50162 + dwcep->desc_addr[i].status.b_iso_in.pid = nat + 1;
50163 + dwcep->desc_addr[i].status.b_iso_in.l = 0;
50165 + /* Process the last descriptor */
50166 + if (i == ereq->pio_pkt_count - 1) {
50167 + dwcep->desc_addr[i].status.b_iso_in.ioc = 1;
50168 + dwcep->desc_addr[i].status.b_iso_in.l = 1;
50172 + /* Setup and start the transfer for this endpoint */
50173 + dwcep->xiso_active_xfers++;
50174 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->dev_if->
50175 + in_ep_regs[dwcep->num]->diepdma,
50176 + dwcep->dma_desc_addr);
50178 + diepctl.b.epena = 1;
50179 + diepctl.b.cnak = 1;
50180 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->dev_if->
50181 + in_ep_regs[dwcep->num]->diepctl, 0,
50184 + /* Setup DMA Descriptor chain for OUT Isoc request */
50185 + for (i = 0; i < ereq->pio_pkt_count; i++) {
50186 + //if ((i % (nat + 1)) == 0)
50187 + dwcep->xiso_frame_num = (dwcep->xiso_bInterval +
50188 + dwcep->xiso_frame_num) & 0x3FFF;
50189 + dwcep->desc_addr[i].buf =
50190 + req->dma + ddesc_iso[i].offset;
50191 + dwcep->desc_addr[i].status.b_iso_out.rxbytes =
50192 + ddesc_iso[i].length;
50193 + dwcep->desc_addr[i].status.b_iso_out.framenum =
50194 + dwcep->xiso_frame_num;
50195 + dwcep->desc_addr[i].status.b_iso_out.bs =
50197 + dwcep->desc_addr[i].status.b_iso_out.rxsts = 0;
50198 + dwcep->desc_addr[i].status.b_iso_out.sp =
50199 + (ddesc_iso[i].length %
50200 + dwcep->maxpacket) ? 1 : 0;
50201 + dwcep->desc_addr[i].status.b_iso_out.ioc = 0;
50202 + dwcep->desc_addr[i].status.b_iso_out.pid = nat + 1;
50203 + dwcep->desc_addr[i].status.b_iso_out.l = 0;
50205 + /* Process the last descriptor */
50206 + if (i == ereq->pio_pkt_count - 1) {
50207 + dwcep->desc_addr[i].status.b_iso_out.ioc = 1;
50208 + dwcep->desc_addr[i].status.b_iso_out.l = 1;
50212 + /* Setup and start the transfer for this endpoint */
50213 + dwcep->xiso_active_xfers++;
50214 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->
50215 + dev_if->out_ep_regs[dwcep->num]->
50216 + doepdma, dwcep->dma_desc_addr);
50218 + diepctl.b.epena = 1;
50219 + diepctl.b.cnak = 1;
50220 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->
50221 + dev_if->out_ep_regs[dwcep->num]->
50222 + doepctl, 0, diepctl.d32);
50233 + * - Remove the request from the queue
50235 +void complete_xiso_ep(dwc_otg_pcd_ep_t * ep)
50237 + dwc_otg_pcd_request_t *req = NULL;
50238 + struct dwc_iso_xreq_port *ereq = NULL;
50239 + struct dwc_iso_pkt_desc_port *ddesc_iso = NULL;
50240 + dwc_ep_t *dwcep = NULL;
50244 + dwcep = &ep->dwc_ep;
50246 + /* Get the first pending request from the queue */
50247 + if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
50248 + req = DWC_CIRCLEQ_FIRST(&ep->queue);
50250 + DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
50253 + dwcep->xiso_active_xfers--;
50254 + dwcep->xiso_queued_xfers--;
50255 + /* Remove this request from the queue */
50256 + DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry);
50258 + DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
50263 + ereq = &req->ext_req;
50264 + ddesc_iso = ereq->per_io_frame_descs;
50266 + if (dwcep->xiso_active_xfers < 0) {
50267 + DWC_WARN("EP#%d (xiso_active_xfers=%d)", dwcep->num,
50268 + dwcep->xiso_active_xfers);
50271 + /* Fill the Isoc descs of portable extended req from dma descriptors */
50272 + for (i = 0; i < ereq->pio_pkt_count; i++) {
50273 + if (dwcep->is_in) { /* IN endpoints */
50274 + ddesc_iso[i].actual_length = ddesc_iso[i].length -
50275 + dwcep->desc_addr[i].status.b_iso_in.txbytes;
50276 + ddesc_iso[i].status =
50277 + dwcep->desc_addr[i].status.b_iso_in.txsts;
50278 + } else { /* OUT endpoints */
50279 + ddesc_iso[i].actual_length = ddesc_iso[i].length -
50280 + dwcep->desc_addr[i].status.b_iso_out.rxbytes;
50281 + ddesc_iso[i].status =
50282 + dwcep->desc_addr[i].status.b_iso_out.rxsts;
50286 + DWC_SPINUNLOCK(ep->pcd->lock);
50288 + /* Call the completion function in the non-portable logic */
50289 + ep->pcd->fops->xisoc_complete(ep->pcd, ep->priv, req->priv, 0,
50292 + DWC_SPINLOCK(ep->pcd->lock);
50294 + /* Free the request - specific freeing needed for extended request object */
50295 + dwc_pcd_xiso_ereq_free(ep, req);
50297 + /* Start the next request */
50298 + dwc_otg_pcd_xiso_start_next_request(ep->pcd, ep);
50304 + * Create and initialize the Isoc pkt descriptors of the extended request.
50307 +static int dwc_otg_pcd_xiso_create_pkt_descs(dwc_otg_pcd_request_t * req,
50308 + void *ereq_nonport,
50309 + int atomic_alloc)
50311 + struct dwc_iso_xreq_port *ereq = NULL;
50312 + struct dwc_iso_xreq_port *req_mapped = NULL;
50313 + struct dwc_iso_pkt_desc_port *ipds = NULL; /* To be created in this function */
50314 + uint32_t pkt_count;
50317 + ereq = &req->ext_req;
50318 + req_mapped = (struct dwc_iso_xreq_port *)ereq_nonport;
50319 + pkt_count = req_mapped->pio_pkt_count;
50321 + /* Create the isoc descs */
50322 + if (atomic_alloc) {
50323 + ipds = DWC_ALLOC_ATOMIC(sizeof(*ipds) * pkt_count);
50325 + ipds = DWC_ALLOC(sizeof(*ipds) * pkt_count);
50329 + DWC_ERROR("Failed to allocate isoc descriptors");
50330 + return -DWC_E_NO_MEMORY;
50333 + /* Initialize the extended request fields */
50334 + ereq->per_io_frame_descs = ipds;
50335 + ereq->error_count = 0;
50336 + ereq->pio_alloc_pkt_count = pkt_count;
50337 + ereq->pio_pkt_count = pkt_count;
50338 + ereq->tr_sub_flags = req_mapped->tr_sub_flags;
50340 + /* Init the Isoc descriptors */
50341 + for (i = 0; i < pkt_count; i++) {
50342 + ipds[i].length = req_mapped->per_io_frame_descs[i].length;
50343 + ipds[i].offset = req_mapped->per_io_frame_descs[i].offset;
50344 + ipds[i].status = req_mapped->per_io_frame_descs[i].status; /* 0 */
50345 + ipds[i].actual_length =
50346 + req_mapped->per_io_frame_descs[i].actual_length;
50352 +static void prn_ext_request(struct dwc_iso_xreq_port *ereq)
50354 + struct dwc_iso_pkt_desc_port *xfd = NULL;
50357 + DWC_DEBUG("per_io_frame_descs=%p", ereq->per_io_frame_descs);
50358 + DWC_DEBUG("tr_sub_flags=%d", ereq->tr_sub_flags);
50359 + DWC_DEBUG("error_count=%d", ereq->error_count);
50360 + DWC_DEBUG("pio_alloc_pkt_count=%d", ereq->pio_alloc_pkt_count);
50361 + DWC_DEBUG("pio_pkt_count=%d", ereq->pio_pkt_count);
50362 + DWC_DEBUG("res=%d", ereq->res);
50364 + for (i = 0; i < ereq->pio_pkt_count; i++) {
50365 + xfd = &ereq->per_io_frame_descs[0];
50366 + DWC_DEBUG("FD #%d", i);
50368 + DWC_DEBUG("xfd->actual_length=%d", xfd->actual_length);
50369 + DWC_DEBUG("xfd->length=%d", xfd->length);
50370 + DWC_DEBUG("xfd->offset=%d", xfd->offset);
50371 + DWC_DEBUG("xfd->status=%d", xfd->status);
50378 +int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
50379 + uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen,
50380 + int zero, void *req_handle, int atomic_alloc,
50381 + void *ereq_nonport)
50383 + dwc_otg_pcd_request_t *req = NULL;
50384 + dwc_otg_pcd_ep_t *ep;
50385 + dwc_irqflags_t flags;
50388 + ep = get_ep_from_handle(pcd, ep_handle);
50390 + DWC_WARN("bad ep\n");
50391 + return -DWC_E_INVALID;
50394 + /* We support this extension only for DDMA mode */
50395 + if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)
50396 + if (!GET_CORE_IF(pcd)->dma_desc_enable)
50397 + return -DWC_E_INVALID;
50399 + /* Create a dwc_otg_pcd_request_t object */
50400 + if (atomic_alloc) {
50401 + req = DWC_ALLOC_ATOMIC(sizeof(*req));
50403 + req = DWC_ALLOC(sizeof(*req));
50407 + return -DWC_E_NO_MEMORY;
50410 + /* Create the Isoc descs for this request which shall be the exact match
50411 + * of the structure sent to us from the non-portable logic */
50413 + dwc_otg_pcd_xiso_create_pkt_descs(req, ereq_nonport, atomic_alloc);
50415 + DWC_WARN("Failed to init the Isoc descriptors");
50420 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
50422 + DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry);
50424 + req->dma = dma_buf;
50425 + req->length = buflen;
50426 + req->sent_zlp = zero;
50427 + req->priv = req_handle;
50429 + //DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
50430 + ep->dwc_ep.dma_addr = dma_buf;
50431 + ep->dwc_ep.start_xfer_buff = buf;
50432 + ep->dwc_ep.xfer_buff = buf;
50433 + ep->dwc_ep.xfer_len = 0;
50434 + ep->dwc_ep.xfer_count = 0;
50435 + ep->dwc_ep.sent_zlp = 0;
50436 + ep->dwc_ep.total_len = buflen;
50438 + /* Add this request to the tail */
50439 + DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
50440 + ep->dwc_ep.xiso_queued_xfers++;
50442 +//DWC_DEBUG("CP_0");
50443 +//DWC_DEBUG("req->ext_req.tr_sub_flags=%d", req->ext_req.tr_sub_flags);
50444 +//prn_ext_request((struct dwc_iso_xreq_port *) ereq_nonport);
50445 +//prn_ext_request(&req->ext_req);
50447 + //DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50449 + /* If the req->status == ASAP then check if there is any active transfer
50450 + * for this endpoint. If no active transfers, then get the first entry
50451 + * from the queue and start that transfer
50453 + if (req->ext_req.tr_sub_flags == DWC_EREQ_TF_ASAP) {
50454 + res = dwc_otg_pcd_xiso_start_next_request(pcd, ep);
50456 + DWC_WARN("Failed to start the next Isoc transfer");
50457 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50463 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50468 +/* END ifdef DWC_UTE_PER_IO ***************************************************/
50469 +int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
50470 + uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen,
50471 + int zero, void *req_handle, int atomic_alloc)
50473 + struct device *dev = dwc_otg_pcd_to_dev(pcd);
50474 + dwc_irqflags_t flags;
50475 + dwc_otg_pcd_request_t *req;
50476 + dwc_otg_pcd_ep_t *ep;
50477 + uint32_t max_transfer;
50479 + ep = get_ep_from_handle(pcd, ep_handle);
50480 + if (!ep || (!ep->desc && ep->dwc_ep.num != 0)) {
50481 + DWC_WARN("bad ep\n");
50482 + return -DWC_E_INVALID;
50485 + if (atomic_alloc) {
50486 + req = DWC_ALLOC_ATOMIC(sizeof(*req));
50488 + req = DWC_ALLOC(sizeof(*req));
50492 + return -DWC_E_NO_MEMORY;
50494 + DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry);
50495 + if (!GET_CORE_IF(pcd)->core_params->opt) {
50496 + if (ep->dwc_ep.num != 0) {
50497 + DWC_ERROR("queue req %p, len %d buf %p\n",
50498 + req_handle, buflen, buf);
50503 + req->dma = dma_buf;
50504 + req->length = buflen;
50505 + req->sent_zlp = zero;
50506 + req->priv = req_handle;
50507 + req->dw_align_buf = NULL;
50508 + if ((dma_buf & 0x3) && GET_CORE_IF(pcd)->dma_enable
50509 + && !GET_CORE_IF(pcd)->dma_desc_enable)
50510 + req->dw_align_buf = DWC_DMA_ALLOC(dev, buflen,
50511 + &req->dw_align_buf_dma);
50512 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
50515 + * After adding request to the queue for IN ISOC wait for In Token Received
50516 + * when TX FIFO is empty interrupt and for OUT ISOC wait for OUT Token
50517 + * Received when EP is disabled interrupt to obtain starting microframe
50518 + * (odd/even) start transfer
50520 + if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
50522 + depctl_data_t depctl = {.d32 =
50523 + DWC_READ_REG32(&pcd->core_if->dev_if->
50524 + in_ep_regs[ep->dwc_ep.num]->
50526 + ++pcd->request_pending;
50528 + DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
50529 + if (ep->dwc_ep.is_in) {
50530 + depctl.b.cnak = 1;
50531 + DWC_WRITE_REG32(&pcd->core_if->dev_if->
50532 + in_ep_regs[ep->dwc_ep.num]->
50533 + diepctl, depctl.d32);
50536 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50542 + * For EP0 IN without premature status, zlp is required?
50544 + if (ep->dwc_ep.num == 0 && ep->dwc_ep.is_in) {
50545 + DWC_DEBUGPL(DBG_PCDV, "%d-OUT ZLP\n", ep->dwc_ep.num);
50546 + //_req->zero = 1;
50549 + /* Start the transfer */
50550 + if (DWC_CIRCLEQ_EMPTY(&ep->queue) && !ep->stopped) {
50551 + /* EP0 Transfer? */
50552 + if (ep->dwc_ep.num == 0) {
50553 + switch (pcd->ep0state) {
50554 + case EP0_IN_DATA_PHASE:
50555 + DWC_DEBUGPL(DBG_PCD,
50556 + "%s ep0: EP0_IN_DATA_PHASE\n",
50560 + case EP0_OUT_DATA_PHASE:
50561 + DWC_DEBUGPL(DBG_PCD,
50562 + "%s ep0: EP0_OUT_DATA_PHASE\n",
50564 + if (pcd->request_config) {
50565 + /* Complete STATUS PHASE */
50566 + ep->dwc_ep.is_in = 1;
50567 + pcd->ep0state = EP0_IN_STATUS_PHASE;
50571 + case EP0_IN_STATUS_PHASE:
50572 + DWC_DEBUGPL(DBG_PCD,
50573 + "%s ep0: EP0_IN_STATUS_PHASE\n",
50578 + DWC_DEBUGPL(DBG_ANY, "ep0: odd state %d\n",
50580 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50581 + return -DWC_E_SHUTDOWN;
50584 + ep->dwc_ep.dma_addr = dma_buf;
50585 + ep->dwc_ep.start_xfer_buff = buf;
50586 + ep->dwc_ep.xfer_buff = buf;
50587 + ep->dwc_ep.xfer_len = buflen;
50588 + ep->dwc_ep.xfer_count = 0;
50589 + ep->dwc_ep.sent_zlp = 0;
50590 + ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
50593 + if ((ep->dwc_ep.xfer_len %
50594 + ep->dwc_ep.maxpacket == 0)
50595 + && (ep->dwc_ep.xfer_len != 0)) {
50596 + ep->dwc_ep.sent_zlp = 1;
50601 + dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd),
50603 + } // non-ep0 endpoints
50605 +#ifdef DWC_UTE_CFI
50606 + if (ep->dwc_ep.buff_mode != BM_STANDARD) {
50607 + /* store the request length */
50608 + ep->dwc_ep.cfi_req_len = buflen;
50609 + pcd->cfi->ops.build_descriptors(pcd->cfi, pcd,
50614 + GET_CORE_IF(ep->pcd)->core_params->
50615 + max_transfer_size;
50617 + /* Setup and start the Transfer */
50618 + if (req->dw_align_buf){
50619 + if (ep->dwc_ep.is_in)
50620 + dwc_memcpy(req->dw_align_buf,
50622 + ep->dwc_ep.dma_addr =
50623 + req->dw_align_buf_dma;
50624 + ep->dwc_ep.start_xfer_buff =
50625 + req->dw_align_buf;
50626 + ep->dwc_ep.xfer_buff =
50627 + req->dw_align_buf;
50629 + ep->dwc_ep.dma_addr = dma_buf;
50630 + ep->dwc_ep.start_xfer_buff = buf;
50631 + ep->dwc_ep.xfer_buff = buf;
50633 + ep->dwc_ep.xfer_len = 0;
50634 + ep->dwc_ep.xfer_count = 0;
50635 + ep->dwc_ep.sent_zlp = 0;
50636 + ep->dwc_ep.total_len = buflen;
50638 + ep->dwc_ep.maxxfer = max_transfer;
50639 + if (GET_CORE_IF(pcd)->dma_desc_enable) {
50640 + uint32_t out_max_xfer =
50641 + DDMA_MAX_TRANSFER_SIZE -
50642 + (DDMA_MAX_TRANSFER_SIZE % 4);
50643 + if (ep->dwc_ep.is_in) {
50644 + if (ep->dwc_ep.maxxfer >
50645 + DDMA_MAX_TRANSFER_SIZE) {
50646 + ep->dwc_ep.maxxfer =
50647 + DDMA_MAX_TRANSFER_SIZE;
50650 + if (ep->dwc_ep.maxxfer >
50652 + ep->dwc_ep.maxxfer =
50657 + if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) {
50658 + ep->dwc_ep.maxxfer -=
50659 + (ep->dwc_ep.maxxfer %
50660 + ep->dwc_ep.maxpacket);
50664 + if ((ep->dwc_ep.total_len %
50665 + ep->dwc_ep.maxpacket == 0)
50666 + && (ep->dwc_ep.total_len != 0)) {
50667 + ep->dwc_ep.sent_zlp = 1;
50670 +#ifdef DWC_UTE_CFI
50673 + dwc_otg_ep_start_transfer(GET_CORE_IF(pcd),
50679 + ++pcd->request_pending;
50680 + DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
50681 + if (ep->dwc_ep.is_in && ep->stopped
50682 + && !(GET_CORE_IF(pcd)->dma_enable)) {
50683 + /** @todo NGS Create a function for this. */
50684 + diepmsk_data_t diepmsk = {.d32 = 0 };
50685 + diepmsk.b.intktxfemp = 1;
50686 + if (GET_CORE_IF(pcd)->multiproc_int_enable) {
50687 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->
50688 + dev_if->dev_global_regs->diepeachintmsk
50689 + [ep->dwc_ep.num], 0,
50692 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->
50693 + dev_if->dev_global_regs->
50694 + diepmsk, 0, diepmsk.d32);
50699 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50704 +int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
50705 + void *req_handle)
50707 + dwc_irqflags_t flags;
50708 + dwc_otg_pcd_request_t *req;
50709 + dwc_otg_pcd_ep_t *ep;
50711 + ep = get_ep_from_handle(pcd, ep_handle);
50712 + if (!ep || (!ep->desc && ep->dwc_ep.num != 0)) {
50713 + DWC_WARN("bad argument\n");
50714 + return -DWC_E_INVALID;
50717 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
50719 + /* make sure it's actually queued on this endpoint */
50720 + DWC_CIRCLEQ_FOREACH(req, &ep->queue, queue_entry) {
50721 + if (req->priv == (void *)req_handle) {
50726 + if (req->priv != (void *)req_handle) {
50727 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50728 + return -DWC_E_INVALID;
50731 + if (!DWC_CIRCLEQ_EMPTY_ENTRY(req, queue_entry)) {
50732 + dwc_otg_request_done(ep, req, -DWC_E_RESTART);
50737 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50739 + return req ? 0 : -DWC_E_SHUTDOWN;
50744 + * dwc_otg_pcd_ep_wedge - sets the halt feature and ignores clear requests
50746 + * Use this to stall an endpoint and ignore CLEAR_FEATURE(HALT_ENDPOINT)
50747 + * requests. If the gadget driver clears the halt status, it will
50748 + * automatically unwedge the endpoint.
50750 + * Returns zero on success, else negative DWC error code.
50752 +int dwc_otg_pcd_ep_wedge(dwc_otg_pcd_t * pcd, void *ep_handle)
50754 + dwc_otg_pcd_ep_t *ep;
50755 + dwc_irqflags_t flags;
50758 + ep = get_ep_from_handle(pcd, ep_handle);
50760 + if ((!ep->desc && ep != &pcd->ep0) ||
50761 + (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) {
50762 + DWC_WARN("%s, bad ep\n", __func__);
50763 + return -DWC_E_INVALID;
50766 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
50767 + if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
50768 + DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num,
50769 + ep->dwc_ep.is_in ? "IN" : "OUT");
50770 + retval = -DWC_E_AGAIN;
50772 + /* This code needs to be reviewed */
50773 + if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) {
50774 + dtxfsts_data_t txstatus;
50775 + fifosize_data_t txfifosize;
50778 + DWC_READ_REG32(&GET_CORE_IF(pcd)->
50779 + core_global_regs->dtxfsiz[ep->dwc_ep.
50782 + DWC_READ_REG32(&GET_CORE_IF(pcd)->
50783 + dev_if->in_ep_regs[ep->dwc_ep.num]->
50786 + if (txstatus.b.txfspcavail < txfifosize.b.depth) {
50787 + DWC_WARN("%s() Data In Tx Fifo\n", __func__);
50788 + retval = -DWC_E_AGAIN;
50790 + if (ep->dwc_ep.num == 0) {
50791 + pcd->ep0state = EP0_STALL;
50795 + dwc_otg_ep_set_stall(GET_CORE_IF(pcd),
50799 + if (ep->dwc_ep.num == 0) {
50800 + pcd->ep0state = EP0_STALL;
50804 + dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
50808 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50813 +int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value)
50815 + dwc_otg_pcd_ep_t *ep;
50816 + dwc_irqflags_t flags;
50819 + ep = get_ep_from_handle(pcd, ep_handle);
50821 + if (!ep || (!ep->desc && ep != &pcd->ep0) ||
50822 + (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) {
50823 + DWC_WARN("%s, bad ep\n", __func__);
50824 + return -DWC_E_INVALID;
50827 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
50828 + if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
50829 + DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num,
50830 + ep->dwc_ep.is_in ? "IN" : "OUT");
50831 + retval = -DWC_E_AGAIN;
50832 + } else if (value == 0) {
50833 + dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
50834 + } else if (value == 1) {
50835 + if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) {
50836 + dtxfsts_data_t txstatus;
50837 + fifosize_data_t txfifosize;
50840 + DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs->
50841 + dtxfsiz[ep->dwc_ep.tx_fifo_num]);
50843 + DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
50844 + in_ep_regs[ep->dwc_ep.num]->dtxfsts);
50846 + if (txstatus.b.txfspcavail < txfifosize.b.depth) {
50847 + DWC_WARN("%s() Data In Tx Fifo\n", __func__);
50848 + retval = -DWC_E_AGAIN;
50850 + if (ep->dwc_ep.num == 0) {
50851 + pcd->ep0state = EP0_STALL;
50855 + dwc_otg_ep_set_stall(GET_CORE_IF(pcd),
50859 + if (ep->dwc_ep.num == 0) {
50860 + pcd->ep0state = EP0_STALL;
50864 + dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
50866 + } else if (value == 2) {
50867 + ep->dwc_ep.stall_clear_flag = 0;
50868 + } else if (value == 3) {
50869 + ep->dwc_ep.stall_clear_flag = 1;
50872 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50878 + * This function initiates remote wakeup of the host from suspend state.
50880 +void dwc_otg_pcd_rem_wkup_from_suspend(dwc_otg_pcd_t * pcd, int set)
50882 + dctl_data_t dctl = { 0 };
50883 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
50884 + dsts_data_t dsts;
50886 + dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
50887 + if (!dsts.b.suspsts) {
50888 + DWC_WARN("Remote wakeup while is not in suspend state\n");
50890 + /* Check if DEVICE_REMOTE_WAKEUP feature enabled */
50891 + if (pcd->remote_wakeup_enable) {
50894 + if (core_if->adp_enable) {
50895 + gpwrdn_data_t gpwrdn;
50897 + dwc_otg_adp_probe_stop(core_if);
50899 + /* Mask SRP detected interrupt from Power Down Logic */
50901 + gpwrdn.b.srp_det_msk = 1;
50902 + DWC_MODIFY_REG32(&core_if->
50903 + core_global_regs->gpwrdn,
50906 + /* Disable Power Down Logic */
50908 + gpwrdn.b.pmuactv = 1;
50909 + DWC_MODIFY_REG32(&core_if->
50910 + core_global_regs->gpwrdn,
50914 + * Initialize the Core for Device mode.
50916 + core_if->op_state = B_PERIPHERAL;
50917 + dwc_otg_core_init(core_if);
50918 + dwc_otg_enable_global_interrupts(core_if);
50919 + cil_pcd_start(core_if);
50921 + dwc_otg_initiate_srp(core_if);
50924 + dctl.b.rmtwkupsig = 1;
50925 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
50926 + dctl, 0, dctl.d32);
50927 + DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
50930 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
50931 + dctl, dctl.d32, 0);
50932 + DWC_DEBUGPL(DBG_PCD, "Clear Remote Wakeup\n");
50935 + DWC_DEBUGPL(DBG_PCD, "Remote Wakeup is disabled\n");
50939 +#ifdef CONFIG_USB_DWC_OTG_LPM
50941 + * This function initiates remote wakeup of the host from L1 sleep state.
50943 +void dwc_otg_pcd_rem_wkup_from_sleep(dwc_otg_pcd_t * pcd, int set)
50945 + glpmcfg_data_t lpmcfg;
50946 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
50948 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
50950 + /* Check if we are in L1 state */
50951 + if (!lpmcfg.b.prt_sleep_sts) {
50952 + DWC_DEBUGPL(DBG_PCD, "Device is not in sleep state\n");
50956 + /* Check if host allows remote wakeup */
50957 + if (!lpmcfg.b.rem_wkup_en) {
50958 + DWC_DEBUGPL(DBG_PCD, "Host does not allow remote wakeup\n");
50962 + /* Check if Resume OK */
50963 + if (!lpmcfg.b.sleep_state_resumeok) {
50964 + DWC_DEBUGPL(DBG_PCD, "Sleep state resume is not OK\n");
50968 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
50969 + lpmcfg.b.en_utmi_sleep = 0;
50970 + lpmcfg.b.hird_thres &= (~(1 << 4));
50971 + DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
50974 + dctl_data_t dctl = {.d32 = 0 };
50975 + dctl.b.rmtwkupsig = 1;
50976 + /* Set RmtWkUpSig bit to start remote wakup signaling.
50977 + * Hardware will automatically clear this bit.
50979 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl,
50981 + DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
50988 + * Performs remote wakeup.
50990 +void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set)
50992 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
50993 + dwc_irqflags_t flags;
50994 + if (dwc_otg_is_device_mode(core_if)) {
50995 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
50996 +#ifdef CONFIG_USB_DWC_OTG_LPM
50997 + if (core_if->lx_state == DWC_OTG_L1) {
50998 + dwc_otg_pcd_rem_wkup_from_sleep(pcd, set);
51001 + dwc_otg_pcd_rem_wkup_from_suspend(pcd, set);
51002 +#ifdef CONFIG_USB_DWC_OTG_LPM
51005 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
51010 +void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs)
51012 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
51013 + dctl_data_t dctl = { 0 };
51015 + if (dwc_otg_is_device_mode(core_if)) {
51016 + dctl.b.sftdiscon = 1;
51017 + DWC_PRINTF("Soft disconnect for %d useconds\n",no_of_usecs);
51018 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
51019 + dwc_udelay(no_of_usecs);
51020 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32,0);
51023 + DWC_PRINTF("NOT SUPPORTED IN HOST MODE\n");
51029 +int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd)
51031 + dsts_data_t dsts;
51032 + gotgctl_data_t gotgctl;
51035 + * This function starts the Protocol if no session is in progress. If
51036 + * a session is already in progress, but the device is suspended,
51037 + * remote wakeup signaling is started.
51040 + /* Check if valid session */
51042 + DWC_READ_REG32(&(GET_CORE_IF(pcd)->core_global_regs->gotgctl));
51043 + if (gotgctl.b.bsesvld) {
51044 + /* Check if suspend state */
51047 + (GET_CORE_IF(pcd)->dev_if->
51048 + dev_global_regs->dsts));
51049 + if (dsts.b.suspsts) {
51050 + dwc_otg_pcd_remote_wakeup(pcd, 1);
51053 + dwc_otg_pcd_initiate_srp(pcd);
51061 + * Start the SRP timer to detect when the SRP does not complete within
51064 + * @param pcd the pcd structure.
51066 +void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd)
51068 + dwc_irqflags_t flags;
51069 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
51070 + dwc_otg_initiate_srp(GET_CORE_IF(pcd));
51071 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
51074 +int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd)
51076 + return dwc_otg_get_frame_number(GET_CORE_IF(pcd));
51079 +int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd)
51081 + return GET_CORE_IF(pcd)->core_params->lpm_enable;
51084 +uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd)
51086 + return pcd->b_hnp_enable;
51089 +uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd)
51091 + return pcd->a_hnp_support;
51094 +uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd)
51096 + return pcd->a_alt_hnp_support;
51099 +int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd)
51101 + return pcd->remote_wakeup_enable;
51104 +#endif /* DWC_HOST_ONLY */
51106 +++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd.h
51108 +/* ==========================================================================
51109 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $
51110 + * $Revision: #48 $
51111 + * $Date: 2012/08/10 $
51112 + * $Change: 2047372 $
51114 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
51115 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
51116 + * otherwise expressly agreed to in writing between Synopsys and you.
51118 + * The Software IS NOT an item of Licensed Software or Licensed Product under
51119 + * any End User Software License Agreement or Agreement for Licensed Product
51120 + * with Synopsys or any supplement thereto. You are permitted to use and
51121 + * redistribute this Software in source and binary forms, with or without
51122 + * modification, provided that redistributions of source code must retain this
51123 + * notice. You may not view, use, disclose, copy or distribute this file or
51124 + * any information contained herein except pursuant to this license grant from
51125 + * Synopsys. If you do not agree with this notice, including the disclaimer
51126 + * below, then you are not authorized to use the Software.
51128 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
51129 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
51130 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
51131 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
51132 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
51133 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
51134 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
51135 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
51136 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
51137 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
51139 + * ========================================================================== */
51140 +#ifndef DWC_HOST_ONLY
51141 +#if !defined(__DWC_PCD_H__)
51142 +#define __DWC_PCD_H__
51144 +#include "dwc_otg_os_dep.h"
51146 +#include "dwc_otg_cil.h"
51147 +#include "dwc_otg_pcd_if.h"
51148 +#include "dwc_otg_driver.h"
51155 + * This file contains the structures, constants, and interfaces for
51156 + * the Perpherial Contoller Driver (PCD).
51158 + * The Peripheral Controller Driver (PCD) for Linux will implement the
51159 + * Gadget API, so that the existing Gadget drivers can be used. For
51160 + * the Mass Storage Function driver the File-backed USB Storage Gadget
51161 + * (FBS) driver will be used. The FBS driver supports the
51162 + * Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only
51167 +/** Invalid DMA Address */
51168 +#define DWC_DMA_ADDR_INVALID (~(dwc_dma_t)0)
51170 +/** Max Transfer size for any EP */
51171 +#define DDMA_MAX_TRANSFER_SIZE 65535
51174 + * Get the pointer to the core_if from the pcd pointer.
51176 +#define GET_CORE_IF( _pcd ) (_pcd->core_if)
51181 +typedef enum ep0_state {
51182 + EP0_DISCONNECT, /* no host */
51184 + EP0_IN_DATA_PHASE,
51185 + EP0_OUT_DATA_PHASE,
51186 + EP0_IN_STATUS_PHASE,
51187 + EP0_OUT_STATUS_PHASE,
51191 +/** Fordward declaration.*/
51192 +struct dwc_otg_pcd;
51194 +/** DWC_otg iso request structure.
51197 +typedef struct usb_iso_request dwc_otg_pcd_iso_request_t;
51199 +#ifdef DWC_UTE_PER_IO
51202 + * This shall be the exact analogy of the same type structure defined in the
51203 + * usb_gadget.h. Each descriptor contains
51205 +struct dwc_iso_pkt_desc_port {
51207 + uint32_t length; /* expected length */
51208 + uint32_t actual_length;
51212 +struct dwc_iso_xreq_port {
51213 + /** transfer/submission flag */
51214 + uint32_t tr_sub_flags;
51215 + /** Start the request ASAP */
51216 +#define DWC_EREQ_TF_ASAP 0x00000002
51217 + /** Just enqueue the request w/o initiating a transfer */
51218 +#define DWC_EREQ_TF_ENQUEUE 0x00000004
51221 + * count of ISO packets attached to this request - shall
51222 + * not exceed the pio_alloc_pkt_count
51224 + uint32_t pio_pkt_count;
51225 + /** count of ISO packets allocated for this request */
51226 + uint32_t pio_alloc_pkt_count;
51227 + /** number of ISO packet errors */
51228 + uint32_t error_count;
51229 + /** reserved for future extension */
51231 + /** Will be allocated and freed in the UTE gadget and based on the CFC value */
51232 + struct dwc_iso_pkt_desc_port *per_io_frame_descs;
51235 +/** DWC_otg request structure.
51236 + * This structure is a list of requests.
51238 +typedef struct dwc_otg_pcd_request {
51244 + unsigned sent_zlp:1;
51246 + * Used instead of original buffer if
51247 + * it(physical address) is not dword-aligned.
51249 + uint8_t *dw_align_buf;
51250 + dwc_dma_t dw_align_buf_dma;
51252 + DWC_CIRCLEQ_ENTRY(dwc_otg_pcd_request) queue_entry;
51253 +#ifdef DWC_UTE_PER_IO
51254 + struct dwc_iso_xreq_port ext_req;
51255 + //void *priv_ereq_nport; /* */
51257 +} dwc_otg_pcd_request_t;
51259 +DWC_CIRCLEQ_HEAD(req_list, dwc_otg_pcd_request);
51261 +/** PCD EP structure.
51262 + * This structure describes an EP, there is an array of EPs in the PCD
51265 +typedef struct dwc_otg_pcd_ep {
51266 + /** USB EP Descriptor */
51267 + const usb_endpoint_descriptor_t *desc;
51269 + /** queue of dwc_otg_pcd_requests. */
51270 + struct req_list queue;
51271 + unsigned stopped:1;
51272 + unsigned disabling:1;
51274 + unsigned queue_sof:1;
51276 +#ifdef DWC_EN_ISOC
51277 + /** ISOC req handle passed */
51278 + void *iso_req_handle;
51279 +#endif //_EN_ISOC_
51281 + /** DWC_otg ep data. */
51284 + /** Pointer to PCD */
51285 + struct dwc_otg_pcd *pcd;
51288 +} dwc_otg_pcd_ep_t;
51290 +/** DWC_otg PCD Structure.
51291 + * This structure encapsulates the data for the dwc_otg PCD.
51293 +struct dwc_otg_pcd {
51294 + const struct dwc_otg_pcd_function_ops *fops;
51295 + /** The DWC otg device pointer */
51296 + struct dwc_otg_device *otg_dev;
51297 + /** Core Interface */
51298 + dwc_otg_core_if_t *core_if;
51299 + /** State of EP0 */
51300 + ep0state_e ep0state;
51301 + /** EP0 Request is pending */
51302 + unsigned ep0_pending:1;
51303 + /** Indicates when SET CONFIGURATION Request is in process */
51304 + unsigned request_config:1;
51305 + /** The state of the Remote Wakeup Enable. */
51306 + unsigned remote_wakeup_enable:1;
51307 + /** The state of the B-Device HNP Enable. */
51308 + unsigned b_hnp_enable:1;
51309 + /** The state of A-Device HNP Support. */
51310 + unsigned a_hnp_support:1;
51311 + /** The state of the A-Device Alt HNP support. */
51312 + unsigned a_alt_hnp_support:1;
51313 + /** Count of pending Requests */
51314 + unsigned request_pending;
51316 + /** SETUP packet for EP0
51317 + * This structure is allocated as a DMA buffer on PCD initialization
51318 + * with enough space for up to 3 setup packets.
51321 + usb_device_request_t req;
51325 + dwc_dma_t setup_pkt_dma_handle;
51327 + /* Additional buffer and flag for CTRL_WR premature case */
51328 + uint8_t *backup_buf;
51329 + unsigned data_terminated;
51331 + /** 2-byte dma buffer used to return status from GET_STATUS */
51332 + uint16_t *status_buf;
51333 + dwc_dma_t status_buf_dma_handle;
51336 + dwc_otg_pcd_ep_t ep0;
51338 + /** Array of IN EPs. */
51339 + dwc_otg_pcd_ep_t in_ep[MAX_EPS_CHANNELS - 1];
51340 + /** Array of OUT EPs. */
51341 + dwc_otg_pcd_ep_t out_ep[MAX_EPS_CHANNELS - 1];
51342 + /** number of valid EPs in the above array. */
51343 +// unsigned num_eps : 4;
51344 + dwc_spinlock_t *lock;
51346 + /** Tasklet to defer starting of TEST mode transmissions until
51347 + * Status Phase has been completed.
51349 + dwc_tasklet_t *test_mode_tasklet;
51351 + /** Tasklet to delay starting of xfer in DMA mode */
51352 + dwc_tasklet_t *start_xfer_tasklet;
51354 + /** The test mode to enter when the tasklet is executed. */
51355 + unsigned test_mode;
51356 + /** The cfi_api structure that implements most of the CFI API
51357 + * and OTG specific core configuration functionality
51359 +#ifdef DWC_UTE_CFI
51360 + struct cfiobject *cfi;
51365 +static inline struct device *dwc_otg_pcd_to_dev(struct dwc_otg_pcd *pcd)
51367 + return &pcd->otg_dev->os_dep.platformdev->dev;
51370 +//FIXME this functions should be static, and this prototypes should be removed
51371 +extern void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep);
51372 +extern void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep,
51373 + dwc_otg_pcd_request_t * req, int32_t status);
51375 +void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
51376 + void *req_handle);
51378 +extern void do_test_mode(void *data);
51380 +#endif /* DWC_HOST_ONLY */
51382 +++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h
51384 +/* ==========================================================================
51385 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_if.h $
51386 + * $Revision: #11 $
51387 + * $Date: 2011/10/26 $
51388 + * $Change: 1873028 $
51390 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
51391 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
51392 + * otherwise expressly agreed to in writing between Synopsys and you.
51394 + * The Software IS NOT an item of Licensed Software or Licensed Product under
51395 + * any End User Software License Agreement or Agreement for Licensed Product
51396 + * with Synopsys or any supplement thereto. You are permitted to use and
51397 + * redistribute this Software in source and binary forms, with or without
51398 + * modification, provided that redistributions of source code must retain this
51399 + * notice. You may not view, use, disclose, copy or distribute this file or
51400 + * any information contained herein except pursuant to this license grant from
51401 + * Synopsys. If you do not agree with this notice, including the disclaimer
51402 + * below, then you are not authorized to use the Software.
51404 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
51405 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
51406 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
51407 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
51408 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
51409 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
51410 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
51411 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
51412 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
51413 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
51415 + * ========================================================================== */
51416 +#ifndef DWC_HOST_ONLY
51418 +#if !defined(__DWC_PCD_IF_H__)
51419 +#define __DWC_PCD_IF_H__
51421 +//#include "dwc_os.h"
51422 +#include "dwc_otg_core_if.h"
51423 +#include "dwc_otg_driver.h"
51426 + * This file defines DWC_OTG PCD Core API.
51429 +struct dwc_otg_pcd;
51430 +typedef struct dwc_otg_pcd dwc_otg_pcd_t;
51432 +/** Maxpacket size for EP0 */
51433 +#define MAX_EP0_SIZE 64
51434 +/** Maxpacket size for any EP */
51435 +#define MAX_PACKET_SIZE 1024
51437 +/** @name Function Driver Callbacks */
51440 +/** This function will be called whenever a previously queued request has
51441 + * completed. The status value will be set to -DWC_E_SHUTDOWN to indicated a
51442 + * failed or aborted transfer, or -DWC_E_RESTART to indicate the device was reset,
51443 + * or -DWC_E_TIMEOUT to indicate it timed out, or -DWC_E_INVALID to indicate invalid
51445 +typedef int (*dwc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
51446 + void *req_handle, int32_t status,
51447 + uint32_t actual);
51449 + * This function will be called whenever a previousle queued ISOC request has
51450 + * completed. Count of ISOC packets could be read using dwc_otg_pcd_get_iso_packet_count
51452 + * The status of each ISOC packet could be read using dwc_otg_pcd_get_iso_packet_*
51455 +typedef int (*dwc_isoc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
51456 + void *req_handle, int proc_buf_num);
51457 +/** This function should handle any SETUP request that cannot be handled by the
51458 + * PCD Core. This includes most GET_DESCRIPTORs, SET_CONFIGS, Any
51459 + * class-specific requests, etc. The function must non-blocking.
51461 + * Returns 0 on success.
51462 + * Returns -DWC_E_NOT_SUPPORTED if the request is not supported.
51463 + * Returns -DWC_E_INVALID if the setup request had invalid parameters or bytes.
51464 + * Returns -DWC_E_SHUTDOWN on any other error. */
51465 +typedef int (*dwc_setup_cb_t) (dwc_otg_pcd_t * pcd, uint8_t * bytes);
51466 +/** This is called whenever the device has been disconnected. The function
51467 + * driver should take appropriate action to clean up all pending requests in the
51468 + * PCD Core, remove all endpoints (except ep0), and initialize back to reset
51470 +typedef int (*dwc_disconnect_cb_t) (dwc_otg_pcd_t * pcd);
51471 +/** This function is called when device has been connected. */
51472 +typedef int (*dwc_connect_cb_t) (dwc_otg_pcd_t * pcd, int speed);
51473 +/** This function is called when device has been suspended */
51474 +typedef int (*dwc_suspend_cb_t) (dwc_otg_pcd_t * pcd);
51475 +/** This function is called when device has received LPM tokens, i.e.
51476 + * device has been sent to sleep state. */
51477 +typedef int (*dwc_sleep_cb_t) (dwc_otg_pcd_t * pcd);
51478 +/** This function is called when device has been resumed
51479 + * from suspend(L2) or L1 sleep state. */
51480 +typedef int (*dwc_resume_cb_t) (dwc_otg_pcd_t * pcd);
51481 +/** This function is called whenever hnp params has been changed.
51482 + * User can call get_b_hnp_enable, get_a_hnp_support, get_a_alt_hnp_support functions
51483 + * to get hnp parameters. */
51484 +typedef int (*dwc_hnp_params_changed_cb_t) (dwc_otg_pcd_t * pcd);
51485 +/** This function is called whenever USB RESET is detected. */
51486 +typedef int (*dwc_reset_cb_t) (dwc_otg_pcd_t * pcd);
51488 +typedef int (*cfi_setup_cb_t) (dwc_otg_pcd_t * pcd, void *ctrl_req_bytes);
51492 + * @param ep_handle Void pointer to the usb_ep structure
51493 + * @param ereq_port Pointer to the extended request structure created in the
51496 +typedef int (*xiso_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
51497 + void *req_handle, int32_t status,
51498 + void *ereq_port);
51499 +/** Function Driver Ops Data Structure */
51500 +struct dwc_otg_pcd_function_ops {
51501 + dwc_connect_cb_t connect;
51502 + dwc_disconnect_cb_t disconnect;
51503 + dwc_setup_cb_t setup;
51504 + dwc_completion_cb_t complete;
51505 + dwc_isoc_completion_cb_t isoc_complete;
51506 + dwc_suspend_cb_t suspend;
51507 + dwc_sleep_cb_t sleep;
51508 + dwc_resume_cb_t resume;
51509 + dwc_reset_cb_t reset;
51510 + dwc_hnp_params_changed_cb_t hnp_changed;
51511 + cfi_setup_cb_t cfi_setup;
51512 +#ifdef DWC_UTE_PER_IO
51513 + xiso_completion_cb_t xisoc_complete;
51518 +/** @name Function Driver Functions */
51521 +/** Call this function to get pointer on dwc_otg_pcd_t,
51522 + * this pointer will be used for all PCD API functions.
51524 + * @param core_if The DWC_OTG Core
51526 +extern dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_device_t *otg_dev);
51528 +/** Frees PCD allocated by dwc_otg_pcd_init
51530 + * @param pcd The PCD
51532 +extern void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd);
51534 +/** Call this to bind the function driver to the PCD Core.
51536 + * @param pcd Pointer on dwc_otg_pcd_t returned by dwc_otg_pcd_init function.
51537 + * @param fops The Function Driver Ops data structure containing pointers to all callbacks.
51539 +extern void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
51540 + const struct dwc_otg_pcd_function_ops *fops);
51542 +/** Enables an endpoint for use. This function enables an endpoint in
51543 + * the PCD. The endpoint is described by the ep_desc which has the
51544 + * same format as a USB ep descriptor. The ep_handle parameter is used to refer
51545 + * to the endpoint from other API functions and in callbacks. Normally this
51546 + * should be called after a SET_CONFIGURATION/SET_INTERFACE to configure the
51547 + * core for that interface.
51549 + * Returns -DWC_E_INVALID if invalid parameters were passed.
51550 + * Returns -DWC_E_SHUTDOWN if any other error ocurred.
51551 + * Returns 0 on success.
51553 + * @param pcd The PCD
51554 + * @param ep_desc Endpoint descriptor
51555 + * @param usb_ep Handle on endpoint, that will be used to identify endpoint.
51557 +extern int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
51558 + const uint8_t * ep_desc, void *usb_ep);
51560 +/** Disable the endpoint referenced by ep_handle.
51562 + * Returns -DWC_E_INVALID if invalid parameters were passed.
51563 + * Returns -DWC_E_SHUTDOWN if any other error occurred.
51564 + * Returns 0 on success. */
51565 +extern int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle);
51567 +/** Queue a data transfer request on the endpoint referenced by ep_handle.
51568 + * After the transfer is completes, the complete callback will be called with
51569 + * the request status.
51571 + * @param pcd The PCD
51572 + * @param ep_handle The handle of the endpoint
51573 + * @param buf The buffer for the data
51574 + * @param dma_buf The DMA buffer for the data
51575 + * @param buflen The length of the data transfer
51576 + * @param zero Specifies whether to send zero length last packet.
51577 + * @param req_handle Set this handle to any value to use to reference this
51578 + * request in the ep_dequeue function or from the complete callback
51579 + * @param atomic_alloc If driver need to perform atomic allocations
51580 + * for internal data structures.
51582 + * Returns -DWC_E_INVALID if invalid parameters were passed.
51583 + * Returns -DWC_E_SHUTDOWN if any other error ocurred.
51584 + * Returns 0 on success. */
51585 +extern int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
51586 + uint8_t * buf, dwc_dma_t dma_buf,
51587 + uint32_t buflen, int zero, void *req_handle,
51588 + int atomic_alloc);
51589 +#ifdef DWC_UTE_PER_IO
51592 + * @param ereq_nonport Pointer to the extended request part of the
51593 + * usb_request structure defined in usb_gadget.h file.
51595 +extern int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
51596 + uint8_t * buf, dwc_dma_t dma_buf,
51597 + uint32_t buflen, int zero,
51598 + void *req_handle, int atomic_alloc,
51599 + void *ereq_nonport);
51603 +/** De-queue the specified data transfer that has not yet completed.
51605 + * Returns -DWC_E_INVALID if invalid parameters were passed.
51606 + * Returns -DWC_E_SHUTDOWN if any other error ocurred.
51607 + * Returns 0 on success. */
51608 +extern int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
51609 + void *req_handle);
51611 +/** Halt (STALL) an endpoint or clear it.
51613 + * Returns -DWC_E_INVALID if invalid parameters were passed.
51614 + * Returns -DWC_E_SHUTDOWN if any other error ocurred.
51615 + * Returns -DWC_E_AGAIN if the STALL cannot be sent and must be tried again later
51616 + * Returns 0 on success. */
51617 +extern int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value);
51619 +/** This function */
51620 +extern int dwc_otg_pcd_ep_wedge(dwc_otg_pcd_t * pcd, void *ep_handle);
51622 +/** This function should be called on every hardware interrupt */
51623 +extern int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd);
51625 +/** This function returns current frame number */
51626 +extern int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd);
51629 + * Start isochronous transfers on the endpoint referenced by ep_handle.
51630 + * For isochronous transfers duble buffering is used.
51631 + * After processing each of buffers comlete callback will be called with
51632 + * status for each transaction.
51634 + * @param pcd The PCD
51635 + * @param ep_handle The handle of the endpoint
51636 + * @param buf0 The virtual address of first data buffer
51637 + * @param buf1 The virtual address of second data buffer
51638 + * @param dma0 The DMA address of first data buffer
51639 + * @param dma1 The DMA address of second data buffer
51640 + * @param sync_frame Data pattern frame number
51641 + * @param dp_frame Data size for pattern frame
51642 + * @param data_per_frame Data size for regular frame
51643 + * @param start_frame Frame number to start transfers, if -1 then start transfers ASAP.
51644 + * @param buf_proc_intrvl Interval of ISOC Buffer processing
51645 + * @param req_handle Handle of ISOC request
51646 + * @param atomic_alloc Specefies whether to perform atomic allocation for
51647 + * internal data structures.
51649 + * Returns -DWC_E_NO_MEMORY if there is no enough memory.
51650 + * Returns -DWC_E_INVALID if incorrect arguments are passed to the function.
51651 + * Returns -DW_E_SHUTDOWN for any other error.
51652 + * Returns 0 on success
51654 +extern int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
51655 + uint8_t * buf0, uint8_t * buf1,
51656 + dwc_dma_t dma0, dwc_dma_t dma1,
51657 + int sync_frame, int dp_frame,
51658 + int data_per_frame, int start_frame,
51659 + int buf_proc_intrvl, void *req_handle,
51660 + int atomic_alloc);
51662 +/** Stop ISOC transfers on endpoint referenced by ep_handle.
51664 + * @param pcd The PCD
51665 + * @param ep_handle The handle of the endpoint
51666 + * @param req_handle Handle of ISOC request
51668 + * Returns -DWC_E_INVALID if incorrect arguments are passed to the function
51669 + * Returns 0 on success
51671 +int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
51672 + void *req_handle);
51674 +/** Get ISOC packet status.
51676 + * @param pcd The PCD
51677 + * @param ep_handle The handle of the endpoint
51678 + * @param iso_req_handle Isochronoush request handle
51679 + * @param packet Number of packet
51680 + * @param status Out parameter for returning status
51681 + * @param actual Out parameter for returning actual length
51682 + * @param offset Out parameter for returning offset
51685 +extern void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd,
51687 + void *iso_req_handle, int packet,
51688 + int *status, int *actual,
51691 +/** Get ISOC packet count.
51693 + * @param pcd The PCD
51694 + * @param ep_handle The handle of the endpoint
51695 + * @param iso_req_handle
51697 +extern int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd,
51699 + void *iso_req_handle);
51701 +/** This function starts the SRP Protocol if no session is in progress. If
51702 + * a session is already in progress, but the device is suspended,
51703 + * remote wakeup signaling is started.
51705 +extern int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd);
51707 +/** This function returns 1 if LPM support is enabled, and 0 otherwise. */
51708 +extern int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd);
51710 +/** This function returns 1 if remote wakeup is allowed and 0, otherwise. */
51711 +extern int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd);
51713 +/** Initiate SRP */
51714 +extern void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd);
51716 +/** Starts remote wakeup signaling. */
51717 +extern void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set);
51719 +/** Starts micorsecond soft disconnect. */
51720 +extern void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs);
51721 +/** This function returns whether device is dualspeed.*/
51722 +extern uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd);
51724 +/** This function returns whether device is otg. */
51725 +extern uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd);
51727 +/** These functions allow to get hnp parameters */
51728 +extern uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd);
51729 +extern uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd);
51730 +extern uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd);
51732 +/** CFI specific Interface functions */
51733 +/** Allocate a cfi buffer */
51734 +extern uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep,
51735 + dwc_dma_t * addr, size_t buflen,
51738 +/******************************************************************************/
51742 +#endif /* __DWC_PCD_IF_H__ */
51744 +#endif /* DWC_HOST_ONLY */
51746 +++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c
51748 +/* ==========================================================================
51749 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_intr.c $
51750 + * $Revision: #116 $
51751 + * $Date: 2012/08/10 $
51752 + * $Change: 2047372 $
51754 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
51755 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
51756 + * otherwise expressly agreed to in writing between Synopsys and you.
51758 + * The Software IS NOT an item of Licensed Software or Licensed Product under
51759 + * any End User Software License Agreement or Agreement for Licensed Product
51760 + * with Synopsys or any supplement thereto. You are permitted to use and
51761 + * redistribute this Software in source and binary forms, with or without
51762 + * modification, provided that redistributions of source code must retain this
51763 + * notice. You may not view, use, disclose, copy or distribute this file or
51764 + * any information contained herein except pursuant to this license grant from
51765 + * Synopsys. If you do not agree with this notice, including the disclaimer
51766 + * below, then you are not authorized to use the Software.
51768 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
51769 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
51770 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
51771 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
51772 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
51773 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
51774 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
51775 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
51776 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
51777 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
51779 + * ========================================================================== */
51780 +#ifndef DWC_HOST_ONLY
51782 +#include "dwc_otg_pcd.h"
51784 +#ifdef DWC_UTE_CFI
51785 +#include "dwc_otg_cfi.h"
51788 +#ifdef DWC_UTE_PER_IO
51789 +extern void complete_xiso_ep(dwc_otg_pcd_ep_t * ep);
51791 +//#define PRINT_CFI_DMA_DESCS
51796 + * This function updates OTG.
51798 +static void dwc_otg_pcd_update_otg(dwc_otg_pcd_t * pcd, const unsigned reset)
51802 + pcd->b_hnp_enable = 0;
51803 + pcd->a_hnp_support = 0;
51804 + pcd->a_alt_hnp_support = 0;
51807 + if (pcd->fops->hnp_changed) {
51808 + pcd->fops->hnp_changed(pcd);
51813 + * This file contains the implementation of the PCD Interrupt handlers.
51815 + * The PCD handles the device interrupts. Many conditions can cause a
51816 + * device interrupt. When an interrupt occurs, the device interrupt
51817 + * service routine determines the cause of the interrupt and
51818 + * dispatches handling to the appropriate function. These interrupt
51819 + * handling functions are described below.
51820 + * All interrupt registers are processed from LSB to MSB.
51824 + * This function prints the ep0 state for debug purposes.
51826 +static inline void print_ep0_state(dwc_otg_pcd_t * pcd)
51831 + switch (pcd->ep0state) {
51832 + case EP0_DISCONNECT:
51833 + dwc_strcpy(str, "EP0_DISCONNECT");
51836 + dwc_strcpy(str, "EP0_IDLE");
51838 + case EP0_IN_DATA_PHASE:
51839 + dwc_strcpy(str, "EP0_IN_DATA_PHASE");
51841 + case EP0_OUT_DATA_PHASE:
51842 + dwc_strcpy(str, "EP0_OUT_DATA_PHASE");
51844 + case EP0_IN_STATUS_PHASE:
51845 + dwc_strcpy(str, "EP0_IN_STATUS_PHASE");
51847 + case EP0_OUT_STATUS_PHASE:
51848 + dwc_strcpy(str, "EP0_OUT_STATUS_PHASE");
51851 + dwc_strcpy(str, "EP0_STALL");
51854 + dwc_strcpy(str, "EP0_INVALID");
51857 + DWC_DEBUGPL(DBG_ANY, "%s(%d)\n", str, pcd->ep0state);
51862 + * This function calculate the size of the payload in the memory
51863 + * for out endpoints and prints size for debug purposes(used in
51864 + * 2.93a DevOutNak feature).
51866 +static inline void print_memory_payload(dwc_otg_pcd_t * pcd, dwc_ep_t * ep)
51869 + deptsiz_data_t deptsiz_init = {.d32 = 0 };
51870 + deptsiz_data_t deptsiz_updt = {.d32 = 0 };
51872 + unsigned payload;
51874 + deptsiz_init.d32 = pcd->core_if->start_doeptsiz_val[ep->num];
51875 + deptsiz_updt.d32 =
51876 + DWC_READ_REG32(&pcd->core_if->dev_if->
51877 + out_ep_regs[ep->num]->doeptsiz);
51878 + /* Payload will be */
51879 + payload = deptsiz_init.b.xfersize - deptsiz_updt.b.xfersize;
51880 + /* Packet count is decremented every time a packet
51881 + * is written to the RxFIFO not in to the external memory
51882 + * So, if payload == 0, then it means no packet was sent to ext memory*/
51883 + pack_num = (!payload) ? 0 : (deptsiz_init.b.pktcnt - deptsiz_updt.b.pktcnt);
51884 + DWC_DEBUGPL(DBG_PCDV,
51885 + "Payload for EP%d-%s\n",
51886 + ep->num, (ep->is_in ? "IN" : "OUT"));
51887 + DWC_DEBUGPL(DBG_PCDV,
51888 + "Number of transfered bytes = 0x%08x\n", payload);
51889 + DWC_DEBUGPL(DBG_PCDV,
51890 + "Number of transfered packets = %d\n", pack_num);
51895 +#ifdef DWC_UTE_CFI
51896 +static inline void print_desc(struct dwc_otg_dma_desc *ddesc,
51897 + const uint8_t * epname, int descnum)
51900 + ("%s DMA_DESC(%d) buf=0x%08x bytes=0x%04x; sp=0x%x; l=0x%x; sts=0x%02x; bs=0x%02x\n",
51901 + epname, descnum, ddesc->buf, ddesc->status.b.bytes,
51902 + ddesc->status.b.sp, ddesc->status.b.l, ddesc->status.b.sts,
51903 + ddesc->status.b.bs);
51908 + * This function returns pointer to in ep struct with number ep_num
51910 +static inline dwc_otg_pcd_ep_t *get_in_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)
51913 + int num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
51914 + if (ep_num == 0) {
51915 + return &pcd->ep0;
51917 + for (i = 0; i < num_in_eps; ++i) {
51918 + if (pcd->in_ep[i].dwc_ep.num == ep_num)
51919 + return &pcd->in_ep[i];
51926 + * This function returns pointer to out ep struct with number ep_num
51928 +static inline dwc_otg_pcd_ep_t *get_out_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)
51931 + int num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
51932 + if (ep_num == 0) {
51933 + return &pcd->ep0;
51935 + for (i = 0; i < num_out_eps; ++i) {
51936 + if (pcd->out_ep[i].dwc_ep.num == ep_num)
51937 + return &pcd->out_ep[i];
51944 + * This functions gets a pointer to an EP from the wIndex address
51945 + * value of the control request.
51947 +dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex)
51949 + dwc_otg_pcd_ep_t *ep;
51950 + uint32_t ep_num = UE_GET_ADDR(wIndex);
51952 + if (ep_num == 0) {
51954 + } else if (UE_GET_DIR(wIndex) == UE_DIR_IN) { /* in ep */
51955 + ep = &pcd->in_ep[ep_num - 1];
51957 + ep = &pcd->out_ep[ep_num - 1];
51964 + * This function checks the EP request queue, if the queue is not
51965 + * empty the next request is started.
51967 +void start_next_request(dwc_otg_pcd_ep_t * ep)
51969 + dwc_otg_pcd_request_t *req = 0;
51970 + uint32_t max_transfer =
51971 + GET_CORE_IF(ep->pcd)->core_params->max_transfer_size;
51973 +#ifdef DWC_UTE_CFI
51974 + struct dwc_otg_pcd *pcd;
51978 + if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
51979 + req = DWC_CIRCLEQ_FIRST(&ep->queue);
51981 +#ifdef DWC_UTE_CFI
51982 + if (ep->dwc_ep.buff_mode != BM_STANDARD) {
51983 + ep->dwc_ep.cfi_req_len = req->length;
51984 + pcd->cfi->ops.build_descriptors(pcd->cfi, pcd, ep, req);
51987 + /* Setup and start the Transfer */
51988 + if (req->dw_align_buf) {
51989 + ep->dwc_ep.dma_addr = req->dw_align_buf_dma;
51990 + ep->dwc_ep.start_xfer_buff = req->dw_align_buf;
51991 + ep->dwc_ep.xfer_buff = req->dw_align_buf;
51993 + ep->dwc_ep.dma_addr = req->dma;
51994 + ep->dwc_ep.start_xfer_buff = req->buf;
51995 + ep->dwc_ep.xfer_buff = req->buf;
51997 + ep->dwc_ep.sent_zlp = 0;
51998 + ep->dwc_ep.total_len = req->length;
51999 + ep->dwc_ep.xfer_len = 0;
52000 + ep->dwc_ep.xfer_count = 0;
52002 + ep->dwc_ep.maxxfer = max_transfer;
52003 + if (GET_CORE_IF(ep->pcd)->dma_desc_enable) {
52004 + uint32_t out_max_xfer = DDMA_MAX_TRANSFER_SIZE
52005 + - (DDMA_MAX_TRANSFER_SIZE % 4);
52006 + if (ep->dwc_ep.is_in) {
52007 + if (ep->dwc_ep.maxxfer >
52008 + DDMA_MAX_TRANSFER_SIZE) {
52009 + ep->dwc_ep.maxxfer =
52010 + DDMA_MAX_TRANSFER_SIZE;
52013 + if (ep->dwc_ep.maxxfer > out_max_xfer) {
52014 + ep->dwc_ep.maxxfer =
52019 + if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) {
52020 + ep->dwc_ep.maxxfer -=
52021 + (ep->dwc_ep.maxxfer % ep->dwc_ep.maxpacket);
52023 + if (req->sent_zlp) {
52024 + if ((ep->dwc_ep.total_len %
52025 + ep->dwc_ep.maxpacket == 0)
52026 + && (ep->dwc_ep.total_len != 0)) {
52027 + ep->dwc_ep.sent_zlp = 1;
52031 +#ifdef DWC_UTE_CFI
52034 + dwc_otg_ep_start_transfer(GET_CORE_IF(ep->pcd), &ep->dwc_ep);
52035 + } else if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
52036 + DWC_PRINTF("There are no more ISOC requests \n");
52037 + ep->dwc_ep.frame_num = 0xFFFFFFFF;
52042 + * This function handles the SOF Interrupts. At this time the SOF
52043 + * Interrupt is disabled.
52045 +int32_t dwc_otg_pcd_handle_sof_intr(dwc_otg_pcd_t * pcd)
52047 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
52049 + gintsts_data_t gintsts;
52051 + DWC_DEBUGPL(DBG_PCD, "SOF\n");
52053 + /* Clear interrupt */
52055 + gintsts.b.sofintr = 1;
52056 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
52062 + * This function handles the Rx Status Queue Level Interrupt, which
52063 + * indicates that there is a least one packet in the Rx FIFO. The
52064 + * packets are moved from the FIFO to memory, where they will be
52065 + * processed when the Endpoint Interrupt Register indicates Transfer
52066 + * Complete or SETUP Phase Done.
52068 + * Repeat the following until the Rx Status Queue is empty:
52069 + * -# Read the Receive Status Pop Register (GRXSTSP) to get Packet
52071 + * -# If Receive FIFO is empty then skip to step Clear the interrupt
52073 + * -# If SETUP Packet call dwc_otg_read_setup_packet to copy the
52074 + * SETUP data to the buffer
52075 + * -# If OUT Data Packet call dwc_otg_read_packet to copy the data
52076 + * to the destination buffer
52078 +int32_t dwc_otg_pcd_handle_rx_status_q_level_intr(dwc_otg_pcd_t * pcd)
52080 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
52081 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
52082 + gintmsk_data_t gintmask = {.d32 = 0 };
52083 + device_grxsts_data_t status;
52084 + dwc_otg_pcd_ep_t *ep;
52085 + gintsts_data_t gintsts;
52087 + static char *dpid_str[] = { "D0", "D2", "D1", "MDATA" };
52090 + //DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _pcd);
52091 + /* Disable the Rx Status Queue Level interrupt */
52092 + gintmask.b.rxstsqlvl = 1;
52093 + DWC_MODIFY_REG32(&global_regs->gintmsk, gintmask.d32, 0);
52095 + /* Get the Status from the top of the FIFO */
52096 + status.d32 = DWC_READ_REG32(&global_regs->grxstsp);
52098 + DWC_DEBUGPL(DBG_PCD, "EP:%d BCnt:%d DPID:%s "
52099 + "pktsts:%x Frame:%d(0x%0x)\n",
52100 + status.b.epnum, status.b.bcnt,
52101 + dpid_str[status.b.dpid],
52102 + status.b.pktsts, status.b.fn, status.b.fn);
52103 + /* Get pointer to EP structure */
52104 + ep = get_out_ep(pcd, status.b.epnum);
52106 + switch (status.b.pktsts) {
52107 + case DWC_DSTS_GOUT_NAK:
52108 + DWC_DEBUGPL(DBG_PCDV, "Global OUT NAK\n");
52110 + case DWC_STS_DATA_UPDT:
52111 + DWC_DEBUGPL(DBG_PCDV, "OUT Data Packet\n");
52112 + if (status.b.bcnt && ep->dwc_ep.xfer_buff) {
52113 + /** @todo NGS Check for buffer overflow? */
52114 + dwc_otg_read_packet(core_if,
52115 + ep->dwc_ep.xfer_buff,
52117 + ep->dwc_ep.xfer_count += status.b.bcnt;
52118 + ep->dwc_ep.xfer_buff += status.b.bcnt;
52121 + case DWC_STS_XFER_COMP:
52122 + DWC_DEBUGPL(DBG_PCDV, "OUT Complete\n");
52124 + case DWC_DSTS_SETUP_COMP:
52126 + DWC_DEBUGPL(DBG_PCDV, "Setup Complete\n");
52129 + case DWC_DSTS_SETUP_UPDT:
52130 + dwc_otg_read_setup_packet(core_if, pcd->setup_pkt->d32);
52132 + DWC_DEBUGPL(DBG_PCD,
52133 + "SETUP PKT: %02x.%02x v%04x i%04x l%04x\n",
52134 + pcd->setup_pkt->req.bmRequestType,
52135 + pcd->setup_pkt->req.bRequest,
52136 + UGETW(pcd->setup_pkt->req.wValue),
52137 + UGETW(pcd->setup_pkt->req.wIndex),
52138 + UGETW(pcd->setup_pkt->req.wLength));
52140 + ep->dwc_ep.xfer_count += status.b.bcnt;
52143 + DWC_DEBUGPL(DBG_PCDV, "Invalid Packet Status (0x%0x)\n",
52144 + status.b.pktsts);
52148 + /* Enable the Rx Status Queue Level interrupt */
52149 + DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmask.d32);
52150 + /* Clear interrupt */
52152 + gintsts.b.rxstsqlvl = 1;
52153 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
52155 + //DWC_DEBUGPL(DBG_PCDV, "EXIT: %s\n", __func__);
52160 + * This function examines the Device IN Token Learning Queue to
52161 + * determine the EP number of the last IN token received. This
52162 + * implementation is for the Mass Storage device where there are only
52163 + * 2 IN EPs (Control-IN and BULK-IN).
52165 + * The EP numbers for the first six IN Tokens are in DTKNQR1 and there
52166 + * are 8 EP Numbers in each of the other possible DTKNQ Registers.
52168 + * @param core_if Programming view of DWC_otg controller.
52171 +static inline int get_ep_of_last_in_token(dwc_otg_core_if_t * core_if)
52173 + dwc_otg_device_global_regs_t *dev_global_regs =
52174 + core_if->dev_if->dev_global_regs;
52175 + const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;
52176 + /* Number of Token Queue Registers */
52177 + const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
52178 + dtknq1_data_t dtknqr1;
52179 + uint32_t in_tkn_epnums[4];
52182 + volatile uint32_t *addr = &dev_global_regs->dtknqr1;
52185 + //DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);
52187 + /* Read the DTKNQ Registers */
52188 + for (i = 0; i < DTKNQ_REG_CNT; i++) {
52189 + in_tkn_epnums[i] = DWC_READ_REG32(addr);
52190 + DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1,
52191 + in_tkn_epnums[i]);
52192 + if (addr == &dev_global_regs->dvbusdis) {
52193 + addr = &dev_global_regs->dtknqr3_dthrctl;
52200 + /* Copy the DTKNQR1 data to the bit field. */
52201 + dtknqr1.d32 = in_tkn_epnums[0];
52202 + /* Get the EP numbers */
52203 + in_tkn_epnums[0] = dtknqr1.b.epnums0_5;
52204 + ndx = dtknqr1.b.intknwptr - 1;
52206 + //DWC_DEBUGPL(DBG_PCDV,"ndx=%d\n",ndx);
52208 + /** @todo Find a simpler way to calculate the max
52209 + * queue position.*/
52210 + int cnt = TOKEN_Q_DEPTH;
52211 + if (TOKEN_Q_DEPTH <= 6) {
52212 + cnt = TOKEN_Q_DEPTH - 1;
52213 + } else if (TOKEN_Q_DEPTH <= 14) {
52214 + cnt = TOKEN_Q_DEPTH - 7;
52215 + } else if (TOKEN_Q_DEPTH <= 22) {
52216 + cnt = TOKEN_Q_DEPTH - 15;
52218 + cnt = TOKEN_Q_DEPTH - 23;
52220 + epnum = (in_tkn_epnums[DTKNQ_REG_CNT - 1] >> (cnt * 4)) & 0xF;
52223 + epnum = (in_tkn_epnums[0] >> (ndx * 4)) & 0xF;
52224 + } else if (ndx <= 13) {
52226 + epnum = (in_tkn_epnums[1] >> (ndx * 4)) & 0xF;
52227 + } else if (ndx <= 21) {
52229 + epnum = (in_tkn_epnums[2] >> (ndx * 4)) & 0xF;
52230 + } else if (ndx <= 29) {
52232 + epnum = (in_tkn_epnums[3] >> (ndx * 4)) & 0xF;
52235 + //DWC_DEBUGPL(DBG_PCD,"epnum=%d\n",epnum);
52240 + * This interrupt occurs when the non-periodic Tx FIFO is half-empty.
52241 + * The active request is checked for the next packet to be loaded into
52242 + * the non-periodic Tx FIFO.
52244 +int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr(dwc_otg_pcd_t * pcd)
52246 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
52247 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
52248 + dwc_otg_dev_in_ep_regs_t *ep_regs;
52249 + gnptxsts_data_t txstatus = {.d32 = 0 };
52250 + gintsts_data_t gintsts;
52253 + dwc_otg_pcd_ep_t *ep = 0;
52254 + uint32_t len = 0;
52257 + /* Get the epnum from the IN Token Learning Queue. */
52258 + epnum = get_ep_of_last_in_token(core_if);
52259 + ep = get_in_ep(pcd, epnum);
52261 + DWC_DEBUGPL(DBG_PCD, "NP TxFifo Empty: %d \n", epnum);
52263 + ep_regs = core_if->dev_if->in_ep_regs[epnum];
52265 + len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
52266 + if (len > ep->dwc_ep.maxpacket) {
52267 + len = ep->dwc_ep.maxpacket;
52269 + dwords = (len + 3) / 4;
52271 + /* While there is space in the queue and space in the FIFO and
52272 + * More data to tranfer, Write packets to the Tx FIFO */
52273 + txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
52274 + DWC_DEBUGPL(DBG_PCDV, "b4 GNPTXSTS=0x%08x\n", txstatus.d32);
52276 + while (txstatus.b.nptxqspcavail > 0 &&
52277 + txstatus.b.nptxfspcavail > dwords &&
52278 + ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len) {
52279 + /* Write the FIFO */
52280 + dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
52281 + len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
52283 + if (len > ep->dwc_ep.maxpacket) {
52284 + len = ep->dwc_ep.maxpacket;
52287 + dwords = (len + 3) / 4;
52288 + txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
52289 + DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n", txstatus.d32);
52292 + DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n",
52293 + DWC_READ_REG32(&global_regs->gnptxsts));
52295 + /* Clear interrupt */
52297 + gintsts.b.nptxfempty = 1;
52298 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
52304 + * This function is called when dedicated Tx FIFO Empty interrupt occurs.
52305 + * The active request is checked for the next packet to be loaded into
52306 + * apropriate Tx FIFO.
52308 +static int32_t write_empty_tx_fifo(dwc_otg_pcd_t * pcd, uint32_t epnum)
52310 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
52311 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
52312 + dwc_otg_dev_in_ep_regs_t *ep_regs;
52313 + dtxfsts_data_t txstatus = {.d32 = 0 };
52314 + dwc_otg_pcd_ep_t *ep = 0;
52315 + uint32_t len = 0;
52318 + ep = get_in_ep(pcd, epnum);
52320 + DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum);
52322 + ep_regs = core_if->dev_if->in_ep_regs[epnum];
52324 + len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
52326 + if (len > ep->dwc_ep.maxpacket) {
52327 + len = ep->dwc_ep.maxpacket;
52330 + dwords = (len + 3) / 4;
52332 + /* While there is space in the queue and space in the FIFO and
52333 + * More data to tranfer, Write packets to the Tx FIFO */
52334 + txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
52335 + DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
52337 + while (txstatus.b.txfspcavail > dwords &&
52338 + ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len &&
52339 + ep->dwc_ep.xfer_len != 0) {
52340 + /* Write the FIFO */
52341 + dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
52343 + len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
52344 + if (len > ep->dwc_ep.maxpacket) {
52345 + len = ep->dwc_ep.maxpacket;
52348 + dwords = (len + 3) / 4;
52350 + DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
52351 + DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum,
52355 + DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum,
52356 + DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts));
52362 + * This function is called when the Device is disconnected. It stops
52363 + * any active requests and informs the Gadget driver of the
52366 +void dwc_otg_pcd_stop(dwc_otg_pcd_t * pcd)
52368 + int i, num_in_eps, num_out_eps;
52369 + dwc_otg_pcd_ep_t *ep;
52371 + gintmsk_data_t intr_mask = {.d32 = 0 };
52373 + DWC_SPINLOCK(pcd->lock);
52375 + num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
52376 + num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
52378 + DWC_DEBUGPL(DBG_PCDV, "%s() \n", __func__);
52379 + /* don't disconnect drivers more than once */
52380 + if (pcd->ep0state == EP0_DISCONNECT) {
52381 + DWC_DEBUGPL(DBG_ANY, "%s() Already Disconnected\n", __func__);
52382 + DWC_SPINUNLOCK(pcd->lock);
52385 + pcd->ep0state = EP0_DISCONNECT;
52387 + /* Reset the OTG state. */
52388 + dwc_otg_pcd_update_otg(pcd, 1);
52390 + /* Disable the NP Tx Fifo Empty Interrupt. */
52391 + intr_mask.b.nptxfempty = 1;
52392 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
52393 + intr_mask.d32, 0);
52395 + /* Flush the FIFOs */
52396 + /**@todo NGS Flush Periodic FIFOs */
52397 + dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), 0x10);
52398 + dwc_otg_flush_rx_fifo(GET_CORE_IF(pcd));
52400 + /* prevent new request submissions, kill any outstanding requests */
52402 + dwc_otg_request_nuke(ep);
52403 + /* prevent new request submissions, kill any outstanding requests */
52404 + for (i = 0; i < num_in_eps; i++) {
52405 + dwc_otg_pcd_ep_t *ep = &pcd->in_ep[i];
52406 + dwc_otg_request_nuke(ep);
52408 + /* prevent new request submissions, kill any outstanding requests */
52409 + for (i = 0; i < num_out_eps; i++) {
52410 + dwc_otg_pcd_ep_t *ep = &pcd->out_ep[i];
52411 + dwc_otg_request_nuke(ep);
52414 + /* report disconnect; the driver is already quiesced */
52415 + if (pcd->fops->disconnect) {
52416 + DWC_SPINUNLOCK(pcd->lock);
52417 + pcd->fops->disconnect(pcd);
52418 + DWC_SPINLOCK(pcd->lock);
52420 + DWC_SPINUNLOCK(pcd->lock);
52424 + * This interrupt indicates that ...
52426 +int32_t dwc_otg_pcd_handle_i2c_intr(dwc_otg_pcd_t * pcd)
52428 + gintmsk_data_t intr_mask = {.d32 = 0 };
52429 + gintsts_data_t gintsts;
52431 + DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "i2cintr");
52432 + intr_mask.b.i2cintr = 1;
52433 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
52434 + intr_mask.d32, 0);
52436 + /* Clear interrupt */
52438 + gintsts.b.i2cintr = 1;
52439 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
52445 + * This interrupt indicates that ...
52447 +int32_t dwc_otg_pcd_handle_early_suspend_intr(dwc_otg_pcd_t * pcd)
52449 + gintsts_data_t gintsts;
52450 +#if defined(VERBOSE)
52451 + DWC_PRINTF("Early Suspend Detected\n");
52454 + /* Clear interrupt */
52456 + gintsts.b.erlysuspend = 1;
52457 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
52463 + * This function configures EPO to receive SETUP packets.
52465 + * @todo NGS: Update the comments from the HW FS.
52467 + * -# Program the following fields in the endpoint specific registers
52468 + * for Control OUT EP 0, in order to receive a setup packet
52469 + * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back
52471 + * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back
52472 + * to back setup packets)
52473 + * - In DMA mode, DOEPDMA0 Register with a memory address to
52474 + * store any setup packets received
52476 + * @param core_if Programming view of DWC_otg controller.
52477 + * @param pcd Programming view of the PCD.
52479 +static inline void ep0_out_start(dwc_otg_core_if_t * core_if,
52480 + dwc_otg_pcd_t * pcd)
52482 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
52483 + deptsiz0_data_t doeptsize0 = {.d32 = 0 };
52484 + dwc_otg_dev_dma_desc_t *dma_desc;
52485 + depctl_data_t doepctl = {.d32 = 0 };
52488 + DWC_DEBUGPL(DBG_PCDV, "%s() doepctl0=%0x\n", __func__,
52489 + DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
52491 + if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
52492 + doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl);
52493 + if (doepctl.b.epena) {
52498 + doeptsize0.b.supcnt = 3;
52499 + doeptsize0.b.pktcnt = 1;
52500 + doeptsize0.b.xfersize = 8 * 3;
52502 + if (core_if->dma_enable) {
52503 + if (!core_if->dma_desc_enable) {
52504 + /** put here as for Hermes mode deptisz register should not be written */
52505 + DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz,
52508 + /** @todo dma needs to handle multiple setup packets (up to 3) */
52509 + DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma,
52510 + pcd->setup_pkt_dma_handle);
52512 + dev_if->setup_desc_index =
52513 + (dev_if->setup_desc_index + 1) & 1;
52515 + dev_if->setup_desc_addr[dev_if->setup_desc_index];
52517 + /** DMA Descriptor Setup */
52518 + dma_desc->status.b.bs = BS_HOST_BUSY;
52519 + if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
52520 + dma_desc->status.b.sr = 0;
52521 + dma_desc->status.b.mtrf = 0;
52523 + dma_desc->status.b.l = 1;
52524 + dma_desc->status.b.ioc = 1;
52525 + dma_desc->status.b.bytes = pcd->ep0.dwc_ep.maxpacket;
52526 + dma_desc->buf = pcd->setup_pkt_dma_handle;
52527 + dma_desc->status.b.sts = 0;
52528 + dma_desc->status.b.bs = BS_HOST_READY;
52530 + /** DOEPDMA0 Register write */
52531 + DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma,
52532 + dev_if->dma_setup_desc_addr
52533 + [dev_if->setup_desc_index]);
52537 + /** put here as for Hermes mode deptisz register should not be written */
52538 + DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz,
52542 + /** DOEPCTL0 Register write cnak will be set after setup interrupt */
52544 + doepctl.b.epena = 1;
52545 + if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
52546 + doepctl.b.cnak = 1;
52547 + DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
52549 + DWC_MODIFY_REG32(&dev_if->out_ep_regs[0]->doepctl, 0, doepctl.d32);
52553 + DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
52554 + DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
52555 + DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
52556 + DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl));
52561 + * This interrupt occurs when a USB Reset is detected. When the USB
52562 + * Reset Interrupt occurs the device state is set to DEFAULT and the
52563 + * EP0 state is set to IDLE.
52564 + * -# Set the NAK bit for all OUT endpoints (DOEPCTLn.SNAK = 1)
52565 + * -# Unmask the following interrupt bits
52566 + * - DAINTMSK.INEP0 = 1 (Control 0 IN endpoint)
52567 + * - DAINTMSK.OUTEP0 = 1 (Control 0 OUT endpoint)
52568 + * - DOEPMSK.SETUP = 1
52569 + * - DOEPMSK.XferCompl = 1
52570 + * - DIEPMSK.XferCompl = 1
52571 + * - DIEPMSK.TimeOut = 1
52572 + * -# Program the following fields in the endpoint specific registers
52573 + * for Control OUT EP 0, in order to receive a setup packet
52574 + * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back
52576 + * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back
52577 + * to back setup packets)
52578 + * - In DMA mode, DOEPDMA0 Register with a memory address to
52579 + * store any setup packets received
52580 + * At this point, all the required initialization, except for enabling
52581 + * the control 0 OUT endpoint is done, for receiving SETUP packets.
52583 +int32_t dwc_otg_pcd_handle_usb_reset_intr(dwc_otg_pcd_t * pcd)
52585 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
52586 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
52587 + depctl_data_t doepctl = {.d32 = 0 };
52588 + depctl_data_t diepctl = {.d32 = 0 };
52589 + daint_data_t daintmsk = {.d32 = 0 };
52590 + doepmsk_data_t doepmsk = {.d32 = 0 };
52591 + diepmsk_data_t diepmsk = {.d32 = 0 };
52592 + dcfg_data_t dcfg = {.d32 = 0 };
52593 + grstctl_t resetctl = {.d32 = 0 };
52594 + dctl_data_t dctl = {.d32 = 0 };
52596 + gintsts_data_t gintsts;
52597 + pcgcctl_data_t power = {.d32 = 0 };
52599 + power.d32 = DWC_READ_REG32(core_if->pcgcctl);
52600 + if (power.b.stoppclk) {
52602 + power.b.stoppclk = 1;
52603 + DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
52605 + power.b.pwrclmp = 1;
52606 + DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
52608 + power.b.rstpdwnmodule = 1;
52609 + DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
52612 + core_if->lx_state = DWC_OTG_L0;
52614 + DWC_PRINTF("USB RESET\n");
52615 +#ifdef DWC_EN_ISOC
52616 + for (i = 1; i < 16; ++i) {
52617 + dwc_otg_pcd_ep_t *ep;
52618 + dwc_ep_t *dwc_ep;
52619 + ep = get_in_ep(pcd, i);
52621 + dwc_ep = &ep->dwc_ep;
52622 + dwc_ep->next_frame = 0xffffffff;
52625 +#endif /* DWC_EN_ISOC */
52627 + /* reset the HNP settings */
52628 + dwc_otg_pcd_update_otg(pcd, 1);
52630 + /* Clear the Remote Wakeup Signalling */
52631 + dctl.b.rmtwkupsig = 1;
52632 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
52634 + /* Set NAK for all OUT EPs */
52635 + doepctl.b.snak = 1;
52636 + for (i = 0; i <= dev_if->num_out_eps; i++) {
52637 + DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32);
52640 + /* Flush the NP Tx FIFO */
52641 + dwc_otg_flush_tx_fifo(core_if, 0x10);
52642 + /* Flush the Learning Queue */
52643 + resetctl.b.intknqflsh = 1;
52644 + DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
52646 + if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) {
52647 + core_if->start_predict = 0;
52648 + for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) {
52649 + core_if->nextep_seq[i] = 0xff; // 0xff - EP not active
52651 + core_if->nextep_seq[0] = 0;
52652 + core_if->first_in_nextep_seq = 0;
52653 + diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
52654 + diepctl.b.nextep = 0;
52655 + DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
52657 + /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */
52658 + dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
52659 + dcfg.b.epmscnt = 2;
52660 + DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
52662 + DWC_DEBUGPL(DBG_PCDV,
52663 + "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
52664 + __func__, core_if->first_in_nextep_seq);
52665 + for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
52666 + DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]);
52670 + if (core_if->multiproc_int_enable) {
52671 + daintmsk.b.inep0 = 1;
52672 + daintmsk.b.outep0 = 1;
52673 + DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk,
52676 + doepmsk.b.setup = 1;
52677 + doepmsk.b.xfercompl = 1;
52678 + doepmsk.b.ahberr = 1;
52679 + doepmsk.b.epdisabled = 1;
52681 + if ((core_if->dma_desc_enable) ||
52682 + (core_if->dma_enable
52683 + && core_if->snpsid >= OTG_CORE_REV_3_00a)) {
52684 + doepmsk.b.stsphsercvd = 1;
52686 + if (core_if->dma_desc_enable)
52687 + doepmsk.b.bna = 1;
52689 + doepmsk.b.babble = 1;
52690 + doepmsk.b.nyet = 1;
52692 + if (core_if->dma_enable) {
52693 + doepmsk.b.nak = 1;
52696 + DWC_WRITE_REG32(&dev_if->dev_global_regs->doepeachintmsk[0],
52699 + diepmsk.b.xfercompl = 1;
52700 + diepmsk.b.timeout = 1;
52701 + diepmsk.b.epdisabled = 1;
52702 + diepmsk.b.ahberr = 1;
52703 + diepmsk.b.intknepmis = 1;
52704 + if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
52705 + diepmsk.b.intknepmis = 0;
52707 +/* if (core_if->dma_desc_enable) {
52708 + diepmsk.b.bna = 1;
52712 + if (core_if->dma_enable) {
52713 + diepmsk.b.nak = 1;
52716 + DWC_WRITE_REG32(&dev_if->dev_global_regs->diepeachintmsk[0],
52719 + daintmsk.b.inep0 = 1;
52720 + daintmsk.b.outep0 = 1;
52721 + DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk,
52724 + doepmsk.b.setup = 1;
52725 + doepmsk.b.xfercompl = 1;
52726 + doepmsk.b.ahberr = 1;
52727 + doepmsk.b.epdisabled = 1;
52729 + if ((core_if->dma_desc_enable) ||
52730 + (core_if->dma_enable
52731 + && core_if->snpsid >= OTG_CORE_REV_3_00a)) {
52732 + doepmsk.b.stsphsercvd = 1;
52734 + if (core_if->dma_desc_enable)
52735 + doepmsk.b.bna = 1;
52736 + DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, doepmsk.d32);
52738 + diepmsk.b.xfercompl = 1;
52739 + diepmsk.b.timeout = 1;
52740 + diepmsk.b.epdisabled = 1;
52741 + diepmsk.b.ahberr = 1;
52742 + if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
52743 + diepmsk.b.intknepmis = 0;
52745 + if (core_if->dma_desc_enable) {
52746 + diepmsk.b.bna = 1;
52750 + DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32);
52753 + /* Reset Device Address */
52754 + dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
52755 + dcfg.b.devaddr = 0;
52756 + DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
52758 + /* setup EP0 to receive SETUP packets */
52759 + if (core_if->snpsid <= OTG_CORE_REV_2_94a)
52760 + ep0_out_start(core_if, pcd);
52762 + /* Clear interrupt */
52764 + gintsts.b.usbreset = 1;
52765 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
52771 + * Get the device speed from the device status register and convert it
52772 + * to USB speed constant.
52774 + * @param core_if Programming view of DWC_otg controller.
52776 +static int get_device_speed(dwc_otg_core_if_t * core_if)
52778 + dsts_data_t dsts;
52780 + dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
52782 + switch (dsts.b.enumspd) {
52783 + case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
52784 + speed = USB_SPEED_HIGH;
52786 + case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
52787 + case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
52788 + speed = USB_SPEED_FULL;
52791 + case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
52792 + speed = USB_SPEED_LOW;
52800 + * Read the device status register and set the device speed in the
52801 + * data structure.
52802 + * Set up EP0 to receive SETUP packets by calling dwc_ep0_activate.
52804 +int32_t dwc_otg_pcd_handle_enum_done_intr(dwc_otg_pcd_t * pcd)
52806 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
52807 + gintsts_data_t gintsts;
52808 + gusbcfg_data_t gusbcfg;
52809 + dwc_otg_core_global_regs_t *global_regs =
52810 + GET_CORE_IF(pcd)->core_global_regs;
52811 + uint8_t utmi16b, utmi8b;
52813 + DWC_DEBUGPL(DBG_PCD, "SPEED ENUM\n");
52815 + if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_2_60a) {
52816 + utmi16b = 6; //vahrama old value was 6;
52822 + dwc_otg_ep0_activate(GET_CORE_IF(pcd), &ep0->dwc_ep);
52823 + if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_3_00a) {
52824 + ep0_out_start(GET_CORE_IF(pcd), pcd);
52828 + print_ep0_state(pcd);
52831 + if (pcd->ep0state == EP0_DISCONNECT) {
52832 + pcd->ep0state = EP0_IDLE;
52833 + } else if (pcd->ep0state == EP0_STALL) {
52834 + pcd->ep0state = EP0_IDLE;
52837 + pcd->ep0state = EP0_IDLE;
52839 + ep0->stopped = 0;
52841 + speed = get_device_speed(GET_CORE_IF(pcd));
52842 + pcd->fops->connect(pcd, speed);
52844 + /* Set USB turnaround time based on device speed and PHY interface. */
52845 + gusbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
52846 + if (speed == USB_SPEED_HIGH) {
52847 + if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
52848 + DWC_HWCFG2_HS_PHY_TYPE_ULPI) {
52849 + /* ULPI interface */
52850 + gusbcfg.b.usbtrdtim = 9;
52852 + if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
52853 + DWC_HWCFG2_HS_PHY_TYPE_UTMI) {
52854 + /* UTMI+ interface */
52855 + if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 0) {
52856 + gusbcfg.b.usbtrdtim = utmi8b;
52857 + } else if (GET_CORE_IF(pcd)->hwcfg4.
52858 + b.utmi_phy_data_width == 1) {
52859 + gusbcfg.b.usbtrdtim = utmi16b;
52860 + } else if (GET_CORE_IF(pcd)->
52861 + core_params->phy_utmi_width == 8) {
52862 + gusbcfg.b.usbtrdtim = utmi8b;
52864 + gusbcfg.b.usbtrdtim = utmi16b;
52867 + if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
52868 + DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI) {
52869 + /* UTMI+ OR ULPI interface */
52870 + if (gusbcfg.b.ulpi_utmi_sel == 1) {
52871 + /* ULPI interface */
52872 + gusbcfg.b.usbtrdtim = 9;
52874 + /* UTMI+ interface */
52875 + if (GET_CORE_IF(pcd)->
52876 + core_params->phy_utmi_width == 16) {
52877 + gusbcfg.b.usbtrdtim = utmi16b;
52879 + gusbcfg.b.usbtrdtim = utmi8b;
52884 + /* Full or low speed */
52885 + gusbcfg.b.usbtrdtim = 9;
52887 + DWC_WRITE_REG32(&global_regs->gusbcfg, gusbcfg.d32);
52889 + /* Clear interrupt */
52891 + gintsts.b.enumdone = 1;
52892 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
52898 + * This interrupt indicates that the ISO OUT Packet was dropped due to
52899 + * Rx FIFO full or Rx Status Queue Full. If this interrupt occurs
52900 + * read all the data from the Rx FIFO.
52902 +int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(dwc_otg_pcd_t * pcd)
52904 + gintmsk_data_t intr_mask = {.d32 = 0 };
52905 + gintsts_data_t gintsts;
52907 + DWC_WARN("INTERRUPT Handler not implemented for %s\n",
52908 + "ISOC Out Dropped");
52910 + intr_mask.b.isooutdrop = 1;
52911 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
52912 + intr_mask.d32, 0);
52914 + /* Clear interrupt */
52916 + gintsts.b.isooutdrop = 1;
52917 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
52924 + * This interrupt indicates the end of the portion of the micro-frame
52925 + * for periodic transactions. If there is a periodic transaction for
52926 + * the next frame, load the packets into the EP periodic Tx FIFO.
52928 +int32_t dwc_otg_pcd_handle_end_periodic_frame_intr(dwc_otg_pcd_t * pcd)
52930 + gintmsk_data_t intr_mask = {.d32 = 0 };
52931 + gintsts_data_t gintsts;
52932 + DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "EOP");
52934 + intr_mask.b.eopframe = 1;
52935 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
52936 + intr_mask.d32, 0);
52938 + /* Clear interrupt */
52940 + gintsts.b.eopframe = 1;
52941 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
52948 + * This interrupt indicates that EP of the packet on the top of the
52949 + * non-periodic Tx FIFO does not match EP of the IN Token received.
52951 + * The "Device IN Token Queue" Registers are read to determine the
52952 + * order the IN Tokens have been received. The non-periodic Tx FIFO
52953 + * is flushed, so it can be reloaded in the order seen in the IN Token
52956 +int32_t dwc_otg_pcd_handle_ep_mismatch_intr(dwc_otg_pcd_t * pcd)
52958 + gintsts_data_t gintsts;
52959 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
52960 + dctl_data_t dctl;
52961 + gintmsk_data_t intr_mask = {.d32 = 0 };
52963 + if (!core_if->en_multiple_tx_fifo && core_if->dma_enable) {
52964 + core_if->start_predict = 1;
52966 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
52968 + gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
52969 + if (!gintsts.b.ginnakeff) {
52970 + /* Disable EP Mismatch interrupt */
52971 + intr_mask.d32 = 0;
52972 + intr_mask.b.epmismatch = 1;
52973 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
52974 + /* Enable the Global IN NAK Effective Interrupt */
52975 + intr_mask.d32 = 0;
52976 + intr_mask.b.ginnakeff = 1;
52977 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32);
52978 + /* Set the global non-periodic IN NAK handshake */
52979 + dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
52980 + dctl.b.sgnpinnak = 1;
52981 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
52983 + DWC_PRINTF("gintsts.b.ginnakeff = 1! dctl.b.sgnpinnak not set\n");
52985 + /* Disabling of all EP's will be done in dwc_otg_pcd_handle_in_nak_effective()
52986 + * handler after Global IN NAK Effective interrupt will be asserted */
52988 + /* Clear interrupt */
52990 + gintsts.b.epmismatch = 1;
52991 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
52997 + * This interrupt is valid only in DMA mode. This interrupt indicates that the
52998 + * core has stopped fetching data for IN endpoints due to the unavailability of
52999 + * TxFIFO space or Request Queue space. This interrupt is used by the
53000 + * application for an endpoint mismatch algorithm.
53002 + * @param pcd The PCD
53004 +int32_t dwc_otg_pcd_handle_ep_fetsusp_intr(dwc_otg_pcd_t * pcd)
53006 + gintsts_data_t gintsts;
53007 + gintmsk_data_t gintmsk_data;
53008 + dctl_data_t dctl;
53009 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
53010 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
53012 + /* Clear the global non-periodic IN NAK handshake */
53014 + dctl.b.cgnpinnak = 1;
53015 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
53017 + /* Mask GINTSTS.FETSUSP interrupt */
53018 + gintmsk_data.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
53019 + gintmsk_data.b.fetsusp = 0;
53020 + DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_data.d32);
53022 + /* Clear interrupt */
53024 + gintsts.b.fetsusp = 1;
53025 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
53030 + * This funcion stalls EP0.
53032 +static inline void ep0_do_stall(dwc_otg_pcd_t * pcd, const int err_val)
53034 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
53035 + usb_device_request_t *ctrl = &pcd->setup_pkt->req;
53036 + DWC_WARN("req %02x.%02x protocol STALL; err %d\n",
53037 + ctrl->bmRequestType, ctrl->bRequest, err_val);
53039 + ep0->dwc_ep.is_in = 1;
53040 + dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep0->dwc_ep);
53041 + pcd->ep0.stopped = 1;
53042 + pcd->ep0state = EP0_IDLE;
53043 + ep0_out_start(GET_CORE_IF(pcd), pcd);
53047 + * This functions delegates the setup command to the gadget driver.
53049 +static inline void do_gadget_setup(dwc_otg_pcd_t * pcd,
53050 + usb_device_request_t * ctrl)
53053 + DWC_SPINUNLOCK(pcd->lock);
53054 + ret = pcd->fops->setup(pcd, (uint8_t *) ctrl);
53055 + DWC_SPINLOCK(pcd->lock);
53057 + ep0_do_stall(pcd, ret);
53060 + /** @todo This is a g_file_storage gadget driver specific
53061 + * workaround: a DELAYED_STATUS result from the fsg_setup
53062 + * routine will result in the gadget queueing a EP0 IN status
53063 + * phase for a two-stage control transfer. Exactly the same as
53064 + * a SET_CONFIGURATION/SET_INTERFACE except that this is a class
53065 + * specific request. Need a generic way to know when the gadget
53066 + * driver will queue the status phase. Can we assume when we
53067 + * call the gadget driver setup() function that it will always
53068 + * queue and require the following flag? Need to look into
53072 + if (ret == 256 + 999) {
53073 + pcd->request_config = 1;
53077 +#ifdef DWC_UTE_CFI
53079 + * This functions delegates the CFI setup commands to the gadget driver.
53080 + * This function will return a negative value to indicate a failure.
53082 +static inline int cfi_gadget_setup(dwc_otg_pcd_t * pcd,
53083 + struct cfi_usb_ctrlrequest *ctrl_req)
53087 + if (pcd->fops && pcd->fops->cfi_setup) {
53088 + DWC_SPINUNLOCK(pcd->lock);
53089 + ret = pcd->fops->cfi_setup(pcd, ctrl_req);
53090 + DWC_SPINLOCK(pcd->lock);
53092 + ep0_do_stall(pcd, ret);
53102 + * This function starts the Zero-Length Packet for the IN status phase
53103 + * of a 2 stage control transfer.
53105 +static inline void do_setup_in_status_phase(dwc_otg_pcd_t * pcd)
53107 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
53108 + if (pcd->ep0state == EP0_STALL) {
53112 + pcd->ep0state = EP0_IN_STATUS_PHASE;
53114 + /* Prepare for more SETUP Packets */
53115 + DWC_DEBUGPL(DBG_PCD, "EP0 IN ZLP\n");
53116 + if ((GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_3_00a)
53117 + && (pcd->core_if->dma_desc_enable)
53118 + && (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len)) {
53119 + DWC_DEBUGPL(DBG_PCDV,
53120 + "Data terminated wait next packet in out_desc_addr\n");
53121 + pcd->backup_buf = phys_to_virt(ep0->dwc_ep.dma_addr);
53122 + pcd->data_terminated = 1;
53124 + ep0->dwc_ep.xfer_len = 0;
53125 + ep0->dwc_ep.xfer_count = 0;
53126 + ep0->dwc_ep.is_in = 1;
53127 + ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
53128 + dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
53130 + /* Prepare for more SETUP Packets */
53131 + //ep0_out_start(GET_CORE_IF(pcd), pcd);
53135 + * This function starts the Zero-Length Packet for the OUT status phase
53136 + * of a 2 stage control transfer.
53138 +static inline void do_setup_out_status_phase(dwc_otg_pcd_t * pcd)
53140 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
53141 + if (pcd->ep0state == EP0_STALL) {
53142 + DWC_DEBUGPL(DBG_PCD, "EP0 STALLED\n");
53145 + pcd->ep0state = EP0_OUT_STATUS_PHASE;
53147 + DWC_DEBUGPL(DBG_PCD, "EP0 OUT ZLP\n");
53148 + ep0->dwc_ep.xfer_len = 0;
53149 + ep0->dwc_ep.xfer_count = 0;
53150 + ep0->dwc_ep.is_in = 0;
53151 + ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
53152 + dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
53154 + /* Prepare for more SETUP Packets */
53155 + if (GET_CORE_IF(pcd)->dma_enable == 0) {
53156 + ep0_out_start(GET_CORE_IF(pcd), pcd);
53161 + * Clear the EP halt (STALL) and if pending requests start the
53164 +static inline void pcd_clear_halt(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)
53166 + if (ep->dwc_ep.stall_clear_flag == 0)
53167 + dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
53169 + /* Reactive the EP */
53170 + dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
53171 + if (ep->stopped) {
53173 + /* If there is a request in the EP queue start it */
53175 + /** @todo FIXME: this causes an EP mismatch in DMA mode.
53176 + * epmismatch not yet implemented. */
53179 + * Above fixme is solved by implmenting a tasklet to call the
53180 + * start_next_request(), outside of interrupt context at some
53181 + * time after the current time, after a clear-halt setup packet.
53182 + * Still need to implement ep mismatch in the future if a gadget
53183 + * ever uses more than one endpoint at once
53185 + ep->queue_sof = 1;
53186 + DWC_TASK_SCHEDULE(pcd->start_xfer_tasklet);
53188 + /* Start Control Status Phase */
53189 + do_setup_in_status_phase(pcd);
53193 + * This function is called when the SET_FEATURE TEST_MODE Setup packet
53194 + * is sent from the host. The Device Control register is written with
53195 + * the Test Mode bits set to the specified Test Mode. This is done as
53196 + * a tasklet so that the "Status" phase of the control transfer
53197 + * completes before transmitting the TEST packets.
53199 + * @todo This has not been tested since the tasklet struct was put
53200 + * into the PCD struct!
53203 +void do_test_mode(void *data)
53205 + dctl_data_t dctl;
53206 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data;
53207 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
53208 + int test_mode = pcd->test_mode;
53210 +// DWC_WARN("%s() has not been tested since being rewritten!\n", __func__);
53212 + dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
53213 + switch (test_mode) {
53214 + case 1: // TEST_J
53215 + dctl.b.tstctl = 1;
53218 + case 2: // TEST_K
53219 + dctl.b.tstctl = 2;
53222 + case 3: // TEST_SE0_NAK
53223 + dctl.b.tstctl = 3;
53226 + case 4: // TEST_PACKET
53227 + dctl.b.tstctl = 4;
53230 + case 5: // TEST_FORCE_ENABLE
53231 + dctl.b.tstctl = 5;
53234 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
53238 + * This function process the GET_STATUS Setup Commands.
53240 +static inline void do_get_status(dwc_otg_pcd_t * pcd)
53242 + usb_device_request_t ctrl = pcd->setup_pkt->req;
53243 + dwc_otg_pcd_ep_t *ep;
53244 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
53245 + uint16_t *status = pcd->status_buf;
53246 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
53249 + DWC_DEBUGPL(DBG_PCD,
53250 + "GET_STATUS %02x.%02x v%04x i%04x l%04x\n",
53251 + ctrl.bmRequestType, ctrl.bRequest,
53252 + UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
53253 + UGETW(ctrl.wLength));
53256 + switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
53258 + if(UGETW(ctrl.wIndex) == 0xF000) { /* OTG Status selector */
53259 + DWC_PRINTF("wIndex - %d\n", UGETW(ctrl.wIndex));
53260 + DWC_PRINTF("OTG VERSION - %d\n", core_if->otg_ver);
53261 + DWC_PRINTF("OTG CAP - %d, %d\n",
53262 + core_if->core_params->otg_cap,
53263 + DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
53264 + if (core_if->otg_ver == 1
53265 + && core_if->core_params->otg_cap ==
53266 + DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
53267 + uint8_t *otgsts = (uint8_t*)pcd->status_buf;
53268 + *otgsts = (core_if->otg_sts & 0x1);
53269 + pcd->ep0_pending = 1;
53270 + ep0->dwc_ep.start_xfer_buff =
53271 + (uint8_t *) otgsts;
53272 + ep0->dwc_ep.xfer_buff = (uint8_t *) otgsts;
53273 + ep0->dwc_ep.dma_addr =
53274 + pcd->status_buf_dma_handle;
53275 + ep0->dwc_ep.xfer_len = 1;
53276 + ep0->dwc_ep.xfer_count = 0;
53277 + ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;
53278 + dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd),
53282 + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
53287 + *status = 0x1; /* Self powered */
53288 + *status |= pcd->remote_wakeup_enable << 1;
53291 + case UT_INTERFACE:
53295 + case UT_ENDPOINT:
53296 + ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
53297 + if (ep == 0 || UGETW(ctrl.wLength) > 2) {
53298 + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
53301 + /** @todo check for EP stall */
53302 + *status = ep->stopped;
53305 + pcd->ep0_pending = 1;
53306 + ep0->dwc_ep.start_xfer_buff = (uint8_t *) status;
53307 + ep0->dwc_ep.xfer_buff = (uint8_t *) status;
53308 + ep0->dwc_ep.dma_addr = pcd->status_buf_dma_handle;
53309 + ep0->dwc_ep.xfer_len = 2;
53310 + ep0->dwc_ep.xfer_count = 0;
53311 + ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;
53312 + dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
53316 + * This function process the SET_FEATURE Setup Commands.
53318 +static inline void do_set_feature(dwc_otg_pcd_t * pcd)
53320 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
53321 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
53322 + usb_device_request_t ctrl = pcd->setup_pkt->req;
53323 + dwc_otg_pcd_ep_t *ep = 0;
53324 + int32_t otg_cap_param = core_if->core_params->otg_cap;
53325 + gotgctl_data_t gotgctl = {.d32 = 0 };
53327 + DWC_DEBUGPL(DBG_PCD, "SET_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
53328 + ctrl.bmRequestType, ctrl.bRequest,
53329 + UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
53330 + UGETW(ctrl.wLength));
53331 + DWC_DEBUGPL(DBG_PCD, "otg_cap=%d\n", otg_cap_param);
53333 + switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
53335 + switch (UGETW(ctrl.wValue)) {
53336 + case UF_DEVICE_REMOTE_WAKEUP:
53337 + pcd->remote_wakeup_enable = 1;
53340 + case UF_TEST_MODE:
53341 + /* Setup the Test Mode tasklet to do the Test
53342 + * Packet generation after the SETUP Status
53343 + * phase has completed. */
53345 + /** @todo This has not been tested since the
53346 + * tasklet struct was put into the PCD
53348 + pcd->test_mode = UGETW(ctrl.wIndex) >> 8;
53349 + DWC_TASK_SCHEDULE(pcd->test_mode_tasklet);
53352 + case UF_DEVICE_B_HNP_ENABLE:
53353 + DWC_DEBUGPL(DBG_PCDV,
53354 + "SET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
53356 + /* dev may initiate HNP */
53357 + if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
53358 + pcd->b_hnp_enable = 1;
53359 + dwc_otg_pcd_update_otg(pcd, 0);
53360 + DWC_DEBUGPL(DBG_PCD, "Request B HNP\n");
53361 + /**@todo Is the gotgctl.devhnpen cleared
53362 + * by a USB Reset? */
53363 + gotgctl.b.devhnpen = 1;
53364 + gotgctl.b.hnpreq = 1;
53365 + DWC_WRITE_REG32(&global_regs->gotgctl,
53368 + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
53373 + case UF_DEVICE_A_HNP_SUPPORT:
53374 + /* RH port supports HNP */
53375 + DWC_DEBUGPL(DBG_PCDV,
53376 + "SET_FEATURE: USB_DEVICE_A_HNP_SUPPORT\n");
53377 + if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
53378 + pcd->a_hnp_support = 1;
53379 + dwc_otg_pcd_update_otg(pcd, 0);
53381 + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
53386 + case UF_DEVICE_A_ALT_HNP_SUPPORT:
53387 + /* other RH port does */
53388 + DWC_DEBUGPL(DBG_PCDV,
53389 + "SET_FEATURE: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
53390 + if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
53391 + pcd->a_alt_hnp_support = 1;
53392 + dwc_otg_pcd_update_otg(pcd, 0);
53394 + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
53400 + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
53404 + do_setup_in_status_phase(pcd);
53407 + case UT_INTERFACE:
53408 + do_gadget_setup(pcd, &ctrl);
53411 + case UT_ENDPOINT:
53412 + if (UGETW(ctrl.wValue) == UF_ENDPOINT_HALT) {
53413 + ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
53415 + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
53419 + dwc_otg_ep_set_stall(core_if, &ep->dwc_ep);
53421 + do_setup_in_status_phase(pcd);
53427 + * This function process the CLEAR_FEATURE Setup Commands.
53429 +static inline void do_clear_feature(dwc_otg_pcd_t * pcd)
53431 + usb_device_request_t ctrl = pcd->setup_pkt->req;
53432 + dwc_otg_pcd_ep_t *ep = 0;
53434 + DWC_DEBUGPL(DBG_PCD,
53435 + "CLEAR_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
53436 + ctrl.bmRequestType, ctrl.bRequest,
53437 + UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
53438 + UGETW(ctrl.wLength));
53440 + switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
53442 + switch (UGETW(ctrl.wValue)) {
53443 + case UF_DEVICE_REMOTE_WAKEUP:
53444 + pcd->remote_wakeup_enable = 0;
53447 + case UF_TEST_MODE:
53448 + /** @todo Add CLEAR_FEATURE for TEST modes. */
53452 + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
53455 + do_setup_in_status_phase(pcd);
53458 + case UT_ENDPOINT:
53459 + ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
53461 + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
53465 + pcd_clear_halt(pcd, ep);
53472 + * This function process the SET_ADDRESS Setup Commands.
53474 +static inline void do_set_address(dwc_otg_pcd_t * pcd)
53476 + dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
53477 + usb_device_request_t ctrl = pcd->setup_pkt->req;
53479 + if (ctrl.bmRequestType == UT_DEVICE) {
53480 + dcfg_data_t dcfg = {.d32 = 0 };
53483 +// DWC_DEBUGPL(DBG_PCDV, "SET_ADDRESS:%d\n", ctrl.wValue);
53485 + dcfg.b.devaddr = UGETW(ctrl.wValue);
53486 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->dcfg, 0, dcfg.d32);
53487 + do_setup_in_status_phase(pcd);
53492 + * This function processes SETUP commands. In Linux, the USB Command
53493 + * processing is done in two places - the first being the PCD and the
53494 + * second in the Gadget Driver (for example, the File-Backed Storage
53495 + * Gadget Driver).
53498 + * <tr><td>Command </td><td>Driver </td><td>Description</td></tr>
53500 + * <tr><td>GET_STATUS </td><td>PCD </td><td>Command is processed as
53501 + * defined in chapter 9 of the USB 2.0 Specification chapter 9
53504 + * <tr><td>CLEAR_FEATURE </td><td>PCD </td><td>The Device and Endpoint
53505 + * requests are the ENDPOINT_HALT feature is procesed, all others the
53506 + * interface requests are ignored.</td></tr>
53508 + * <tr><td>SET_FEATURE </td><td>PCD </td><td>The Device and Endpoint
53509 + * requests are processed by the PCD. Interface requests are passed
53510 + * to the Gadget Driver.</td></tr>
53512 + * <tr><td>SET_ADDRESS </td><td>PCD </td><td>Program the DCFG reg,
53513 + * with device address received </td></tr>
53515 + * <tr><td>GET_DESCRIPTOR </td><td>Gadget Driver </td><td>Return the
53516 + * requested descriptor</td></tr>
53518 + * <tr><td>SET_DESCRIPTOR </td><td>Gadget Driver </td><td>Optional -
53519 + * not implemented by any of the existing Gadget Drivers.</td></tr>
53521 + * <tr><td>SET_CONFIGURATION </td><td>Gadget Driver </td><td>Disable
53522 + * all EPs and enable EPs for new configuration.</td></tr>
53524 + * <tr><td>GET_CONFIGURATION </td><td>Gadget Driver </td><td>Return
53525 + * the current configuration</td></tr>
53527 + * <tr><td>SET_INTERFACE </td><td>Gadget Driver </td><td>Disable all
53528 + * EPs and enable EPs for new configuration.</td></tr>
53530 + * <tr><td>GET_INTERFACE </td><td>Gadget Driver </td><td>Return the
53531 + * current interface.</td></tr>
53533 + * <tr><td>SYNC_FRAME </td><td>PCD </td><td>Display debug
53534 + * message.</td></tr>
53537 + * When the SETUP Phase Done interrupt occurs, the PCD SETUP commands are
53538 + * processed by pcd_setup. Calling the Function Driver's setup function from
53539 + * pcd_setup processes the gadget SETUP commands.
53541 +static inline void pcd_setup(dwc_otg_pcd_t * pcd)
53543 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
53544 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
53545 + usb_device_request_t ctrl = pcd->setup_pkt->req;
53546 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
53548 + deptsiz0_data_t doeptsize0 = {.d32 = 0 };
53550 +#ifdef DWC_UTE_CFI
53552 + struct cfi_usb_ctrlrequest cfi_req;
53555 + doeptsize0.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doeptsiz);
53557 + /** In BDMA more then 1 setup packet is not supported till 3.00a */
53558 + if (core_if->dma_enable && core_if->dma_desc_enable == 0
53559 + && (doeptsize0.b.supcnt < 2)
53560 + && (core_if->snpsid < OTG_CORE_REV_2_94a)) {
53562 + ("\n\n----------- CANNOT handle > 1 setup packet in DMA mode\n\n");
53564 + if ((core_if->snpsid >= OTG_CORE_REV_3_00a)
53565 + && (core_if->dma_enable == 1) && (core_if->dma_desc_enable == 0)) {
53567 + (pcd->setup_pkt +
53568 + (3 - doeptsize0.b.supcnt - 1 +
53569 + ep0->dwc_ep.stp_rollover))->req;
53572 + DWC_DEBUGPL(DBG_PCD, "SETUP %02x.%02x v%04x i%04x l%04x\n",
53573 + ctrl.bmRequestType, ctrl.bRequest,
53574 + UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
53575 + UGETW(ctrl.wLength));
53578 + /* Clean up the request queue */
53579 + dwc_otg_request_nuke(ep0);
53580 + ep0->stopped = 0;
53582 + if (ctrl.bmRequestType & UE_DIR_IN) {
53583 + ep0->dwc_ep.is_in = 1;
53584 + pcd->ep0state = EP0_IN_DATA_PHASE;
53586 + ep0->dwc_ep.is_in = 0;
53587 + pcd->ep0state = EP0_OUT_DATA_PHASE;
53590 + if (UGETW(ctrl.wLength) == 0) {
53591 + ep0->dwc_ep.is_in = 1;
53592 + pcd->ep0state = EP0_IN_STATUS_PHASE;
53595 + if (UT_GET_TYPE(ctrl.bmRequestType) != UT_STANDARD) {
53597 +#ifdef DWC_UTE_CFI
53598 + DWC_MEMCPY(&cfi_req, &ctrl, sizeof(usb_device_request_t));
53600 + //printk(KERN_ALERT "CFI: req_type=0x%02x; req=0x%02x\n",
53601 + ctrl.bRequestType, ctrl.bRequest);
53602 + if (UT_GET_TYPE(cfi_req.bRequestType) == UT_VENDOR) {
53603 + if (cfi_req.bRequest > 0xB0 && cfi_req.bRequest < 0xBF) {
53604 + retval = cfi_setup(pcd, &cfi_req);
53605 + if (retval < 0) {
53606 + ep0_do_stall(pcd, retval);
53607 + pcd->ep0_pending = 0;
53611 + /* if need gadget setup then call it and check the retval */
53612 + if (pcd->cfi->need_gadget_att) {
53614 + cfi_gadget_setup(pcd,
53617 + if (retval < 0) {
53618 + pcd->ep0_pending = 0;
53623 + if (pcd->cfi->need_status_in_complete) {
53624 + do_setup_in_status_phase(pcd);
53631 + /* handle non-standard (class/vendor) requests in the gadget driver */
53632 + do_gadget_setup(pcd, &ctrl);
53636 + /** @todo NGS: Handle bad setup packet? */
53638 +///////////////////////////////////////////
53639 +//// --- Standard Request handling --- ////
53641 + switch (ctrl.bRequest) {
53642 + case UR_GET_STATUS:
53643 + do_get_status(pcd);
53646 + case UR_CLEAR_FEATURE:
53647 + do_clear_feature(pcd);
53650 + case UR_SET_FEATURE:
53651 + do_set_feature(pcd);
53654 + case UR_SET_ADDRESS:
53655 + do_set_address(pcd);
53658 + case UR_SET_INTERFACE:
53659 + case UR_SET_CONFIG:
53660 +// _pcd->request_config = 1; /* Configuration changed */
53661 + do_gadget_setup(pcd, &ctrl);
53664 + case UR_SYNCH_FRAME:
53665 + do_gadget_setup(pcd, &ctrl);
53669 + /* Call the Gadget Driver's setup functions */
53670 + do_gadget_setup(pcd, &ctrl);
53676 + * This function completes the ep0 control transfer.
53678 +static int32_t ep0_complete_request(dwc_otg_pcd_ep_t * ep)
53680 + dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
53681 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
53682 + dwc_otg_dev_in_ep_regs_t *in_ep_regs =
53683 + dev_if->in_ep_regs[ep->dwc_ep.num];
53685 + dwc_otg_dev_out_ep_regs_t *out_ep_regs =
53686 + dev_if->out_ep_regs[ep->dwc_ep.num];
53688 + deptsiz0_data_t deptsiz;
53689 + dev_dma_desc_sts_t desc_sts;
53690 + dwc_otg_pcd_request_t *req;
53692 + dwc_otg_pcd_t *pcd = ep->pcd;
53694 +#ifdef DWC_UTE_CFI
53695 + struct cfi_usb_ctrlrequest *ctrlreq;
53696 + int retval = -DWC_E_NOT_SUPPORTED;
53699 + desc_sts.b.bytes = 0;
53701 + if (pcd->ep0_pending && DWC_CIRCLEQ_EMPTY(&ep->queue)) {
53702 + if (ep->dwc_ep.is_in) {
53704 + DWC_DEBUGPL(DBG_PCDV, "Do setup OUT status phase\n");
53706 + do_setup_out_status_phase(pcd);
53709 + DWC_DEBUGPL(DBG_PCDV, "Do setup IN status phase\n");
53712 +#ifdef DWC_UTE_CFI
53713 + ctrlreq = &pcd->cfi->ctrl_req;
53715 + if (UT_GET_TYPE(ctrlreq->bRequestType) == UT_VENDOR) {
53716 + if (ctrlreq->bRequest > 0xB0
53717 + && ctrlreq->bRequest < 0xBF) {
53719 + /* Return if the PCD failed to handle the request */
53722 + ctrl_write_complete(pcd->cfi,
53725 + ("ERROR setting a new value in the PCD(%d)\n",
53727 + ep0_do_stall(pcd, retval);
53728 + pcd->ep0_pending = 0;
53732 + /* If the gadget needs to be notified on the request */
53733 + if (pcd->cfi->need_gadget_att == 1) {
53734 + //retval = do_gadget_setup(pcd, &pcd->cfi->ctrl_req);
53736 + cfi_gadget_setup(pcd,
53740 + /* Return from the function if the gadget failed to process
53741 + * the request properly - this should never happen !!!
53743 + if (retval < 0) {
53745 + ("ERROR setting a new value in the gadget(%d)\n",
53747 + pcd->ep0_pending = 0;
53752 + CFI_INFO("%s: RETVAL=%d\n", __func__,
53754 + /* If we hit here then the PCD and the gadget has properly
53755 + * handled the request - so send the ZLP IN to the host.
53757 + /* @todo: MAS - decide whether we need to start the setup
53758 + * stage based on the need_setup value of the cfi object
53760 + do_setup_in_status_phase(pcd);
53761 + pcd->ep0_pending = 0;
53767 + do_setup_in_status_phase(pcd);
53769 + pcd->ep0_pending = 0;
53773 + if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
53776 + req = DWC_CIRCLEQ_FIRST(&ep->queue);
53778 + if (pcd->ep0state == EP0_OUT_STATUS_PHASE
53779 + || pcd->ep0state == EP0_IN_STATUS_PHASE) {
53781 + } else if (ep->dwc_ep.is_in) {
53782 + deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz);
53783 + if (core_if->dma_desc_enable != 0)
53784 + desc_sts = dev_if->in_desc_addr->status;
53786 + DWC_DEBUGPL(DBG_PCDV, "%d len=%d xfersize=%d pktcnt=%d\n",
53787 + ep->dwc_ep.num, ep->dwc_ep.xfer_len,
53788 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
53791 + if (((core_if->dma_desc_enable == 0)
53792 + && (deptsiz.b.xfersize == 0))
53793 + || ((core_if->dma_desc_enable != 0)
53794 + && (desc_sts.b.bytes == 0))) {
53795 + req->actual = ep->dwc_ep.xfer_count;
53796 + /* Is a Zero Len Packet needed? */
53797 + if (req->sent_zlp) {
53799 + DWC_DEBUGPL(DBG_PCD, "Setup Rx ZLP\n");
53801 + req->sent_zlp = 0;
53803 + do_setup_out_status_phase(pcd);
53808 + deptsiz.d32 = DWC_READ_REG32(&out_ep_regs->doeptsiz);
53809 + DWC_DEBUGPL(DBG_PCDV, "%d len=%d xsize=%d pktcnt=%d\n",
53810 + ep->dwc_ep.num, ep->dwc_ep.xfer_len,
53811 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
53813 + req->actual = ep->dwc_ep.xfer_count;
53815 + /* Is a Zero Len Packet needed? */
53816 + if (req->sent_zlp) {
53818 + DWC_DEBUGPL(DBG_PCDV, "Setup Tx ZLP\n");
53820 + req->sent_zlp = 0;
53822 + /* For older cores do setup in status phase in Slave/BDMA modes,
53823 + * starting from 3.00 do that only in slave, and for DMA modes
53824 + * just re-enable ep 0 OUT here*/
53825 + if (core_if->dma_enable == 0
53826 + || (core_if->dma_desc_enable == 0
53827 + && core_if->snpsid <= OTG_CORE_REV_2_94a)) {
53828 + do_setup_in_status_phase(pcd);
53829 + } else if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
53830 + DWC_DEBUGPL(DBG_PCDV,
53831 + "Enable out ep before in status phase\n");
53832 + ep0_out_start(core_if, pcd);
53836 + /* Complete the request */
53838 + dwc_otg_request_done(ep, req, 0);
53839 + ep->dwc_ep.start_xfer_buff = 0;
53840 + ep->dwc_ep.xfer_buff = 0;
53841 + ep->dwc_ep.xfer_len = 0;
53847 +#ifdef DWC_UTE_CFI
53849 + * This function calculates traverses all the CFI DMA descriptors and
53850 + * and accumulates the bytes that are left to be transfered.
53852 + * @return The total bytes left to transfered, or a negative value as failure
53854 +static inline int cfi_calc_desc_residue(dwc_otg_pcd_ep_t * ep)
53858 + struct dwc_otg_dma_desc *ddesc = NULL;
53859 + struct cfi_ep *cfiep;
53861 + /* See if the pcd_ep has its respective cfi_ep mapped */
53862 + cfiep = get_cfi_ep_by_pcd_ep(ep->pcd->cfi, ep);
53864 + CFI_INFO("%s: Failed to find ep\n", __func__);
53868 + ddesc = ep->dwc_ep.descs;
53870 + for (i = 0; (i < cfiep->desc_count) && (i < MAX_DMA_DESCS_PER_EP); i++) {
53872 +#if defined(PRINT_CFI_DMA_DESCS)
53873 + print_desc(ddesc, ep->ep.name, i);
53875 + ret += ddesc->status.b.bytes;
53880 + CFI_INFO("!!!!!!!!!! WARNING (%s) - residue=%d\n", __func__,
53888 + * This function completes the request for the EP. If there are
53889 + * additional requests for the EP in the queue they will be started.
53891 +static void complete_ep(dwc_otg_pcd_ep_t * ep)
53893 + dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
53894 + struct device *dev = dwc_otg_pcd_to_dev(ep->pcd);
53895 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
53896 + dwc_otg_dev_in_ep_regs_t *in_ep_regs =
53897 + dev_if->in_ep_regs[ep->dwc_ep.num];
53898 + deptsiz_data_t deptsiz;
53899 + dev_dma_desc_sts_t desc_sts;
53900 + dwc_otg_pcd_request_t *req = 0;
53901 + dwc_otg_dev_dma_desc_t *dma_desc;
53902 + uint32_t byte_count = 0;
53906 + DWC_DEBUGPL(DBG_PCDV, "%s() %d-%s\n", __func__, ep->dwc_ep.num,
53907 + (ep->dwc_ep.is_in ? "IN" : "OUT"));
53909 + /* Get any pending requests */
53910 + if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
53911 + req = DWC_CIRCLEQ_FIRST(&ep->queue);
53913 + DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
53917 + DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
53921 + DWC_DEBUGPL(DBG_PCD, "Requests %d\n", ep->pcd->request_pending);
53923 + if (ep->dwc_ep.is_in) {
53924 + deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz);
53926 + if (core_if->dma_enable) {
53927 + if (core_if->dma_desc_enable == 0) {
53928 + if (deptsiz.b.xfersize == 0
53929 + && deptsiz.b.pktcnt == 0) {
53931 + ep->dwc_ep.xfer_len -
53932 + ep->dwc_ep.xfer_count;
53934 + ep->dwc_ep.xfer_buff += byte_count;
53935 + ep->dwc_ep.dma_addr += byte_count;
53936 + ep->dwc_ep.xfer_count += byte_count;
53938 + DWC_DEBUGPL(DBG_PCDV,
53939 + "%d-%s len=%d xfersize=%d pktcnt=%d\n",
53942 + is_in ? "IN" : "OUT"),
53943 + ep->dwc_ep.xfer_len,
53944 + deptsiz.b.xfersize,
53945 + deptsiz.b.pktcnt);
53947 + if (ep->dwc_ep.xfer_len <
53948 + ep->dwc_ep.total_len) {
53949 + dwc_otg_ep_start_transfer
53950 + (core_if, &ep->dwc_ep);
53951 + } else if (ep->dwc_ep.sent_zlp) {
53953 + * This fragment of code should initiate 0
53954 + * length transfer in case if it is queued
53955 + * a transfer with size divisible to EPs max
53956 + * packet size and with usb_request zero field
53957 + * is set, which means that after data is transfered,
53958 + * it is also should be transfered
53959 + * a 0 length packet at the end. For Slave and
53960 + * Buffer DMA modes in this case SW has
53961 + * to initiate 2 transfers one with transfer size,
53962 + * and the second with 0 size. For Descriptor
53963 + * DMA mode SW is able to initiate a transfer,
53964 + * which will handle all the packets including
53965 + * the last 0 length.
53967 + ep->dwc_ep.sent_zlp = 0;
53968 + dwc_otg_ep_start_zl_transfer
53969 + (core_if, &ep->dwc_ep);
53974 + if (ep->dwc_ep.type ==
53975 + DWC_OTG_EP_TYPE_ISOC) {
53977 + dwc_otg_request_done(ep, req, 0);
53979 + ep->dwc_ep.start_xfer_buff = 0;
53980 + ep->dwc_ep.xfer_buff = 0;
53981 + ep->dwc_ep.xfer_len = 0;
53983 + /* If there is a request in the queue start it. */
53984 + start_next_request(ep);
53987 + ("Incomplete transfer (%d - %s [siz=%d pkt=%d])\n",
53989 + (ep->dwc_ep.is_in ? "IN" : "OUT"),
53990 + deptsiz.b.xfersize,
53991 + deptsiz.b.pktcnt);
53994 + dma_desc = ep->dwc_ep.desc_addr;
53996 + ep->dwc_ep.sent_zlp = 0;
53998 +#ifdef DWC_UTE_CFI
53999 + CFI_INFO("%s: BUFFER_MODE=%d\n", __func__,
54000 + ep->dwc_ep.buff_mode);
54001 + if (ep->dwc_ep.buff_mode != BM_STANDARD) {
54004 + residue = cfi_calc_desc_residue(ep);
54008 + byte_count = residue;
54011 + for (i = 0; i < ep->dwc_ep.desc_cnt;
54013 + desc_sts = dma_desc->status;
54014 + byte_count += desc_sts.b.bytes;
54017 +#ifdef DWC_UTE_CFI
54020 + if (byte_count == 0) {
54021 + ep->dwc_ep.xfer_count =
54022 + ep->dwc_ep.total_len;
54025 + DWC_WARN("Incomplete transfer\n");
54029 + if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) {
54030 + DWC_DEBUGPL(DBG_PCDV,
54031 + "%d-%s len=%d xfersize=%d pktcnt=%d\n",
54033 + ep->dwc_ep.is_in ? "IN" : "OUT",
54034 + ep->dwc_ep.xfer_len,
54035 + deptsiz.b.xfersize,
54036 + deptsiz.b.pktcnt);
54038 + /* Check if the whole transfer was completed,
54039 + * if no, setup transfer for next portion of data
54041 + if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
54042 + dwc_otg_ep_start_transfer(core_if,
54044 + } else if (ep->dwc_ep.sent_zlp) {
54046 + * This fragment of code should initiate 0
54047 + * length trasfer in case if it is queued
54048 + * a trasfer with size divisible to EPs max
54049 + * packet size and with usb_request zero field
54050 + * is set, which means that after data is transfered,
54051 + * it is also should be transfered
54052 + * a 0 length packet at the end. For Slave and
54053 + * Buffer DMA modes in this case SW has
54054 + * to initiate 2 transfers one with transfer size,
54055 + * and the second with 0 size. For Desriptor
54056 + * DMA mode SW is able to initiate a transfer,
54057 + * which will handle all the packets including
54058 + * the last 0 legth.
54060 + ep->dwc_ep.sent_zlp = 0;
54061 + dwc_otg_ep_start_zl_transfer(core_if,
54068 + ("Incomplete transfer (%d-%s [siz=%d pkt=%d])\n",
54070 + (ep->dwc_ep.is_in ? "IN" : "OUT"),
54071 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
54075 + dwc_otg_dev_out_ep_regs_t *out_ep_regs =
54076 + dev_if->out_ep_regs[ep->dwc_ep.num];
54077 + desc_sts.d32 = 0;
54078 + if (core_if->dma_enable) {
54079 + if (core_if->dma_desc_enable) {
54080 + dma_desc = ep->dwc_ep.desc_addr;
54082 + ep->dwc_ep.sent_zlp = 0;
54084 +#ifdef DWC_UTE_CFI
54085 + CFI_INFO("%s: BUFFER_MODE=%d\n", __func__,
54086 + ep->dwc_ep.buff_mode);
54087 + if (ep->dwc_ep.buff_mode != BM_STANDARD) {
54089 + residue = cfi_calc_desc_residue(ep);
54092 + byte_count = residue;
54096 + for (i = 0; i < ep->dwc_ep.desc_cnt;
54098 + desc_sts = dma_desc->status;
54099 + byte_count += desc_sts.b.bytes;
54103 +#ifdef DWC_UTE_CFI
54106 + /* Checking for interrupt Out transfers with not
54107 + * dword aligned mps sizes
54109 + if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_INTR &&
54110 + (ep->dwc_ep.maxpacket%4)) {
54111 + ep->dwc_ep.xfer_count =
54112 + ep->dwc_ep.total_len - byte_count;
54113 + if ((ep->dwc_ep.xfer_len %
54114 + ep->dwc_ep.maxpacket)
54115 + && (ep->dwc_ep.xfer_len /
54116 + ep->dwc_ep.maxpacket <
54117 + MAX_DMA_DESC_CNT))
54118 + ep->dwc_ep.xfer_len -=
54119 + (ep->dwc_ep.desc_cnt -
54120 + 1) * ep->dwc_ep.maxpacket +
54121 + ep->dwc_ep.xfer_len %
54122 + ep->dwc_ep.maxpacket;
54124 + ep->dwc_ep.xfer_len -=
54125 + ep->dwc_ep.desc_cnt *
54126 + ep->dwc_ep.maxpacket;
54127 + if (ep->dwc_ep.xfer_len > 0) {
54128 + dwc_otg_ep_start_transfer
54129 + (core_if, &ep->dwc_ep);
54134 + ep->dwc_ep.xfer_count =
54135 + ep->dwc_ep.total_len - byte_count +
54138 + total_len & 0x3)) & 0x3);
54144 + DWC_READ_REG32(&out_ep_regs->doeptsiz);
54146 + byte_count = (ep->dwc_ep.xfer_len -
54147 + ep->dwc_ep.xfer_count -
54148 + deptsiz.b.xfersize);
54149 + ep->dwc_ep.xfer_buff += byte_count;
54150 + ep->dwc_ep.dma_addr += byte_count;
54151 + ep->dwc_ep.xfer_count += byte_count;
54153 + /* Check if the whole transfer was completed,
54154 + * if no, setup transfer for next portion of data
54156 + if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
54157 + dwc_otg_ep_start_transfer(core_if,
54159 + } else if (ep->dwc_ep.sent_zlp) {
54161 + * This fragment of code should initiate 0
54162 + * length trasfer in case if it is queued
54163 + * a trasfer with size divisible to EPs max
54164 + * packet size and with usb_request zero field
54165 + * is set, which means that after data is transfered,
54166 + * it is also should be transfered
54167 + * a 0 length packet at the end. For Slave and
54168 + * Buffer DMA modes in this case SW has
54169 + * to initiate 2 transfers one with transfer size,
54170 + * and the second with 0 size. For Desriptor
54171 + * DMA mode SW is able to initiate a transfer,
54172 + * which will handle all the packets including
54173 + * the last 0 legth.
54175 + ep->dwc_ep.sent_zlp = 0;
54176 + dwc_otg_ep_start_zl_transfer(core_if,
54183 + /* Check if the whole transfer was completed,
54184 + * if no, setup transfer for next portion of data
54186 + if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
54187 + dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
54188 + } else if (ep->dwc_ep.sent_zlp) {
54190 + * This fragment of code should initiate 0
54191 + * length transfer in case if it is queued
54192 + * a transfer with size divisible to EPs max
54193 + * packet size and with usb_request zero field
54194 + * is set, which means that after data is transfered,
54195 + * it is also should be transfered
54196 + * a 0 length packet at the end. For Slave and
54197 + * Buffer DMA modes in this case SW has
54198 + * to initiate 2 transfers one with transfer size,
54199 + * and the second with 0 size. For Descriptor
54200 + * DMA mode SW is able to initiate a transfer,
54201 + * which will handle all the packets including
54202 + * the last 0 length.
54204 + ep->dwc_ep.sent_zlp = 0;
54205 + dwc_otg_ep_start_zl_transfer(core_if,
54212 + DWC_DEBUGPL(DBG_PCDV,
54213 + "addr %p, %d-%s len=%d cnt=%d xsize=%d pktcnt=%d\n",
54214 + &out_ep_regs->doeptsiz, ep->dwc_ep.num,
54215 + ep->dwc_ep.is_in ? "IN" : "OUT",
54216 + ep->dwc_ep.xfer_len, ep->dwc_ep.xfer_count,
54217 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
54220 + /* Complete the request */
54222 +#ifdef DWC_UTE_CFI
54223 + if (ep->dwc_ep.buff_mode != BM_STANDARD) {
54224 + req->actual = ep->dwc_ep.cfi_req_len - byte_count;
54227 + req->actual = ep->dwc_ep.xfer_count;
54228 +#ifdef DWC_UTE_CFI
54231 + if (req->dw_align_buf) {
54232 + if (!ep->dwc_ep.is_in) {
54233 + dwc_memcpy(req->buf, req->dw_align_buf, req->length);
54235 + DWC_DMA_FREE(dev, req->length, req->dw_align_buf,
54236 + req->dw_align_buf_dma);
54239 + dwc_otg_request_done(ep, req, 0);
54241 + ep->dwc_ep.start_xfer_buff = 0;
54242 + ep->dwc_ep.xfer_buff = 0;
54243 + ep->dwc_ep.xfer_len = 0;
54245 + /* If there is a request in the queue start it. */
54246 + start_next_request(ep);
54250 +#ifdef DWC_EN_ISOC
54253 + * This function BNA interrupt for Isochronous EPs
54256 +static void dwc_otg_pcd_handle_iso_bna(dwc_otg_pcd_ep_t * ep)
54258 + dwc_ep_t *dwc_ep = &ep->dwc_ep;
54259 + volatile uint32_t *addr;
54260 + depctl_data_t depctl = {.d32 = 0 };
54261 + dwc_otg_pcd_t *pcd = ep->pcd;
54262 + dwc_otg_dev_dma_desc_t *dma_desc;
54266 + dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * (dwc_ep->proc_buf_num);
54268 + if (dwc_ep->is_in) {
54269 + dev_dma_desc_sts_t sts = {.d32 = 0 };
54270 + for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
54271 + sts.d32 = dma_desc->status.d32;
54272 + sts.b_iso_in.bs = BS_HOST_READY;
54273 + dma_desc->status.d32 = sts.d32;
54276 + dev_dma_desc_sts_t sts = {.d32 = 0 };
54277 + for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
54278 + sts.d32 = dma_desc->status.d32;
54279 + sts.b_iso_out.bs = BS_HOST_READY;
54280 + dma_desc->status.d32 = sts.d32;
54284 + if (dwc_ep->is_in == 0) {
54286 + &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->
54290 + &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
54292 + depctl.b.epena = 1;
54293 + DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
54297 + * This function sets latest iso packet information(non-PTI mode)
54299 + * @param core_if Programming view of DWC_otg controller.
54300 + * @param ep The EP to start the transfer on.
54303 +void set_current_pkt_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
54305 + deptsiz_data_t deptsiz = {.d32 = 0 };
54306 + dma_addr_t dma_addr;
54309 + if (ep->proc_buf_num)
54310 + dma_addr = ep->dma_addr1;
54312 + dma_addr = ep->dma_addr0;
54316 + DWC_READ_REG32(&core_if->dev_if->
54317 + in_ep_regs[ep->num]->dieptsiz);
54318 + offset = ep->data_per_frame;
54321 + DWC_READ_REG32(&core_if->dev_if->
54322 + out_ep_regs[ep->num]->doeptsiz);
54324 + ep->data_per_frame +
54325 + (0x4 & (0x4 - (ep->data_per_frame & 0x3)));
54328 + if (!deptsiz.b.xfersize) {
54329 + ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
54330 + ep->pkt_info[ep->cur_pkt].offset =
54331 + ep->cur_pkt_dma_addr - dma_addr;
54332 + ep->pkt_info[ep->cur_pkt].status = 0;
54334 + ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
54335 + ep->pkt_info[ep->cur_pkt].offset =
54336 + ep->cur_pkt_dma_addr - dma_addr;
54337 + ep->pkt_info[ep->cur_pkt].status = -DWC_E_NO_DATA;
54339 + ep->cur_pkt_addr += offset;
54340 + ep->cur_pkt_dma_addr += offset;
54345 + * This function sets latest iso packet information(DDMA mode)
54347 + * @param core_if Programming view of DWC_otg controller.
54348 + * @param dwc_ep The EP to start the transfer on.
54351 +static void set_ddma_iso_pkts_info(dwc_otg_core_if_t * core_if,
54352 + dwc_ep_t * dwc_ep)
54354 + dwc_otg_dev_dma_desc_t *dma_desc;
54355 + dev_dma_desc_sts_t sts = {.d32 = 0 };
54356 + iso_pkt_info_t *iso_packet;
54357 + uint32_t data_per_desc;
54361 + iso_packet = dwc_ep->pkt_info;
54363 + /** Reinit closed DMA Descriptors*/
54364 + /** ISO OUT EP */
54365 + if (dwc_ep->is_in == 0) {
54367 + dwc_ep->iso_desc_addr +
54368 + dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
54371 + for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
54372 + i += dwc_ep->pkt_per_frm) {
54373 + for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
54375 + ((j + 1) * dwc_ep->maxpacket >
54377 + data_per_frame) ? dwc_ep->data_per_frame -
54378 + j * dwc_ep->maxpacket : dwc_ep->maxpacket;
54380 + (data_per_desc % 4) ? (4 -
54384 + sts.d32 = dma_desc->status.d32;
54386 + /* Write status in iso_packet_decsriptor */
54387 + iso_packet->status =
54388 + sts.b_iso_out.rxsts +
54389 + (sts.b_iso_out.bs ^ BS_DMA_DONE);
54390 + if (iso_packet->status) {
54391 + iso_packet->status = -DWC_E_NO_DATA;
54394 + /* Received data length */
54395 + if (!sts.b_iso_out.rxbytes) {
54396 + iso_packet->length =
54398 + sts.b_iso_out.rxbytes;
54400 + iso_packet->length =
54402 + sts.b_iso_out.rxbytes + (4 -
54403 + dwc_ep->data_per_frame
54407 + iso_packet->offset = offset;
54409 + offset += data_per_desc;
54415 + for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
54417 + ((j + 1) * dwc_ep->maxpacket >
54418 + dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
54419 + j * dwc_ep->maxpacket : dwc_ep->maxpacket;
54421 + (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
54423 + sts.d32 = dma_desc->status.d32;
54425 + /* Write status in iso_packet_decsriptor */
54426 + iso_packet->status =
54427 + sts.b_iso_out.rxsts +
54428 + (sts.b_iso_out.bs ^ BS_DMA_DONE);
54429 + if (iso_packet->status) {
54430 + iso_packet->status = -DWC_E_NO_DATA;
54433 + /* Received data length */
54434 + iso_packet->length =
54435 + dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
54437 + iso_packet->offset = offset;
54439 + offset += data_per_desc;
54444 + sts.d32 = dma_desc->status.d32;
54446 + /* Write status in iso_packet_decsriptor */
54447 + iso_packet->status =
54448 + sts.b_iso_out.rxsts + (sts.b_iso_out.bs ^ BS_DMA_DONE);
54449 + if (iso_packet->status) {
54450 + iso_packet->status = -DWC_E_NO_DATA;
54452 + /* Received data length */
54453 + if (!sts.b_iso_out.rxbytes) {
54454 + iso_packet->length =
54455 + dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
54457 + iso_packet->length =
54458 + dwc_ep->data_per_frame - sts.b_iso_out.rxbytes +
54459 + (4 - dwc_ep->data_per_frame % 4);
54462 + iso_packet->offset = offset;
54467 + dwc_ep->iso_desc_addr +
54468 + dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
54470 + for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
54471 + sts.d32 = dma_desc->status.d32;
54473 + /* Write status in iso packet descriptor */
54474 + iso_packet->status =
54475 + sts.b_iso_in.txsts +
54476 + (sts.b_iso_in.bs ^ BS_DMA_DONE);
54477 + if (iso_packet->status != 0) {
54478 + iso_packet->status = -DWC_E_NO_DATA;
54481 + /* Bytes has been transfered */
54482 + iso_packet->length =
54483 + dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
54489 + sts.d32 = dma_desc->status.d32;
54490 + while (sts.b_iso_in.bs == BS_DMA_BUSY) {
54491 + sts.d32 = dma_desc->status.d32;
54494 + /* Write status in iso packet descriptor ??? do be done with ERROR codes */
54495 + iso_packet->status =
54496 + sts.b_iso_in.txsts + (sts.b_iso_in.bs ^ BS_DMA_DONE);
54497 + if (iso_packet->status != 0) {
54498 + iso_packet->status = -DWC_E_NO_DATA;
54501 + /* Bytes has been transfered */
54502 + iso_packet->length =
54503 + dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
54508 + * This function reinitialize DMA Descriptors for Isochronous transfer
54510 + * @param core_if Programming view of DWC_otg controller.
54511 + * @param dwc_ep The EP to start the transfer on.
54514 +static void reinit_ddma_iso_xfer(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep)
54517 + dwc_otg_dev_dma_desc_t *dma_desc;
54518 + dma_addr_t dma_ad;
54519 + volatile uint32_t *addr;
54520 + dev_dma_desc_sts_t sts = {.d32 = 0 };
54521 + uint32_t data_per_desc;
54523 + if (dwc_ep->is_in == 0) {
54524 + addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
54526 + addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
54529 + if (dwc_ep->proc_buf_num == 0) {
54530 + /** Buffer 0 descriptors setup */
54531 + dma_ad = dwc_ep->dma_addr0;
54533 + /** Buffer 1 descriptors setup */
54534 + dma_ad = dwc_ep->dma_addr1;
54537 + /** Reinit closed DMA Descriptors*/
54538 + /** ISO OUT EP */
54539 + if (dwc_ep->is_in == 0) {
54541 + dwc_ep->iso_desc_addr +
54542 + dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
54544 + sts.b_iso_out.bs = BS_HOST_READY;
54545 + sts.b_iso_out.rxsts = 0;
54546 + sts.b_iso_out.l = 0;
54547 + sts.b_iso_out.sp = 0;
54548 + sts.b_iso_out.ioc = 0;
54549 + sts.b_iso_out.pid = 0;
54550 + sts.b_iso_out.framenum = 0;
54552 + for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
54553 + i += dwc_ep->pkt_per_frm) {
54554 + for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
54556 + ((j + 1) * dwc_ep->maxpacket >
54558 + data_per_frame) ? dwc_ep->data_per_frame -
54559 + j * dwc_ep->maxpacket : dwc_ep->maxpacket;
54561 + (data_per_desc % 4) ? (4 -
54564 + sts.b_iso_out.rxbytes = data_per_desc;
54565 + dma_desc->buf = dma_ad;
54566 + dma_desc->status.d32 = sts.d32;
54568 + dma_ad += data_per_desc;
54573 + for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
54576 + ((j + 1) * dwc_ep->maxpacket >
54577 + dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
54578 + j * dwc_ep->maxpacket : dwc_ep->maxpacket;
54580 + (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
54581 + sts.b_iso_out.rxbytes = data_per_desc;
54583 + dma_desc->buf = dma_ad;
54584 + dma_desc->status.d32 = sts.d32;
54587 + dma_ad += data_per_desc;
54590 + sts.b_iso_out.ioc = 1;
54591 + sts.b_iso_out.l = dwc_ep->proc_buf_num;
54594 + ((j + 1) * dwc_ep->maxpacket >
54595 + dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
54596 + j * dwc_ep->maxpacket : dwc_ep->maxpacket;
54598 + (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
54599 + sts.b_iso_out.rxbytes = data_per_desc;
54601 + dma_desc->buf = dma_ad;
54602 + dma_desc->status.d32 = sts.d32;
54607 + dwc_ep->iso_desc_addr +
54608 + dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
54610 + sts.b_iso_in.bs = BS_HOST_READY;
54611 + sts.b_iso_in.txsts = 0;
54612 + sts.b_iso_in.sp = 0;
54613 + sts.b_iso_in.ioc = 0;
54614 + sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
54615 + sts.b_iso_in.framenum = dwc_ep->next_frame;
54616 + sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
54617 + sts.b_iso_in.l = 0;
54619 + for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
54620 + dma_desc->buf = dma_ad;
54621 + dma_desc->status.d32 = sts.d32;
54623 + sts.b_iso_in.framenum += dwc_ep->bInterval;
54624 + dma_ad += dwc_ep->data_per_frame;
54628 + sts.b_iso_in.ioc = 1;
54629 + sts.b_iso_in.l = dwc_ep->proc_buf_num;
54631 + dma_desc->buf = dma_ad;
54632 + dma_desc->status.d32 = sts.d32;
54634 + dwc_ep->next_frame =
54635 + sts.b_iso_in.framenum + dwc_ep->bInterval * 1;
54637 + dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
54641 + * This function is to handle Iso EP transfer complete interrupt
54642 + * in case Iso out packet was dropped
54644 + * @param core_if Programming view of DWC_otg controller.
54645 + * @param dwc_ep The EP for wihich transfer complete was asserted
54648 +static uint32_t handle_iso_out_pkt_dropped(dwc_otg_core_if_t * core_if,
54649 + dwc_ep_t * dwc_ep)
54651 + uint32_t dma_addr;
54652 + uint32_t drp_pkt;
54653 + uint32_t drp_pkt_cnt;
54654 + deptsiz_data_t deptsiz = {.d32 = 0 };
54655 + depctl_data_t depctl = {.d32 = 0 };
54659 + DWC_READ_REG32(&core_if->dev_if->
54660 + out_ep_regs[dwc_ep->num]->doeptsiz);
54662 + drp_pkt = dwc_ep->pkt_cnt - deptsiz.b.pktcnt;
54663 + drp_pkt_cnt = dwc_ep->pkt_per_frm - (drp_pkt % dwc_ep->pkt_per_frm);
54665 + /* Setting dropped packets status */
54666 + for (i = 0; i < drp_pkt_cnt; ++i) {
54667 + dwc_ep->pkt_info[drp_pkt].status = -DWC_E_NO_DATA;
54669 + deptsiz.b.pktcnt--;
54672 + if (deptsiz.b.pktcnt > 0) {
54673 + deptsiz.b.xfersize =
54674 + dwc_ep->xfer_len - (dwc_ep->pkt_cnt -
54675 + deptsiz.b.pktcnt) * dwc_ep->maxpacket;
54677 + deptsiz.b.xfersize = 0;
54678 + deptsiz.b.pktcnt = 0;
54681 + DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz,
54684 + if (deptsiz.b.pktcnt > 0) {
54685 + if (dwc_ep->proc_buf_num) {
54687 + dwc_ep->dma_addr1 + dwc_ep->xfer_len -
54688 + deptsiz.b.xfersize;
54691 + dwc_ep->dma_addr0 + dwc_ep->xfer_len -
54692 + deptsiz.b.xfersize;;
54695 + DWC_WRITE_REG32(&core_if->dev_if->
54696 + out_ep_regs[dwc_ep->num]->doepdma, dma_addr);
54698 + /** Re-enable endpoint, clear nak */
54700 + depctl.b.epena = 1;
54701 + depctl.b.cnak = 1;
54703 + DWC_MODIFY_REG32(&core_if->dev_if->
54704 + out_ep_regs[dwc_ep->num]->doepctl, depctl.d32,
54713 + * This function sets iso packets information(PTI mode)
54715 + * @param core_if Programming view of DWC_otg controller.
54716 + * @param ep The EP to start the transfer on.
54719 +static uint32_t set_iso_pkts_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
54722 + dma_addr_t dma_ad;
54723 + iso_pkt_info_t *packet_info = ep->pkt_info;
54725 + uint32_t frame_data;
54726 + deptsiz_data_t deptsiz;
54728 + if (ep->proc_buf_num == 0) {
54729 + /** Buffer 0 descriptors setup */
54730 + dma_ad = ep->dma_addr0;
54732 + /** Buffer 1 descriptors setup */
54733 + dma_ad = ep->dma_addr1;
54738 + DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
54742 + DWC_READ_REG32(&core_if->dev_if->out_ep_regs[ep->num]->
54746 + if (!deptsiz.b.xfersize) {
54748 + for (i = 0; i < ep->pkt_cnt; i += ep->pkt_per_frm) {
54749 + frame_data = ep->data_per_frame;
54750 + for (j = 0; j < ep->pkt_per_frm; ++j) {
54752 + /* Packet status - is not set as initially
54753 + * it is set to 0 and if packet was sent
54754 + successfully, status field will remain 0*/
54756 + /* Bytes has been transfered */
54757 + packet_info->length =
54759 + frame_data) ? ep->maxpacket : frame_data;
54761 + /* Received packet offset */
54762 + packet_info->offset = offset;
54763 + offset += packet_info->length;
54764 + frame_data -= packet_info->length;
54771 + /* This is a workaround for in case of Transfer Complete with
54772 + * PktDrpSts interrupts merging - in this case Transfer complete
54773 + * interrupt for Isoc Out Endpoint is asserted without PktDrpSts
54774 + * set and with DOEPTSIZ register non zero. Investigations showed,
54775 + * that this happens when Out packet is dropped, but because of
54776 + * interrupts merging during first interrupt handling PktDrpSts
54777 + * bit is cleared and for next merged interrupts it is not reset.
54778 + * In this case SW hadles the interrupt as if PktDrpSts bit is set.
54783 + return handle_iso_out_pkt_dropped(core_if, ep);
54789 + * This function is to handle Iso EP transfer complete interrupt
54791 + * @param pcd The PCD
54792 + * @param ep The EP for which transfer complete was asserted
54795 +static void complete_iso_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)
54797 + dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
54798 + dwc_ep_t *dwc_ep = &ep->dwc_ep;
54799 + uint8_t is_last = 0;
54801 + if (ep->dwc_ep.next_frame == 0xffffffff) {
54802 + DWC_WARN("Next frame is not set!\n");
54806 + if (core_if->dma_enable) {
54807 + if (core_if->dma_desc_enable) {
54808 + set_ddma_iso_pkts_info(core_if, dwc_ep);
54809 + reinit_ddma_iso_xfer(core_if, dwc_ep);
54812 + if (core_if->pti_enh_enable) {
54813 + if (set_iso_pkts_info(core_if, dwc_ep)) {
54814 + dwc_ep->proc_buf_num =
54815 + (dwc_ep->proc_buf_num ^ 1) & 0x1;
54816 + dwc_otg_iso_ep_start_buf_transfer
54817 + (core_if, dwc_ep);
54821 + set_current_pkt_info(core_if, dwc_ep);
54822 + if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
54824 + dwc_ep->cur_pkt = 0;
54825 + dwc_ep->proc_buf_num =
54826 + (dwc_ep->proc_buf_num ^ 1) & 0x1;
54827 + if (dwc_ep->proc_buf_num) {
54828 + dwc_ep->cur_pkt_addr =
54829 + dwc_ep->xfer_buff1;
54830 + dwc_ep->cur_pkt_dma_addr =
54831 + dwc_ep->dma_addr1;
54833 + dwc_ep->cur_pkt_addr =
54834 + dwc_ep->xfer_buff0;
54835 + dwc_ep->cur_pkt_dma_addr =
54836 + dwc_ep->dma_addr0;
54840 + dwc_otg_iso_ep_start_frm_transfer(core_if,
54845 + set_current_pkt_info(core_if, dwc_ep);
54846 + if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
54848 + dwc_ep->cur_pkt = 0;
54849 + dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
54850 + if (dwc_ep->proc_buf_num) {
54851 + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
54852 + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
54854 + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
54855 + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
54859 + dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep);
54862 + dwc_otg_iso_buffer_done(pcd, ep, ep->iso_req_handle);
54864 +#endif /* DWC_EN_ISOC */
54867 + * This function handle BNA interrupt for Non Isochronous EPs
54870 +static void dwc_otg_pcd_handle_noniso_bna(dwc_otg_pcd_ep_t * ep)
54872 + dwc_ep_t *dwc_ep = &ep->dwc_ep;
54873 + volatile uint32_t *addr;
54874 + depctl_data_t depctl = {.d32 = 0 };
54875 + dwc_otg_pcd_t *pcd = ep->pcd;
54876 + dwc_otg_dev_dma_desc_t *dma_desc;
54877 + dev_dma_desc_sts_t sts = {.d32 = 0 };
54878 + dwc_otg_core_if_t *core_if = ep->pcd->core_if;
54881 + if (!dwc_ep->desc_cnt)
54882 + DWC_WARN("Ep%d %s Descriptor count = %d \n", dwc_ep->num,
54883 + (dwc_ep->is_in ? "IN" : "OUT"), dwc_ep->desc_cnt);
54885 + if (core_if->core_params->cont_on_bna && !dwc_ep->is_in
54886 + && dwc_ep->type != DWC_OTG_EP_TYPE_CONTROL) {
54887 + uint32_t doepdma;
54888 + dwc_otg_dev_out_ep_regs_t *out_regs =
54889 + core_if->dev_if->out_ep_regs[dwc_ep->num];
54890 + doepdma = DWC_READ_REG32(&(out_regs->doepdma));
54891 + start = (doepdma - dwc_ep->dma_desc_addr)/sizeof(dwc_otg_dev_dma_desc_t);
54892 + dma_desc = &(dwc_ep->desc_addr[start]);
54895 + dma_desc = dwc_ep->desc_addr;
54899 + for (i = start; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
54900 + sts.d32 = dma_desc->status.d32;
54901 + sts.b.bs = BS_HOST_READY;
54902 + dma_desc->status.d32 = sts.d32;
54905 + if (dwc_ep->is_in == 0) {
54907 + &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->num]->
54911 + &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
54913 + depctl.b.epena = 1;
54914 + depctl.b.cnak = 1;
54915 + DWC_MODIFY_REG32(addr, 0, depctl.d32);
54919 + * This function handles EP0 Control transfers.
54921 + * The state of the control transfers are tracked in
54922 + * <code>ep0state</code>.
54924 +static void handle_ep0(dwc_otg_pcd_t * pcd)
54926 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
54927 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
54928 + dev_dma_desc_sts_t desc_sts;
54929 + deptsiz0_data_t deptsiz;
54930 + uint32_t byte_count;
54933 + DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
54934 + print_ep0_state(pcd);
54937 +// DWC_PRINTF("HANDLE EP0\n");
54939 + switch (pcd->ep0state) {
54940 + case EP0_DISCONNECT:
54944 + pcd->request_config = 0;
54949 + case EP0_IN_DATA_PHASE:
54951 + DWC_DEBUGPL(DBG_PCD, "DATA_IN EP%d-%s: type=%d, mps=%d\n",
54952 + ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"),
54953 + ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
54956 + if (core_if->dma_enable != 0) {
54958 + * For EP0 we can only program 1 packet at a time so we
54959 + * need to do the make calculations after each complete.
54960 + * Call write_packet to make the calculations, as in
54961 + * slave mode, and use those values to determine if we
54964 + if (core_if->dma_desc_enable == 0) {
54966 + DWC_READ_REG32(&core_if->
54967 + dev_if->in_ep_regs[0]->
54970 + ep0->dwc_ep.xfer_len - deptsiz.b.xfersize;
54973 + core_if->dev_if->in_desc_addr->status;
54975 + ep0->dwc_ep.xfer_len - desc_sts.b.bytes;
54977 + ep0->dwc_ep.xfer_count += byte_count;
54978 + ep0->dwc_ep.xfer_buff += byte_count;
54979 + ep0->dwc_ep.dma_addr += byte_count;
54981 + if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
54982 + dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
54984 + DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
54985 + } else if (ep0->dwc_ep.sent_zlp) {
54986 + dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
54988 + ep0->dwc_ep.sent_zlp = 0;
54989 + DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER sent zlp\n");
54991 + ep0_complete_request(ep0);
54992 + DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
54995 + case EP0_OUT_DATA_PHASE:
54997 + DWC_DEBUGPL(DBG_PCD, "DATA_OUT EP%d-%s: type=%d, mps=%d\n",
54998 + ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"),
54999 + ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
55001 + if (core_if->dma_enable != 0) {
55002 + if (core_if->dma_desc_enable == 0) {
55004 + DWC_READ_REG32(&core_if->
55005 + dev_if->out_ep_regs[0]->
55008 + ep0->dwc_ep.maxpacket - deptsiz.b.xfersize;
55011 + core_if->dev_if->out_desc_addr->status;
55013 + ep0->dwc_ep.maxpacket - desc_sts.b.bytes;
55015 + ep0->dwc_ep.xfer_count += byte_count;
55016 + ep0->dwc_ep.xfer_buff += byte_count;
55017 + ep0->dwc_ep.dma_addr += byte_count;
55019 + if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
55020 + dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
55022 + DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
55023 + } else if (ep0->dwc_ep.sent_zlp) {
55024 + dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
55026 + ep0->dwc_ep.sent_zlp = 0;
55027 + DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER sent zlp\n");
55029 + ep0_complete_request(ep0);
55030 + DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
55034 + case EP0_IN_STATUS_PHASE:
55035 + case EP0_OUT_STATUS_PHASE:
55036 + DWC_DEBUGPL(DBG_PCD, "CASE: EP0_STATUS\n");
55037 + ep0_complete_request(ep0);
55038 + pcd->ep0state = EP0_IDLE;
55039 + ep0->stopped = 1;
55040 + ep0->dwc_ep.is_in = 0; /* OUT for next SETUP */
55042 + /* Prepare for more SETUP Packets */
55043 + if (core_if->dma_enable) {
55044 + ep0_out_start(core_if, pcd);
55049 + DWC_ERROR("EP0 STALLed, should not get here pcd_setup()\n");
55053 + print_ep0_state(pcd);
55058 + * Restart transfer
55060 +static void restart_transfer(dwc_otg_pcd_t * pcd, const uint32_t epnum)
55062 + dwc_otg_core_if_t *core_if;
55063 + dwc_otg_dev_if_t *dev_if;
55064 + deptsiz_data_t dieptsiz = {.d32 = 0 };
55065 + dwc_otg_pcd_ep_t *ep;
55067 + ep = get_in_ep(pcd, epnum);
55069 +#ifdef DWC_EN_ISOC
55070 + if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
55073 +#endif /* DWC_EN_ISOC */
55075 + core_if = GET_CORE_IF(pcd);
55076 + dev_if = core_if->dev_if;
55078 + dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz);
55080 + DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x xfer_len=%0x"
55081 + " stopped=%d\n", ep->dwc_ep.xfer_buff,
55082 + ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len, ep->stopped);
55084 + * If xfersize is 0 and pktcnt in not 0, resend the last packet.
55086 + if (dieptsiz.b.pktcnt && dieptsiz.b.xfersize == 0 &&
55087 + ep->dwc_ep.start_xfer_buff != 0) {
55088 + if (ep->dwc_ep.total_len <= ep->dwc_ep.maxpacket) {
55089 + ep->dwc_ep.xfer_count = 0;
55090 + ep->dwc_ep.xfer_buff = ep->dwc_ep.start_xfer_buff;
55091 + ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
55093 + ep->dwc_ep.xfer_count -= ep->dwc_ep.maxpacket;
55094 + /* convert packet size to dwords. */
55095 + ep->dwc_ep.xfer_buff -= ep->dwc_ep.maxpacket;
55096 + ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
55099 + DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x "
55100 + "xfer_len=%0x stopped=%d\n",
55101 + ep->dwc_ep.xfer_buff,
55102 + ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len,
55104 + if (epnum == 0) {
55105 + dwc_otg_ep0_start_transfer(core_if, &ep->dwc_ep);
55107 + dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
55113 + * This function create new nextep sequnce based on Learn Queue.
55115 + * @param core_if Programming view of DWC_otg controller
55117 +void predict_nextep_seq( dwc_otg_core_if_t * core_if)
55119 + dwc_otg_device_global_regs_t *dev_global_regs =
55120 + core_if->dev_if->dev_global_regs;
55121 + const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;
55122 + /* Number of Token Queue Registers */
55123 + const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
55124 + dtknq1_data_t dtknqr1;
55125 + uint32_t in_tkn_epnums[4];
55126 + uint8_t seqnum[MAX_EPS_CHANNELS];
55127 + uint8_t intkn_seq[TOKEN_Q_DEPTH];
55128 + grstctl_t resetctl = {.d32 = 0 };
55133 + int sort_done = 0;
55135 + volatile uint32_t *addr = &dev_global_regs->dtknqr1;
55138 + DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);
55140 + /* Read the DTKNQ Registers */
55141 + for (i = 0; i < DTKNQ_REG_CNT; i++) {
55142 + in_tkn_epnums[i] = DWC_READ_REG32(addr);
55143 + DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1,
55144 + in_tkn_epnums[i]);
55145 + if (addr == &dev_global_regs->dvbusdis) {
55146 + addr = &dev_global_regs->dtknqr3_dthrctl;
55153 + /* Copy the DTKNQR1 data to the bit field. */
55154 + dtknqr1.d32 = in_tkn_epnums[0];
55155 + if (dtknqr1.b.wrap_bit) {
55156 + ndx = dtknqr1.b.intknwptr;
55159 + end = TOKEN_Q_DEPTH -1;
55162 + end = dtknqr1.b.intknwptr -1;
55168 + /* Fill seqnum[] by initial values: EP number + 31 */
55169 + for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
55170 + seqnum[i] = i +31;
55173 + /* Fill intkn_seq[] from in_tkn_epnums[0] */
55174 + for (i=0; i < 6; i++)
55175 + intkn_seq[i] = (in_tkn_epnums[0] >> ((7-i) * 4)) & 0xf;
55177 + if (TOKEN_Q_DEPTH > 6) {
55178 + /* Fill intkn_seq[] from in_tkn_epnums[1] */
55179 + for (i=6; i < 14; i++)
55181 + (in_tkn_epnums[1] >> ((7 - (i - 6)) * 4)) & 0xf;
55184 + if (TOKEN_Q_DEPTH > 14) {
55185 + /* Fill intkn_seq[] from in_tkn_epnums[1] */
55186 + for (i=14; i < 22; i++)
55188 + (in_tkn_epnums[2] >> ((7 - (i - 14)) * 4)) & 0xf;
55191 + if (TOKEN_Q_DEPTH > 22) {
55192 + /* Fill intkn_seq[] from in_tkn_epnums[1] */
55193 + for (i=22; i < 30; i++)
55195 + (in_tkn_epnums[3] >> ((7 - (i - 22)) * 4)) & 0xf;
55198 + DWC_DEBUGPL(DBG_PCDV, "%s start=%d end=%d intkn_seq[]:\n", __func__,
55200 + for (i=0; i<TOKEN_Q_DEPTH; i++)
55201 + DWC_DEBUGPL(DBG_PCDV,"%d\n", intkn_seq[i]);
55203 + /* Update seqnum based on intkn_seq[] */
55206 + seqnum[intkn_seq[ndx]] = i;
55209 + if (ndx == TOKEN_Q_DEPTH)
55211 + } while ( i < TOKEN_Q_DEPTH );
55213 + /* Mark non active EP's in seqnum[] by 0xff */
55214 + for (i=0; i<=core_if->dev_if->num_in_eps; i++) {
55215 + if (core_if->nextep_seq[i] == 0xff )
55216 + seqnum[i] = 0xff;
55219 + /* Sort seqnum[] */
55221 + while (!sort_done) {
55223 + for (i=0; i<core_if->dev_if->num_in_eps; i++) {
55224 + if (seqnum[i] > seqnum[i+1]) {
55225 + temp = seqnum[i];
55226 + seqnum[i] = seqnum[i+1];
55227 + seqnum[i+1] = temp;
55233 + ndx = start + seqnum[0];
55234 + if (ndx >= TOKEN_Q_DEPTH)
55235 + ndx = ndx % TOKEN_Q_DEPTH;
55236 + core_if->first_in_nextep_seq = intkn_seq[ndx];
55238 + /* Update seqnum[] by EP numbers */
55239 + for (i=0; i<=core_if->dev_if->num_in_eps; i++) {
55241 + if (seqnum[i] < 31) {
55242 + ndx = start + seqnum[i];
55243 + if (ndx >= TOKEN_Q_DEPTH)
55244 + ndx = ndx % TOKEN_Q_DEPTH;
55245 + seqnum[i] = intkn_seq[ndx];
55247 + if (seqnum[i] < 0xff) {
55248 + seqnum[i] = seqnum[i] - 31;
55255 + /* Update nextep_seq[] based on seqnum[] */
55256 + for (i=0; i<core_if->dev_if->num_in_eps; i++) {
55257 + if (seqnum[i] != 0xff) {
55258 + if (seqnum[i+1] != 0xff) {
55259 + core_if->nextep_seq[seqnum[i]] = seqnum[i+1];
55261 + core_if->nextep_seq[seqnum[i]] = core_if->first_in_nextep_seq;
55269 + DWC_DEBUGPL(DBG_PCDV, "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
55270 + __func__, core_if->first_in_nextep_seq);
55271 + for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
55272 + DWC_DEBUGPL(DBG_PCDV,"%2d\n", core_if->nextep_seq[i]);
55275 + /* Flush the Learning Queue */
55276 + resetctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->grstctl);
55277 + resetctl.b.intknqflsh = 1;
55278 + DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
55284 + * handle the IN EP disable interrupt.
55286 +static inline void handle_in_ep_disable_intr(dwc_otg_pcd_t * pcd,
55287 + const uint32_t epnum)
55289 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
55290 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
55291 + deptsiz_data_t dieptsiz = {.d32 = 0 };
55292 + dctl_data_t dctl = {.d32 = 0 };
55293 + dwc_otg_pcd_ep_t *ep;
55294 + dwc_ep_t *dwc_ep;
55295 + gintmsk_data_t gintmsk_data;
55296 + depctl_data_t depctl;
55297 + uint32_t diepdma;
55298 + uint32_t remain_to_transfer = 0;
55300 + uint32_t xfer_size;
55302 + ep = get_in_ep(pcd, epnum);
55303 + dwc_ep = &ep->dwc_ep;
55305 + if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
55306 + dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
55311 + DWC_DEBUGPL(DBG_PCD, "diepctl%d=%0x\n", epnum,
55312 + DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl));
55313 + dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz);
55314 + depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
55316 + DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
55317 + dieptsiz.b.pktcnt, dieptsiz.b.xfersize);
55319 + if ((core_if->start_predict == 0) || (depctl.b.eptype & 1)) {
55320 + if (ep->stopped) {
55321 + if (core_if->en_multiple_tx_fifo)
55322 + /* Flush the Tx FIFO */
55323 + dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
55324 + /* Clear the Global IN NP NAK */
55326 + dctl.b.cgnpinnak = 1;
55327 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
55328 + /* Restart the transaction */
55329 + if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {
55330 + restart_transfer(pcd, epnum);
55333 + /* Restart the transaction */
55334 + if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {
55335 + restart_transfer(pcd, epnum);
55337 + DWC_DEBUGPL(DBG_ANY, "STOPPED!!!\n");
55342 + if (core_if->start_predict > 2) { // NP IN EP
55343 + core_if->start_predict--;
55347 + core_if->start_predict--;
55349 + if (core_if->start_predict == 1) { // All NP IN Ep's disabled now
55351 + predict_nextep_seq(core_if);
55353 + /* Update all active IN EP's NextEP field based of nextep_seq[] */
55354 + for ( i = 0; i <= core_if->dev_if->num_in_eps; i++) {
55356 + DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
55357 + if (core_if->nextep_seq[i] != 0xff) { // Active NP IN EP
55358 + depctl.b.nextep = core_if->nextep_seq[i];
55359 + DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
55362 + /* Flush Shared NP TxFIFO */
55363 + dwc_otg_flush_tx_fifo(core_if, 0);
55364 + /* Rewind buffers */
55365 + if (!core_if->dma_desc_enable) {
55366 + i = core_if->first_in_nextep_seq;
55368 + ep = get_in_ep(pcd, i);
55369 + dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
55370 + xfer_size = ep->dwc_ep.total_len - ep->dwc_ep.xfer_count;
55371 + if (xfer_size > ep->dwc_ep.maxxfer)
55372 + xfer_size = ep->dwc_ep.maxxfer;
55373 + depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
55374 + if (dieptsiz.b.pktcnt != 0) {
55375 + if (xfer_size == 0) {
55376 + remain_to_transfer = 0;
55378 + if ((xfer_size % ep->dwc_ep.maxpacket) == 0) {
55379 + remain_to_transfer =
55380 + dieptsiz.b.pktcnt * ep->dwc_ep.maxpacket;
55382 + remain_to_transfer = ((dieptsiz.b.pktcnt -1) * ep->dwc_ep.maxpacket)
55383 + + (xfer_size % ep->dwc_ep.maxpacket);
55386 + diepdma = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepdma);
55387 + dieptsiz.b.xfersize = remain_to_transfer;
55388 + DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, dieptsiz.d32);
55389 + diepdma = ep->dwc_ep.dma_addr + (xfer_size - remain_to_transfer);
55390 + DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, diepdma);
55392 + i = core_if->nextep_seq[i];
55393 + } while (i != core_if->first_in_nextep_seq);
55394 + } else { // dma_desc_enable
55395 + DWC_PRINTF("%s Learning Queue not supported in DDMA\n", __func__);
55398 + /* Restart transfers in predicted sequences */
55399 + i = core_if->first_in_nextep_seq;
55401 + dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
55402 + depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
55403 + if (dieptsiz.b.pktcnt != 0) {
55404 + depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
55405 + depctl.b.epena = 1;
55406 + depctl.b.cnak = 1;
55407 + DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
55409 + i = core_if->nextep_seq[i];
55410 + } while (i != core_if->first_in_nextep_seq);
55412 + /* Clear the global non-periodic IN NAK handshake */
55414 + dctl.b.cgnpinnak = 1;
55415 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
55417 + /* Unmask EP Mismatch interrupt */
55418 + gintmsk_data.d32 = 0;
55419 + gintmsk_data.b.epmismatch = 1;
55420 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, gintmsk_data.d32);
55422 + core_if->start_predict = 0;
55428 + * Handler for the IN EP timeout handshake interrupt.
55430 +static inline void handle_in_ep_timeout_intr(dwc_otg_pcd_t * pcd,
55431 + const uint32_t epnum)
55433 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
55434 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
55437 + deptsiz_data_t dieptsiz = {.d32 = 0 };
55438 + uint32_t num = 0;
55440 + dctl_data_t dctl = {.d32 = 0 };
55441 + dwc_otg_pcd_ep_t *ep;
55443 + gintmsk_data_t intr_mask = {.d32 = 0 };
55445 + ep = get_in_ep(pcd, epnum);
55447 + /* Disable the NP Tx Fifo Empty Interrrupt */
55448 + if (!core_if->dma_enable) {
55449 + intr_mask.b.nptxfempty = 1;
55450 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
55451 + intr_mask.d32, 0);
55453 + /** @todo NGS Check EP type.
55454 + * Implement for Periodic EPs */
55456 + * Non-periodic EP
55458 + /* Enable the Global IN NAK Effective Interrupt */
55459 + intr_mask.b.ginnakeff = 1;
55460 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32);
55462 + /* Set Global IN NAK */
55463 + dctl.b.sgnpinnak = 1;
55464 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
55469 + dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[num]->dieptsiz);
55470 + DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
55471 + dieptsiz.b.pktcnt, dieptsiz.b.xfersize);
55474 +#ifdef DISABLE_PERIODIC_EP
55476 + * Set the NAK bit for this EP to
55477 + * start the disable process.
55480 + diepctl.b.snak = 1;
55481 + DWC_MODIFY_REG32(&dev_if->in_ep_regs[num]->diepctl, diepctl.d32,
55483 + ep->disabling = 1;
55489 + * Handler for the IN EP NAK interrupt.
55491 +static inline int32_t handle_in_ep_nak_intr(dwc_otg_pcd_t * pcd,
55492 + const uint32_t epnum)
55494 + /** @todo implement ISR */
55495 + dwc_otg_core_if_t *core_if;
55496 + diepmsk_data_t intr_mask = {.d32 = 0 };
55498 + DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "IN EP NAK");
55499 + core_if = GET_CORE_IF(pcd);
55500 + intr_mask.b.nak = 1;
55502 + if (core_if->multiproc_int_enable) {
55503 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
55504 + diepeachintmsk[epnum], intr_mask.d32, 0);
55506 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->diepmsk,
55507 + intr_mask.d32, 0);
55514 + * Handler for the OUT EP Babble interrupt.
55516 +static inline int32_t handle_out_ep_babble_intr(dwc_otg_pcd_t * pcd,
55517 + const uint32_t epnum)
55519 + /** @todo implement ISR */
55520 + dwc_otg_core_if_t *core_if;
55521 + doepmsk_data_t intr_mask = {.d32 = 0 };
55523 + DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
55524 + "OUT EP Babble");
55525 + core_if = GET_CORE_IF(pcd);
55526 + intr_mask.b.babble = 1;
55528 + if (core_if->multiproc_int_enable) {
55529 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
55530 + doepeachintmsk[epnum], intr_mask.d32, 0);
55532 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
55533 + intr_mask.d32, 0);
55540 + * Handler for the OUT EP NAK interrupt.
55542 +static inline int32_t handle_out_ep_nak_intr(dwc_otg_pcd_t * pcd,
55543 + const uint32_t epnum)
55545 + /** @todo implement ISR */
55546 + dwc_otg_core_if_t *core_if;
55547 + doepmsk_data_t intr_mask = {.d32 = 0 };
55549 + DWC_DEBUGPL(DBG_ANY, "INTERRUPT Handler not implemented for %s\n", "OUT EP NAK");
55550 + core_if = GET_CORE_IF(pcd);
55551 + intr_mask.b.nak = 1;
55553 + if (core_if->multiproc_int_enable) {
55554 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
55555 + doepeachintmsk[epnum], intr_mask.d32, 0);
55557 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
55558 + intr_mask.d32, 0);
55565 + * Handler for the OUT EP NYET interrupt.
55567 +static inline int32_t handle_out_ep_nyet_intr(dwc_otg_pcd_t * pcd,
55568 + const uint32_t epnum)
55570 + /** @todo implement ISR */
55571 + dwc_otg_core_if_t *core_if;
55572 + doepmsk_data_t intr_mask = {.d32 = 0 };
55574 + DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "OUT EP NYET");
55575 + core_if = GET_CORE_IF(pcd);
55576 + intr_mask.b.nyet = 1;
55578 + if (core_if->multiproc_int_enable) {
55579 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
55580 + doepeachintmsk[epnum], intr_mask.d32, 0);
55582 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
55583 + intr_mask.d32, 0);
55590 + * This interrupt indicates that an IN EP has a pending Interrupt.
55591 + * The sequence for handling the IN EP interrupt is shown below:
55592 + * -# Read the Device All Endpoint Interrupt register
55593 + * -# Repeat the following for each IN EP interrupt bit set (from
55595 + * -# Read the Device Endpoint Interrupt (DIEPINTn) register
55596 + * -# If "Transfer Complete" call the request complete function
55597 + * -# If "Endpoint Disabled" complete the EP disable procedure.
55598 + * -# If "AHB Error Interrupt" log error
55599 + * -# If "Time-out Handshake" log error
55600 + * -# If "IN Token Received when TxFIFO Empty" write packet to Tx
55602 + * -# If "IN Token EP Mismatch" (disable, this is handled by EP
55603 + * Mismatch Interrupt)
55605 +static int32_t dwc_otg_pcd_handle_in_ep_intr(dwc_otg_pcd_t * pcd)
55607 +#define CLEAR_IN_EP_INTR(__core_if,__epnum,__intr) \
55609 + diepint_data_t diepint = {.d32=0}; \
55610 + diepint.b.__intr = 1; \
55611 + DWC_WRITE_REG32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \
55615 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
55616 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
55617 + diepint_data_t diepint = {.d32 = 0 };
55618 + depctl_data_t depctl = {.d32 = 0 };
55619 + uint32_t ep_intr;
55620 + uint32_t epnum = 0;
55621 + dwc_otg_pcd_ep_t *ep;
55622 + dwc_ep_t *dwc_ep;
55623 + gintmsk_data_t intr_mask = {.d32 = 0 };
55625 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd);
55627 + /* Read in the device interrupt bits */
55628 + ep_intr = dwc_otg_read_dev_all_in_ep_intr(core_if);
55630 + /* Service the Device IN interrupts for each endpoint */
55631 + while (ep_intr) {
55632 + if (ep_intr & 0x1) {
55633 + uint32_t empty_msk;
55634 + /* Get EP pointer */
55635 + ep = get_in_ep(pcd, epnum);
55636 + dwc_ep = &ep->dwc_ep;
55639 + DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
55641 + DWC_READ_REG32(&dev_if->
55642 + dev_global_regs->dtknqr4_fifoemptymsk);
55644 + DWC_DEBUGPL(DBG_PCDV,
55645 + "IN EP INTERRUPT - %d\nepmty_msk - %8x diepctl - %8x\n",
55646 + epnum, empty_msk, depctl.d32);
55648 + DWC_DEBUGPL(DBG_PCD,
55649 + "EP%d-%s: type=%d, mps=%d\n",
55650 + dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"),
55651 + dwc_ep->type, dwc_ep->maxpacket);
55654 + dwc_otg_read_dev_in_ep_intr(core_if, dwc_ep);
55656 + DWC_DEBUGPL(DBG_PCDV,
55657 + "EP %d Interrupt Register - 0x%x\n", epnum,
55659 + /* Transfer complete */
55660 + if (diepint.b.xfercompl) {
55661 + /* Disable the NP Tx FIFO Empty
55663 + if (core_if->en_multiple_tx_fifo == 0) {
55664 + intr_mask.b.nptxfempty = 1;
55666 + (&core_if->core_global_regs->gintmsk,
55667 + intr_mask.d32, 0);
55669 + /* Disable the Tx FIFO Empty Interrupt for this EP */
55670 + uint32_t fifoemptymsk =
55671 + 0x1 << dwc_ep->num;
55672 + DWC_MODIFY_REG32(&core_if->
55673 + dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
55674 + fifoemptymsk, 0);
55676 + /* Clear the bit in DIEPINTn for this interrupt */
55677 + CLEAR_IN_EP_INTR(core_if, epnum, xfercompl);
55679 + /* Complete the transfer */
55680 + if (epnum == 0) {
55683 +#ifdef DWC_EN_ISOC
55684 + else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
55685 + if (!ep->stopped)
55686 + complete_iso_ep(pcd, ep);
55688 +#endif /* DWC_EN_ISOC */
55689 +#ifdef DWC_UTE_PER_IO
55690 + else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
55691 + if (!ep->stopped)
55692 + complete_xiso_ep(ep);
55694 +#endif /* DWC_UTE_PER_IO */
55696 + if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC &&
55697 + dwc_ep->bInterval > 1) {
55698 + dwc_ep->frame_num += dwc_ep->bInterval;
55699 + if (dwc_ep->frame_num > 0x3FFF)
55701 + dwc_ep->frm_overrun = 1;
55702 + dwc_ep->frame_num &= 0x3FFF;
55704 + dwc_ep->frm_overrun = 0;
55707 + if(diepint.b.nak)
55708 + CLEAR_IN_EP_INTR(core_if, epnum, nak);
55711 + /* Endpoint disable */
55712 + if (diepint.b.epdisabled) {
55713 + DWC_DEBUGPL(DBG_ANY, "EP%d IN disabled\n",
55715 + handle_in_ep_disable_intr(pcd, epnum);
55717 + /* Clear the bit in DIEPINTn for this interrupt */
55718 + CLEAR_IN_EP_INTR(core_if, epnum, epdisabled);
55721 + if (diepint.b.ahberr) {
55722 + DWC_ERROR("EP%d IN AHB Error\n", epnum);
55723 + /* Clear the bit in DIEPINTn for this interrupt */
55724 + CLEAR_IN_EP_INTR(core_if, epnum, ahberr);
55726 + /* TimeOUT Handshake (non-ISOC IN EPs) */
55727 + if (diepint.b.timeout) {
55728 + DWC_ERROR("EP%d IN Time-out\n", epnum);
55729 + handle_in_ep_timeout_intr(pcd, epnum);
55731 + CLEAR_IN_EP_INTR(core_if, epnum, timeout);
55733 + /** IN Token received with TxF Empty */
55734 + if (diepint.b.intktxfemp) {
55735 + DWC_DEBUGPL(DBG_ANY,
55736 + "EP%d IN TKN TxFifo Empty\n",
55738 + if (!ep->stopped && epnum != 0) {
55740 + diepmsk_data_t diepmsk = {.d32 = 0 };
55741 + diepmsk.b.intktxfemp = 1;
55743 + if (core_if->multiproc_int_enable) {
55745 + (&dev_if->dev_global_regs->diepeachintmsk
55746 + [epnum], diepmsk.d32, 0);
55749 + (&dev_if->dev_global_regs->diepmsk,
55752 + } else if (core_if->dma_desc_enable
55754 + && pcd->ep0state ==
55755 + EP0_OUT_STATUS_PHASE) {
55756 + // EP0 IN set STALL
55758 + DWC_READ_REG32(&dev_if->in_ep_regs
55759 + [epnum]->diepctl);
55761 + /* set the disable and stall bits */
55762 + if (depctl.b.epena) {
55763 + depctl.b.epdis = 1;
55765 + depctl.b.stall = 1;
55766 + DWC_WRITE_REG32(&dev_if->in_ep_regs
55767 + [epnum]->diepctl,
55770 + CLEAR_IN_EP_INTR(core_if, epnum, intktxfemp);
55772 + /** IN Token Received with EP mismatch */
55773 + if (diepint.b.intknepmis) {
55774 + DWC_DEBUGPL(DBG_ANY,
55775 + "EP%d IN TKN EP Mismatch\n", epnum);
55776 + CLEAR_IN_EP_INTR(core_if, epnum, intknepmis);
55778 + /** IN Endpoint NAK Effective */
55779 + if (diepint.b.inepnakeff) {
55780 + DWC_DEBUGPL(DBG_ANY,
55781 + "EP%d IN EP NAK Effective\n",
55783 + /* Periodic EP */
55784 + if (ep->disabling) {
55786 + depctl.b.snak = 1;
55787 + depctl.b.epdis = 1;
55788 + DWC_MODIFY_REG32(&dev_if->in_ep_regs
55789 + [epnum]->diepctl,
55793 + CLEAR_IN_EP_INTR(core_if, epnum, inepnakeff);
55797 + /** IN EP Tx FIFO Empty Intr */
55798 + if (diepint.b.emptyintr) {
55799 + DWC_DEBUGPL(DBG_ANY,
55800 + "EP%d Tx FIFO Empty Intr \n",
55802 + write_empty_tx_fifo(pcd, epnum);
55804 + CLEAR_IN_EP_INTR(core_if, epnum, emptyintr);
55808 + /** IN EP BNA Intr */
55809 + if (diepint.b.bna) {
55810 + CLEAR_IN_EP_INTR(core_if, epnum, bna);
55811 + if (core_if->dma_desc_enable) {
55812 +#ifdef DWC_EN_ISOC
55813 + if (dwc_ep->type ==
55814 + DWC_OTG_EP_TYPE_ISOC) {
55816 + * This checking is performed to prevent first "false" BNA
55817 + * handling occuring right after reconnect
55819 + if (dwc_ep->next_frame !=
55821 + dwc_otg_pcd_handle_iso_bna(ep);
55823 +#endif /* DWC_EN_ISOC */
55825 + dwc_otg_pcd_handle_noniso_bna(ep);
55829 + /* NAK Interrutp */
55830 + if (diepint.b.nak) {
55831 + DWC_DEBUGPL(DBG_ANY, "EP%d IN NAK Interrupt\n",
55833 + if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
55834 + depctl_data_t depctl;
55835 + if (ep->dwc_ep.frame_num == 0xFFFFFFFF) {
55836 + ep->dwc_ep.frame_num = core_if->frame_num;
55837 + if (ep->dwc_ep.bInterval > 1) {
55839 + depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
55840 + if (ep->dwc_ep.frame_num & 0x1) {
55841 + depctl.b.setd1pid = 1;
55842 + depctl.b.setd0pid = 0;
55844 + depctl.b.setd0pid = 1;
55845 + depctl.b.setd1pid = 0;
55847 + DWC_WRITE_REG32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32);
55849 + start_next_request(ep);
55851 + ep->dwc_ep.frame_num += ep->dwc_ep.bInterval;
55852 + if (dwc_ep->frame_num > 0x3FFF) {
55853 + dwc_ep->frm_overrun = 1;
55854 + dwc_ep->frame_num &= 0x3FFF;
55856 + dwc_ep->frm_overrun = 0;
55859 + CLEAR_IN_EP_INTR(core_if, epnum, nak);
55867 +#undef CLEAR_IN_EP_INTR
55871 + * This interrupt indicates that an OUT EP has a pending Interrupt.
55872 + * The sequence for handling the OUT EP interrupt is shown below:
55873 + * -# Read the Device All Endpoint Interrupt register
55874 + * -# Repeat the following for each OUT EP interrupt bit set (from
55876 + * -# Read the Device Endpoint Interrupt (DOEPINTn) register
55877 + * -# If "Transfer Complete" call the request complete function
55878 + * -# If "Endpoint Disabled" complete the EP disable procedure.
55879 + * -# If "AHB Error Interrupt" log error
55880 + * -# If "Setup Phase Done" process Setup Packet (See Standard USB
55881 + * Command Processing)
55883 +static int32_t dwc_otg_pcd_handle_out_ep_intr(dwc_otg_pcd_t * pcd)
55885 +#define CLEAR_OUT_EP_INTR(__core_if,__epnum,__intr) \
55887 + doepint_data_t doepint = {.d32=0}; \
55888 + doepint.b.__intr = 1; \
55889 + DWC_WRITE_REG32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \
55893 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
55894 + uint32_t ep_intr;
55895 + doepint_data_t doepint = {.d32 = 0 };
55896 + uint32_t epnum = 0;
55897 + dwc_otg_pcd_ep_t *ep;
55898 + dwc_ep_t *dwc_ep;
55899 + dctl_data_t dctl = {.d32 = 0 };
55900 + gintmsk_data_t gintmsk = {.d32 = 0 };
55903 + DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
55905 + /* Read in the device interrupt bits */
55906 + ep_intr = dwc_otg_read_dev_all_out_ep_intr(core_if);
55908 + while (ep_intr) {
55909 + if (ep_intr & 0x1) {
55910 + /* Get EP pointer */
55911 + ep = get_out_ep(pcd, epnum);
55912 + dwc_ep = &ep->dwc_ep;
55915 + DWC_DEBUGPL(DBG_PCDV,
55916 + "EP%d-%s: type=%d, mps=%d\n",
55917 + dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"),
55918 + dwc_ep->type, dwc_ep->maxpacket);
55921 + dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep);
55922 + /* Moved this interrupt upper due to core deffect of asserting
55923 + * OUT EP 0 xfercompl along with stsphsrcvd in BDMA */
55924 + if (doepint.b.stsphsercvd) {
55925 + deptsiz0_data_t deptsiz;
55926 + CLEAR_OUT_EP_INTR(core_if, epnum, stsphsercvd);
55928 + DWC_READ_REG32(&core_if->dev_if->
55929 + out_ep_regs[0]->doeptsiz);
55930 + if (core_if->snpsid >= OTG_CORE_REV_3_00a
55931 + && core_if->dma_enable
55932 + && core_if->dma_desc_enable == 0
55933 + && doepint.b.xfercompl
55934 + && deptsiz.b.xfersize == 24) {
55935 + CLEAR_OUT_EP_INTR(core_if, epnum,
55937 + doepint.b.xfercompl = 0;
55938 + ep0_out_start(core_if, pcd);
55940 + if ((core_if->dma_desc_enable) ||
55941 + (core_if->dma_enable
55942 + && core_if->snpsid >=
55943 + OTG_CORE_REV_3_00a)) {
55944 + do_setup_in_status_phase(pcd);
55947 + /* Transfer complete */
55948 + if (doepint.b.xfercompl) {
55950 + if (epnum == 0) {
55951 + /* Clear the bit in DOEPINTn for this interrupt */
55952 + CLEAR_OUT_EP_INTR(core_if, epnum, xfercompl);
55953 + if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
55954 + DWC_DEBUGPL(DBG_PCDV, "DOEPINT=%x doepint=%x\n",
55955 + DWC_READ_REG32(&core_if->dev_if->out_ep_regs[0]->doepint),
55957 + DWC_DEBUGPL(DBG_PCDV, "DOEPCTL=%x \n",
55958 + DWC_READ_REG32(&core_if->dev_if->out_ep_regs[0]->doepctl));
55960 + if (core_if->snpsid >= OTG_CORE_REV_3_00a
55961 + && core_if->dma_enable == 0) {
55962 + doepint_data_t doepint;
55963 + doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
55964 + out_ep_regs[0]->doepint);
55965 + if (pcd->ep0state == EP0_IDLE && doepint.b.sr) {
55966 + CLEAR_OUT_EP_INTR(core_if, epnum, sr);
55967 + goto exit_xfercompl;
55970 + /* In case of DDMA look at SR bit to go to the Data Stage */
55971 + if (core_if->dma_desc_enable) {
55972 + dev_dma_desc_sts_t status = {.d32 = 0};
55973 + if (pcd->ep0state == EP0_IDLE) {
55974 + status.d32 = core_if->dev_if->setup_desc_addr[core_if->
55975 + dev_if->setup_desc_index]->status.d32;
55976 + if(pcd->data_terminated) {
55977 + pcd->data_terminated = 0;
55978 + status.d32 = core_if->dev_if->out_desc_addr->status.d32;
55979 + dwc_memcpy(&pcd->setup_pkt->req, pcd->backup_buf, 8);
55981 + if (status.b.sr) {
55982 + if (doepint.b.setup) {
55983 + DWC_DEBUGPL(DBG_PCDV, "DMA DESC EP0_IDLE SR=1 setup=1\n");
55984 + /* Already started data stage, clear setup */
55985 + CLEAR_OUT_EP_INTR(core_if, epnum, setup);
55986 + doepint.b.setup = 0;
55988 + /* Prepare for more setup packets */
55989 + if (pcd->ep0state == EP0_IN_STATUS_PHASE ||
55990 + pcd->ep0state == EP0_IN_DATA_PHASE) {
55991 + ep0_out_start(core_if, pcd);
55994 + goto exit_xfercompl;
55996 + /* Prepare for more setup packets */
55997 + DWC_DEBUGPL(DBG_PCDV,
55998 + "EP0_IDLE SR=1 setup=0 new setup comes\n");
55999 + ep0_out_start(core_if, pcd);
56003 + dwc_otg_pcd_request_t *req;
56004 + dev_dma_desc_sts_t status = {.d32 = 0};
56005 + diepint_data_t diepint0;
56006 + diepint0.d32 = DWC_READ_REG32(&core_if->dev_if->
56007 + in_ep_regs[0]->diepint);
56009 + if (pcd->ep0state == EP0_STALL || pcd->ep0state == EP0_DISCONNECT) {
56010 + DWC_ERROR("EP0 is stalled/disconnected\n");
56013 + /* Clear IN xfercompl if set */
56014 + if (diepint0.b.xfercompl && (pcd->ep0state == EP0_IN_STATUS_PHASE
56015 + || pcd->ep0state == EP0_IN_DATA_PHASE)) {
56016 + DWC_WRITE_REG32(&core_if->dev_if->
56017 + in_ep_regs[0]->diepint, diepint0.d32);
56020 + status.d32 = core_if->dev_if->setup_desc_addr[core_if->
56021 + dev_if->setup_desc_index]->status.d32;
56023 + if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len
56024 + && (pcd->ep0state == EP0_OUT_DATA_PHASE))
56025 + status.d32 = core_if->dev_if->out_desc_addr->status.d32;
56026 + if (pcd->ep0state == EP0_OUT_STATUS_PHASE)
56027 + status.d32 = core_if->dev_if->
56028 + out_desc_addr->status.d32;
56030 + if (status.b.sr) {
56031 + if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
56032 + DWC_DEBUGPL(DBG_PCDV, "Request queue empty!!\n");
56034 + DWC_DEBUGPL(DBG_PCDV, "complete req!!\n");
56035 + req = DWC_CIRCLEQ_FIRST(&ep->queue);
56036 + if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len &&
56037 + pcd->ep0state == EP0_OUT_DATA_PHASE) {
56038 + /* Read arrived setup packet from req->buf */
56039 + dwc_memcpy(&pcd->setup_pkt->req,
56040 + req->buf + ep->dwc_ep.xfer_count, 8);
56042 + req->actual = ep->dwc_ep.xfer_count;
56043 + dwc_otg_request_done(ep, req, -ECONNRESET);
56044 + ep->dwc_ep.start_xfer_buff = 0;
56045 + ep->dwc_ep.xfer_buff = 0;
56046 + ep->dwc_ep.xfer_len = 0;
56048 + pcd->ep0state = EP0_IDLE;
56049 + if (doepint.b.setup) {
56050 + DWC_DEBUGPL(DBG_PCDV, "EP0_IDLE SR=1 setup=1\n");
56051 + /* Data stage started, clear setup */
56052 + CLEAR_OUT_EP_INTR(core_if, epnum, setup);
56053 + doepint.b.setup = 0;
56055 + /* Prepare for setup packets if ep0in was enabled*/
56056 + if (pcd->ep0state == EP0_IN_STATUS_PHASE) {
56057 + ep0_out_start(core_if, pcd);
56060 + goto exit_xfercompl;
56062 + /* Prepare for more setup packets */
56063 + DWC_DEBUGPL(DBG_PCDV,
56064 + "EP0_IDLE SR=1 setup=0 new setup comes 2\n");
56065 + ep0_out_start(core_if, pcd);
56070 + if (core_if->snpsid >= OTG_CORE_REV_2_94a && core_if->dma_enable
56071 + && core_if->dma_desc_enable == 0) {
56072 + doepint_data_t doepint_temp = {.d32 = 0};
56073 + deptsiz0_data_t doeptsize0 = {.d32 = 0 };
56074 + doepint_temp.d32 = DWC_READ_REG32(&core_if->dev_if->
56075 + out_ep_regs[ep->dwc_ep.num]->doepint);
56076 + doeptsize0.d32 = DWC_READ_REG32(&core_if->dev_if->
56077 + out_ep_regs[ep->dwc_ep.num]->doeptsiz);
56078 + if (pcd->ep0state == EP0_IDLE) {
56079 + if (doepint_temp.b.sr) {
56080 + CLEAR_OUT_EP_INTR(core_if, epnum, sr);
56082 + doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
56083 + out_ep_regs[0]->doepint);
56084 + if (doeptsize0.b.supcnt == 3) {
56085 + DWC_DEBUGPL(DBG_ANY, "Rolling over!!!!!!!\n");
56086 + ep->dwc_ep.stp_rollover = 1;
56088 + if (doepint.b.setup) {
56090 + /* Already started data stage, clear setup */
56091 + CLEAR_OUT_EP_INTR(core_if, epnum, setup);
56092 + doepint.b.setup = 0;
56094 + ep->dwc_ep.stp_rollover = 0;
56095 + /* Prepare for more setup packets */
56096 + if (pcd->ep0state == EP0_IN_STATUS_PHASE ||
56097 + pcd->ep0state == EP0_IN_DATA_PHASE) {
56098 + ep0_out_start(core_if, pcd);
56100 + goto exit_xfercompl;
56102 + /* Prepare for more setup packets */
56103 + DWC_DEBUGPL(DBG_ANY,
56104 + "EP0_IDLE SR=1 setup=0 new setup comes\n");
56105 + doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
56106 + out_ep_regs[0]->doepint);
56107 + if(doepint.b.setup)
56109 + ep0_out_start(core_if, pcd);
56112 + dwc_otg_pcd_request_t *req;
56113 + diepint_data_t diepint0 = {.d32 = 0};
56114 + doepint_data_t doepint_temp = {.d32 = 0};
56115 + depctl_data_t diepctl0;
56116 + diepint0.d32 = DWC_READ_REG32(&core_if->dev_if->
56117 + in_ep_regs[0]->diepint);
56118 + diepctl0.d32 = DWC_READ_REG32(&core_if->dev_if->
56119 + in_ep_regs[0]->diepctl);
56121 + if (pcd->ep0state == EP0_IN_DATA_PHASE
56122 + || pcd->ep0state == EP0_IN_STATUS_PHASE) {
56123 + if (diepint0.b.xfercompl) {
56124 + DWC_WRITE_REG32(&core_if->dev_if->
56125 + in_ep_regs[0]->diepint, diepint0.d32);
56127 + if (diepctl0.b.epena) {
56128 + diepint_data_t diepint = {.d32 = 0};
56129 + diepctl0.b.snak = 1;
56130 + DWC_WRITE_REG32(&core_if->dev_if->
56131 + in_ep_regs[0]->diepctl, diepctl0.d32);
56134 + diepint.d32 = DWC_READ_REG32(&core_if->dev_if->
56135 + in_ep_regs[0]->diepint);
56136 + } while (!diepint.b.inepnakeff);
56137 + diepint.b.inepnakeff = 1;
56138 + DWC_WRITE_REG32(&core_if->dev_if->
56139 + in_ep_regs[0]->diepint, diepint.d32);
56140 + diepctl0.d32 = 0;
56141 + diepctl0.b.epdis = 1;
56142 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[0]->diepctl,
56146 + diepint.d32 = DWC_READ_REG32(&core_if->dev_if->
56147 + in_ep_regs[0]->diepint);
56148 + } while (!diepint.b.epdisabled);
56149 + diepint.b.epdisabled = 1;
56150 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[0]->diepint,
56154 + doepint_temp.d32 = DWC_READ_REG32(&core_if->dev_if->
56155 + out_ep_regs[ep->dwc_ep.num]->doepint);
56156 + if (doepint_temp.b.sr) {
56157 + CLEAR_OUT_EP_INTR(core_if, epnum, sr);
56158 + if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
56159 + DWC_DEBUGPL(DBG_PCDV, "Request queue empty!!\n");
56161 + DWC_DEBUGPL(DBG_PCDV, "complete req!!\n");
56162 + req = DWC_CIRCLEQ_FIRST(&ep->queue);
56163 + if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len &&
56164 + pcd->ep0state == EP0_OUT_DATA_PHASE) {
56165 + /* Read arrived setup packet from req->buf */
56166 + dwc_memcpy(&pcd->setup_pkt->req,
56167 + req->buf + ep->dwc_ep.xfer_count, 8);
56169 + req->actual = ep->dwc_ep.xfer_count;
56170 + dwc_otg_request_done(ep, req, -ECONNRESET);
56171 + ep->dwc_ep.start_xfer_buff = 0;
56172 + ep->dwc_ep.xfer_buff = 0;
56173 + ep->dwc_ep.xfer_len = 0;
56175 + pcd->ep0state = EP0_IDLE;
56176 + if (doepint.b.setup) {
56177 + DWC_DEBUGPL(DBG_PCDV, "EP0_IDLE SR=1 setup=1\n");
56178 + /* Data stage started, clear setup */
56179 + CLEAR_OUT_EP_INTR(core_if, epnum, setup);
56180 + doepint.b.setup = 0;
56182 + /* Prepare for setup packets if ep0in was enabled*/
56183 + if (pcd->ep0state == EP0_IN_STATUS_PHASE) {
56184 + ep0_out_start(core_if, pcd);
56186 + goto exit_xfercompl;
56188 + /* Prepare for more setup packets */
56189 + DWC_DEBUGPL(DBG_PCDV,
56190 + "EP0_IDLE SR=1 setup=0 new setup comes 2\n");
56191 + ep0_out_start(core_if, pcd);
56196 + if (core_if->dma_enable == 0 || pcd->ep0state != EP0_IDLE)
56199 + DWC_DEBUGPL(DBG_PCDV, "DOEPINT=%x doepint=%x\n",
56200 + dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep), doepint.d32);
56202 + if (core_if->dma_desc_enable == 0
56203 + || pcd->ep0state != EP0_IDLE)
56206 +#ifdef DWC_EN_ISOC
56207 + } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
56208 + if (doepint.b.pktdrpsts == 0) {
56209 + /* Clear the bit in DOEPINTn for this interrupt */
56210 + CLEAR_OUT_EP_INTR(core_if,
56213 + complete_iso_ep(pcd, ep);
56216 + doepint_data_t doepint = {.d32 = 0 };
56217 + doepint.b.xfercompl = 1;
56218 + doepint.b.pktdrpsts = 1;
56220 + (&core_if->dev_if->out_ep_regs
56221 + [epnum]->doepint,
56223 + if (handle_iso_out_pkt_dropped
56224 + (core_if, dwc_ep)) {
56225 + complete_iso_ep(pcd,
56229 +#endif /* DWC_EN_ISOC */
56230 +#ifdef DWC_UTE_PER_IO
56231 + } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
56232 + CLEAR_OUT_EP_INTR(core_if, epnum, xfercompl);
56233 + if (!ep->stopped)
56234 + complete_xiso_ep(ep);
56235 +#endif /* DWC_UTE_PER_IO */
56237 + /* Clear the bit in DOEPINTn for this interrupt */
56238 + CLEAR_OUT_EP_INTR(core_if, epnum,
56241 + if (core_if->core_params->dev_out_nak) {
56242 + DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[epnum]);
56243 + pcd->core_if->ep_xfer_info[epnum].state = 0;
56245 + print_memory_payload(pcd, dwc_ep);
56253 + /* Endpoint disable */
56254 + if (doepint.b.epdisabled) {
56256 + /* Clear the bit in DOEPINTn for this interrupt */
56257 + CLEAR_OUT_EP_INTR(core_if, epnum, epdisabled);
56258 + if (core_if->core_params->dev_out_nak) {
56260 + print_memory_payload(pcd, dwc_ep);
56262 + /* In case of timeout condition */
56263 + if (core_if->ep_xfer_info[epnum].state == 2) {
56264 + dctl.d32 = DWC_READ_REG32(&core_if->dev_if->
56265 + dev_global_regs->dctl);
56266 + dctl.b.cgoutnak = 1;
56267 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
56269 + /* Unmask goutnakeff interrupt which was masked
56270 + * during handle nak out interrupt */
56271 + gintmsk.b.goutnakeff = 1;
56272 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
56278 + if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)
56280 + dctl_data_t dctl;
56281 + gintmsk_data_t intr_mask = {.d32 = 0};
56282 + dwc_otg_pcd_request_t *req = 0;
56284 + dctl.d32 = DWC_READ_REG32(&core_if->dev_if->
56285 + dev_global_regs->dctl);
56286 + dctl.b.cgoutnak = 1;
56287 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
56290 + intr_mask.d32 = 0;
56291 + intr_mask.b.incomplisoout = 1;
56293 + /* Get any pending requests */
56294 + if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
56295 + req = DWC_CIRCLEQ_FIRST(&ep->queue);
56297 + DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
56299 + dwc_otg_request_done(ep, req, 0);
56300 + start_next_request(ep);
56303 + DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
56308 + if (doepint.b.ahberr) {
56309 + DWC_ERROR("EP%d OUT AHB Error\n", epnum);
56310 + DWC_ERROR("EP%d DEPDMA=0x%08x \n",
56311 + epnum, core_if->dev_if->out_ep_regs[epnum]->doepdma);
56312 + CLEAR_OUT_EP_INTR(core_if, epnum, ahberr);
56314 + /* Setup Phase Done (contorl EPs) */
56315 + if (doepint.b.setup) {
56317 + DWC_DEBUGPL(DBG_PCD, "EP%d SETUP Done\n", epnum);
56319 + CLEAR_OUT_EP_INTR(core_if, epnum, setup);
56324 + /** OUT EP BNA Intr */
56325 + if (doepint.b.bna) {
56326 + CLEAR_OUT_EP_INTR(core_if, epnum, bna);
56327 + if (core_if->dma_desc_enable) {
56328 +#ifdef DWC_EN_ISOC
56329 + if (dwc_ep->type ==
56330 + DWC_OTG_EP_TYPE_ISOC) {
56332 + * This checking is performed to prevent first "false" BNA
56333 + * handling occuring right after reconnect
56335 + if (dwc_ep->next_frame !=
56337 + dwc_otg_pcd_handle_iso_bna(ep);
56339 +#endif /* DWC_EN_ISOC */
56341 + dwc_otg_pcd_handle_noniso_bna(ep);
56345 + /* Babble Interrupt */
56346 + if (doepint.b.babble) {
56347 + DWC_DEBUGPL(DBG_ANY, "EP%d OUT Babble\n",
56349 + handle_out_ep_babble_intr(pcd, epnum);
56351 + CLEAR_OUT_EP_INTR(core_if, epnum, babble);
56353 + if (doepint.b.outtknepdis) {
56354 + DWC_DEBUGPL(DBG_ANY, "EP%d OUT Token received when EP is \
56355 + disabled\n",epnum);
56356 + if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
56357 + doepmsk_data_t doepmsk = {.d32 = 0};
56358 + ep->dwc_ep.frame_num = core_if->frame_num;
56359 + if (ep->dwc_ep.bInterval > 1) {
56360 + depctl_data_t depctl;
56361 + depctl.d32 = DWC_READ_REG32(&core_if->dev_if->
56362 + out_ep_regs[epnum]->doepctl);
56363 + if (ep->dwc_ep.frame_num & 0x1) {
56364 + depctl.b.setd1pid = 1;
56365 + depctl.b.setd0pid = 0;
56367 + depctl.b.setd0pid = 1;
56368 + depctl.b.setd1pid = 0;
56370 + DWC_WRITE_REG32(&core_if->dev_if->
56371 + out_ep_regs[epnum]->doepctl, depctl.d32);
56373 + start_next_request(ep);
56374 + doepmsk.b.outtknepdis = 1;
56375 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
56378 + CLEAR_OUT_EP_INTR(core_if, epnum, outtknepdis);
56381 + /* NAK Interrutp */
56382 + if (doepint.b.nak) {
56383 + DWC_DEBUGPL(DBG_ANY, "EP%d OUT NAK\n", epnum);
56384 + handle_out_ep_nak_intr(pcd, epnum);
56386 + CLEAR_OUT_EP_INTR(core_if, epnum, nak);
56388 + /* NYET Interrutp */
56389 + if (doepint.b.nyet) {
56390 + DWC_DEBUGPL(DBG_ANY, "EP%d OUT NYET\n", epnum);
56391 + handle_out_ep_nyet_intr(pcd, epnum);
56393 + CLEAR_OUT_EP_INTR(core_if, epnum, nyet);
56403 +#undef CLEAR_OUT_EP_INTR
56405 +static int drop_transfer(uint32_t trgt_fr, uint32_t curr_fr, uint8_t frm_overrun)
56408 + if(!frm_overrun && curr_fr >= trgt_fr)
56410 + else if (frm_overrun
56411 + && (curr_fr >= trgt_fr && ((curr_fr - trgt_fr) < 0x3FFF / 2)))
56416 + * Incomplete ISO IN Transfer Interrupt.
56417 + * This interrupt indicates one of the following conditions occurred
56418 + * while transmitting an ISOC transaction.
56419 + * - Corrupted IN Token for ISOC EP.
56420 + * - Packet not complete in FIFO.
56421 + * The follow actions will be taken:
56422 + * -# Determine the EP
56423 + * -# Set incomplete flag in dwc_ep structure
56424 + * -# Disable EP; when "Endpoint Disabled" interrupt is received
56427 +int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr(dwc_otg_pcd_t * pcd)
56429 + gintsts_data_t gintsts;
56431 +#ifdef DWC_EN_ISOC
56432 + dwc_otg_dev_if_t *dev_if;
56433 + deptsiz_data_t deptsiz = {.d32 = 0 };
56434 + depctl_data_t depctl = {.d32 = 0 };
56435 + dsts_data_t dsts = {.d32 = 0 };
56436 + dwc_ep_t *dwc_ep;
56439 + dev_if = GET_CORE_IF(pcd)->dev_if;
56441 + for (i = 1; i <= dev_if->num_in_eps; ++i) {
56442 + dwc_ep = &pcd->in_ep[i].dwc_ep;
56443 + if (dwc_ep->active && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
56445 + DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
56447 + DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
56449 + if (depctl.b.epdis && deptsiz.d32) {
56450 + set_current_pkt_info(GET_CORE_IF(pcd), dwc_ep);
56451 + if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
56452 + dwc_ep->cur_pkt = 0;
56453 + dwc_ep->proc_buf_num =
56454 + (dwc_ep->proc_buf_num ^ 1) & 0x1;
56456 + if (dwc_ep->proc_buf_num) {
56457 + dwc_ep->cur_pkt_addr =
56458 + dwc_ep->xfer_buff1;
56459 + dwc_ep->cur_pkt_dma_addr =
56460 + dwc_ep->dma_addr1;
56462 + dwc_ep->cur_pkt_addr =
56463 + dwc_ep->xfer_buff0;
56464 + dwc_ep->cur_pkt_dma_addr =
56465 + dwc_ep->dma_addr0;
56471 + DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
56472 + dev_global_regs->dsts);
56473 + dwc_ep->next_frame = dsts.b.soffn;
56475 + dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF
56483 + depctl_data_t depctl = {.d32 = 0 };
56484 + dwc_ep_t *dwc_ep;
56485 + dwc_otg_dev_if_t *dev_if;
56487 + dev_if = GET_CORE_IF(pcd)->dev_if;
56489 + DWC_DEBUGPL(DBG_PCD,"Incomplete ISO IN \n");
56491 + for (i = 1; i <= dev_if->num_in_eps; ++i) {
56492 + dwc_ep = &pcd->in_ep[i-1].dwc_ep;
56494 + DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
56495 + if (depctl.b.epena && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
56496 + if (drop_transfer(dwc_ep->frame_num, GET_CORE_IF(pcd)->frame_num,
56497 + dwc_ep->frm_overrun))
56500 + DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
56501 + depctl.b.snak = 1;
56502 + depctl.b.epdis = 1;
56503 + DWC_MODIFY_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32, depctl.d32);
56508 + /*intr_mask.b.incomplisoin = 1;
56509 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
56510 + intr_mask.d32, 0); */
56511 +#endif //DWC_EN_ISOC
56513 + /* Clear interrupt */
56515 + gintsts.b.incomplisoin = 1;
56516 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
56523 + * Incomplete ISO OUT Transfer Interrupt.
56525 + * This interrupt indicates that the core has dropped an ISO OUT
56526 + * packet. The following conditions can be the cause:
56527 + * - FIFO Full, the entire packet would not fit in the FIFO.
56529 + * - Corrupted Token
56530 + * The follow actions will be taken:
56531 + * -# Determine the EP
56532 + * -# Set incomplete flag in dwc_ep structure
56533 + * -# Read any data from the FIFO
56534 + * -# Disable EP. When "Endpoint Disabled" interrupt is received
56537 +int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr(dwc_otg_pcd_t * pcd)
56540 + gintsts_data_t gintsts;
56542 +#ifdef DWC_EN_ISOC
56543 + dwc_otg_dev_if_t *dev_if;
56544 + deptsiz_data_t deptsiz = {.d32 = 0 };
56545 + depctl_data_t depctl = {.d32 = 0 };
56546 + dsts_data_t dsts = {.d32 = 0 };
56547 + dwc_ep_t *dwc_ep;
56550 + dev_if = GET_CORE_IF(pcd)->dev_if;
56552 + for (i = 1; i <= dev_if->num_out_eps; ++i) {
56553 + dwc_ep = &pcd->in_ep[i].dwc_ep;
56554 + if (pcd->out_ep[i].dwc_ep.active &&
56555 + pcd->out_ep[i].dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
56557 + DWC_READ_REG32(&dev_if->out_ep_regs[i]->doeptsiz);
56559 + DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
56561 + if (depctl.b.epdis && deptsiz.d32) {
56562 + set_current_pkt_info(GET_CORE_IF(pcd),
56563 + &pcd->out_ep[i].dwc_ep);
56564 + if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
56565 + dwc_ep->cur_pkt = 0;
56566 + dwc_ep->proc_buf_num =
56567 + (dwc_ep->proc_buf_num ^ 1) & 0x1;
56569 + if (dwc_ep->proc_buf_num) {
56570 + dwc_ep->cur_pkt_addr =
56571 + dwc_ep->xfer_buff1;
56572 + dwc_ep->cur_pkt_dma_addr =
56573 + dwc_ep->dma_addr1;
56575 + dwc_ep->cur_pkt_addr =
56576 + dwc_ep->xfer_buff0;
56577 + dwc_ep->cur_pkt_dma_addr =
56578 + dwc_ep->dma_addr0;
56584 + DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
56585 + dev_global_regs->dsts);
56586 + dwc_ep->next_frame = dsts.b.soffn;
56588 + dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF
56595 + /** @todo implement ISR */
56596 + gintmsk_data_t intr_mask = {.d32 = 0 };
56597 + dwc_otg_core_if_t *core_if;
56598 + deptsiz_data_t deptsiz = {.d32 = 0 };
56599 + depctl_data_t depctl = {.d32 = 0 };
56600 + dctl_data_t dctl = {.d32 = 0 };
56601 + dwc_ep_t *dwc_ep = NULL;
56603 + core_if = GET_CORE_IF(pcd);
56605 + for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
56606 + dwc_ep = &pcd->out_ep[i].dwc_ep;
56608 + DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl);
56609 + if (depctl.b.epena && depctl.b.dpid == (core_if->frame_num & 0x1)) {
56610 + core_if->dev_if->isoc_ep = dwc_ep;
56612 + DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz);
56616 + dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
56617 + gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
56618 + intr_mask.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
56620 + if (!intr_mask.b.goutnakeff) {
56622 + intr_mask.b.goutnakeff = 1;
56623 + DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32);
56625 + if (!gintsts.b.goutnakeff) {
56626 + dctl.b.sgoutnak = 1;
56628 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
56630 + depctl.d32 = DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl);
56631 + if (depctl.b.epena) {
56632 + depctl.b.epdis = 1;
56633 + depctl.b.snak = 1;
56635 + DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl, depctl.d32);
56637 + intr_mask.d32 = 0;
56638 + intr_mask.b.incomplisoout = 1;
56640 +#endif /* DWC_EN_ISOC */
56642 + /* Clear interrupt */
56644 + gintsts.b.incomplisoout = 1;
56645 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
56652 + * This function handles the Global IN NAK Effective interrupt.
56655 +int32_t dwc_otg_pcd_handle_in_nak_effective(dwc_otg_pcd_t * pcd)
56657 + dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
56658 + depctl_data_t diepctl = {.d32 = 0 };
56659 + gintmsk_data_t intr_mask = {.d32 = 0 };
56660 + gintsts_data_t gintsts;
56661 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
56664 + DWC_DEBUGPL(DBG_PCD, "Global IN NAK Effective\n");
56666 + /* Disable all active IN EPs */
56667 + for (i = 0; i <= dev_if->num_in_eps; i++) {
56668 + diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
56669 + if (!(diepctl.b.eptype & 1) && diepctl.b.epena) {
56670 + if (core_if->start_predict > 0)
56671 + core_if->start_predict++;
56672 + diepctl.b.epdis = 1;
56673 + diepctl.b.snak = 1;
56674 + DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, diepctl.d32);
56679 + /* Disable the Global IN NAK Effective Interrupt */
56680 + intr_mask.b.ginnakeff = 1;
56681 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
56682 + intr_mask.d32, 0);
56684 + /* Clear interrupt */
56686 + gintsts.b.ginnakeff = 1;
56687 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
56694 + * OUT NAK Effective.
56697 +int32_t dwc_otg_pcd_handle_out_nak_effective(dwc_otg_pcd_t * pcd)
56699 + dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
56700 + gintmsk_data_t intr_mask = {.d32 = 0 };
56701 + gintsts_data_t gintsts;
56702 + depctl_data_t doepctl;
56705 + /* Disable the Global OUT NAK Effective Interrupt */
56706 + intr_mask.b.goutnakeff = 1;
56707 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
56708 + intr_mask.d32, 0);
56710 + /* If DEV OUT NAK enabled*/
56711 + if (pcd->core_if->core_params->dev_out_nak) {
56712 + /* Run over all out endpoints to determine the ep number on
56713 + * which the timeout has happened
56715 + for (i = 0; i <= dev_if->num_out_eps; i++) {
56716 + if ( pcd->core_if->ep_xfer_info[i].state == 2 )
56719 + if (i > dev_if->num_out_eps) {
56720 + dctl_data_t dctl;
56722 + DWC_READ_REG32(&dev_if->dev_global_regs->dctl);
56723 + dctl.b.cgoutnak = 1;
56724 + DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl,
56729 + /* Disable the endpoint */
56730 + doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
56731 + if (doepctl.b.epena) {
56732 + doepctl.b.epdis = 1;
56733 + doepctl.b.snak = 1;
56735 + DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32);
56738 + /* We come here from Incomplete ISO OUT handler */
56739 + if (dev_if->isoc_ep) {
56740 + dwc_ep_t *dwc_ep = (dwc_ep_t *)dev_if->isoc_ep;
56741 + uint32_t epnum = dwc_ep->num;
56742 + doepint_data_t doepint;
56744 + DWC_READ_REG32(&dev_if->out_ep_regs[dwc_ep->num]->doepint);
56745 + dev_if->isoc_ep = NULL;
56747 + DWC_READ_REG32(&dev_if->out_ep_regs[epnum]->doepctl);
56748 + DWC_PRINTF("Before disable DOEPCTL = %08x\n", doepctl.d32);
56749 + if (doepctl.b.epena) {
56750 + doepctl.b.epdis = 1;
56751 + doepctl.b.snak = 1;
56753 + DWC_WRITE_REG32(&dev_if->out_ep_regs[epnum]->doepctl,
56757 + DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
56758 + "Global OUT NAK Effective\n");
56761 + /* Clear interrupt */
56763 + gintsts.b.goutnakeff = 1;
56764 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
56771 + * PCD interrupt handler.
56773 + * The PCD handles the device interrupts. Many conditions can cause a
56774 + * device interrupt. When an interrupt occurs, the device interrupt
56775 + * service routine determines the cause of the interrupt and
56776 + * dispatches handling to the appropriate function. These interrupt
56777 + * handling functions are described below.
56779 + * All interrupt registers are processed from LSB to MSB.
56782 +int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd)
56784 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
56786 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
56788 + gintsts_data_t gintr_status;
56789 + int32_t retval = 0;
56791 + /* Exit from ISR if core is hibernated */
56792 + if (core_if->hibernation_suspend == 1) {
56796 + DWC_DEBUGPL(DBG_ANY, "%s() gintsts=%08x gintmsk=%08x\n",
56798 + DWC_READ_REG32(&global_regs->gintsts),
56799 + DWC_READ_REG32(&global_regs->gintmsk));
56802 + if (dwc_otg_is_device_mode(core_if)) {
56803 + DWC_SPINLOCK(pcd->lock);
56805 + DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%08x gintmsk=%08x\n",
56807 + DWC_READ_REG32(&global_regs->gintsts),
56808 + DWC_READ_REG32(&global_regs->gintmsk));
56811 + gintr_status.d32 = dwc_otg_read_core_intr(core_if);
56813 + DWC_DEBUGPL(DBG_PCDV, "%s: gintsts&gintmsk=%08x\n",
56814 + __func__, gintr_status.d32);
56816 + if (gintr_status.b.sofintr) {
56817 + retval |= dwc_otg_pcd_handle_sof_intr(pcd);
56819 + if (gintr_status.b.rxstsqlvl) {
56821 + dwc_otg_pcd_handle_rx_status_q_level_intr(pcd);
56823 + if (gintr_status.b.nptxfempty) {
56824 + retval |= dwc_otg_pcd_handle_np_tx_fifo_empty_intr(pcd);
56826 + if (gintr_status.b.goutnakeff) {
56827 + retval |= dwc_otg_pcd_handle_out_nak_effective(pcd);
56829 + if (gintr_status.b.i2cintr) {
56830 + retval |= dwc_otg_pcd_handle_i2c_intr(pcd);
56832 + if (gintr_status.b.erlysuspend) {
56833 + retval |= dwc_otg_pcd_handle_early_suspend_intr(pcd);
56835 + if (gintr_status.b.usbreset) {
56836 + retval |= dwc_otg_pcd_handle_usb_reset_intr(pcd);
56838 + if (gintr_status.b.enumdone) {
56839 + retval |= dwc_otg_pcd_handle_enum_done_intr(pcd);
56841 + if (gintr_status.b.isooutdrop) {
56843 + dwc_otg_pcd_handle_isoc_out_packet_dropped_intr
56846 + if (gintr_status.b.eopframe) {
56848 + dwc_otg_pcd_handle_end_periodic_frame_intr(pcd);
56850 + if (gintr_status.b.inepint) {
56851 + if (!core_if->multiproc_int_enable) {
56852 + retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
56855 + if (gintr_status.b.outepintr) {
56856 + if (!core_if->multiproc_int_enable) {
56857 + retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
56860 + if (gintr_status.b.epmismatch) {
56861 + retval |= dwc_otg_pcd_handle_ep_mismatch_intr(pcd);
56863 + if (gintr_status.b.fetsusp) {
56864 + retval |= dwc_otg_pcd_handle_ep_fetsusp_intr(pcd);
56866 + if (gintr_status.b.ginnakeff) {
56867 + retval |= dwc_otg_pcd_handle_in_nak_effective(pcd);
56869 + if (gintr_status.b.incomplisoin) {
56871 + dwc_otg_pcd_handle_incomplete_isoc_in_intr(pcd);
56873 + if (gintr_status.b.incomplisoout) {
56875 + dwc_otg_pcd_handle_incomplete_isoc_out_intr(pcd);
56878 + /* In MPI mode Device Endpoints interrupts are asserted
56879 + * without setting outepintr and inepint bits set, so these
56880 + * Interrupt handlers are called without checking these bit-fields
56882 + if (core_if->multiproc_int_enable) {
56883 + retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
56884 + retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
56887 + DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%0x\n", __func__,
56888 + DWC_READ_REG32(&global_regs->gintsts));
56890 + DWC_SPINUNLOCK(pcd->lock);
56895 +#endif /* DWC_HOST_ONLY */
56897 +++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c
56899 + /* ==========================================================================
56900 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_linux.c $
56901 + * $Revision: #21 $
56902 + * $Date: 2012/08/10 $
56903 + * $Change: 2047372 $
56905 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
56906 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
56907 + * otherwise expressly agreed to in writing between Synopsys and you.
56909 + * The Software IS NOT an item of Licensed Software or Licensed Product under
56910 + * any End User Software License Agreement or Agreement for Licensed Product
56911 + * with Synopsys or any supplement thereto. You are permitted to use and
56912 + * redistribute this Software in source and binary forms, with or without
56913 + * modification, provided that redistributions of source code must retain this
56914 + * notice. You may not view, use, disclose, copy or distribute this file or
56915 + * any information contained herein except pursuant to this license grant from
56916 + * Synopsys. If you do not agree with this notice, including the disclaimer
56917 + * below, then you are not authorized to use the Software.
56919 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
56920 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
56921 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
56922 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
56923 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
56924 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
56925 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
56926 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
56927 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
56928 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
56930 + * ========================================================================== */
56931 +#ifndef DWC_HOST_ONLY
56934 + * This file implements the Peripheral Controller Driver.
56936 + * The Peripheral Controller Driver (PCD) is responsible for
56937 + * translating requests from the Function Driver into the appropriate
56938 + * actions on the DWC_otg controller. It isolates the Function Driver
56939 + * from the specifics of the controller by providing an API to the
56940 + * Function Driver.
56942 + * The Peripheral Controller Driver for Linux will implement the
56943 + * Gadget API, so that the existing Gadget drivers can be used.
56944 + * (Gadget Driver is the Linux terminology for a Function Driver.)
56946 + * The Linux Gadget API is defined in the header file
56947 + * <code><linux/usb_gadget.h></code>. The USB EP operations API is
56948 + * defined in the structure <code>usb_ep_ops</code> and the USB
56949 + * Controller API is defined in the structure
56950 + * <code>usb_gadget_ops</code>.
56954 +#include "dwc_otg_os_dep.h"
56955 +#include "dwc_otg_pcd_if.h"
56956 +#include "dwc_otg_pcd.h"
56957 +#include "dwc_otg_driver.h"
56958 +#include "dwc_otg_dbg.h"
56960 +extern bool fiq_enable;
56962 +static struct gadget_wrapper {
56963 + dwc_otg_pcd_t *pcd;
56965 + struct usb_gadget gadget;
56966 + struct usb_gadget_driver *driver;
56968 + struct usb_ep ep0;
56969 + struct usb_ep in_ep[16];
56970 + struct usb_ep out_ep[16];
56972 +} *gadget_wrapper;
56974 +/* Display the contents of the buffer */
56975 +extern void dump_msg(const u8 * buf, unsigned int length);
56977 + * Get the dwc_otg_pcd_ep_t* from usb_ep* pointer - NULL in case
56978 + * if the endpoint is not found
56980 +static struct dwc_otg_pcd_ep *ep_from_handle(dwc_otg_pcd_t * pcd, void *handle)
56983 + if (pcd->ep0.priv == handle) {
56984 + return &pcd->ep0;
56987 + for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) {
56988 + if (pcd->in_ep[i].priv == handle)
56989 + return &pcd->in_ep[i];
56990 + if (pcd->out_ep[i].priv == handle)
56991 + return &pcd->out_ep[i];
56997 +/* USB Endpoint Operations */
56999 + * The following sections briefly describe the behavior of the Gadget
57000 + * API endpoint operations implemented in the DWC_otg driver
57001 + * software. Detailed descriptions of the generic behavior of each of
57002 + * these functions can be found in the Linux header file
57003 + * include/linux/usb_gadget.h.
57005 + * The Gadget API provides wrapper functions for each of the function
57006 + * pointers defined in usb_ep_ops. The Gadget Driver calls the wrapper
57007 + * function, which then calls the underlying PCD function. The
57008 + * following sections are named according to the wrapper
57009 + * functions. Within each section, the corresponding DWC_otg PCD
57010 + * function name is specified.
57015 + * This function is called by the Gadget Driver for each EP to be
57016 + * configured for the current configuration (SET_CONFIGURATION).
57018 + * This function initializes the dwc_otg_ep_t data structure, and then
57019 + * calls dwc_otg_ep_activate.
57021 +static int ep_enable(struct usb_ep *usb_ep,
57022 + const struct usb_endpoint_descriptor *ep_desc)
57026 + DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, ep_desc);
57028 + if (!usb_ep || !ep_desc || ep_desc->bDescriptorType != USB_DT_ENDPOINT) {
57029 + DWC_WARN("%s, bad ep or descriptor\n", __func__);
57032 + if (usb_ep == &gadget_wrapper->ep0) {
57033 + DWC_WARN("%s, bad ep(0)\n", __func__);
57037 + /* Check FIFO size? */
57038 + if (!ep_desc->wMaxPacketSize) {
57039 + DWC_WARN("%s, bad %s maxpacket\n", __func__, usb_ep->name);
57043 + if (!gadget_wrapper->driver ||
57044 + gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
57045 + DWC_WARN("%s, bogus device state\n", __func__);
57046 + return -ESHUTDOWN;
57049 + /* Delete after check - MAS */
57051 + nat = (uint32_t) ep_desc->wMaxPacketSize;
57052 + printk(KERN_ALERT "%s: nat (before) =%d\n", __func__, nat);
57053 + nat = (nat >> 11) & 0x03;
57054 + printk(KERN_ALERT "%s: nat (after) =%d\n", __func__, nat);
57056 + retval = dwc_otg_pcd_ep_enable(gadget_wrapper->pcd,
57057 + (const uint8_t *)ep_desc,
57060 + DWC_WARN("dwc_otg_pcd_ep_enable failed\n");
57064 + usb_ep->maxpacket = le16_to_cpu(ep_desc->wMaxPacketSize);
57070 + * This function is called when an EP is disabled due to disconnect or
57071 + * change in configuration. Any pending requests will terminate with a
57072 + * status of -ESHUTDOWN.
57074 + * This function modifies the dwc_otg_ep_t data structure for this EP,
57075 + * and then calls dwc_otg_ep_deactivate.
57077 +static int ep_disable(struct usb_ep *usb_ep)
57081 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, usb_ep);
57083 + DWC_DEBUGPL(DBG_PCD, "%s, %s not enabled\n", __func__,
57084 + usb_ep ? usb_ep->name : NULL);
57088 + retval = dwc_otg_pcd_ep_disable(gadget_wrapper->pcd, usb_ep);
57090 + retval = -EINVAL;
57097 + * This function allocates a request object to use with the specified
57100 + * @param ep The endpoint to be used with with the request
57101 + * @param gfp_flags the GFP_* flags to use.
57103 +static struct usb_request *dwc_otg_pcd_alloc_request(struct usb_ep *ep,
57106 + struct usb_request *usb_req;
57108 + DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d)\n", __func__, ep, gfp_flags);
57110 + DWC_WARN("%s() %s\n", __func__, "Invalid EP!\n");
57113 + usb_req = kzalloc(sizeof(*usb_req), gfp_flags);
57114 + if (0 == usb_req) {
57115 + DWC_WARN("%s() %s\n", __func__, "request allocation failed!\n");
57118 + usb_req->dma = DWC_DMA_ADDR_INVALID;
57124 + * This function frees a request object.
57126 + * @param ep The endpoint associated with the request
57127 + * @param req The request being freed
57129 +static void dwc_otg_pcd_free_request(struct usb_ep *ep, struct usb_request *req)
57131 + DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, ep, req);
57133 + if (0 == ep || 0 == req) {
57134 + DWC_WARN("%s() %s\n", __func__,
57135 + "Invalid ep or req argument!\n");
57143 + * This function is used to submit an I/O Request to an EP.
57145 + * - When the request completes the request's completion callback
57146 + * is called to return the request to the driver.
57147 + * - An EP, except control EPs, may have multiple requests
57149 + * - Once submitted the request cannot be examined or modified.
57150 + * - Each request is turned into one or more packets.
57151 + * - A BULK EP can queue any amount of data; the transfer is
57153 + * - Zero length Packets are specified with the request 'zero'
57156 +static int ep_queue(struct usb_ep *usb_ep, struct usb_request *usb_req,
57159 + dwc_otg_pcd_t *pcd;
57160 + struct dwc_otg_pcd_ep *ep = NULL;
57161 + int retval = 0, is_isoc_ep = 0;
57162 + dma_addr_t dma_addr = DWC_DMA_ADDR_INVALID;
57164 + DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p,%d)\n",
57165 + __func__, usb_ep, usb_req, gfp_flags);
57167 + if (!usb_req || !usb_req->complete || !usb_req->buf) {
57168 + DWC_WARN("bad params\n");
57173 + DWC_WARN("bad ep\n");
57177 + pcd = gadget_wrapper->pcd;
57178 + if (!gadget_wrapper->driver ||
57179 + gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
57180 + DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n",
57181 + gadget_wrapper->gadget.speed);
57182 + DWC_WARN("bogus device state\n");
57183 + return -ESHUTDOWN;
57186 + DWC_DEBUGPL(DBG_PCD, "%s queue req %p, len %d buf %p\n",
57187 + usb_ep->name, usb_req, usb_req->length, usb_req->buf);
57189 + usb_req->status = -EINPROGRESS;
57190 + usb_req->actual = 0;
57192 + ep = ep_from_handle(pcd, usb_ep);
57196 + is_isoc_ep = (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) ? 1 : 0;
57197 + if (GET_CORE_IF(pcd)->dma_enable) {
57198 + dwc_otg_device_t *otg_dev = gadget_wrapper->pcd->otg_dev;
57199 + struct device *dev = NULL;
57201 + if (otg_dev != NULL)
57202 + dev = DWC_OTG_OS_GETDEV(otg_dev->os_dep);
57204 + if (usb_req->length != 0 &&
57205 + usb_req->dma == DWC_DMA_ADDR_INVALID) {
57206 + dma_addr = dma_map_single(dev, usb_req->buf,
57208 + ep->dwc_ep.is_in ?
57210 + DMA_FROM_DEVICE);
57214 +#ifdef DWC_UTE_PER_IO
57215 + if (is_isoc_ep == 1) {
57216 + retval = dwc_otg_pcd_xiso_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr,
57217 + usb_req->length, usb_req->zero, usb_req,
57218 + gfp_flags == GFP_ATOMIC ? 1 : 0, &usb_req->ext_req);
57225 + retval = dwc_otg_pcd_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr,
57226 + usb_req->length, usb_req->zero, usb_req,
57227 + gfp_flags == GFP_ATOMIC ? 1 : 0);
57236 + * This function cancels an I/O request from an EP.
57238 +static int ep_dequeue(struct usb_ep *usb_ep, struct usb_request *usb_req)
57240 + DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, usb_req);
57242 + if (!usb_ep || !usb_req) {
57243 + DWC_WARN("bad argument\n");
57246 + if (!gadget_wrapper->driver ||
57247 + gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
57248 + DWC_WARN("bogus device state\n");
57249 + return -ESHUTDOWN;
57251 + if (dwc_otg_pcd_ep_dequeue(gadget_wrapper->pcd, usb_ep, usb_req)) {
57259 + * usb_ep_set_halt stalls an endpoint.
57261 + * usb_ep_clear_halt clears an endpoint halt and resets its data
57264 + * Both of these functions are implemented with the same underlying
57265 + * function. The behavior depends on the value argument.
57267 + * @param[in] usb_ep the Endpoint to halt or clear halt.
57268 + * @param[in] value
57269 + * - 0 means clear_halt.
57270 + * - 1 means set_halt,
57271 + * - 2 means clear stall lock flag.
57272 + * - 3 means set stall lock flag.
57274 +static int ep_halt(struct usb_ep *usb_ep, int value)
57278 + DWC_DEBUGPL(DBG_PCD, "HALT %s %d\n", usb_ep->name, value);
57281 + DWC_WARN("bad ep\n");
57285 + retval = dwc_otg_pcd_ep_halt(gadget_wrapper->pcd, usb_ep, value);
57286 + if (retval == -DWC_E_AGAIN) {
57288 + } else if (retval) {
57289 + retval = -EINVAL;
57296 + * ep_wedge: sets the halt feature and ignores clear requests
57298 + * @usb_ep: the endpoint being wedged
57300 + * Use this to stall an endpoint and ignore CLEAR_FEATURE(HALT_ENDPOINT)
57301 + * requests. If the gadget driver clears the halt status, it will
57302 + * automatically unwedge the endpoint.
57304 + * Returns zero on success, else negative errno. *
57305 + * Check usb_ep_set_wedge() at "usb_gadget.h" for details
57307 +static int ep_wedge(struct usb_ep *usb_ep)
57311 + DWC_DEBUGPL(DBG_PCD, "WEDGE %s\n", usb_ep->name);
57314 + DWC_WARN("bad ep\n");
57318 + retval = dwc_otg_pcd_ep_wedge(gadget_wrapper->pcd, usb_ep);
57319 + if (retval == -DWC_E_AGAIN) {
57320 + retval = -EAGAIN;
57321 + } else if (retval) {
57322 + retval = -EINVAL;
57328 +#ifdef DWC_EN_ISOC
57330 + * This function is used to submit an ISOC Transfer Request to an EP.
57332 + * - Every time a sync period completes the request's completion callback
57333 + * is called to provide data to the gadget driver.
57334 + * - Once submitted the request cannot be modified.
57335 + * - Each request is turned into periodic data packets untill ISO
57336 + * Transfer is stopped..
57338 +static int iso_ep_start(struct usb_ep *usb_ep, struct usb_iso_request *req,
57343 + if (!req || !req->process_buffer || !req->buf0 || !req->buf1) {
57344 + DWC_WARN("bad params\n");
57349 + DWC_PRINTF("bad params\n");
57353 + req->status = -EINPROGRESS;
57356 + dwc_otg_pcd_iso_ep_start(gadget_wrapper->pcd, usb_ep, req->buf0,
57357 + req->buf1, req->dma0, req->dma1,
57358 + req->sync_frame, req->data_pattern_frame,
57359 + req->data_per_frame,
57361 + flags & USB_REQ_ISO_ASAP ? -1 :
57362 + req->start_frame, req->buf_proc_intrvl,
57363 + req, gfp_flags == GFP_ATOMIC ? 1 : 0);
57373 + * This function stops ISO EP Periodic Data Transfer.
57375 +static int iso_ep_stop(struct usb_ep *usb_ep, struct usb_iso_request *req)
57379 + DWC_WARN("bad ep\n");
57382 + if (!gadget_wrapper->driver ||
57383 + gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
57384 + DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n",
57385 + gadget_wrapper->gadget.speed);
57386 + DWC_WARN("bogus device state\n");
57389 + dwc_otg_pcd_iso_ep_stop(gadget_wrapper->pcd, usb_ep, req);
57391 + retval = -EINVAL;
57397 +static struct usb_iso_request *alloc_iso_request(struct usb_ep *ep,
57398 + int packets, gfp_t gfp_flags)
57400 + struct usb_iso_request *pReq = NULL;
57401 + uint32_t req_size;
57403 + req_size = sizeof(struct usb_iso_request);
57405 + (2 * packets * (sizeof(struct usb_gadget_iso_packet_descriptor)));
57407 + pReq = kmalloc(req_size, gfp_flags);
57409 + DWC_WARN("Can't allocate Iso Request\n");
57412 + pReq->iso_packet_desc0 = (void *)(pReq + 1);
57414 + pReq->iso_packet_desc1 = pReq->iso_packet_desc0 + packets;
57419 +static void free_iso_request(struct usb_ep *ep, struct usb_iso_request *req)
57424 +static struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops = {
57426 + .enable = ep_enable,
57427 + .disable = ep_disable,
57429 + .alloc_request = dwc_otg_pcd_alloc_request,
57430 + .free_request = dwc_otg_pcd_free_request,
57432 + .queue = ep_queue,
57433 + .dequeue = ep_dequeue,
57435 + .set_halt = ep_halt,
57436 + .fifo_status = 0,
57439 + .iso_ep_start = iso_ep_start,
57440 + .iso_ep_stop = iso_ep_stop,
57441 + .alloc_iso_request = alloc_iso_request,
57442 + .free_iso_request = free_iso_request,
57447 + int (*enable) (struct usb_ep *ep,
57448 + const struct usb_endpoint_descriptor *desc);
57449 + int (*disable) (struct usb_ep *ep);
57451 + struct usb_request *(*alloc_request) (struct usb_ep *ep,
57452 + gfp_t gfp_flags);
57453 + void (*free_request) (struct usb_ep *ep, struct usb_request *req);
57455 + int (*queue) (struct usb_ep *ep, struct usb_request *req,
57456 + gfp_t gfp_flags);
57457 + int (*dequeue) (struct usb_ep *ep, struct usb_request *req);
57459 + int (*set_halt) (struct usb_ep *ep, int value);
57460 + int (*set_wedge) (struct usb_ep *ep);
57462 + int (*fifo_status) (struct usb_ep *ep);
57463 + void (*fifo_flush) (struct usb_ep *ep);
57464 +static struct usb_ep_ops dwc_otg_pcd_ep_ops = {
57465 + .enable = ep_enable,
57466 + .disable = ep_disable,
57468 + .alloc_request = dwc_otg_pcd_alloc_request,
57469 + .free_request = dwc_otg_pcd_free_request,
57471 + /* .set_wedge = ep_wedge, */
57472 + .set_wedge = NULL, /* uses set_halt instead */
57474 + .queue = ep_queue,
57475 + .dequeue = ep_dequeue,
57477 + .set_halt = ep_halt,
57478 + .fifo_status = 0,
57483 +#endif /* _EN_ISOC_ */
57484 +/* Gadget Operations */
57486 + * The following gadget operations will be implemented in the DWC_otg
57487 + * PCD. Functions in the API that are not described below are not
57490 + * The Gadget API provides wrapper functions for each of the function
57491 + * pointers defined in usb_gadget_ops. The Gadget Driver calls the
57492 + * wrapper function, which then calls the underlying PCD function. The
57493 + * following sections are named according to the wrapper functions
57494 + * (except for ioctl, which doesn't have a wrapper function). Within
57495 + * each section, the corresponding DWC_otg PCD function name is
57501 + *Gets the USB Frame number of the last SOF.
57503 +static int get_frame_number(struct usb_gadget *gadget)
57505 + struct gadget_wrapper *d;
57507 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget);
57509 + if (gadget == 0) {
57513 + d = container_of(gadget, struct gadget_wrapper, gadget);
57514 + return dwc_otg_pcd_get_frame_number(d->pcd);
57517 +#ifdef CONFIG_USB_DWC_OTG_LPM
57518 +static int test_lpm_enabled(struct usb_gadget *gadget)
57520 + struct gadget_wrapper *d;
57522 + d = container_of(gadget, struct gadget_wrapper, gadget);
57524 + return dwc_otg_pcd_is_lpm_enabled(d->pcd);
57529 + * Initiates Session Request Protocol (SRP) to wakeup the host if no
57530 + * session is in progress. If a session is already in progress, but
57531 + * the device is suspended, remote wakeup signaling is started.
57534 +static int wakeup(struct usb_gadget *gadget)
57536 + struct gadget_wrapper *d;
57538 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget);
57540 + if (gadget == 0) {
57543 + d = container_of(gadget, struct gadget_wrapper, gadget);
57545 + dwc_otg_pcd_wakeup(d->pcd);
57549 +static const struct usb_gadget_ops dwc_otg_pcd_ops = {
57550 + .get_frame = get_frame_number,
57551 + .wakeup = wakeup,
57552 +#ifdef CONFIG_USB_DWC_OTG_LPM
57553 + .lpm_support = test_lpm_enabled,
57555 + // current versions must always be self-powered
57558 +static int _setup(dwc_otg_pcd_t * pcd, uint8_t * bytes)
57560 + int retval = -DWC_E_NOT_SUPPORTED;
57561 + if (gadget_wrapper->driver && gadget_wrapper->driver->setup) {
57562 + retval = gadget_wrapper->driver->setup(&gadget_wrapper->gadget,
57563 + (struct usb_ctrlrequest
57567 + if (retval == -ENOTSUPP) {
57568 + retval = -DWC_E_NOT_SUPPORTED;
57569 + } else if (retval < 0) {
57570 + retval = -DWC_E_INVALID;
57576 +#ifdef DWC_EN_ISOC
57577 +static int _isoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle,
57578 + void *req_handle, int proc_buf_num)
57580 + int i, packet_count;
57581 + struct usb_gadget_iso_packet_descriptor *iso_packet = 0;
57582 + struct usb_iso_request *iso_req = req_handle;
57584 + if (proc_buf_num) {
57585 + iso_packet = iso_req->iso_packet_desc1;
57587 + iso_packet = iso_req->iso_packet_desc0;
57590 + dwc_otg_pcd_get_iso_packet_count(pcd, ep_handle, req_handle);
57591 + for (i = 0; i < packet_count; ++i) {
57595 + dwc_otg_pcd_get_iso_packet_params(pcd, ep_handle, req_handle,
57596 + i, &status, &actual, &offset);
57597 + switch (status) {
57598 + case -DWC_E_NO_DATA:
57599 + status = -ENODATA;
57603 + DWC_PRINTF("unknown status in isoc packet\n");
57607 + iso_packet[i].status = status;
57608 + iso_packet[i].offset = offset;
57609 + iso_packet[i].actual_length = actual;
57612 + iso_req->status = 0;
57613 + iso_req->process_buffer(ep_handle, iso_req);
57617 +#endif /* DWC_EN_ISOC */
57619 +#ifdef DWC_UTE_PER_IO
57621 + * Copy the contents of the extended request to the Linux usb_request's
57622 + * extended part and call the gadget's completion.
57624 + * @param pcd Pointer to the pcd structure
57625 + * @param ep_handle Void pointer to the usb_ep structure
57626 + * @param req_handle Void pointer to the usb_request structure
57627 + * @param status Request status returned from the portable logic
57628 + * @param ereq_port Void pointer to the extended request structure
57629 + * created in the the portable part that contains the
57630 + * results of the processed iso packets.
57632 +static int _xisoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle,
57633 + void *req_handle, int32_t status, void *ereq_port)
57635 + struct dwc_ute_iso_req_ext *ereqorg = NULL;
57636 + struct dwc_iso_xreq_port *ereqport = NULL;
57637 + struct dwc_ute_iso_packet_descriptor *desc_org = NULL;
57639 + struct usb_request *req;
57640 + //struct dwc_ute_iso_packet_descriptor *
57641 + //int status = 0;
57643 + req = (struct usb_request *)req_handle;
57644 + ereqorg = &req->ext_req;
57645 + ereqport = (struct dwc_iso_xreq_port *)ereq_port;
57646 + desc_org = ereqorg->per_io_frame_descs;
57648 + if (req && req->complete) {
57649 + /* Copy the request data from the portable logic to our request */
57650 + for (i = 0; i < ereqport->pio_pkt_count; i++) {
57651 + desc_org[i].actual_length =
57652 + ereqport->per_io_frame_descs[i].actual_length;
57653 + desc_org[i].status =
57654 + ereqport->per_io_frame_descs[i].status;
57657 + switch (status) {
57658 + case -DWC_E_SHUTDOWN:
57659 + req->status = -ESHUTDOWN;
57661 + case -DWC_E_RESTART:
57662 + req->status = -ECONNRESET;
57664 + case -DWC_E_INVALID:
57665 + req->status = -EINVAL;
57667 + case -DWC_E_TIMEOUT:
57668 + req->status = -ETIMEDOUT;
57671 + req->status = status;
57674 + /* And call the gadget's completion */
57675 + req->complete(ep_handle, req);
57680 +#endif /* DWC_UTE_PER_IO */
57682 +static int _complete(dwc_otg_pcd_t * pcd, void *ep_handle,
57683 + void *req_handle, int32_t status, uint32_t actual)
57685 + struct usb_request *req = (struct usb_request *)req_handle;
57686 + struct dwc_otg_pcd_ep *ep = NULL;
57688 + if (req && req->complete) {
57689 + switch (status) {
57690 + case -DWC_E_SHUTDOWN:
57691 + req->status = -ESHUTDOWN;
57693 + case -DWC_E_RESTART:
57694 + req->status = -ECONNRESET;
57696 + case -DWC_E_INVALID:
57697 + req->status = -EINVAL;
57699 + case -DWC_E_TIMEOUT:
57700 + req->status = -ETIMEDOUT;
57703 + req->status = status;
57707 + req->actual = actual;
57708 + DWC_SPINUNLOCK(pcd->lock);
57709 + req->complete(ep_handle, req);
57710 + DWC_SPINLOCK(pcd->lock);
57712 + ep = ep_from_handle(pcd, ep_handle);
57713 + if (GET_CORE_IF(pcd)->dma_enable) {
57714 + if (req->length != 0) {
57715 + dwc_otg_device_t *otg_dev = gadget_wrapper->pcd->otg_dev;
57716 + struct device *dev = NULL;
57718 + if (otg_dev != NULL)
57719 + dev = DWC_OTG_OS_GETDEV(otg_dev->os_dep);
57721 + dma_unmap_single(dev, req->dma, req->length,
57722 + ep->dwc_ep.is_in ?
57723 + DMA_TO_DEVICE: DMA_FROM_DEVICE);
57730 +static int _connect(dwc_otg_pcd_t * pcd, int speed)
57732 + gadget_wrapper->gadget.speed = speed;
57736 +static int _disconnect(dwc_otg_pcd_t * pcd)
57738 + if (gadget_wrapper->driver && gadget_wrapper->driver->disconnect) {
57739 + gadget_wrapper->driver->disconnect(&gadget_wrapper->gadget);
57744 +static int _resume(dwc_otg_pcd_t * pcd)
57746 + if (gadget_wrapper->driver && gadget_wrapper->driver->resume) {
57747 + gadget_wrapper->driver->resume(&gadget_wrapper->gadget);
57753 +static int _suspend(dwc_otg_pcd_t * pcd)
57755 + if (gadget_wrapper->driver && gadget_wrapper->driver->suspend) {
57756 + gadget_wrapper->driver->suspend(&gadget_wrapper->gadget);
57762 + * This function updates the otg values in the gadget structure.
57764 +static int _hnp_changed(dwc_otg_pcd_t * pcd)
57767 + if (!gadget_wrapper->gadget.is_otg)
57770 + gadget_wrapper->gadget.b_hnp_enable = get_b_hnp_enable(pcd);
57771 + gadget_wrapper->gadget.a_hnp_support = get_a_hnp_support(pcd);
57772 + gadget_wrapper->gadget.a_alt_hnp_support = get_a_alt_hnp_support(pcd);
57776 +static int _reset(dwc_otg_pcd_t * pcd)
57781 +#ifdef DWC_UTE_CFI
57782 +static int _cfi_setup(dwc_otg_pcd_t * pcd, void *cfi_req)
57784 + int retval = -DWC_E_INVALID;
57785 + if (gadget_wrapper->driver->cfi_feature_setup) {
57787 + gadget_wrapper->driver->
57788 + cfi_feature_setup(&gadget_wrapper->gadget,
57789 + (struct cfi_usb_ctrlrequest *)cfi_req);
57796 +static const struct dwc_otg_pcd_function_ops fops = {
57797 + .complete = _complete,
57798 +#ifdef DWC_EN_ISOC
57799 + .isoc_complete = _isoc_complete,
57802 + .disconnect = _disconnect,
57803 + .connect = _connect,
57804 + .resume = _resume,
57805 + .suspend = _suspend,
57806 + .hnp_changed = _hnp_changed,
57808 +#ifdef DWC_UTE_CFI
57809 + .cfi_setup = _cfi_setup,
57811 +#ifdef DWC_UTE_PER_IO
57812 + .xisoc_complete = _xisoc_complete,
57817 + * This function is the top level PCD interrupt handler.
57819 +static irqreturn_t dwc_otg_pcd_irq(int irq, void *dev)
57821 + dwc_otg_pcd_t *pcd = dev;
57822 + int32_t retval = IRQ_NONE;
57824 + retval = dwc_otg_pcd_handle_intr(pcd);
57825 + if (retval != 0) {
57826 + S3C2410X_CLEAR_EINTPEND();
57828 + return IRQ_RETVAL(retval);
57832 + * This function initialized the usb_ep structures to there default
57835 + * @param d Pointer on gadget_wrapper.
57837 +void gadget_add_eps(struct gadget_wrapper *d)
57839 + static const char *names[] = {
57875 + struct usb_ep *ep;
57876 + int8_t dev_endpoints;
57878 + DWC_DEBUGPL(DBG_PCDV, "%s\n", __func__);
57880 + INIT_LIST_HEAD(&d->gadget.ep_list);
57881 + d->gadget.ep0 = &d->ep0;
57882 + d->gadget.speed = USB_SPEED_UNKNOWN;
57884 + INIT_LIST_HEAD(&d->gadget.ep0->ep_list);
57887 + * Initialize the EP0 structure.
57891 + /* Init the usb_ep structure. */
57892 + ep->name = names[0];
57893 + ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
57896 + * @todo NGS: What should the max packet size be set to
57897 + * here? Before EP type is set?
57899 + ep->maxpacket = MAX_PACKET_SIZE;
57900 + dwc_otg_pcd_ep_enable(d->pcd, NULL, ep);
57902 + list_add_tail(&ep->ep_list, &d->gadget.ep_list);
57905 + * Initialize the EP structures.
57907 + dev_endpoints = d->pcd->core_if->dev_if->num_in_eps;
57909 + for (i = 0; i < dev_endpoints; i++) {
57910 + ep = &d->in_ep[i];
57912 + /* Init the usb_ep structure. */
57913 + ep->name = names[d->pcd->in_ep[i].dwc_ep.num];
57914 + ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
57917 + * @todo NGS: What should the max packet size be set to
57918 + * here? Before EP type is set?
57920 + ep->maxpacket = MAX_PACKET_SIZE;
57921 + list_add_tail(&ep->ep_list, &d->gadget.ep_list);
57924 + dev_endpoints = d->pcd->core_if->dev_if->num_out_eps;
57926 + for (i = 0; i < dev_endpoints; i++) {
57927 + ep = &d->out_ep[i];
57929 + /* Init the usb_ep structure. */
57930 + ep->name = names[15 + d->pcd->out_ep[i].dwc_ep.num];
57931 + ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
57934 + * @todo NGS: What should the max packet size be set to
57935 + * here? Before EP type is set?
57937 + ep->maxpacket = MAX_PACKET_SIZE;
57939 + list_add_tail(&ep->ep_list, &d->gadget.ep_list);
57942 + /* remove ep0 from the list. There is a ep0 pointer. */
57943 + list_del_init(&d->ep0.ep_list);
57945 + d->ep0.maxpacket = MAX_EP0_SIZE;
57949 + * This function releases the Gadget device.
57950 + * required by device_unregister().
57952 + * @todo Should this do something? Should it free the PCD?
57954 +static void dwc_otg_pcd_gadget_release(struct device *dev)
57956 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, dev);
57959 +static struct gadget_wrapper *alloc_wrapper(dwc_bus_dev_t *_dev)
57961 + static char pcd_name[] = "dwc_otg_pcd";
57962 + dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
57963 + struct gadget_wrapper *d;
57966 + d = DWC_ALLOC(sizeof(*d));
57971 + memset(d, 0, sizeof(*d));
57973 + d->gadget.name = pcd_name;
57974 + d->pcd = otg_dev->pcd;
57976 + dev_set_name(&d->gadget.dev, "%s", "gadget");
57978 + d->gadget.dev.parent = &_dev->dev;
57979 + d->gadget.dev.release = dwc_otg_pcd_gadget_release;
57980 + d->gadget.ops = &dwc_otg_pcd_ops;
57981 + d->gadget.max_speed = dwc_otg_pcd_is_dualspeed(otg_dev->pcd) ? USB_SPEED_HIGH:USB_SPEED_FULL;
57982 + d->gadget.is_otg = dwc_otg_pcd_is_otg(otg_dev->pcd);
57985 + /* Register the gadget device */
57986 + retval = device_register(&d->gadget.dev);
57987 + if (retval != 0) {
57988 + DWC_ERROR("device_register failed\n");
57996 +static void free_wrapper(struct gadget_wrapper *d)
57999 + /* should have been done already by driver model core */
58000 + DWC_WARN("driver '%s' is still registered\n",
58001 + d->driver->driver.name);
58002 +#ifdef CONFIG_USB_GADGET
58003 + usb_gadget_unregister_driver(d->driver);
58007 + device_unregister(&d->gadget.dev);
58012 + * This function initialized the PCD portion of the driver.
58015 +int pcd_init(dwc_bus_dev_t *_dev)
58017 + dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
58020 + DWC_DEBUGPL(DBG_PCDV, "%s(%p) otg_dev=%p\n", __func__, _dev, otg_dev);
58022 + otg_dev->pcd = dwc_otg_pcd_init(otg_dev);
58024 + if (!otg_dev->pcd) {
58025 + DWC_ERROR("dwc_otg_pcd_init failed\n");
58029 + otg_dev->pcd->otg_dev = otg_dev;
58030 + gadget_wrapper = alloc_wrapper(_dev);
58033 + * Initialize EP structures
58035 + gadget_add_eps(gadget_wrapper);
58037 + * Setup interupt handler
58039 + DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n",
58040 + otg_dev->os_dep.irq_num);
58041 + retval = request_irq(otg_dev->os_dep.irq_num, dwc_otg_pcd_irq,
58042 + IRQF_SHARED, gadget_wrapper->gadget.name,
58044 + if (retval != 0) {
58045 + DWC_ERROR("request of irq%d failed\n", otg_dev->os_dep.irq_num);
58046 + free_wrapper(gadget_wrapper);
58050 + dwc_otg_pcd_start(gadget_wrapper->pcd, &fops);
58056 + * Cleanup the PCD.
58058 +void pcd_remove(dwc_bus_dev_t *_dev)
58060 + dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
58061 + dwc_otg_pcd_t *pcd = otg_dev->pcd;
58063 + DWC_DEBUGPL(DBG_PCDV, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev);
58068 + free_irq(otg_dev->os_dep.irq_num, pcd);
58069 + dwc_otg_pcd_remove(otg_dev->pcd);
58070 + free_wrapper(gadget_wrapper);
58071 + otg_dev->pcd = 0;
58074 +#endif /* DWC_HOST_ONLY */
58076 +++ b/drivers/usb/host/dwc_otg/dwc_otg_regs.h
58078 +/* ==========================================================================
58079 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $
58080 + * $Revision: #98 $
58081 + * $Date: 2012/08/10 $
58082 + * $Change: 2047372 $
58084 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
58085 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
58086 + * otherwise expressly agreed to in writing between Synopsys and you.
58088 + * The Software IS NOT an item of Licensed Software or Licensed Product under
58089 + * any End User Software License Agreement or Agreement for Licensed Product
58090 + * with Synopsys or any supplement thereto. You are permitted to use and
58091 + * redistribute this Software in source and binary forms, with or without
58092 + * modification, provided that redistributions of source code must retain this
58093 + * notice. You may not view, use, disclose, copy or distribute this file or
58094 + * any information contained herein except pursuant to this license grant from
58095 + * Synopsys. If you do not agree with this notice, including the disclaimer
58096 + * below, then you are not authorized to use the Software.
58098 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
58099 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
58100 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
58101 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
58102 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
58103 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
58104 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
58105 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
58106 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
58107 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
58109 + * ========================================================================== */
58111 +#ifndef __DWC_OTG_REGS_H__
58112 +#define __DWC_OTG_REGS_H__
58114 +#include "dwc_otg_core_if.h"
58119 + * This file contains the data structures for accessing the DWC_otg core registers.
58121 + * The application interfaces with the HS OTG core by reading from and
58122 + * writing to the Control and Status Register (CSR) space through the
58123 + * AHB Slave interface. These registers are 32 bits wide, and the
58124 + * addresses are 32-bit-block aligned.
58125 + * CSRs are classified as follows:
58126 + * - Core Global Registers
58127 + * - Device Mode Registers
58128 + * - Device Global Registers
58129 + * - Device Endpoint Specific Registers
58130 + * - Host Mode Registers
58131 + * - Host Global Registers
58132 + * - Host Port CSRs
58133 + * - Host Channel Specific Registers
58135 + * Only the Core Global registers can be accessed in both Device and
58136 + * Host modes. When the HS OTG core is operating in one mode, either
58137 + * Device or Host, the application must not access registers from the
58138 + * other mode. When the core switches from one mode to another, the
58139 + * registers in the new mode of operation must be reprogrammed as they
58140 + * would be after a power-on reset.
58143 +/****************************************************************************/
58144 +/** DWC_otg Core registers .
58145 + * The dwc_otg_core_global_regs structure defines the size
58146 + * and relative field offsets for the Core Global registers.
58148 +typedef struct dwc_otg_core_global_regs {
58149 + /** OTG Control and Status Register. <i>Offset: 000h</i> */
58150 + volatile uint32_t gotgctl;
58151 + /** OTG Interrupt Register. <i>Offset: 004h</i> */
58152 + volatile uint32_t gotgint;
58153 + /**Core AHB Configuration Register. <i>Offset: 008h</i> */
58154 + volatile uint32_t gahbcfg;
58156 +#define DWC_GLBINTRMASK 0x0001
58157 +#define DWC_DMAENABLE 0x0020
58158 +#define DWC_NPTXEMPTYLVL_EMPTY 0x0080
58159 +#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000
58160 +#define DWC_PTXEMPTYLVL_EMPTY 0x0100
58161 +#define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000
58163 + /**Core USB Configuration Register. <i>Offset: 00Ch</i> */
58164 + volatile uint32_t gusbcfg;
58165 + /**Core Reset Register. <i>Offset: 010h</i> */
58166 + volatile uint32_t grstctl;
58167 + /**Core Interrupt Register. <i>Offset: 014h</i> */
58168 + volatile uint32_t gintsts;
58169 + /**Core Interrupt Mask Register. <i>Offset: 018h</i> */
58170 + volatile uint32_t gintmsk;
58171 + /**Receive Status Queue Read Register (Read Only). <i>Offset: 01Ch</i> */
58172 + volatile uint32_t grxstsr;
58173 + /**Receive Status Queue Read & POP Register (Read Only). <i>Offset: 020h</i>*/
58174 + volatile uint32_t grxstsp;
58175 + /**Receive FIFO Size Register. <i>Offset: 024h</i> */
58176 + volatile uint32_t grxfsiz;
58177 + /**Non Periodic Transmit FIFO Size Register. <i>Offset: 028h</i> */
58178 + volatile uint32_t gnptxfsiz;
58179 + /**Non Periodic Transmit FIFO/Queue Status Register (Read
58180 + * Only). <i>Offset: 02Ch</i> */
58181 + volatile uint32_t gnptxsts;
58182 + /**I2C Access Register. <i>Offset: 030h</i> */
58183 + volatile uint32_t gi2cctl;
58184 + /**PHY Vendor Control Register. <i>Offset: 034h</i> */
58185 + volatile uint32_t gpvndctl;
58186 + /**General Purpose Input/Output Register. <i>Offset: 038h</i> */
58187 + volatile uint32_t ggpio;
58188 + /**User ID Register. <i>Offset: 03Ch</i> */
58189 + volatile uint32_t guid;
58190 + /**Synopsys ID Register (Read Only). <i>Offset: 040h</i> */
58191 + volatile uint32_t gsnpsid;
58192 + /**User HW Config1 Register (Read Only). <i>Offset: 044h</i> */
58193 + volatile uint32_t ghwcfg1;
58194 + /**User HW Config2 Register (Read Only). <i>Offset: 048h</i> */
58195 + volatile uint32_t ghwcfg2;
58196 +#define DWC_SLAVE_ONLY_ARCH 0
58197 +#define DWC_EXT_DMA_ARCH 1
58198 +#define DWC_INT_DMA_ARCH 2
58200 +#define DWC_MODE_HNP_SRP_CAPABLE 0
58201 +#define DWC_MODE_SRP_ONLY_CAPABLE 1
58202 +#define DWC_MODE_NO_HNP_SRP_CAPABLE 2
58203 +#define DWC_MODE_SRP_CAPABLE_DEVICE 3
58204 +#define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4
58205 +#define DWC_MODE_SRP_CAPABLE_HOST 5
58206 +#define DWC_MODE_NO_SRP_CAPABLE_HOST 6
58208 + /**User HW Config3 Register (Read Only). <i>Offset: 04Ch</i> */
58209 + volatile uint32_t ghwcfg3;
58210 + /**User HW Config4 Register (Read Only). <i>Offset: 050h</i>*/
58211 + volatile uint32_t ghwcfg4;
58212 + /** Core LPM Configuration register <i>Offset: 054h</i>*/
58213 + volatile uint32_t glpmcfg;
58214 + /** Global PowerDn Register <i>Offset: 058h</i> */
58215 + volatile uint32_t gpwrdn;
58216 + /** Global DFIFO SW Config Register <i>Offset: 05Ch</i> */
58217 + volatile uint32_t gdfifocfg;
58218 + /** ADP Control Register <i>Offset: 060h</i> */
58219 + volatile uint32_t adpctl;
58220 + /** Reserved <i>Offset: 064h-0FFh</i> */
58221 + volatile uint32_t reserved39[39];
58222 + /** Host Periodic Transmit FIFO Size Register. <i>Offset: 100h</i> */
58223 + volatile uint32_t hptxfsiz;
58224 + /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled,
58225 + otherwise Device Transmit FIFO#n Register.
58226 + * <i>Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15).</i> */
58227 + volatile uint32_t dtxfsiz[15];
58228 +} dwc_otg_core_global_regs_t;
58231 + * This union represents the bit fields of the Core OTG Control
58232 + * and Status Register (GOTGCTL). Set the bits using the bit
58233 + * fields then write the <i>d32</i> value to the register.
58235 +typedef union gotgctl_data {
58236 + /** raw register data */
58238 + /** register bits */
58240 + unsigned sesreqscs:1;
58241 + unsigned sesreq:1;
58242 + unsigned vbvalidoven:1;
58243 + unsigned vbvalidovval:1;
58244 + unsigned avalidoven:1;
58245 + unsigned avalidovval:1;
58246 + unsigned bvalidoven:1;
58247 + unsigned bvalidovval:1;
58248 + unsigned hstnegscs:1;
58249 + unsigned hnpreq:1;
58250 + unsigned hstsethnpen:1;
58251 + unsigned devhnpen:1;
58252 + unsigned reserved12_15:4;
58253 + unsigned conidsts:1;
58254 + unsigned dbnctime:1;
58255 + unsigned asesvld:1;
58256 + unsigned bsesvld:1;
58257 + unsigned otgver:1;
58258 + unsigned reserved1:1;
58259 + unsigned multvalidbc:5;
58260 + unsigned chirpen:1;
58261 + unsigned reserved28_31:4;
58266 + * This union represents the bit fields of the Core OTG Interrupt Register
58267 + * (GOTGINT). Set/clear the bits using the bit fields then write the <i>d32</i>
58268 + * value to the register.
58270 +typedef union gotgint_data {
58271 + /** raw register data */
58273 + /** register bits */
58275 + /** Current Mode */
58276 + unsigned reserved0_1:2;
58278 + /** Session End Detected */
58279 + unsigned sesenddet:1;
58281 + unsigned reserved3_7:5;
58283 + /** Session Request Success Status Change */
58284 + unsigned sesreqsucstschng:1;
58285 + /** Host Negotiation Success Status Change */
58286 + unsigned hstnegsucstschng:1;
58288 + unsigned reserved10_16:7;
58290 + /** Host Negotiation Detected */
58291 + unsigned hstnegdet:1;
58292 + /** A-Device Timeout Change */
58293 + unsigned adevtoutchng:1;
58294 + /** Debounce Done */
58295 + unsigned debdone:1;
58296 + /** Multi-Valued input changed */
58299 + unsigned reserved31_21:11;
58305 + * This union represents the bit fields of the Core AHB Configuration
58306 + * Register (GAHBCFG). Set/clear the bits using the bit fields then
58307 + * write the <i>d32</i> value to the register.
58309 +typedef union gahbcfg_data {
58310 + /** raw register data */
58312 + /** register bits */
58314 + unsigned glblintrmsk:1;
58315 +#define DWC_GAHBCFG_GLBINT_ENABLE 1
58317 + unsigned hburstlen:4;
58318 +#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0
58319 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR 1
58320 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3
58321 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5
58322 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7
58324 + unsigned dmaenable:1;
58325 +#define DWC_GAHBCFG_DMAENABLE 1
58326 + unsigned reserved:1;
58327 + unsigned nptxfemplvl_txfemplvl:1;
58328 + unsigned ptxfemplvl:1;
58329 +#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1
58330 +#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
58331 + unsigned reserved9_20:12;
58332 + unsigned remmemsupp:1;
58333 + unsigned notialldmawrit:1;
58334 + unsigned ahbsingle:1;
58335 + unsigned reserved24_31:8;
58340 + * This union represents the bit fields of the Core USB Configuration
58341 + * Register (GUSBCFG). Set the bits using the bit fields then write
58342 + * the <i>d32</i> value to the register.
58344 +typedef union gusbcfg_data {
58345 + /** raw register data */
58347 + /** register bits */
58349 + unsigned toutcal:3;
58350 + unsigned phyif:1;
58351 + unsigned ulpi_utmi_sel:1;
58352 + unsigned fsintf:1;
58353 + unsigned physel:1;
58354 + unsigned ddrsel:1;
58355 + unsigned srpcap:1;
58356 + unsigned hnpcap:1;
58357 + unsigned usbtrdtim:4;
58358 + unsigned reserved1:1;
58359 + unsigned phylpwrclksel:1;
58360 + unsigned otgutmifssel:1;
58361 + unsigned ulpi_fsls:1;
58362 + unsigned ulpi_auto_res:1;
58363 + unsigned ulpi_clk_sus_m:1;
58364 + unsigned ulpi_ext_vbus_drv:1;
58365 + unsigned ulpi_int_vbus_indicator:1;
58366 + unsigned term_sel_dl_pulse:1;
58367 + unsigned indicator_complement:1;
58368 + unsigned indicator_pass_through:1;
58369 + unsigned ulpi_int_prot_dis:1;
58370 + unsigned ic_usb_cap:1;
58371 + unsigned ic_traffic_pull_remove:1;
58372 + unsigned tx_end_delay:1;
58373 + unsigned force_host_mode:1;
58374 + unsigned force_dev_mode:1;
58375 + unsigned reserved31:1;
58380 + * This union represents the bit fields of the Core Reset Register
58381 + * (GRSTCTL). Set/clear the bits using the bit fields then write the
58382 + * <i>d32</i> value to the register.
58384 +typedef union grstctl_data {
58385 + /** raw register data */
58387 + /** register bits */
58389 + /** Core Soft Reset (CSftRst) (Device and Host)
58391 + * The application can flush the control logic in the
58392 + * entire core using this bit. This bit resets the
58393 + * pipelines in the AHB Clock domain as well as the
58394 + * PHY Clock domain.
58396 + * The state machines are reset to an IDLE state, the
58397 + * control bits in the CSRs are cleared, all the
58398 + * transmit FIFOs and the receive FIFO are flushed.
58400 + * The status mask bits that control the generation of
58401 + * the interrupt, are cleared, to clear the
58402 + * interrupt. The interrupt status bits are not
58403 + * cleared, so the application can get the status of
58404 + * any events that occurred in the core after it has
58407 + * Any transactions on the AHB are terminated as soon
58408 + * as possible following the protocol. Any
58409 + * transactions on the USB are terminated immediately.
58411 + * The configuration settings in the CSRs are
58412 + * unchanged, so the software doesn't have to
58413 + * reprogram these registers (Device
58414 + * Configuration/Host Configuration/Core System
58415 + * Configuration/Core PHY Configuration).
58417 + * The application can write to this bit, any time it
58418 + * wants to reset the core. This is a self clearing
58419 + * bit and the core clears this bit after all the
58420 + * necessary logic is reset in the core, which may
58421 + * take several clocks, depending on the current state
58424 + unsigned csftrst:1;
58425 + /** Hclk Soft Reset
58427 + * The application uses this bit to reset the control logic in
58428 + * the AHB clock domain. Only AHB clock domain pipelines are
58431 + unsigned hsftrst:1;
58432 + /** Host Frame Counter Reset (Host Only)<br>
58434 + * The application can reset the (micro)frame number
58435 + * counter inside the core, using this bit. When the
58436 + * (micro)frame counter is reset, the subsequent SOF
58437 + * sent out by the core, will have a (micro)frame
58440 + unsigned hstfrm:1;
58441 + /** In Token Sequence Learning Queue Flush
58442 + * (INTknQFlsh) (Device Only)
58444 + unsigned intknqflsh:1;
58445 + /** RxFIFO Flush (RxFFlsh) (Device and Host)
58447 + * The application can flush the entire Receive FIFO
58448 + * using this bit. The application must first
58449 + * ensure that the core is not in the middle of a
58450 + * transaction. The application should write into
58451 + * this bit, only after making sure that neither the
58452 + * DMA engine is reading from the RxFIFO nor the MAC
58453 + * is writing the data in to the FIFO. The
58454 + * application should wait until the bit is cleared
58455 + * before performing any other operations. This bit
58456 + * will takes 8 clocks (slowest of PHY or AHB clock)
58459 + unsigned rxfflsh:1;
58460 + /** TxFIFO Flush (TxFFlsh) (Device and Host).
58462 + * This bit is used to selectively flush a single or
58463 + * all transmit FIFOs. The application must first
58464 + * ensure that the core is not in the middle of a
58465 + * transaction. The application should write into
58466 + * this bit, only after making sure that neither the
58467 + * DMA engine is writing into the TxFIFO nor the MAC
58468 + * is reading the data out of the FIFO. The
58469 + * application should wait until the core clears this
58470 + * bit, before performing any operations. This bit
58471 + * will takes 8 clocks (slowest of PHY or AHB clock)
58474 + unsigned txfflsh:1;
58476 + /** TxFIFO Number (TxFNum) (Device and Host).
58478 + * This is the FIFO number which needs to be flushed,
58479 + * using the TxFIFO Flush bit. This field should not
58480 + * be changed until the TxFIFO Flush bit is cleared by
58482 + * - 0x0 : Non Periodic TxFIFO Flush
58483 + * - 0x1 : Periodic TxFIFO #1 Flush in device mode
58484 + * or Periodic TxFIFO in host mode
58485 + * - 0x2 : Periodic TxFIFO #2 Flush in device mode.
58487 + * - 0xF : Periodic TxFIFO #15 Flush in device mode
58488 + * - 0x10: Flush all the Transmit NonPeriodic and
58489 + * Transmit Periodic FIFOs in the core
58491 + unsigned txfnum:5;
58493 + unsigned reserved11_29:19;
58494 + /** DMA Request Signal. Indicated DMA request is in
58495 + * probress. Used for debug purpose. */
58496 + unsigned dmareq:1;
58497 + /** AHB Master Idle. Indicates the AHB Master State
58498 + * Machine is in IDLE condition. */
58499 + unsigned ahbidle:1;
58504 + * This union represents the bit fields of the Core Interrupt Mask
58505 + * Register (GINTMSK). Set/clear the bits using the bit fields then
58506 + * write the <i>d32</i> value to the register.
58508 +typedef union gintmsk_data {
58509 + /** raw register data */
58511 + /** register bits */
58513 + unsigned reserved0:1;
58514 + unsigned modemismatch:1;
58515 + unsigned otgintr:1;
58516 + unsigned sofintr:1;
58517 + unsigned rxstsqlvl:1;
58518 + unsigned nptxfempty:1;
58519 + unsigned ginnakeff:1;
58520 + unsigned goutnakeff:1;
58521 + unsigned ulpickint:1;
58522 + unsigned i2cintr:1;
58523 + unsigned erlysuspend:1;
58524 + unsigned usbsuspend:1;
58525 + unsigned usbreset:1;
58526 + unsigned enumdone:1;
58527 + unsigned isooutdrop:1;
58528 + unsigned eopframe:1;
58529 + unsigned restoredone:1;
58530 + unsigned epmismatch:1;
58531 + unsigned inepintr:1;
58532 + unsigned outepintr:1;
58533 + unsigned incomplisoin:1;
58534 + unsigned incomplisoout:1;
58535 + unsigned fetsusp:1;
58536 + unsigned resetdet:1;
58537 + unsigned portintr:1;
58538 + unsigned hcintr:1;
58539 + unsigned ptxfempty:1;
58540 + unsigned lpmtranrcvd:1;
58541 + unsigned conidstschng:1;
58542 + unsigned disconnect:1;
58543 + unsigned sessreqintr:1;
58544 + unsigned wkupintr:1;
58548 + * This union represents the bit fields of the Core Interrupt Register
58549 + * (GINTSTS). Set/clear the bits using the bit fields then write the
58550 + * <i>d32</i> value to the register.
58552 +typedef union gintsts_data {
58553 + /** raw register data */
58555 +#define DWC_SOF_INTR_MASK 0x0008
58556 + /** register bits */
58558 +#define DWC_HOST_MODE 1
58559 + unsigned curmode:1;
58560 + unsigned modemismatch:1;
58561 + unsigned otgintr:1;
58562 + unsigned sofintr:1;
58563 + unsigned rxstsqlvl:1;
58564 + unsigned nptxfempty:1;
58565 + unsigned ginnakeff:1;
58566 + unsigned goutnakeff:1;
58567 + unsigned ulpickint:1;
58568 + unsigned i2cintr:1;
58569 + unsigned erlysuspend:1;
58570 + unsigned usbsuspend:1;
58571 + unsigned usbreset:1;
58572 + unsigned enumdone:1;
58573 + unsigned isooutdrop:1;
58574 + unsigned eopframe:1;
58575 + unsigned restoredone:1;
58576 + unsigned epmismatch:1;
58577 + unsigned inepint:1;
58578 + unsigned outepintr:1;
58579 + unsigned incomplisoin:1;
58580 + unsigned incomplisoout:1;
58581 + unsigned fetsusp:1;
58582 + unsigned resetdet:1;
58583 + unsigned portintr:1;
58584 + unsigned hcintr:1;
58585 + unsigned ptxfempty:1;
58586 + unsigned lpmtranrcvd:1;
58587 + unsigned conidstschng:1;
58588 + unsigned disconnect:1;
58589 + unsigned sessreqintr:1;
58590 + unsigned wkupintr:1;
58595 + * This union represents the bit fields in the Device Receive Status Read and
58596 + * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
58597 + * element then read out the bits using the <i>b</i>it elements.
58599 +typedef union device_grxsts_data {
58600 + /** raw register data */
58602 + /** register bits */
58604 + unsigned epnum:4;
58605 + unsigned bcnt:11;
58608 +#define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet
58609 +#define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete
58611 +#define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK
58612 +#define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete
58613 +#define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet
58614 + unsigned pktsts:4;
58616 + unsigned reserved25_31:7;
58618 +} device_grxsts_data_t;
58621 + * This union represents the bit fields in the Host Receive Status Read and
58622 + * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
58623 + * element then read out the bits using the <i>b</i>it elements.
58625 +typedef union host_grxsts_data {
58626 + /** raw register data */
58628 + /** register bits */
58630 + unsigned chnum:4;
58631 + unsigned bcnt:11;
58634 + unsigned pktsts:4;
58635 +#define DWC_GRXSTS_PKTSTS_IN 0x2
58636 +#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3
58637 +#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5
58638 +#define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7
58640 + unsigned reserved21_31:11;
58642 +} host_grxsts_data_t;
58645 + * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ,
58646 + * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the <i>d32</i> element
58647 + * then read out the bits using the <i>b</i>it elements.
58649 +typedef union fifosize_data {
58650 + /** raw register data */
58652 + /** register bits */
58654 + unsigned startaddr:16;
58655 + unsigned depth:16;
58657 +} fifosize_data_t;
58660 + * This union represents the bit fields in the Non-Periodic Transmit
58661 + * FIFO/Queue Status Register (GNPTXSTS). Read the register into the
58662 + * <i>d32</i> element then read out the bits using the <i>b</i>it
58665 +typedef union gnptxsts_data {
58666 + /** raw register data */
58668 + /** register bits */
58670 + unsigned nptxfspcavail:16;
58671 + unsigned nptxqspcavail:8;
58672 + /** Top of the Non-Periodic Transmit Request Queue
58673 + * - bit 24 - Terminate (Last entry for the selected
58675 + * - bits 26:25 - Token Type
58676 + * - 2'b00 - IN/OUT
58677 + * - 2'b01 - Zero Length OUT
58678 + * - 2'b10 - PING/Complete Split
58679 + * - 2'b11 - Channel Halt
58680 + * - bits 30:27 - Channel/EP Number
58682 + unsigned nptxqtop_terminate:1;
58683 + unsigned nptxqtop_token:2;
58684 + unsigned nptxqtop_chnep:4;
58685 + unsigned reserved:1;
58687 +} gnptxsts_data_t;
58690 + * This union represents the bit fields in the Transmit
58691 + * FIFO Status Register (DTXFSTS). Read the register into the
58692 + * <i>d32</i> element then read out the bits using the <i>b</i>it
58695 +typedef union dtxfsts_data {
58696 + /** raw register data */
58698 + /** register bits */
58700 + unsigned txfspcavail:16;
58701 + unsigned reserved:16;
58706 + * This union represents the bit fields in the I2C Control Register
58707 + * (I2CCTL). Read the register into the <i>d32</i> element then read out the
58708 + * bits using the <i>b</i>it elements.
58710 +typedef union gi2cctl_data {
58711 + /** raw register data */
58713 + /** register bits */
58715 + unsigned rwdata:8;
58716 + unsigned regaddr:8;
58718 + unsigned i2cen:1;
58720 + unsigned i2csuspctl:1;
58721 + unsigned i2cdevaddr:2;
58722 + unsigned i2cdatse0:1;
58723 + unsigned reserved:1;
58725 + unsigned bsydne:1;
58730 + * This union represents the bit fields in the PHY Vendor Control Register
58731 + * (GPVNDCTL). Read the register into the <i>d32</i> element then read out the
58732 + * bits using the <i>b</i>it elements.
58734 +typedef union gpvndctl_data {
58735 + /** raw register data */
58737 + /** register bits */
58739 + unsigned regdata:8;
58740 + unsigned vctrl:8;
58741 + unsigned regaddr16_21:6;
58742 + unsigned regwr:1;
58743 + unsigned reserved23_24:2;
58744 + unsigned newregreq:1;
58745 + unsigned vstsbsy:1;
58746 + unsigned vstsdone:1;
58747 + unsigned reserved28_30:3;
58748 + unsigned disulpidrvr:1;
58750 +} gpvndctl_data_t;
58753 + * This union represents the bit fields in the General Purpose
58754 + * Input/Output Register (GGPIO).
58755 + * Read the register into the <i>d32</i> element then read out the
58756 + * bits using the <i>b</i>it elements.
58758 +typedef union ggpio_data {
58759 + /** raw register data */
58761 + /** register bits */
58769 + * This union represents the bit fields in the User ID Register
58770 + * (GUID). Read the register into the <i>d32</i> element then read out the
58771 + * bits using the <i>b</i>it elements.
58773 +typedef union guid_data {
58774 + /** raw register data */
58776 + /** register bits */
58778 + unsigned rwdata:32;
58783 + * This union represents the bit fields in the Synopsys ID Register
58784 + * (GSNPSID). Read the register into the <i>d32</i> element then read out the
58785 + * bits using the <i>b</i>it elements.
58787 +typedef union gsnpsid_data {
58788 + /** raw register data */
58790 + /** register bits */
58792 + unsigned rwdata:32;
58797 + * This union represents the bit fields in the User HW Config1
58798 + * Register. Read the register into the <i>d32</i> element then read
58799 + * out the bits using the <i>b</i>it elements.
58801 +typedef union hwcfg1_data {
58802 + /** raw register data */
58804 + /** register bits */
58806 + unsigned ep_dir0:2;
58807 + unsigned ep_dir1:2;
58808 + unsigned ep_dir2:2;
58809 + unsigned ep_dir3:2;
58810 + unsigned ep_dir4:2;
58811 + unsigned ep_dir5:2;
58812 + unsigned ep_dir6:2;
58813 + unsigned ep_dir7:2;
58814 + unsigned ep_dir8:2;
58815 + unsigned ep_dir9:2;
58816 + unsigned ep_dir10:2;
58817 + unsigned ep_dir11:2;
58818 + unsigned ep_dir12:2;
58819 + unsigned ep_dir13:2;
58820 + unsigned ep_dir14:2;
58821 + unsigned ep_dir15:2;
58826 + * This union represents the bit fields in the User HW Config2
58827 + * Register. Read the register into the <i>d32</i> element then read
58828 + * out the bits using the <i>b</i>it elements.
58830 +typedef union hwcfg2_data {
58831 + /** raw register data */
58833 + /** register bits */
58836 + unsigned op_mode:3;
58837 +#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0
58838 +#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
58839 +#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
58840 +#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
58841 +#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
58842 +#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
58843 +#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
58845 + unsigned architecture:2;
58846 + unsigned point2point:1;
58847 + unsigned hs_phy_type:2;
58848 +#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
58849 +#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1
58850 +#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2
58851 +#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
58853 + unsigned fs_phy_type:2;
58854 + unsigned num_dev_ep:4;
58855 + unsigned num_host_chan:4;
58856 + unsigned perio_ep_supported:1;
58857 + unsigned dynamic_fifo:1;
58858 + unsigned multi_proc_int:1;
58859 + unsigned reserved21:1;
58860 + unsigned nonperio_tx_q_depth:2;
58861 + unsigned host_perio_tx_q_depth:2;
58862 + unsigned dev_token_q_depth:5;
58863 + unsigned otg_enable_ic_usb:1;
58868 + * This union represents the bit fields in the User HW Config3
58869 + * Register. Read the register into the <i>d32</i> element then read
58870 + * out the bits using the <i>b</i>it elements.
58872 +typedef union hwcfg3_data {
58873 + /** raw register data */
58875 + /** register bits */
58878 + unsigned xfer_size_cntr_width:4;
58879 + unsigned packet_size_cntr_width:3;
58880 + unsigned otg_func:1;
58882 + unsigned vendor_ctrl_if:1;
58883 + unsigned optional_features:1;
58884 + unsigned synch_reset_type:1;
58885 + unsigned adp_supp:1;
58886 + unsigned otg_enable_hsic:1;
58887 + unsigned bc_support:1;
58888 + unsigned otg_lpm_en:1;
58889 + unsigned dfifo_depth:16;
58894 + * This union represents the bit fields in the User HW Config4
58895 + * Register. Read the register into the <i>d32</i> element then read
58896 + * out the bits using the <i>b</i>it elements.
58898 +typedef union hwcfg4_data {
58899 + /** raw register data */
58901 + /** register bits */
58903 + unsigned num_dev_perio_in_ep:4;
58904 + unsigned power_optimiz:1;
58905 + unsigned min_ahb_freq:1;
58906 + unsigned hiber:1;
58907 + unsigned xhiber:1;
58908 + unsigned reserved:6;
58909 + unsigned utmi_phy_data_width:2;
58910 + unsigned num_dev_mode_ctrl_ep:4;
58911 + unsigned iddig_filt_en:1;
58912 + unsigned vbus_valid_filt_en:1;
58913 + unsigned a_valid_filt_en:1;
58914 + unsigned b_valid_filt_en:1;
58915 + unsigned session_end_filt_en:1;
58916 + unsigned ded_fifo_en:1;
58917 + unsigned num_in_eps:4;
58918 + unsigned desc_dma:1;
58919 + unsigned desc_dma_dyn:1;
58924 + * This union represents the bit fields of the Core LPM Configuration
58925 + * Register (GLPMCFG). Set the bits using bit fields then write
58926 + * the <i>d32</i> value to the register.
58928 +typedef union glpmctl_data {
58929 + /** raw register data */
58931 + /** register bits */
58933 + /** LPM-Capable (LPMCap) (Device and Host)
58934 + * The application uses this bit to control
58935 + * the DWC_otg core LPM capabilities.
58937 + unsigned lpm_cap_en:1;
58938 + /** LPM response programmed by application (AppL1Res) (Device)
58939 + * Handshake response to LPM token pre-programmed
58940 + * by device application software.
58942 + unsigned appl_resp:1;
58943 + /** Host Initiated Resume Duration (HIRD) (Device and Host)
58944 + * In Host mode this field indicates the value of HIRD
58945 + * to be sent in an LPM transaction.
58946 + * In Device mode this field is updated with the
58947 + * Received LPM Token HIRD bmAttribute
58948 + * when an ACK/NYET/STALL response is sent
58949 + * to an LPM transaction.
58952 + /** RemoteWakeEnable (bRemoteWake) (Device and Host)
58953 + * In Host mode this bit indicates the value of remote
58954 + * wake up to be sent in wIndex field of LPM transaction.
58955 + * In Device mode this field is updated with the
58956 + * Received LPM Token bRemoteWake bmAttribute
58957 + * when an ACK/NYET/STALL response is sent
58958 + * to an LPM transaction.
58960 + unsigned rem_wkup_en:1;
58961 + /** Enable utmi_sleep_n (EnblSlpM) (Device and Host)
58962 + * The application uses this bit to control
58963 + * the utmi_sleep_n assertion to the PHY when in L1 state.
58965 + unsigned en_utmi_sleep:1;
58966 + /** HIRD Threshold (HIRD_Thres) (Device and Host)
58968 + unsigned hird_thres:5;
58969 + /** LPM Response (CoreL1Res) (Device and Host)
58970 + * In Host mode this bit contains handsake response to
58971 + * LPM transaction.
58972 + * In Device mode the response of the core to
58973 + * LPM transaction received is reflected in these two bits.
58974 + - 0x0 : ERROR (No handshake response)
58979 + unsigned lpm_resp:2;
58980 + /** Port Sleep Status (SlpSts) (Device and Host)
58981 + * This bit is set as long as a Sleep condition
58982 + * is present on the USB bus.
58984 + unsigned prt_sleep_sts:1;
58985 + /** Sleep State Resume OK (L1ResumeOK) (Device and Host)
58986 + * Indicates that the application or host
58987 + * can start resume from Sleep state.
58989 + unsigned sleep_state_resumeok:1;
58990 + /** LPM channel Index (LPM_Chnl_Indx) (Host)
58991 + * The channel number on which the LPM transaction
58992 + * has to be applied while sending
58993 + * an LPM transaction to the local device.
58995 + unsigned lpm_chan_index:4;
58996 + /** LPM Retry Count (LPM_Retry_Cnt) (Host)
58997 + * Number host retries that would be performed
58998 + * if the device response was not valid response.
59000 + unsigned retry_count:3;
59001 + /** Send LPM Transaction (SndLPM) (Host)
59002 + * When set by application software,
59003 + * an LPM transaction containing two tokens
59006 + unsigned send_lpm:1;
59007 + /** LPM Retry status (LPM_RetryCnt_Sts) (Host)
59008 + * Number of LPM Host Retries still remaining
59009 + * to be transmitted for the current LPM sequence
59011 + unsigned retry_count_sts:3;
59012 + unsigned reserved28_29:2;
59013 + /** In host mode once this bit is set, the host
59014 + * configures to drive the HSIC Idle state on the bus.
59015 + * It then waits for the device to initiate the Connect sequence.
59016 + * In device mode once this bit is set, the device waits for
59017 + * the HSIC Idle line state on the bus. Upon receving the Idle
59018 + * line state, it initiates the HSIC Connect sequence.
59020 + unsigned hsic_connect:1;
59021 + /** This bit overrides and functionally inverts
59022 + * the if_select_hsic input port signal.
59024 + unsigned inv_sel_hsic:1;
59029 + * This union represents the bit fields of the Core ADP Timer, Control and
59030 + * Status Register (ADPTIMCTLSTS). Set the bits using bit fields then write
59031 + * the <i>d32</i> value to the register.
59033 +typedef union adpctl_data {
59034 + /** raw register data */
59036 + /** register bits */
59038 + /** Probe Discharge (PRB_DSCHG)
59039 + * These bits set the times for TADP_DSCHG.
59040 + * These bits are defined as follows:
59043 + * 2'b10 - 16 msec
59044 + * 2'b11 - 32 msec
59046 + unsigned prb_dschg:2;
59047 + /** Probe Delta (PRB_DELTA)
59048 + * These bits set the resolution for RTIM value.
59049 + * The bits are defined in units of 32 kHz clock cycles as follows:
59050 + * 2'b00 - 1 cycles
59051 + * 2'b01 - 2 cycles
59052 + * 2'b10 - 3 cycles
59053 + * 2'b11 - 4 cycles
59054 + * For example if this value is chosen to 2'b01, it means that RTIM
59055 + * increments for every 3(three) 32Khz clock cycles.
59057 + unsigned prb_delta:2;
59058 + /** Probe Period (PRB_PER)
59059 + * These bits sets the TADP_PRD as shown in Figure 4 as follows:
59060 + * 2'b00 - 0.625 to 0.925 sec (typical 0.775 sec)
59061 + * 2'b01 - 1.25 to 1.85 sec (typical 1.55 sec)
59062 + * 2'b10 - 1.9 to 2.6 sec (typical 2.275 sec)
59063 + * 2'b11 - Reserved
59065 + unsigned prb_per:2;
59066 + /** These bits capture the latest time it took for VBUS to ramp from
59067 + * VADP_SINK to VADP_PRB.
59068 + * 0x000 - 1 cycles
59069 + * 0x001 - 2 cycles
59070 + * 0x002 - 3 cycles
59072 + * 0x7FF - 2048 cycles
59073 + * A time of 1024 cycles at 32 kHz corresponds to a time of 32 msec.
59075 + unsigned rtim:11;
59076 + /** Enable Probe (EnaPrb)
59077 + * When programmed to 1'b1, the core performs a probe operation.
59078 + * This bit is valid only if OTG_Ver = 1'b1.
59080 + unsigned enaprb:1;
59081 + /** Enable Sense (EnaSns)
59082 + * When programmed to 1'b1, the core performs a Sense operation.
59083 + * This bit is valid only if OTG_Ver = 1'b1.
59085 + unsigned enasns:1;
59086 + /** ADP Reset (ADPRes)
59087 + * When set, ADP controller is reset.
59088 + * This bit is valid only if OTG_Ver = 1'b1.
59090 + unsigned adpres:1;
59091 + /** ADP Enable (ADPEn)
59092 + * When set, the core performs either ADP probing or sensing
59093 + * based on EnaPrb or EnaSns.
59094 + * This bit is valid only if OTG_Ver = 1'b1.
59096 + unsigned adpen:1;
59097 + /** ADP Probe Interrupt (ADP_PRB_INT)
59098 + * When this bit is set, it means that the VBUS
59099 + * voltage is greater than VADP_PRB or VADP_PRB is reached.
59100 + * This bit is valid only if OTG_Ver = 1'b1.
59102 + unsigned adp_prb_int:1;
59104 + * ADP Sense Interrupt (ADP_SNS_INT)
59105 + * When this bit is set, it means that the VBUS voltage is greater than
59106 + * VADP_SNS value or VADP_SNS is reached.
59107 + * This bit is valid only if OTG_Ver = 1'b1.
59109 + unsigned adp_sns_int:1;
59110 + /** ADP Tomeout Interrupt (ADP_TMOUT_INT)
59111 + * This bit is relevant only for an ADP probe.
59112 + * When this bit is set, it means that the ramp time has
59113 + * completed ie ADPCTL.RTIM has reached its terminal value
59114 + * of 0x7FF. This is a debug feature that allows software
59115 + * to read the ramp time after each cycle.
59116 + * This bit is valid only if OTG_Ver = 1'b1.
59118 + unsigned adp_tmout_int:1;
59119 + /** ADP Probe Interrupt Mask (ADP_PRB_INT_MSK)
59120 + * When this bit is set, it unmasks the interrupt due to ADP_PRB_INT.
59121 + * This bit is valid only if OTG_Ver = 1'b1.
59123 + unsigned adp_prb_int_msk:1;
59124 + /** ADP Sense Interrupt Mask (ADP_SNS_INT_MSK)
59125 + * When this bit is set, it unmasks the interrupt due to ADP_SNS_INT.
59126 + * This bit is valid only if OTG_Ver = 1'b1.
59128 + unsigned adp_sns_int_msk:1;
59129 + /** ADP Timoeout Interrupt Mask (ADP_TMOUT_MSK)
59130 + * When this bit is set, it unmasks the interrupt due to ADP_TMOUT_INT.
59131 + * This bit is valid only if OTG_Ver = 1'b1.
59133 + unsigned adp_tmout_int_msk:1;
59134 + /** Access Request
59135 + * 2'b00 - Read/Write Valid (updated by the core)
59138 + * 2'b00 - Reserved
59142 + unsigned reserved29_31:3;
59146 +////////////////////////////////////////////
59147 +// Device Registers
59149 + * Device Global Registers. <i>Offsets 800h-BFFh</i>
59151 + * The following structures define the size and relative field offsets
59152 + * for the Device Mode Registers.
59154 + * <i>These registers are visible only in Device mode and must not be
59155 + * accessed in Host mode, as the results are unknown.</i>
59157 +typedef struct dwc_otg_dev_global_regs {
59158 + /** Device Configuration Register. <i>Offset 800h</i> */
59159 + volatile uint32_t dcfg;
59160 + /** Device Control Register. <i>Offset: 804h</i> */
59161 + volatile uint32_t dctl;
59162 + /** Device Status Register (Read Only). <i>Offset: 808h</i> */
59163 + volatile uint32_t dsts;
59164 + /** Reserved. <i>Offset: 80Ch</i> */
59166 + /** Device IN Endpoint Common Interrupt Mask
59167 + * Register. <i>Offset: 810h</i> */
59168 + volatile uint32_t diepmsk;
59169 + /** Device OUT Endpoint Common Interrupt Mask
59170 + * Register. <i>Offset: 814h</i> */
59171 + volatile uint32_t doepmsk;
59172 + /** Device All Endpoints Interrupt Register. <i>Offset: 818h</i> */
59173 + volatile uint32_t daint;
59174 + /** Device All Endpoints Interrupt Mask Register. <i>Offset:
59176 + volatile uint32_t daintmsk;
59177 + /** Device IN Token Queue Read Register-1 (Read Only).
59178 + * <i>Offset: 820h</i> */
59179 + volatile uint32_t dtknqr1;
59180 + /** Device IN Token Queue Read Register-2 (Read Only).
59181 + * <i>Offset: 824h</i> */
59182 + volatile uint32_t dtknqr2;
59183 + /** Device VBUS discharge Register. <i>Offset: 828h</i> */
59184 + volatile uint32_t dvbusdis;
59185 + /** Device VBUS Pulse Register. <i>Offset: 82Ch</i> */
59186 + volatile uint32_t dvbuspulse;
59187 + /** Device IN Token Queue Read Register-3 (Read Only). /
59188 + * Device Thresholding control register (Read/Write)
59189 + * <i>Offset: 830h</i> */
59190 + volatile uint32_t dtknqr3_dthrctl;
59191 + /** Device IN Token Queue Read Register-4 (Read Only). /
59192 + * Device IN EPs empty Inr. Mask Register (Read/Write)
59193 + * <i>Offset: 834h</i> */
59194 + volatile uint32_t dtknqr4_fifoemptymsk;
59195 + /** Device Each Endpoint Interrupt Register (Read Only). /
59196 + * <i>Offset: 838h</i> */
59197 + volatile uint32_t deachint;
59198 + /** Device Each Endpoint Interrupt mask Register (Read/Write). /
59199 + * <i>Offset: 83Ch</i> */
59200 + volatile uint32_t deachintmsk;
59201 + /** Device Each In Endpoint Interrupt mask Register (Read/Write). /
59202 + * <i>Offset: 840h</i> */
59203 + volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS];
59204 + /** Device Each Out Endpoint Interrupt mask Register (Read/Write). /
59205 + * <i>Offset: 880h</i> */
59206 + volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS];
59207 +} dwc_otg_device_global_regs_t;
59210 + * This union represents the bit fields in the Device Configuration
59211 + * Register. Read the register into the <i>d32</i> member then
59212 + * set/clear the bits using the <i>b</i>it elements. Write the
59213 + * <i>d32</i> member to the dcfg register.
59215 +typedef union dcfg_data {
59216 + /** raw register data */
59218 + /** register bits */
59220 + /** Device Speed */
59221 + unsigned devspd:2;
59222 + /** Non Zero Length Status OUT Handshake */
59223 + unsigned nzstsouthshk:1;
59224 +#define DWC_DCFG_SEND_STALL 1
59226 + unsigned ena32khzs:1;
59227 + /** Device Addresses */
59228 + unsigned devaddr:7;
59229 + /** Periodic Frame Interval */
59230 + unsigned perfrint:2;
59231 +#define DWC_DCFG_FRAME_INTERVAL_80 0
59232 +#define DWC_DCFG_FRAME_INTERVAL_85 1
59233 +#define DWC_DCFG_FRAME_INTERVAL_90 2
59234 +#define DWC_DCFG_FRAME_INTERVAL_95 3
59236 + /** Enable Device OUT NAK for bulk in DDMA mode */
59237 + unsigned endevoutnak:1;
59239 + unsigned reserved14_17:4;
59240 + /** In Endpoint Mis-match count */
59241 + unsigned epmscnt:5;
59242 + /** Enable Descriptor DMA in Device mode */
59243 + unsigned descdma:1;
59244 + unsigned perschintvl:2;
59245 + unsigned resvalid:6;
59250 + * This union represents the bit fields in the Device Control
59251 + * Register. Read the register into the <i>d32</i> member then
59252 + * set/clear the bits using the <i>b</i>it elements.
59254 +typedef union dctl_data {
59255 + /** raw register data */
59257 + /** register bits */
59259 + /** Remote Wakeup */
59260 + unsigned rmtwkupsig:1;
59261 + /** Soft Disconnect */
59262 + unsigned sftdiscon:1;
59263 + /** Global Non-Periodic IN NAK Status */
59264 + unsigned gnpinnaksts:1;
59265 + /** Global OUT NAK Status */
59266 + unsigned goutnaksts:1;
59267 + /** Test Control */
59268 + unsigned tstctl:3;
59269 + /** Set Global Non-Periodic IN NAK */
59270 + unsigned sgnpinnak:1;
59271 + /** Clear Global Non-Periodic IN NAK */
59272 + unsigned cgnpinnak:1;
59273 + /** Set Global OUT NAK */
59274 + unsigned sgoutnak:1;
59275 + /** Clear Global OUT NAK */
59276 + unsigned cgoutnak:1;
59277 + /** Power-On Programming Done */
59278 + unsigned pwronprgdone:1;
59280 + unsigned reserved:1;
59281 + /** Global Multi Count */
59283 + /** Ignore Frame Number for ISOC EPs */
59284 + unsigned ifrmnum:1;
59285 + /** NAK on Babble */
59286 + unsigned nakonbble:1;
59287 + /** Enable Continue on BNA */
59288 + unsigned encontonbna:1;
59290 + unsigned reserved18_31:14;
59295 + * This union represents the bit fields in the Device Status
59296 + * Register. Read the register into the <i>d32</i> member then
59297 + * set/clear the bits using the <i>b</i>it elements.
59299 +typedef union dsts_data {
59300 + /** raw register data */
59302 + /** register bits */
59304 + /** Suspend Status */
59305 + unsigned suspsts:1;
59306 + /** Enumerated Speed */
59307 + unsigned enumspd:2;
59308 +#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
59309 +#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
59310 +#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2
59311 +#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3
59312 + /** Erratic Error */
59313 + unsigned errticerr:1;
59314 + unsigned reserved4_7:4;
59315 + /** Frame or Microframe Number of the received SOF */
59316 + unsigned soffn:14;
59317 + unsigned reserved22_31:10;
59322 + * This union represents the bit fields in the Device IN EP Interrupt
59323 + * Register and the Device IN EP Common Mask Register.
59325 + * - Read the register into the <i>d32</i> member then set/clear the
59326 + * bits using the <i>b</i>it elements.
59328 +typedef union diepint_data {
59329 + /** raw register data */
59331 + /** register bits */
59333 + /** Transfer complete mask */
59334 + unsigned xfercompl:1;
59335 + /** Endpoint disable mask */
59336 + unsigned epdisabled:1;
59337 + /** AHB Error mask */
59338 + unsigned ahberr:1;
59339 + /** TimeOUT Handshake mask (non-ISOC EPs) */
59340 + unsigned timeout:1;
59341 + /** IN Token received with TxF Empty mask */
59342 + unsigned intktxfemp:1;
59343 + /** IN Token Received with EP mismatch mask */
59344 + unsigned intknepmis:1;
59345 + /** IN Endpoint NAK Effective mask */
59346 + unsigned inepnakeff:1;
59348 + unsigned emptyintr:1;
59350 + unsigned txfifoundrn:1;
59352 + /** BNA Interrupt mask */
59355 + unsigned reserved10_12:3;
59356 + /** BNA Interrupt mask */
59359 + unsigned reserved14_31:18;
59364 + * This union represents the bit fields in the Device IN EP
59365 + * Common/Dedicated Interrupt Mask Register.
59367 +typedef union diepint_data diepmsk_data_t;
59370 + * This union represents the bit fields in the Device OUT EP Interrupt
59371 + * Registerand Device OUT EP Common Interrupt Mask Register.
59373 + * - Read the register into the <i>d32</i> member then set/clear the
59374 + * bits using the <i>b</i>it elements.
59376 +typedef union doepint_data {
59377 + /** raw register data */
59379 + /** register bits */
59381 + /** Transfer complete */
59382 + unsigned xfercompl:1;
59383 + /** Endpoint disable */
59384 + unsigned epdisabled:1;
59386 + unsigned ahberr:1;
59387 + /** Setup Phase Done (contorl EPs) */
59388 + unsigned setup:1;
59389 + /** OUT Token Received when Endpoint Disabled */
59390 + unsigned outtknepdis:1;
59392 + unsigned stsphsercvd:1;
59393 + /** Back-to-Back SETUP Packets Received */
59394 + unsigned back2backsetup:1;
59396 + unsigned reserved7:1;
59397 + /** OUT packet Error */
59398 + unsigned outpkterr:1;
59399 + /** BNA Interrupt */
59402 + unsigned reserved10:1;
59403 + /** Packet Drop Status */
59404 + unsigned pktdrpsts:1;
59405 + /** Babble Interrupt */
59406 + unsigned babble:1;
59407 + /** NAK Interrupt */
59409 + /** NYET Interrupt */
59411 + /** Bit indicating setup packet received */
59414 + unsigned reserved16_31:16;
59419 + * This union represents the bit fields in the Device OUT EP
59420 + * Common/Dedicated Interrupt Mask Register.
59422 +typedef union doepint_data doepmsk_data_t;
59425 + * This union represents the bit fields in the Device All EP Interrupt
59426 + * and Mask Registers.
59427 + * - Read the register into the <i>d32</i> member then set/clear the
59428 + * bits using the <i>b</i>it elements.
59430 +typedef union daint_data {
59431 + /** raw register data */
59433 + /** register bits */
59435 + /** IN Endpoint bits */
59437 + /** OUT Endpoint bits */
59441 + /** IN Endpoint bits */
59442 + unsigned inep0:1;
59443 + unsigned inep1:1;
59444 + unsigned inep2:1;
59445 + unsigned inep3:1;
59446 + unsigned inep4:1;
59447 + unsigned inep5:1;
59448 + unsigned inep6:1;
59449 + unsigned inep7:1;
59450 + unsigned inep8:1;
59451 + unsigned inep9:1;
59452 + unsigned inep10:1;
59453 + unsigned inep11:1;
59454 + unsigned inep12:1;
59455 + unsigned inep13:1;
59456 + unsigned inep14:1;
59457 + unsigned inep15:1;
59458 + /** OUT Endpoint bits */
59459 + unsigned outep0:1;
59460 + unsigned outep1:1;
59461 + unsigned outep2:1;
59462 + unsigned outep3:1;
59463 + unsigned outep4:1;
59464 + unsigned outep5:1;
59465 + unsigned outep6:1;
59466 + unsigned outep7:1;
59467 + unsigned outep8:1;
59468 + unsigned outep9:1;
59469 + unsigned outep10:1;
59470 + unsigned outep11:1;
59471 + unsigned outep12:1;
59472 + unsigned outep13:1;
59473 + unsigned outep14:1;
59474 + unsigned outep15:1;
59479 + * This union represents the bit fields in the Device IN Token Queue
59480 + * Read Registers.
59481 + * - Read the register into the <i>d32</i> member.
59482 + * - READ-ONLY Register
59484 +typedef union dtknq1_data {
59485 + /** raw register data */
59487 + /** register bits */
59489 + /** In Token Queue Write Pointer */
59490 + unsigned intknwptr:5;
59492 + unsigned reserved05_06:2;
59493 + /** write pointer has wrapped. */
59494 + unsigned wrap_bit:1;
59495 + /** EP Numbers of IN Tokens 0 ... 4 */
59496 + unsigned epnums0_5:24;
59501 + * This union represents Threshold control Register
59502 + * - Read and write the register into the <i>d32</i> member.
59503 + * - READ-WRITABLE Register
59505 +typedef union dthrctl_data {
59506 + /** raw register data */
59508 + /** register bits */
59510 + /** non ISO Tx Thr. Enable */
59511 + unsigned non_iso_thr_en:1;
59512 + /** ISO Tx Thr. Enable */
59513 + unsigned iso_thr_en:1;
59514 + /** Tx Thr. Length */
59515 + unsigned tx_thr_len:9;
59516 + /** AHB Threshold ratio */
59517 + unsigned ahb_thr_ratio:2;
59519 + unsigned reserved13_15:3;
59520 + /** Rx Thr. Enable */
59521 + unsigned rx_thr_en:1;
59522 + /** Rx Thr. Length */
59523 + unsigned rx_thr_len:9;
59524 + unsigned reserved26:1;
59525 + /** Arbiter Parking Enable*/
59526 + unsigned arbprken:1;
59528 + unsigned reserved28_31:4;
59533 + * Device Logical IN Endpoint-Specific Registers. <i>Offsets
59536 + * There will be one set of endpoint registers per logical endpoint
59539 + * <i>These registers are visible only in Device mode and must not be
59540 + * accessed in Host mode, as the results are unknown.</i>
59542 +typedef struct dwc_otg_dev_in_ep_regs {
59543 + /** Device IN Endpoint Control Register. <i>Offset:900h +
59544 + * (ep_num * 20h) + 00h</i> */
59545 + volatile uint32_t diepctl;
59546 + /** Reserved. <i>Offset:900h + (ep_num * 20h) + 04h</i> */
59547 + uint32_t reserved04;
59548 + /** Device IN Endpoint Interrupt Register. <i>Offset:900h +
59549 + * (ep_num * 20h) + 08h</i> */
59550 + volatile uint32_t diepint;
59551 + /** Reserved. <i>Offset:900h + (ep_num * 20h) + 0Ch</i> */
59552 + uint32_t reserved0C;
59553 + /** Device IN Endpoint Transfer Size
59554 + * Register. <i>Offset:900h + (ep_num * 20h) + 10h</i> */
59555 + volatile uint32_t dieptsiz;
59556 + /** Device IN Endpoint DMA Address Register. <i>Offset:900h +
59557 + * (ep_num * 20h) + 14h</i> */
59558 + volatile uint32_t diepdma;
59559 + /** Device IN Endpoint Transmit FIFO Status Register. <i>Offset:900h +
59560 + * (ep_num * 20h) + 18h</i> */
59561 + volatile uint32_t dtxfsts;
59562 + /** Device IN Endpoint DMA Buffer Register. <i>Offset:900h +
59563 + * (ep_num * 20h) + 1Ch</i> */
59564 + volatile uint32_t diepdmab;
59565 +} dwc_otg_dev_in_ep_regs_t;
59568 + * Device Logical OUT Endpoint-Specific Registers. <i>Offsets:
59571 + * There will be one set of endpoint registers per logical endpoint
59574 + * <i>These registers are visible only in Device mode and must not be
59575 + * accessed in Host mode, as the results are unknown.</i>
59577 +typedef struct dwc_otg_dev_out_ep_regs {
59578 + /** Device OUT Endpoint Control Register. <i>Offset:B00h +
59579 + * (ep_num * 20h) + 00h</i> */
59580 + volatile uint32_t doepctl;
59581 + /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 04h</i> */
59582 + uint32_t reserved04;
59583 + /** Device OUT Endpoint Interrupt Register. <i>Offset:B00h +
59584 + * (ep_num * 20h) + 08h</i> */
59585 + volatile uint32_t doepint;
59586 + /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 0Ch</i> */
59587 + uint32_t reserved0C;
59588 + /** Device OUT Endpoint Transfer Size Register. <i>Offset:
59589 + * B00h + (ep_num * 20h) + 10h</i> */
59590 + volatile uint32_t doeptsiz;
59591 + /** Device OUT Endpoint DMA Address Register. <i>Offset:B00h
59592 + * + (ep_num * 20h) + 14h</i> */
59593 + volatile uint32_t doepdma;
59594 + /** Reserved. <i>Offset:B00h + * (ep_num * 20h) + 18h</i> */
59596 + /** Device OUT Endpoint DMA Buffer Register. <i>Offset:B00h
59597 + * + (ep_num * 20h) + 1Ch</i> */
59598 + uint32_t doepdmab;
59599 +} dwc_otg_dev_out_ep_regs_t;
59602 + * This union represents the bit fields in the Device EP Control
59603 + * Register. Read the register into the <i>d32</i> member then
59604 + * set/clear the bits using the <i>b</i>it elements.
59606 +typedef union depctl_data {
59607 + /** raw register data */
59609 + /** register bits */
59611 + /** Maximum Packet Size
59613 + * IN/OUT EP0 - 2 bits
59614 + * 2'b00: 64 Bytes
59619 +#define DWC_DEP0CTL_MPS_64 0
59620 +#define DWC_DEP0CTL_MPS_32 1
59621 +#define DWC_DEP0CTL_MPS_16 2
59622 +#define DWC_DEP0CTL_MPS_8 3
59624 + /** Next Endpoint
59626 + * OUT EPn/OUT EP0 - reserved */
59627 + unsigned nextep:4;
59629 + /** USB Active Endpoint */
59630 + unsigned usbactep:1;
59632 + /** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
59633 + * This field contains the PID of the packet going to
59634 + * be received or transmitted on this endpoint. The
59635 + * application should program the PID of the first
59636 + * packet going to be received or transmitted on this
59637 + * endpoint , after the endpoint is
59638 + * activated. Application use the SetD1PID and
59639 + * SetD0PID fields of this register to program either
59642 + * The encoding for this field is
59648 + /** NAK Status */
59649 + unsigned naksts:1;
59651 + /** Endpoint Type
59653 + * 2'b01: Isochronous
59655 + * 2'b11: Interrupt */
59656 + unsigned eptype:2;
59659 + * OUT EPn/OUT EP0
59660 + * IN EPn/IN EP0 - reserved */
59663 + /** Stall Handshake */
59664 + unsigned stall:1;
59666 + /** Tx Fifo Number
59668 + * OUT EPn/OUT EP0 - reserved */
59669 + unsigned txfnum:4;
59675 + /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
59676 + * Writing to this field sets the Endpoint DPID (DPID)
59677 + * field in this register to DATA0. Set Even
59678 + * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
59679 + * Writing to this field sets the Even/Odd
59680 + * (micro)frame (EO_FrNum) field to even (micro)
59683 + unsigned setd0pid:1;
59684 + /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
59685 + * Writing to this field sets the Endpoint DPID (DPID)
59686 + * field in this register to DATA1 Set Odd
59687 + * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
59688 + * Writing to this field sets the Even/Odd
59689 + * (micro)frame (EO_FrNum) field to odd (micro) frame.
59691 + unsigned setd1pid:1;
59693 + /** Endpoint Disable */
59694 + unsigned epdis:1;
59695 + /** Endpoint Enable */
59696 + unsigned epena:1;
59701 + * This union represents the bit fields in the Device EP Transfer
59702 + * Size Register. Read the register into the <i>d32</i> member then
59703 + * set/clear the bits using the <i>b</i>it elements.
59705 +typedef union deptsiz_data {
59706 + /** raw register data */
59708 + /** register bits */
59710 + /** Transfer size */
59711 + unsigned xfersize:19;
59712 +/** Max packet count for EP (pow(2,10)-1) */
59713 +#define MAX_PKT_CNT 1023
59714 + /** Packet Count */
59715 + unsigned pktcnt:10;
59716 + /** Multi Count - Periodic IN endpoints */
59718 + unsigned reserved:1;
59723 + * This union represents the bit fields in the Device EP 0 Transfer
59724 + * Size Register. Read the register into the <i>d32</i> member then
59725 + * set/clear the bits using the <i>b</i>it elements.
59727 +typedef union deptsiz0_data {
59728 + /** raw register data */
59730 + /** register bits */
59732 + /** Transfer size */
59733 + unsigned xfersize:7;
59735 + unsigned reserved7_18:12;
59736 + /** Packet Count */
59737 + unsigned pktcnt:2;
59739 + unsigned reserved21_28:8;
59740 + /**Setup Packet Count (DOEPTSIZ0 Only) */
59741 + unsigned supcnt:2;
59742 + unsigned reserved31;
59744 +} deptsiz0_data_t;
59746 +/////////////////////////////////////////////////
59747 +// DMA Descriptor Specific Structures
59750 +/** Buffer status definitions */
59752 +#define BS_HOST_READY 0x0
59753 +#define BS_DMA_BUSY 0x1
59754 +#define BS_DMA_DONE 0x2
59755 +#define BS_HOST_BUSY 0x3
59757 +/** Receive/Transmit status definitions */
59759 +#define RTS_SUCCESS 0x0
59760 +#define RTS_BUFFLUSH 0x1
59761 +#define RTS_RESERVED 0x2
59762 +#define RTS_BUFERR 0x3
59765 + * This union represents the bit fields in the DMA Descriptor
59766 + * status quadlet. Read the quadlet into the <i>d32</i> member then
59767 + * set/clear the bits using the <i>b</i>it, <i>b_iso_out</i> and
59768 + * <i>b_iso_in</i> elements.
59770 +typedef union dev_dma_desc_sts {
59771 + /** raw register data */
59773 + /** quadlet bits */
59775 + /** Received number of bytes */
59776 + unsigned bytes:16;
59777 + /** NAK bit - only for OUT EPs */
59779 + unsigned reserved17_22:6;
59780 + /** Multiple Transfer - only for OUT EPs */
59782 + /** Setup Packet received - only for OUT EPs */
59784 + /** Interrupt On Complete */
59786 + /** Short Packet */
59790 + /** Receive Status */
59792 + /** Buffer Status */
59796 +//#ifdef DWC_EN_ISOC
59797 + /** iso out quadlet bits */
59799 + /** Received number of bytes */
59800 + unsigned rxbytes:11;
59802 + unsigned reserved11:1;
59803 + /** Frame Number */
59804 + unsigned framenum:11;
59805 + /** Received ISO Data PID */
59807 + /** Interrupt On Complete */
59809 + /** Short Packet */
59813 + /** Receive Status */
59814 + unsigned rxsts:2;
59815 + /** Buffer Status */
59819 + /** iso in quadlet bits */
59821 + /** Transmited number of bytes */
59822 + unsigned txbytes:12;
59823 + /** Frame Number */
59824 + unsigned framenum:11;
59825 + /** Transmited ISO Data PID */
59827 + /** Interrupt On Complete */
59829 + /** Short Packet */
59833 + /** Transmit Status */
59834 + unsigned txsts:2;
59835 + /** Buffer Status */
59838 +//#endif /* DWC_EN_ISOC */
59839 +} dev_dma_desc_sts_t;
59842 + * DMA Descriptor structure
59844 + * DMA Descriptor structure contains two quadlets:
59845 + * Status quadlet and Data buffer pointer.
59847 +typedef struct dwc_otg_dev_dma_desc {
59848 + /** DMA Descriptor status quadlet */
59849 + dev_dma_desc_sts_t status;
59850 + /** DMA Descriptor data buffer pointer */
59852 +} dwc_otg_dev_dma_desc_t;
59855 + * The dwc_otg_dev_if structure contains information needed to manage
59856 + * the DWC_otg controller acting in device mode. It represents the
59857 + * programming view of the device-specific aspects of the controller.
59859 +typedef struct dwc_otg_dev_if {
59860 + /** Pointer to device Global registers.
59861 + * Device Global Registers starting at offset 800h
59863 + dwc_otg_device_global_regs_t *dev_global_regs;
59864 +#define DWC_DEV_GLOBAL_REG_OFFSET 0x800
59867 + * Device Logical IN Endpoint-Specific Registers 900h-AFCh
59869 + dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS];
59870 +#define DWC_DEV_IN_EP_REG_OFFSET 0x900
59871 +#define DWC_EP_REG_OFFSET 0x20
59873 + /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */
59874 + dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS];
59875 +#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00
59877 + /* Device configuration information */
59878 + uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */
59879 + uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */
59880 + uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/
59882 + /** Size of periodic FIFOs (Bytes) */
59883 + uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS];
59885 + /** Size of Tx FIFOs (Bytes) */
59886 + uint16_t tx_fifo_size[MAX_TX_FIFOS];
59888 + /** Thresholding enable flags and length varaiables **/
59889 + uint16_t rx_thr_en;
59890 + uint16_t iso_tx_thr_en;
59891 + uint16_t non_iso_tx_thr_en;
59893 + uint16_t rx_thr_length;
59894 + uint16_t tx_thr_length;
59897 + * Pointers to the DMA Descriptors for EP0 Control
59898 + * transfers (virtual and physical)
59901 + /** 2 descriptors for SETUP packets */
59902 + dwc_dma_t dma_setup_desc_addr[2];
59903 + dwc_otg_dev_dma_desc_t *setup_desc_addr[2];
59905 + /** Pointer to Descriptor with latest SETUP packet */
59906 + dwc_otg_dev_dma_desc_t *psetup;
59908 + /** Index of current SETUP handler descriptor */
59909 + uint32_t setup_desc_index;
59911 + /** Descriptor for Data In or Status In phases */
59912 + dwc_dma_t dma_in_desc_addr;
59913 + dwc_otg_dev_dma_desc_t *in_desc_addr;
59915 + /** Descriptor for Data Out or Status Out phases */
59916 + dwc_dma_t dma_out_desc_addr;
59917 + dwc_otg_dev_dma_desc_t *out_desc_addr;
59919 + /** Setup Packet Detected - if set clear NAK when queueing */
59921 + /** Isoc ep pointer on which incomplete happens */
59924 +} dwc_otg_dev_if_t;
59926 +/////////////////////////////////////////////////
59927 +// Host Mode Register Structures
59930 + * The Host Global Registers structure defines the size and relative
59931 + * field offsets for the Host Mode Global Registers. Host Global
59932 + * Registers offsets 400h-7FFh.
59934 +typedef struct dwc_otg_host_global_regs {
59935 + /** Host Configuration Register. <i>Offset: 400h</i> */
59936 + volatile uint32_t hcfg;
59937 + /** Host Frame Interval Register. <i>Offset: 404h</i> */
59938 + volatile uint32_t hfir;
59939 + /** Host Frame Number / Frame Remaining Register. <i>Offset: 408h</i> */
59940 + volatile uint32_t hfnum;
59941 + /** Reserved. <i>Offset: 40Ch</i> */
59942 + uint32_t reserved40C;
59943 + /** Host Periodic Transmit FIFO/ Queue Status Register. <i>Offset: 410h</i> */
59944 + volatile uint32_t hptxsts;
59945 + /** Host All Channels Interrupt Register. <i>Offset: 414h</i> */
59946 + volatile uint32_t haint;
59947 + /** Host All Channels Interrupt Mask Register. <i>Offset: 418h</i> */
59948 + volatile uint32_t haintmsk;
59949 + /** Host Frame List Base Address Register . <i>Offset: 41Ch</i> */
59950 + volatile uint32_t hflbaddr;
59951 +} dwc_otg_host_global_regs_t;
59954 + * This union represents the bit fields in the Host Configuration Register.
59955 + * Read the register into the <i>d32</i> member then set/clear the bits using
59956 + * the <i>b</i>it elements. Write the <i>d32</i> member to the hcfg register.
59958 +typedef union hcfg_data {
59959 + /** raw register data */
59962 + /** register bits */
59964 + /** FS/LS Phy Clock Select */
59965 + unsigned fslspclksel:2;
59966 +#define DWC_HCFG_30_60_MHZ 0
59967 +#define DWC_HCFG_48_MHZ 1
59968 +#define DWC_HCFG_6_MHZ 2
59970 + /** FS/LS Only Support */
59971 + unsigned fslssupp:1;
59972 + unsigned reserved3_6:4;
59973 + /** Enable 32-KHz Suspend Mode */
59974 + unsigned ena32khzs:1;
59975 + /** Resume Validation Periiod */
59976 + unsigned resvalid:8;
59977 + unsigned reserved16_22:7;
59978 + /** Enable Scatter/gather DMA in Host mode */
59979 + unsigned descdma:1;
59980 + /** Frame List Entries */
59981 + unsigned frlisten:2;
59982 + /** Enable Periodic Scheduling */
59983 + unsigned perschedena:1;
59984 + unsigned reserved27_30:4;
59985 + unsigned modechtimen:1;
59990 + * This union represents the bit fields in the Host Frame Remaing/Number
59993 +typedef union hfir_data {
59994 + /** raw register data */
59997 + /** register bits */
59999 + unsigned frint:16;
60000 + unsigned hfirrldctrl:1;
60001 + unsigned reserved:15;
60006 + * This union represents the bit fields in the Host Frame Remaing/Number
60009 +typedef union hfnum_data {
60010 + /** raw register data */
60013 + /** register bits */
60015 + unsigned frnum:16;
60016 +#define DWC_HFNUM_MAX_FRNUM 0x3FFF
60017 + unsigned frrem:16;
60021 +typedef union hptxsts_data {
60022 + /** raw register data */
60025 + /** register bits */
60027 + unsigned ptxfspcavail:16;
60028 + unsigned ptxqspcavail:8;
60029 + /** Top of the Periodic Transmit Request Queue
60030 + * - bit 24 - Terminate (last entry for the selected channel)
60031 + * - bits 26:25 - Token Type
60032 + * - 2'b00 - Zero length
60034 + * - 2'b10 - Disable
60035 + * - bits 30:27 - Channel Number
60036 + * - bit 31 - Odd/even microframe
60038 + unsigned ptxqtop_terminate:1;
60039 + unsigned ptxqtop_token:2;
60040 + unsigned ptxqtop_chnum:4;
60041 + unsigned ptxqtop_odd:1;
60046 + * This union represents the bit fields in the Host Port Control and Status
60047 + * Register. Read the register into the <i>d32</i> member then set/clear the
60048 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
60049 + * hprt0 register.
60051 +typedef union hprt0_data {
60052 + /** raw register data */
60054 + /** register bits */
60056 + unsigned prtconnsts:1;
60057 + unsigned prtconndet:1;
60058 + unsigned prtena:1;
60059 + unsigned prtenchng:1;
60060 + unsigned prtovrcurract:1;
60061 + unsigned prtovrcurrchng:1;
60062 + unsigned prtres:1;
60063 + unsigned prtsusp:1;
60064 + unsigned prtrst:1;
60065 + unsigned reserved9:1;
60066 + unsigned prtlnsts:2;
60067 + unsigned prtpwr:1;
60068 + unsigned prttstctl:4;
60069 + unsigned prtspd:2;
60070 +#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0
60071 +#define DWC_HPRT0_PRTSPD_FULL_SPEED 1
60072 +#define DWC_HPRT0_PRTSPD_LOW_SPEED 2
60073 + unsigned reserved19_31:13;
60078 + * This union represents the bit fields in the Host All Interrupt
60081 +typedef union haint_data {
60082 + /** raw register data */
60084 + /** register bits */
60102 + unsigned reserved:16;
60106 + unsigned chint:16;
60107 + unsigned reserved:16;
60112 + * This union represents the bit fields in the Host All Interrupt
60115 +typedef union haintmsk_data {
60116 + /** raw register data */
60118 + /** register bits */
60136 + unsigned reserved:16;
60140 + unsigned chint:16;
60141 + unsigned reserved:16;
60143 +} haintmsk_data_t;
60146 + * Host Channel Specific Registers. <i>500h-5FCh</i>
60148 +typedef struct dwc_otg_hc_regs {
60149 + /** Host Channel 0 Characteristic Register. <i>Offset: 500h + (chan_num * 20h) + 00h</i> */
60150 + volatile uint32_t hcchar;
60151 + /** Host Channel 0 Split Control Register. <i>Offset: 500h + (chan_num * 20h) + 04h</i> */
60152 + volatile uint32_t hcsplt;
60153 + /** Host Channel 0 Interrupt Register. <i>Offset: 500h + (chan_num * 20h) + 08h</i> */
60154 + volatile uint32_t hcint;
60155 + /** Host Channel 0 Interrupt Mask Register. <i>Offset: 500h + (chan_num * 20h) + 0Ch</i> */
60156 + volatile uint32_t hcintmsk;
60157 + /** Host Channel 0 Transfer Size Register. <i>Offset: 500h + (chan_num * 20h) + 10h</i> */
60158 + volatile uint32_t hctsiz;
60159 + /** Host Channel 0 DMA Address Register. <i>Offset: 500h + (chan_num * 20h) + 14h</i> */
60160 + volatile uint32_t hcdma;
60161 + volatile uint32_t reserved;
60162 + /** Host Channel 0 DMA Buffer Address Register. <i>Offset: 500h + (chan_num * 20h) + 1Ch</i> */
60163 + volatile uint32_t hcdmab;
60164 +} dwc_otg_hc_regs_t;
60167 + * This union represents the bit fields in the Host Channel Characteristics
60168 + * Register. Read the register into the <i>d32</i> member then set/clear the
60169 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
60170 + * hcchar register.
60172 +typedef union hcchar_data {
60173 + /** raw register data */
60176 + /** register bits */
60178 + /** Maximum packet size in bytes */
60181 + /** Endpoint number */
60182 + unsigned epnum:4;
60184 + /** 0: OUT, 1: IN */
60185 + unsigned epdir:1;
60187 + unsigned reserved:1;
60189 + /** 0: Full/high speed device, 1: Low speed device */
60190 + unsigned lspddev:1;
60192 + /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */
60193 + unsigned eptype:2;
60195 + /** Packets per frame for periodic transfers. 0 is reserved. */
60196 + unsigned multicnt:2;
60198 + /** Device address */
60199 + unsigned devaddr:7;
60202 + * Frame to transmit periodic transaction.
60203 + * 0: even, 1: odd
60205 + unsigned oddfrm:1;
60207 + /** Channel disable */
60208 + unsigned chdis:1;
60210 + /** Channel enable */
60215 +typedef union hcsplt_data {
60216 + /** raw register data */
60219 + /** register bits */
60221 + /** Port Address */
60222 + unsigned prtaddr:7;
60224 + /** Hub Address */
60225 + unsigned hubaddr:7;
60227 + /** Transaction Position */
60228 + unsigned xactpos:2;
60229 +#define DWC_HCSPLIT_XACTPOS_MID 0
60230 +#define DWC_HCSPLIT_XACTPOS_END 1
60231 +#define DWC_HCSPLIT_XACTPOS_BEGIN 2
60232 +#define DWC_HCSPLIT_XACTPOS_ALL 3
60234 + /** Do Complete Split */
60235 + unsigned compsplt:1;
60238 + unsigned reserved:14;
60240 + /** Split Enble */
60241 + unsigned spltena:1;
60246 + * This union represents the bit fields in the Host All Interrupt
60249 +typedef union hcint_data {
60250 + /** raw register data */
60252 + /** register bits */
60254 + /** Transfer Complete */
60255 + unsigned xfercomp:1;
60256 + /** Channel Halted */
60257 + unsigned chhltd:1;
60259 + unsigned ahberr:1;
60260 + /** STALL Response Received */
60261 + unsigned stall:1;
60262 + /** NAK Response Received */
60264 + /** ACK Response Received */
60266 + /** NYET Response Received */
60268 + /** Transaction Err */
60269 + unsigned xacterr:1;
60270 + /** Babble Error */
60271 + unsigned bblerr:1;
60272 + /** Frame Overrun */
60273 + unsigned frmovrun:1;
60274 + /** Data Toggle Error */
60275 + unsigned datatglerr:1;
60276 + /** Buffer Not Available (only for DDMA mode) */
60278 + /** Exessive transaction error (only for DDMA mode) */
60279 + unsigned xcs_xact:1;
60280 + /** Frame List Rollover interrupt */
60281 + unsigned frm_list_roll:1;
60283 + unsigned reserved14_31:18;
60288 + * This union represents the bit fields in the Host Channel Interrupt Mask
60289 + * Register. Read the register into the <i>d32</i> member then set/clear the
60290 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
60291 + * hcintmsk register.
60293 +typedef union hcintmsk_data {
60294 + /** raw register data */
60297 + /** register bits */
60299 + unsigned xfercompl:1;
60300 + unsigned chhltd:1;
60301 + unsigned ahberr:1;
60302 + unsigned stall:1;
60306 + unsigned xacterr:1;
60307 + unsigned bblerr:1;
60308 + unsigned frmovrun:1;
60309 + unsigned datatglerr:1;
60311 + unsigned xcs_xact:1;
60312 + unsigned frm_list_roll:1;
60313 + unsigned reserved14_31:18;
60315 +} hcintmsk_data_t;
60318 + * This union represents the bit fields in the Host Channel Transfer Size
60319 + * Register. Read the register into the <i>d32</i> member then set/clear the
60320 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
60321 + * hcchar register.
60324 +typedef union hctsiz_data {
60325 + /** raw register data */
60328 + /** register bits */
60330 + /** Total transfer size in bytes */
60331 + unsigned xfersize:19;
60333 + /** Data packets to transfer */
60334 + unsigned pktcnt:10;
60337 + * Packet ID for next data packet
60341 + * 3: MDATA (non-Control), SETUP (Control)
60344 +#define DWC_HCTSIZ_DATA0 0
60345 +#define DWC_HCTSIZ_DATA1 2
60346 +#define DWC_HCTSIZ_DATA2 1
60347 +#define DWC_HCTSIZ_MDATA 3
60348 +#define DWC_HCTSIZ_SETUP 3
60350 + /** Do PING protocol when 1 */
60351 + unsigned dopng:1;
60354 + /** register bits */
60356 + /** Scheduling information */
60357 + unsigned schinfo:8;
60359 + /** Number of transfer descriptors.
60362 + * 256 only for HS isochronous endpoint.
60366 + /** Data packets to transfer */
60367 + unsigned reserved16_28:13;
60370 + * Packet ID for next data packet
60374 + * 3: MDATA (non-Control)
60378 + /** Do PING protocol when 1 */
60379 + unsigned dopng:1;
60384 + * This union represents the bit fields in the Host DMA Address
60385 + * Register used in Descriptor DMA mode.
60387 +typedef union hcdma_data {
60388 + /** raw register data */
60390 + /** register bits */
60392 + unsigned reserved0_2:3;
60393 + /** Current Transfer Descriptor. Not used for ISOC */
60395 + /** Start Address of Descriptor List */
60396 + unsigned dma_addr:21;
60401 + * This union represents the bit fields in the DMA Descriptor
60402 + * status quadlet for host mode. Read the quadlet into the <i>d32</i> member then
60403 + * set/clear the bits using the <i>b</i>it elements.
60405 +typedef union host_dma_desc_sts {
60406 + /** raw register data */
60408 + /** quadlet bits */
60410 + /* for non-isochronous */
60412 + /** Number of bytes */
60413 + unsigned n_bytes:17;
60414 + /** QTD offset to jump when Short Packet received - only for IN EPs */
60415 + unsigned qtd_offset:6;
60417 + * Set to request the core to jump to alternate QTD if
60418 + * Short Packet received - only for IN EPs
60420 + unsigned a_qtd:1;
60422 + * Setup Packet bit. When set indicates that buffer contains
60426 + /** Interrupt On Complete */
60428 + /** End of List */
60430 + unsigned reserved27:1;
60431 + /** Rx/Tx Status */
60433 +#define DMA_DESC_STS_PKTERR 1
60434 + unsigned reserved30:1;
60435 + /** Active Bit */
60438 + /* for isochronous */
60440 + /** Number of bytes */
60441 + unsigned n_bytes:12;
60442 + unsigned reserved12_24:13;
60443 + /** Interrupt On Complete */
60445 + unsigned reserved26_27:2;
60446 + /** Rx/Tx Status */
60448 + unsigned reserved30:1;
60449 + /** Active Bit */
60452 +} host_dma_desc_sts_t;
60454 +#define MAX_DMA_DESC_SIZE 131071
60455 +#define MAX_DMA_DESC_NUM_GENERIC 64
60456 +#define MAX_DMA_DESC_NUM_HS_ISOC 256
60457 +#define MAX_FRLIST_EN_NUM 64
60459 + * Host-mode DMA Descriptor structure
60461 + * DMA Descriptor structure contains two quadlets:
60462 + * Status quadlet and Data buffer pointer.
60464 +typedef struct dwc_otg_host_dma_desc {
60465 + /** DMA Descriptor status quadlet */
60466 + host_dma_desc_sts_t status;
60467 + /** DMA Descriptor data buffer pointer */
60469 +} dwc_otg_host_dma_desc_t;
60471 +/** OTG Host Interface Structure.
60473 + * The OTG Host Interface Structure structure contains information
60474 + * needed to manage the DWC_otg controller acting in host mode. It
60475 + * represents the programming view of the host-specific aspects of the
60478 +typedef struct dwc_otg_host_if {
60479 + /** Host Global Registers starting at offset 400h.*/
60480 + dwc_otg_host_global_regs_t *host_global_regs;
60481 +#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400
60483 + /** Host Port 0 Control and Status Register */
60484 + volatile uint32_t *hprt0;
60485 +#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440
60487 + /** Host Channel Specific Registers at offsets 500h-5FCh. */
60488 + dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS];
60489 +#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500
60490 +#define DWC_OTG_CHAN_REGS_OFFSET 0x20
60492 + /* Host configuration information */
60493 + /** Number of Host Channels (range: 1-16) */
60494 + uint8_t num_host_channels;
60495 + /** Periodic EPs supported (0: no, 1: yes) */
60496 + uint8_t perio_eps_supported;
60497 + /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */
60498 + uint16_t perio_tx_fifo_size;
60500 +} dwc_otg_host_if_t;
60503 + * This union represents the bit fields in the Power and Clock Gating Control
60504 + * Register. Read the register into the <i>d32</i> member then set/clear the
60505 + * bits using the <i>b</i>it elements.
60507 +typedef union pcgcctl_data {
60508 + /** raw register data */
60511 + /** register bits */
60514 + unsigned stoppclk:1;
60516 + unsigned gatehclk:1;
60517 + /** Power Clamp */
60518 + unsigned pwrclmp:1;
60519 + /** Reset Power Down Modules */
60520 + unsigned rstpdwnmodule:1;
60522 + unsigned reserved:1;
60523 + /** Enable Sleep Clock Gating (Enbl_L1Gating) */
60524 + unsigned enbl_sleep_gating:1;
60525 + /** PHY In Sleep (PhySleep) */
60526 + unsigned phy_in_sleep:1;
60528 + unsigned deep_sleep:1;
60529 + unsigned resetaftsusp:1;
60530 + unsigned restoremode:1;
60531 + unsigned enbl_extnd_hiber:1;
60532 + unsigned extnd_hiber_pwrclmp:1;
60533 + unsigned extnd_hiber_switch:1;
60534 + unsigned ess_reg_restored:1;
60535 + unsigned prt_clk_sel:2;
60536 + unsigned port_power:1;
60537 + unsigned max_xcvrselect:2;
60538 + unsigned max_termsel:1;
60539 + unsigned mac_dev_addr:7;
60540 + unsigned p2hd_dev_enum_spd:2;
60541 + unsigned p2hd_prt_spd:2;
60542 + unsigned if_dev_mode:1;
60547 + * This union represents the bit fields in the Global Data FIFO Software
60548 + * Configuration Register. Read the register into the <i>d32</i> member then
60549 + * set/clear the bits using the <i>b</i>it elements.
60551 +typedef union gdfifocfg_data {
60552 + /* raw register data */
60554 + /** register bits */
60556 + /** OTG Data FIFO depth */
60557 + unsigned gdfifocfg:16;
60558 + /** Start address of EP info controller */
60559 + unsigned epinfobase:16;
60561 +} gdfifocfg_data_t;
60564 + * This union represents the bit fields in the Global Power Down Register
60565 + * Register. Read the register into the <i>d32</i> member then set/clear the
60566 + * bits using the <i>b</i>it elements.
60568 +typedef union gpwrdn_data {
60569 + /* raw register data */
60572 + /** register bits */
60574 + /** PMU Interrupt Select */
60575 + unsigned pmuintsel:1;
60576 + /** PMU Active */
60577 + unsigned pmuactv:1;
60579 + unsigned restore:1;
60580 + /** Power Down Clamp */
60581 + unsigned pwrdnclmp:1;
60582 + /** Power Down Reset */
60583 + unsigned pwrdnrstn:1;
60584 + /** Power Down Switch */
60585 + unsigned pwrdnswtch:1;
60586 + /** Disable VBUS */
60587 + unsigned dis_vbus:1;
60588 + /** Line State Change */
60589 + unsigned lnstschng:1;
60590 + /** Line state change mask */
60591 + unsigned lnstchng_msk:1;
60592 + /** Reset Detected */
60593 + unsigned rst_det:1;
60594 + /** Reset Detect mask */
60595 + unsigned rst_det_msk:1;
60596 + /** Disconnect Detected */
60597 + unsigned disconn_det:1;
60598 + /** Disconnect Detect mask */
60599 + unsigned disconn_det_msk:1;
60600 + /** Connect Detected*/
60601 + unsigned connect_det:1;
60602 + /** Connect Detected Mask*/
60603 + unsigned connect_det_msk:1;
60604 + /** SRP Detected */
60605 + unsigned srp_det:1;
60606 + /** SRP Detect mask */
60607 + unsigned srp_det_msk:1;
60608 + /** Status Change Interrupt */
60609 + unsigned sts_chngint:1;
60610 + /** Status Change Interrupt Mask */
60611 + unsigned sts_chngint_msk:1;
60612 + /** Line State */
60613 + unsigned linestate:2;
60614 + /** Indicates current mode(status of IDDIG signal) */
60615 + unsigned idsts:1;
60616 + /** B Session Valid signal status*/
60617 + unsigned bsessvld:1;
60618 + /** ADP Event Detected */
60619 + unsigned adp_int:1;
60620 + /** Multi Valued ID pin */
60621 + unsigned mult_val_id_bc:5;
60622 + /** Reserved 24_31 */
60623 + unsigned reserved29_31:3;
60629 +++ b/drivers/usb/host/dwc_otg/test/Makefile
60632 +PERL=/usr/bin/perl
60633 +PL_TESTS=test_sysfs.pl test_mod_param.pl
60640 + @echo Running perl tests
60641 + @for test in $(PL_TESTS); do \
60642 + if $(PERL) ./$$test ; then \
60643 + echo "=======> $$test, PASSED" ; \
60644 + else echo "=======> $$test, FAILED" ; \
60648 +++ b/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm
60650 +package dwc_otg_test;
60655 +use vars qw(@ISA @EXPORT
60656 +$sysfsdir $paramdir $errors $params
60659 +@ISA = qw(Exporter);
60664 +$sysfsdir = "/sys/devices/lm0";
60665 +$paramdir = "/sys/module/dwc_otg";
60670 + NAME => "otg_cap",
60677 + NAME => "dma_enable",
60684 + NAME => "dma_burst_size",
60686 + ENUM => [1, 4, 8, 16, 32, 64, 128, 256],
60691 + NAME => "host_speed",
60698 + NAME => "host_support_fs_ls_low_power",
60705 + NAME => "host_ls_low_power_phy_clk",
60712 + NAME => "dev_speed",
60719 + NAME => "enable_dynamic_fifo",
60726 + NAME => "data_fifo_size",
60733 + NAME => "dev_rx_fifo_size",
60740 + NAME => "dev_nperio_tx_fifo_size",
60747 + NAME => "dev_perio_tx_fifo_size_1",
60754 + NAME => "dev_perio_tx_fifo_size_2",
60761 + NAME => "dev_perio_tx_fifo_size_3",
60768 + NAME => "dev_perio_tx_fifo_size_4",
60775 + NAME => "dev_perio_tx_fifo_size_5",
60782 + NAME => "dev_perio_tx_fifo_size_6",
60789 + NAME => "dev_perio_tx_fifo_size_7",
60796 + NAME => "dev_perio_tx_fifo_size_8",
60803 + NAME => "dev_perio_tx_fifo_size_9",
60810 + NAME => "dev_perio_tx_fifo_size_10",
60817 + NAME => "dev_perio_tx_fifo_size_11",
60824 + NAME => "dev_perio_tx_fifo_size_12",
60831 + NAME => "dev_perio_tx_fifo_size_13",
60838 + NAME => "dev_perio_tx_fifo_size_14",
60845 + NAME => "dev_perio_tx_fifo_size_15",
60852 + NAME => "host_rx_fifo_size",
60859 + NAME => "host_nperio_tx_fifo_size",
60866 + NAME => "host_perio_tx_fifo_size",
60873 + NAME => "max_transfer_size",
60874 + DEFAULT => 65535,
60880 + NAME => "max_packet_count",
60887 + NAME => "host_channels",
60894 + NAME => "dev_endpoints",
60901 + NAME => "phy_type",
60908 + NAME => "phy_utmi_width",
60915 + NAME => "phy_ulpi_ddr",
60929 + unless (m/armv4tl/) {
60930 + warn "# \n# Can't execute on $_. Run on integrator platform.\n# \n";
60939 + my $params = shift;
60940 + print "\nRemoving Module\n";
60941 + system "rmmod dwc_otg";
60942 + print "Loading Module\n";
60943 + if ($params ne "") {
60944 + print "Module Parameters: $params\n";
60946 + if (system("modprobe dwc_otg $params")) {
60947 + warn "Unable to load module\n";
60960 + if (defined $arg) {
60961 + warn "WARNING: $arg\n";
60964 + if ($errors > 0) {
60965 + warn "TEST FAILED with $errors errors\n";
60968 + print "TEST PASSED\n";
60969 + return 0 if (defined $arg);
60988 +++ b/drivers/usb/host/dwc_otg/test/test_mod_param.pl
60990 +#!/usr/bin/perl -w
60992 +# Run this program on the integrator.
60994 +# - Tests module parameter default values.
60995 +# - Tests setting of valid module parameter values via modprobe.
60996 +# - Tests invalid module parameter values.
60997 +# -----------------------------------------------------------------------------
61001 +check_arch() or die;
61006 + my ($param,$expected) = @_;
61007 + my $value = get($param);
61009 + if ($value == $expected) {
61010 + print "$param = $value, okay\n";
61014 + warn "ERROR: value of $param != $expected, $value\n";
61022 + my $param = shift;
61023 + my $tmp = `cat $paramdir/$param`;
61032 + print "\nTesting Module Parameters\n";
61034 + load_module("") or die;
61036 + # Test initial values
61037 + print "\nTesting Default Values\n";
61038 + foreach (@{$params}) {
61039 + test ($_->{NAME}, $_->{DEFAULT});
61043 + print "\nTesting Low Value\n";
61044 + my $cmd_params = "";
61045 + foreach (@{$params}) {
61046 + $cmd_params = $cmd_params . "$_->{NAME}=$_->{LOW} ";
61048 + load_module($cmd_params) or die;
61050 + foreach (@{$params}) {
61051 + test ($_->{NAME}, $_->{LOW});
61054 + # Test high value
61055 + print "\nTesting High Value\n";
61056 + $cmd_params = "";
61057 + foreach (@{$params}) {
61058 + $cmd_params = $cmd_params . "$_->{NAME}=$_->{HIGH} ";
61060 + load_module($cmd_params) or die;
61062 + foreach (@{$params}) {
61063 + test ($_->{NAME}, $_->{HIGH});
61067 + print "\nTesting Enumerated\n";
61068 + foreach (@{$params}) {
61069 + if (defined $_->{ENUM}) {
61071 + foreach $value (@{$_->{ENUM}}) {
61072 + $cmd_params = "$_->{NAME}=$value";
61073 + load_module($cmd_params) or die;
61074 + test ($_->{NAME}, $value);
61079 + # Test Invalid Values
61080 + print "\nTesting Invalid Values\n";
61081 + $cmd_params = "";
61082 + foreach (@{$params}) {
61083 + $cmd_params = $cmd_params . sprintf "$_->{NAME}=%d ", $_->{LOW}-1;
61085 + load_module($cmd_params) or die;
61087 + foreach (@{$params}) {
61088 + test ($_->{NAME}, $_->{DEFAULT});
61091 + $cmd_params = "";
61092 + foreach (@{$params}) {
61093 + $cmd_params = $cmd_params . sprintf "$_->{NAME}=%d ", $_->{HIGH}+1;
61095 + load_module($cmd_params) or die;
61097 + foreach (@{$params}) {
61098 + test ($_->{NAME}, $_->{DEFAULT});
61101 + print "\nTesting Enumerated\n";
61102 + foreach (@{$params}) {
61103 + if (defined $_->{ENUM}) {
61105 + foreach $value (@{$_->{ENUM}}) {
61106 + $value = $value + 1;
61107 + $cmd_params = "$_->{NAME}=$value";
61108 + load_module($cmd_params) or die;
61109 + test ($_->{NAME}, $_->{DEFAULT});
61110 + $value = $value - 2;
61111 + $cmd_params = "$_->{NAME}=$value";
61112 + load_module($cmd_params) or die;
61113 + test ($_->{NAME}, $_->{DEFAULT});
61118 + test_status() or die;
61124 +++ b/drivers/usb/host/dwc_otg/test/test_sysfs.pl
61126 +#!/usr/bin/perl -w
61128 +# Run this program on the integrator
61129 +# - Tests select sysfs attributes.
61130 +# - Todo ... test more attributes, hnp/srp, buspower/bussuspend, etc.
61131 +# -----------------------------------------------------------------------------
61135 +check_arch() or die;
61140 + my ($attr,$expected) = @_;
61141 + my $string = get($attr);
61143 + if ($string eq $expected) {
61144 + printf("$attr = $string, okay\n");
61147 + warn "ERROR: value of $attr != $expected, $string\n";
61155 + my ($reg, $value) = @_;
61156 + system "echo $value > $sysfsdir/$reg";
61162 + my $attr = shift;
61163 + my $string = `cat $sysfsdir/$attr`;
61165 + if ($string =~ m/\s\=\s/) {
61167 + ($tmp, $string) = split /\s=\s/, $string;
61175 + print("\nTesting Sysfs Attributes\n");
61177 + load_module("") or die;
61179 + # Test initial values of regoffset/regvalue/guid/gsnpsid
61180 + print("\nTesting Default Values\n");
61182 + test("regoffset", "0xffffffff");
61183 + test("regvalue", "invalid offset");
61184 + test("guid", "0x12345678"); # this will fail if it has been changed
61185 + test("gsnpsid", "0x4f54200a");
61187 + # Test operation of regoffset/regvalue
61188 + print("\nTesting regoffset\n");
61189 + set('regoffset', '5a5a5a5a');
61190 + test("regoffset", "0xffffffff");
61192 + set('regoffset', '0');
61193 + test("regoffset", "0x00000000");
61195 + set('regoffset', '40000');
61196 + test("regoffset", "0x00000000");
61198 + set('regoffset', '3ffff');
61199 + test("regoffset", "0x0003ffff");
61201 + set('regoffset', '1');
61202 + test("regoffset", "0x00000001");
61204 + print("\nTesting regvalue\n");
61205 + set('regoffset', '3c');
61206 + test("regvalue", "0x12345678");
61207 + set('regvalue', '5a5a5a5a');
61208 + test("regvalue", "0x5a5a5a5a");
61209 + set('regvalue','a5a5a5a5');
61210 + test("regvalue", "0xa5a5a5a5");
61211 + set('guid','12345678');
61213 + # Test HNP Capable
61214 + print("\nTesting HNP Capable bit\n");
61215 + set('hnpcapable', '1');
61216 + test("hnpcapable", "0x1");
61217 + set('hnpcapable','0');
61218 + test("hnpcapable", "0x0");
61220 + set('regoffset','0c');
61222 + my $old = get('gusbcfg');
61223 + print("setting hnpcapable\n");
61224 + set('hnpcapable', '1');
61225 + test("hnpcapable", "0x1");
61226 + test('gusbcfg', sprintf "0x%08x", (oct ($old) | (1<<9)));
61227 + test('regvalue', sprintf "0x%08x", (oct ($old) | (1<<9)));
61229 + $old = get('gusbcfg');
61230 + print("clearing hnpcapable\n");
61231 + set('hnpcapable', '0');
61232 + test("hnpcapable", "0x0");
61233 + test ('gusbcfg', sprintf "0x%08x", oct ($old) & (~(1<<9)));
61234 + test ('regvalue', sprintf "0x%08x", oct ($old) & (~(1<<9)));
61236 + # Test SRP Capable
61237 + print("\nTesting SRP Capable bit\n");
61238 + set('srpcapable', '1');
61239 + test("srpcapable", "0x1");
61240 + set('srpcapable','0');
61241 + test("srpcapable", "0x0");
61243 + set('regoffset','0c');
61245 + $old = get('gusbcfg');
61246 + print("setting srpcapable\n");
61247 + set('srpcapable', '1');
61248 + test("srpcapable", "0x1");
61249 + test('gusbcfg', sprintf "0x%08x", (oct ($old) | (1<<8)));
61250 + test('regvalue', sprintf "0x%08x", (oct ($old) | (1<<8)));
61252 + $old = get('gusbcfg');
61253 + print("clearing srpcapable\n");
61254 + set('srpcapable', '0');
61255 + test("srpcapable", "0x0");
61256 + test('gusbcfg', sprintf "0x%08x", oct ($old) & (~(1<<8)));
61257 + test('regvalue', sprintf "0x%08x", oct ($old) & (~(1<<8)));
61260 + print("\nTesting GGPIO\n");
61261 + set('ggpio','5a5a5a5a');
61262 + test('ggpio','0x5a5a0000');
61263 + set('ggpio','a5a5a5a5');
61264 + test('ggpio','0xa5a50000');
61265 + set('ggpio','11110000');
61266 + test('ggpio','0x11110000');
61267 + set('ggpio','00001111');
61268 + test('ggpio','0x00000000');
61271 + print("\nTesting DEVSPEED\n");
61272 + set('regoffset','800');
61273 + $old = get('regvalue');
61274 + set('devspeed','0');
61275 + test('devspeed','0x0');
61276 + test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3)));
61277 + set('devspeed','1');
61278 + test('devspeed','0x1');
61279 + test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 1));
61280 + set('devspeed','2');
61281 + test('devspeed','0x2');
61282 + test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 2));
61283 + set('devspeed','3');
61284 + test('devspeed','0x3');
61285 + test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 3));
61286 + set('devspeed','4');
61287 + test('devspeed','0x0');
61288 + test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3)));
61289 + set('devspeed','5');
61290 + test('devspeed','0x1');
61291 + test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 1));
61294 + # mode Returns the current mode:0 for device mode1 for host mode Read
61295 + # hnp Initiate the Host Negotiation Protocol. Read returns the status. Read/Write
61296 + # srp Initiate the Session Request Protocol. Read returns the status. Read/Write
61297 + # buspower Get or Set the Power State of the bus (0 - Off or 1 - On) Read/Write
61298 + # bussuspend Suspend the USB bus. Read/Write
61299 + # busconnected Get the connection status of the bus Read
61301 + # gotgctl Get or set the Core Control Status Register. Read/Write
61302 + ## gusbcfg Get or set the Core USB Configuration Register Read/Write
61303 + # grxfsiz Get or set the Receive FIFO Size Register Read/Write
61304 + # gnptxfsiz Get or set the non-periodic Transmit Size Register Read/Write
61305 + # gpvndctl Get or set the PHY Vendor Control Register Read/Write
61306 + ## ggpio Get the value in the lower 16-bits of the General Purpose IO Register or Set the upper 16 bits. Read/Write
61307 + ## guid Get or set the value of the User ID Register Read/Write
61308 + ## gsnpsid Get the value of the Synopsys ID Regester Read
61309 + ## devspeed Get or set the device speed setting in the DCFG register Read/Write
61310 + # enumspeed Gets the device enumeration Speed. Read
61311 + # hptxfsiz Get the value of the Host Periodic Transmit FIFO Read
61312 + # hprt0 Get or Set the value in the Host Port Control and Status Register Read/Write
61314 + test_status("TEST NYI") or die;