1 From 8af8b61bf6b5689af9f29f0e04e57c832dad0406 Mon Sep 17 00:00:00 2001
2 From: Maxime Ripard <maxime@cerno.tech>
3 Date: Fri, 7 Feb 2020 16:01:33 +0100
4 Subject: [PATCH] clk: bcm: rpi: Create a data structure for the clocks
6 So far the driver has really only been providing a single clock, and stored
7 both the data associated to that clock in particular with the data
8 associated to the "controller".
10 Since we will change that in the future, let's decouple the clock data from
13 Cc: Michael Turquette <mturquette@baylibre.com>
14 Cc: linux-clk@vger.kernel.org
15 Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
16 Reviewed-by: Stephen Boyd <sboyd@kernel.org>
17 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
19 drivers/clk/bcm/clk-raspberrypi.c | 40 ++++++++++++++++++++-----------
20 1 file changed, 26 insertions(+), 14 deletions(-)
22 --- a/drivers/clk/bcm/clk-raspberrypi.c
23 +++ b/drivers/clk/bcm/clk-raspberrypi.c
24 @@ -35,11 +35,15 @@ struct raspberrypi_clk {
26 struct rpi_firmware *firmware;
27 struct platform_device *cpufreq;
30 +struct raspberrypi_clk_data {
33 unsigned long min_rate;
34 unsigned long max_rate;
37 + struct raspberrypi_clk *rpi;
41 @@ -83,8 +87,9 @@ static int raspberrypi_clock_property(st
43 static int raspberrypi_fw_pll_is_on(struct clk_hw *hw)
45 - struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
47 + struct raspberrypi_clk_data *data =
48 + container_of(hw, struct raspberrypi_clk_data, hw);
49 + struct raspberrypi_clk *rpi = data->rpi;
53 @@ -101,8 +106,9 @@ static int raspberrypi_fw_pll_is_on(stru
54 static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw,
55 unsigned long parent_rate)
57 - struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
59 + struct raspberrypi_clk_data *data =
60 + container_of(hw, struct raspberrypi_clk_data, hw);
61 + struct raspberrypi_clk *rpi = data->rpi;
65 @@ -119,8 +125,9 @@ static unsigned long raspberrypi_fw_pll_
66 static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,
67 unsigned long parent_rate)
69 - struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
71 + struct raspberrypi_clk_data *data =
72 + container_of(hw, struct raspberrypi_clk_data, hw);
73 + struct raspberrypi_clk *rpi = data->rpi;
74 u32 new_rate = rate / RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
77 @@ -142,13 +149,13 @@ static int raspberrypi_fw_pll_set_rate(s
78 static int raspberrypi_pll_determine_rate(struct clk_hw *hw,
79 struct clk_rate_request *req)
81 - struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
83 + struct raspberrypi_clk_data *data =
84 + container_of(hw, struct raspberrypi_clk_data, hw);
88 /* We can't use req->rate directly as it would overflow */
89 - final_rate = clamp(req->rate, rpi->min_rate, rpi->max_rate);
90 + final_rate = clamp(req->rate, data->min_rate, data->max_rate);
92 div = (u64)final_rate << A2W_PLL_FRAC_BITS;
93 do_div(div, req->best_parent_rate);
94 @@ -173,10 +180,15 @@ static const struct clk_ops raspberrypi_
96 static int raspberrypi_register_pllb(struct raspberrypi_clk *rpi)
98 + struct raspberrypi_clk_data *data;
99 struct clk_init_data init = {};
100 u32 min_rate = 0, max_rate = 0;
103 + data = devm_kzalloc(rpi->dev, sizeof(*data), GFP_KERNEL);
108 /* All of the PLLs derive from the external oscillator. */
109 init.parent_names = (const char *[]){ "osc" };
110 @@ -215,12 +227,12 @@ static int raspberrypi_register_pllb(str
111 dev_info(rpi->dev, "CPU frequency range: min %u, max %u\n",
114 - rpi->min_rate = min_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
115 - rpi->max_rate = max_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
116 + data->min_rate = min_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
117 + data->max_rate = max_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
119 - rpi->pllb.init = &init;
120 + data->hw.init = &init;
122 - return devm_clk_hw_register(rpi->dev, &rpi->pllb);
123 + return devm_clk_hw_register(rpi->dev, &data->hw);
126 static struct clk_fixed_factor raspberrypi_clk_pllb_arm = {