1 From a294de7c4782f91fe724e4e5b05fd99798d50760 Mon Sep 17 00:00:00 2001
2 From: Maxime Ripard <maxime@cerno.tech>
3 Date: Mon, 13 Jan 2020 13:39:20 +0100
4 Subject: [PATCH] drm/vc4: crtc: Add FIFO depth to vc4_crtc_data
6 Not all pixelvalve FIFOs in vc5 have the same depth, so we need to add that
7 to our vc4_crtc_data structure to be able to compute the fill level
10 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
12 drivers/gpu/drm/vc4/vc4_crtc.c | 20 ++++++++++++++++----
13 drivers/gpu/drm/vc4/vc4_drv.h | 3 +++
14 2 files changed, 19 insertions(+), 4 deletions(-)
16 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
17 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
18 @@ -250,11 +250,20 @@ vc4_crtc_update_gamma_lut(struct drm_crt
19 vc4_crtc_lut_load(crtc);
23 -static u32 vc4_get_fifo_full_level(u32 format)
24 +static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format)
26 - static const u32 fifo_len_bytes = 64;
27 + u32 fifo_len_bytes = vc4_crtc->data->fifo_depth;
30 + * Pixels are pulled from the HVS if the number of bytes is
31 + * lower than the FIFO full level.
33 + * The latency of the pixel fetch mechanism is 6 pixels, so we
34 + * need to convert those 6 pixels in bytes, depending on the
35 + * format, and then substract that from the length of the FIFO
36 + * to make sure we never end up in a situation where the FIFO
40 case PV_CONTROL_FORMAT_DSIV_16:
41 case PV_CONTROL_FORMAT_DSIC_16:
42 @@ -369,7 +378,7 @@ static void vc4_crtc_config_pv(struct dr
44 CRTC_WRITE(PV_CONTROL,
45 VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
46 - VC4_SET_FIELD(vc4_get_fifo_full_level(format),
47 + VC4_SET_FIELD(vc4_get_fifo_full_level(vc4_crtc, format),
48 PV_CONTROL_FIFO_LEVEL) |
49 VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
50 PV_CONTROL_CLR_AT_START |
51 @@ -1067,6 +1076,7 @@ static const struct vc4_crtc_data bcm283
52 .hvs_available_channels = BIT(0),
54 .debugfs_name = "crtc0_regs",
56 .pixels_per_clock = 1,
58 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
59 @@ -1078,6 +1088,7 @@ static const struct vc4_crtc_data bcm283
60 .hvs_available_channels = BIT(2),
62 .debugfs_name = "crtc1_regs",
64 .pixels_per_clock = 1,
66 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
67 @@ -1089,6 +1100,7 @@ static const struct vc4_crtc_data bcm283
68 .hvs_available_channels = BIT(1),
70 .debugfs_name = "crtc2_regs",
72 .pixels_per_clock = 1,
74 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
75 --- a/drivers/gpu/drm/vc4/vc4_drv.h
76 +++ b/drivers/gpu/drm/vc4/vc4_drv.h
77 @@ -452,6 +452,9 @@ to_vc4_encoder(struct drm_encoder *encod
80 struct vc4_crtc_data {
81 + /* Depth of the PixelValve FIFO in bytes */
82 + unsigned int fifo_depth;
84 /* Which channels of the HVS can the output source from */
85 unsigned int hvs_available_channels;