1 From 2aa3a92e409ed4ad416eceacef998f0027016a81 Mon Sep 17 00:00:00 2001
2 From: Dom Cobley <popcornmix@gmail.com>
3 Date: Thu, 7 May 2020 18:16:07 +0100
4 Subject: [PATCH] vc4_hdmi_regs: Add Intr2 register block
6 Signed-off-by: Dom Cobley <popcornmix@gmail.com>
8 arch/arm/boot/dts/bcm2711.dtsi | 14 ++++++++++----
9 drivers/gpu/drm/vc4/vc4_hdmi.c | 8 ++++++++
10 drivers/gpu/drm/vc4/vc4_hdmi.h | 2 ++
11 drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 17 +++++++++++++++++
12 4 files changed, 37 insertions(+), 4 deletions(-)
14 --- a/arch/arm/boot/dts/bcm2711.dtsi
15 +++ b/arch/arm/boot/dts/bcm2711.dtsi
33 clocks = <&firmware_clocks 13>;
38 dma-names = "audio-rx";
39 + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
61 clocks = <&firmware_clocks 13>;
65 dma-names = "audio-rx";
66 + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
70 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
71 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
72 @@ -1582,6 +1582,14 @@ static int vc5_hdmi_init_resources(struc
73 if (IS_ERR(vc4_hdmi->dvp_regs))
74 return PTR_ERR(vc4_hdmi->dvp_regs);
76 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr2");
80 + vc4_hdmi->intr2_regs = devm_ioremap(dev, res->start, resource_size(res));
81 + if (IS_ERR(vc4_hdmi->intr2_regs))
82 + return PTR_ERR(vc4_hdmi->intr2_regs);
84 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
87 --- a/drivers/gpu/drm/vc4/vc4_hdmi.h
88 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
89 @@ -140,6 +140,8 @@ struct vc4_hdmi {
90 void __iomem *ram_regs;
92 void __iomem *rm_regs;
94 + void __iomem *intr2_regs;
98 --- a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
99 +++ b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
100 @@ -24,6 +24,7 @@ enum vc4_hdmi_regs {
107 enum vc4_hdmi_field {
108 @@ -148,6 +149,7 @@ struct vc4_hdmi_register {
109 #define VC5_CEC_REG(reg, offset) _VC4_REG(VC5_CEC, reg, offset)
110 #define VC5_CSC_REG(reg, offset) _VC4_REG(VC5_CSC, reg, offset)
111 #define VC5_DVP_REG(reg, offset) _VC4_REG(VC5_DVP, reg, offset)
112 +#define VC5_INTR2_REG(reg, offset) _VC4_REG(VC5_INTR2, reg, offset)
113 #define VC5_PHY_REG(reg, offset) _VC4_REG(VC5_PHY, reg, offset)
114 #define VC5_RAM_REG(reg, offset) _VC4_REG(VC5_RAM, reg, offset)
115 #define VC5_RM_REG(reg, offset) _VC4_REG(VC5_RM, reg, offset)
116 @@ -280,6 +282,12 @@ static const struct vc4_hdmi_register vc
117 VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
118 VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
119 VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
120 + VC5_INTR2_REG(HDMI_CEC_CPU_STATUS, 0x0000),
121 + VC5_INTR2_REG(HDMI_CEC_CPU_SET, 0x0004),
122 + VC5_INTR2_REG(HDMI_CEC_CPU_CLEAR, 0x0008),
123 + VC5_INTR2_REG(HDMI_CEC_CPU_MASK_STATUS, 0x000c),
124 + VC5_INTR2_REG(HDMI_CEC_CPU_MASK_SET, 0x0010),
125 + VC5_INTR2_REG(HDMI_CEC_CPU_MASK_CLEAR, 0x0014),
127 VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
128 VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
129 @@ -356,6 +364,12 @@ static const struct vc4_hdmi_register vc
130 VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
131 VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
132 VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
133 + VC5_INTR2_REG(HDMI_CEC_CPU_STATUS, 0x0000),
134 + VC5_INTR2_REG(HDMI_CEC_CPU_SET, 0x0004),
135 + VC5_INTR2_REG(HDMI_CEC_CPU_CLEAR, 0x0008),
136 + VC5_INTR2_REG(HDMI_CEC_CPU_MASK_STATUS, 0x000c),
137 + VC5_INTR2_REG(HDMI_CEC_CPU_MASK_SET, 0x0010),
138 + VC5_INTR2_REG(HDMI_CEC_CPU_MASK_CLEAR, 0x0014),
140 VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
141 VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
142 @@ -386,6 +400,9 @@ void __iomem *__vc4_hdmi_get_field_base(
144 return hdmi->dvp_regs;
147 + return hdmi->intr2_regs;
150 return hdmi->phy_regs;