1 --- a/arch/mips/include/asm/r4kcache.h
2 +++ b/arch/mips/include/asm/r4kcache.h
4 extern void (*r4k_blast_dcache)(void);
5 extern void (*r4k_blast_icache)(void);
7 +#if defined(CONFIG_BCM47XX) && !defined(CONFIG_CPU_MIPS32_R2)
8 +#include <asm/paccess.h>
9 +#include <linux/ssb/ssb.h>
10 +#define BCM4710_DUMMY_RREG() bcm4710_dummy_rreg()
12 +static inline unsigned long bcm4710_dummy_rreg(void)
14 + return *(volatile unsigned long *)(KSEG1ADDR(SSB_ENUM_BASE));
17 +#define BCM4710_FILL_TLB(addr) bcm4710_fill_tlb((void *)(addr))
19 +static inline unsigned long bcm4710_fill_tlb(void *addr)
21 + return *(unsigned long *)addr;
24 +#define BCM4710_PROTECTED_FILL_TLB(addr) bcm4710_protected_fill_tlb((void *)(addr))
26 +static inline void bcm4710_protected_fill_tlb(void *addr)
29 + get_dbe(x, (unsigned long *)addr);;
33 +#define BCM4710_DUMMY_RREG()
35 +#define BCM4710_FILL_TLB(addr)
36 +#define BCM4710_PROTECTED_FILL_TLB(addr)
40 * This macro return a properly sign-extended address suitable as base address
41 * for indexed cache operations. Two issues here:
42 @@ -61,6 +93,7 @@ static inline void flush_icache_line_ind
44 static inline void flush_dcache_line_indexed(unsigned long addr)
46 + BCM4710_DUMMY_RREG();
47 cache_op(Index_Writeback_Inv_D, addr);
50 @@ -84,11 +117,13 @@ static inline void flush_icache_line(uns
52 static inline void flush_dcache_line(unsigned long addr)
54 + BCM4710_DUMMY_RREG();
55 cache_op(Hit_Writeback_Inv_D, addr);
58 static inline void invalidate_dcache_line(unsigned long addr)
60 + BCM4710_DUMMY_RREG();
61 cache_op(Hit_Invalidate_D, addr);
64 @@ -161,6 +196,7 @@ static inline int protected_flush_icache
66 return protected_cachee_op(Hit_Invalidate_I, addr);
68 + BCM4710_DUMMY_RREG();
69 return protected_cache_op(Hit_Invalidate_I, addr);
72 @@ -174,6 +210,7 @@ static inline int protected_flush_icache
74 static inline int protected_writeback_dcache_line(unsigned long addr)
76 + BCM4710_DUMMY_RREG();
78 return protected_cachee_op(Hit_Writeback_Inv_D, addr);
80 @@ -203,8 +240,51 @@ static inline void invalidate_tcache_pag
81 unroll(times, _cache_op, insn, op, (addr) + (i++ * (lsize))); \
84 +static inline void blast_dcache(void)
86 + unsigned long start = KSEG0;
87 + unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
88 + unsigned long end = (start + dcache_size);
91 + BCM4710_DUMMY_RREG();
92 + cache_op(Index_Writeback_Inv_D, start);
93 + start += current_cpu_data.dcache.linesz;
94 + } while(start < end);
97 +static inline void blast_dcache_page(unsigned long page)
99 + unsigned long start = page;
100 + unsigned long end = start + PAGE_SIZE;
102 + BCM4710_FILL_TLB(start);
104 + BCM4710_DUMMY_RREG();
105 + cache_op(Hit_Writeback_Inv_D, start);
106 + start += current_cpu_data.dcache.linesz;
107 + } while(start < end);
110 +static inline void blast_dcache_page_indexed(unsigned long page)
112 + unsigned long start = page;
113 + unsigned long end = start + PAGE_SIZE;
114 + unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
115 + unsigned long ws_end = current_cpu_data.dcache.ways <<
116 + current_cpu_data.dcache.waybit;
117 + unsigned long ws, addr;
118 + for (ws = 0; ws < ws_end; ws += ws_inc) {
120 + for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
121 + BCM4710_DUMMY_RREG();
122 + cache_op(Index_Writeback_Inv_D, addr);
127 /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
128 -#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra) \
129 +#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra, war) \
130 static inline void extra##blast_##pfx##cache##lsize(void) \
132 unsigned long start = INDEX_BASE; \
133 @@ -214,6 +294,7 @@ static inline void extra##blast_##pfx##c
134 current_cpu_data.desc.waybit; \
135 unsigned long ws, addr; \
138 for (ws = 0; ws < ws_end; ws += ws_inc) \
139 for (addr = start; addr < end; addr += lsize * 32) \
140 cache_unroll(32, kernel_cache, indexop, \
141 @@ -225,6 +306,7 @@ static inline void extra##blast_##pfx##c
142 unsigned long start = page; \
143 unsigned long end = page + PAGE_SIZE; \
147 cache_unroll(32, kernel_cache, hitop, start, lsize); \
148 start += lsize * 32; \
149 @@ -241,32 +323,33 @@ static inline void extra##blast_##pfx##c
150 current_cpu_data.desc.waybit; \
151 unsigned long ws, addr; \
154 for (ws = 0; ws < ws_end; ws += ws_inc) \
155 for (addr = start; addr < end; addr += lsize * 32) \
156 cache_unroll(32, kernel_cache, indexop, \
160 -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
161 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, )
162 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
163 -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
164 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, )
165 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_)
166 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
167 -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
168 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )
169 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
170 -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )
171 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )
172 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
174 -__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
175 -__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
176 -__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
177 -__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
178 -__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
179 -__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
180 +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, , )
181 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, , BCM4710_FILL_TLB(start);)
182 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, , )
183 +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, , )
184 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, , BCM4710_FILL_TLB(start);)
185 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_, BCM4710_FILL_TLB(start);)
186 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, , )
187 +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, , )
188 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, , BCM4710_FILL_TLB(start);)
189 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, , )
190 +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, , )
191 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, , )
192 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, , )
194 +__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, , )
195 +__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, , )
196 +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, , )
197 +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, , )
198 +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, , )
199 +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, , )
201 #define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \
202 static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
203 @@ -291,58 +374,29 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Inde
204 __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
206 /* build blast_xxx_range, protected_blast_xxx_range */
207 -#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra) \
208 +#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra, war, war2) \
209 static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \
212 unsigned long lsize = cpu_##desc##_line_size(); \
213 - unsigned long lsize_2 = lsize * 2; \
214 - unsigned long lsize_3 = lsize * 3; \
215 - unsigned long lsize_4 = lsize * 4; \
216 - unsigned long lsize_5 = lsize * 5; \
217 - unsigned long lsize_6 = lsize * 6; \
218 - unsigned long lsize_7 = lsize * 7; \
219 - unsigned long lsize_8 = lsize * 8; \
220 unsigned long addr = start & ~(lsize - 1); \
221 - unsigned long aend = (end + lsize - 1) & ~(lsize - 1); \
222 - int lines = (aend - addr) / lsize; \
224 - while (lines >= 8) { \
225 - prot##cache_op(hitop, addr); \
226 - prot##cache_op(hitop, addr + lsize); \
227 - prot##cache_op(hitop, addr + lsize_2); \
228 - prot##cache_op(hitop, addr + lsize_3); \
229 - prot##cache_op(hitop, addr + lsize_4); \
230 - prot##cache_op(hitop, addr + lsize_5); \
231 - prot##cache_op(hitop, addr + lsize_6); \
232 - prot##cache_op(hitop, addr + lsize_7); \
237 - if (lines & 0x4) { \
238 - prot##cache_op(hitop, addr); \
239 - prot##cache_op(hitop, addr + lsize); \
240 - prot##cache_op(hitop, addr + lsize_2); \
241 - prot##cache_op(hitop, addr + lsize_3); \
244 + unsigned long aend = (end - 1) & ~(lsize - 1); \
246 - if (lines & 0x2) { \
247 - prot##cache_op(hitop, addr); \
248 - prot##cache_op(hitop, addr + lsize); \
253 - if (lines & 0x1) { \
256 prot##cache_op(hitop, addr); \
257 + if (addr == aend) \
265 -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
266 -__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
267 +__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, , BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
268 +__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, , , )
272 @@ -376,15 +430,15 @@ __BUILD_PROT_BLAST_CACHE_RANGE(d, dcache
273 __BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I)
276 -__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
277 +__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, , , )
278 __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
279 - protected_, loongson2_)
280 -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
281 -__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , )
282 -__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
283 + protected_, loongson2_, , )
284 +__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , , BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
285 +__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , , , )
286 +__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , , , )
287 /* blast_inv_dcache_range */
288 -__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
289 -__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )
290 +__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , , , BCM4710_DUMMY_RREG();)
291 +__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , , , )
293 /* Currently, this is very specific to Loongson-3 */
294 #define __BUILD_BLAST_CACHE_NODE(pfx, desc, indexop, hitop, lsize) \
295 --- a/arch/mips/include/asm/stackframe.h
296 +++ b/arch/mips/include/asm/stackframe.h
301 +#ifdef CONFIG_BCM47XX
308 --- a/arch/mips/kernel/genex.S
309 +++ b/arch/mips/kernel/genex.S
312 #include <asm/thread_info.h>
314 +#ifdef CONFIG_BCM47XX
331 NESTED(except_vec3_generic, 0, sp)
334 +#ifdef CONFIG_BCM47XX
340 @@ -53,6 +69,9 @@ NESTED(except_vec3_r4000, 0, sp)
344 +#ifdef CONFIG_BCM47XX
350 --- a/arch/mips/mm/c-r4k.c
351 +++ b/arch/mips/mm/c-r4k.c
353 #include <asm/dma-coherence.h>
354 #include <asm/mips-cps.h>
356 +/* For enabling BCM4710 cache workarounds */
357 +static int bcm4710 = 0;
360 * Bits describing what cache ops an SMP callback function may perform.
362 @@ -190,6 +193,9 @@ static void r4k_blast_dcache_user_page_s
364 unsigned long dc_lsize = cpu_dcache_line_size();
367 + r4k_blast_dcache_page = blast_dcache_page;
370 r4k_blast_dcache_user_page = (void *)cache_noop;
371 else if (dc_lsize == 16)
372 @@ -208,6 +214,9 @@ static void r4k_blast_dcache_page_indexe
374 unsigned long dc_lsize = cpu_dcache_line_size();
377 + r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
380 r4k_blast_dcache_page_indexed = (void *)cache_noop;
381 else if (dc_lsize == 16)
382 @@ -227,6 +236,9 @@ static void r4k_blast_dcache_setup(void)
384 unsigned long dc_lsize = cpu_dcache_line_size();
387 + r4k_blast_dcache = blast_dcache;
390 r4k_blast_dcache = (void *)cache_noop;
391 else if (dc_lsize == 16)
392 @@ -1818,6 +1830,17 @@ static void coherency_setup(void)
393 * silly idea of putting something else there ...
395 switch (current_cpu_type()) {
396 + case CPU_BMIPS3300:
399 + cm = read_c0_diag();
400 + /* Enable icache */
402 + /* Enable dcache */
410 @@ -1864,6 +1887,15 @@ void r4k_cache_init(void)
411 extern void build_copy_page(void);
412 struct cpuinfo_mips *c = ¤t_cpu_data;
414 + /* Check if special workarounds are required */
415 +#if defined(CONFIG_BCM47XX) && !defined(CONFIG_CPU_MIPS32_R2)
416 + if (current_cpu_data.cputype == CPU_BMIPS32 && (current_cpu_data.processor_id & 0xff) == 0) {
417 + printk("Enabling BCM4710A0 cache workarounds.\n");
426 @@ -1940,7 +1972,15 @@ void r4k_cache_init(void)
428 local_r4k___flush_cache_all(NULL);
430 +#ifdef CONFIG_BCM47XX
432 + static void (*_coherency_setup)(void);
433 + _coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);
434 + _coherency_setup();
439 board_cache_error_setup = r4k_cache_error_setup;
442 --- a/arch/mips/mm/tlbex.c
443 +++ b/arch/mips/mm/tlbex.c
444 @@ -984,6 +984,9 @@ void build_get_pgde32(u32 **p, unsigned
445 uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
446 uasm_i_addu(p, ptr, tmp, ptr);
448 +#ifdef CONFIG_BCM47XX
451 UASM_i_LA_mostly(p, ptr, pgdc);
453 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
454 @@ -1345,6 +1348,9 @@ static void build_r4000_tlb_refill_handl
456 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
458 +# ifdef CONFIG_BCM47XX
461 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
464 @@ -1356,6 +1362,9 @@ static void build_r4000_tlb_refill_handl
465 build_update_entries(&p, K0, K1);
466 build_tlb_write_entry(&p, &l, &r, tlb_random);
468 +#ifdef CONFIG_BCM47XX
471 uasm_i_eret(&p); /* return from trap */
473 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
474 @@ -2056,6 +2065,9 @@ build_r4000_tlbchange_handler_head(u32 *
476 build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
478 +# ifdef CONFIG_BCM47XX
481 build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
484 @@ -2102,6 +2114,9 @@ build_r4000_tlbchange_handler_tail(u32 *
485 build_tlb_write_entry(p, l, r, tlb_indexed);
487 build_restore_work_registers(p);
488 +#ifdef CONFIG_BCM47XX
491 uasm_i_eret(p); /* return from trap */