1 From d135d94b3d1fe599d13e7198d5f502912d694c13 Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jonas.gorski@gmail.com>
3 Date: Sun, 3 Jul 2011 15:00:38 +0200
4 Subject: [PATCH 29/60] MIPS: BCM63XX: Register SPI flash if present
6 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
8 arch/mips/bcm63xx/dev-flash.c | 35 +++++++++++++++++++-
9 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 2 +
10 2 files changed, 33 insertions(+), 2 deletions(-)
12 --- a/arch/mips/bcm63xx/dev-flash.c
13 +++ b/arch/mips/bcm63xx/dev-flash.c
15 #include <linux/mtd/partitions.h>
16 #include <linux/mtd/physmap.h>
17 #include <linux/mtd/spi-nor.h>
18 +#include <linux/of.h>
19 +#include <linux/spi/spi.h>
20 +#include <linux/spi/flash.h>
22 #include <bcm63xx_cpu.h>
23 #include <bcm63xx_dev_flash.h>
24 @@ -66,6 +69,41 @@ void __init bcm63xx_flash_force_phys_bas
25 mtd_resources[0].end = end;
28 +static struct spi_board_info bcm63xx_spi_flash_info[] = {
33 + .max_speed_hz = 781000,
34 + .modalias = "m25p80",
38 +static void bcm63xx_of_update_spi_flash_speed(struct device_node *np,
39 + unsigned int new_hz)
41 + struct property *max_hz;
44 + max_hz = kzalloc(sizeof(*max_hz) + sizeof(*hz), GFP_KERNEL);
48 + max_hz->name = kstrdup("spi-max-frequency", GFP_KERNEL);
49 + if (!max_hz->name) {
54 + max_hz->value = max_hz + 1;
55 + max_hz->length = sizeof(*hz);
58 + *hz = cpu_to_be32(new_hz);
60 + of_update_property(np, max_hz);
63 static int __init bcm63xx_detect_flash_type(void)
66 @@ -73,9 +111,15 @@ static int __init bcm63xx_detect_flash_t
67 switch (bcm63xx_get_cpu_id()) {
69 /* only support serial flash */
70 + bcm63xx_spi_flash_info[0].max_speed_hz = 62500000;
71 return BCM63XX_FLASH_TYPE_SERIAL;
73 val = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
74 + if (val & STRAPBUS_6328_HSSPI_CLK_FAST)
75 + bcm63xx_spi_flash_info[0].max_speed_hz = 33333334;
77 + bcm63xx_spi_flash_info[0].max_speed_hz = 16666667;
79 if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
80 return BCM63XX_FLASH_TYPE_SERIAL;
82 @@ -94,18 +138,31 @@ static int __init bcm63xx_detect_flash_t
83 return BCM63XX_FLASH_TYPE_SERIAL;
85 val = bcm_misc_readl(MISC_STRAPBUS_6362_REG);
86 + if (val & STRAPBUS_6362_HSSPI_CLK_FAST)
87 + bcm63xx_spi_flash_info[0].max_speed_hz = 50000000;
89 + bcm63xx_spi_flash_info[0].max_speed_hz = 20000000;
91 if (val & STRAPBUS_6362_BOOT_SEL_SERIAL)
92 return BCM63XX_FLASH_TYPE_SERIAL;
94 return BCM63XX_FLASH_TYPE_NAND;
96 val = bcm_misc_readl(MISC_STRAPBUS_63268_REG);
97 + if (val & STRAPBUS_63268_HSSPI_CLK_FAST)
98 + bcm63xx_spi_flash_info[0].max_speed_hz = 50000000;
100 + bcm63xx_spi_flash_info[0].max_speed_hz = 20000000;
102 if (val & STRAPBUS_63268_BOOT_SEL_SERIAL)
103 return BCM63XX_FLASH_TYPE_SERIAL;
105 return BCM63XX_FLASH_TYPE_NAND;
107 val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
108 + if (val & STRAPBUS_6368_SPI_CLK_FAST)
109 + bcm63xx_spi_flash_info[0].max_speed_hz = 20000000;
111 switch (val & STRAPBUS_6368_BOOT_SEL_MASK) {
112 case STRAPBUS_6368_BOOT_SEL_NAND:
113 return BCM63XX_FLASH_TYPE_NAND;
114 @@ -177,6 +234,7 @@ void __init bcm63xx_flash_detect(void)
116 int __init bcm63xx_flash_register(void)
118 + struct device_node *np;
121 switch (flash_type) {
122 @@ -196,8 +254,14 @@ int __init bcm63xx_flash_register(void)
124 return platform_device_register(&mtd_dev);
125 case BCM63XX_FLASH_TYPE_SERIAL:
126 - pr_warn("unsupported serial flash detected\n");
128 + np = of_find_compatible_node(NULL, NULL, "jedec,spi-nor");
130 + bcm63xx_of_update_spi_flash_speed(np, bcm63xx_spi_flash_info[0].max_speed_hz);
136 case BCM63XX_FLASH_TYPE_NAND:
137 pr_warn("unsupported NAND flash detected\n");
139 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
140 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
142 #define GPIO_STRAPBUS_REG 0x40
143 #define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
144 #define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1)
145 +#define STRAPBUS_6368_SPI_CLK_FAST (1 << 6)
146 #define STRAPBUS_6368_BOOT_SEL_MASK 0x3
147 #define STRAPBUS_6368_BOOT_SEL_NAND 0
148 #define STRAPBUS_6368_BOOT_SEL_SERIAL 1
149 @@ -1565,6 +1566,7 @@
150 #define IDDQ_CTRL_63268_USBH (1 << 4)
152 #define MISC_STRAPBUS_6328_REG 0x240
153 +#define STRAPBUS_6328_HSSPI_CLK_FAST (1 << 4)
154 #define STRAPBUS_6328_FCVO_SHIFT 7
155 #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
156 #define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 18)