target/linux/bmips/image/lzma-loader/src/cacheops.h

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Cache operations for the cache instruction.
   4  *
   5  * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
   6  * (C) Copyright 1999 Silicon Graphics, Inc.
   7  */
   8 #ifndef __ASM_CACHEOPS_H
   9 #define __ASM_CACHEOPS_H
  10
  11 /*
  12  * Cache Operations available on all MIPS processors with R4000-style caches
  13  */
  14 #define Index_Invalidate_I      0x00
  15 #define Index_Writeback_Inv_D   0x01
  16 #define Index_Load_Tag_I        0x04
  17 #define Index_Load_Tag_D        0x05
  18 #define Index_Store_Tag_I       0x08
  19 #define Index_Store_Tag_D       0x09
  20 #if defined(CONFIG_CPU_LOONGSON2)
  21 #define Hit_Invalidate_I        0x00
  22 #else
  23 #define Hit_Invalidate_I        0x10
  24 #endif
  25 #define Hit_Invalidate_D        0x11
  26 #define Hit_Writeback_Inv_D     0x15
  27
  28 /*
  29  * R4000-specific cacheops
  30  */
  31 #define Create_Dirty_Excl_D     0x0d
  32 #define Fill                    0x14
  33 #define Hit_Writeback_I         0x18
  34 #define Hit_Writeback_D         0x19
  35
  36 /*
  37  * R4000SC and R4400SC-specific cacheops
  38  */
  39 #define Index_Invalidate_SI     0x02
  40 #define Index_Writeback_Inv_SD  0x03
  41 #define Index_Load_Tag_SI       0x06
  42 #define Index_Load_Tag_SD       0x07
  43 #define Index_Store_Tag_SI      0x0A
  44 #define Index_Store_Tag_SD      0x0B
  45 #define Create_Dirty_Excl_SD    0x0f
  46 #define Hit_Invalidate_SI       0x12
  47 #define Hit_Invalidate_SD       0x13
  48 #define Hit_Writeback_Inv_SD    0x17
  49 #define Hit_Writeback_SD        0x1b
  50 #define Hit_Set_Virtual_SI      0x1e
  51 #define Hit_Set_Virtual_SD      0x1f
  52
  53 /*
  54  * R5000-specific cacheops
  55  */
  56 #define R5K_Page_Invalidate_S   0x17
  57
  58 /*
  59  * RM7000-specific cacheops
  60  */
  61 #define Page_Invalidate_T       0x16
  62
  63 /*
  64  * R10000-specific cacheops
  65  *
  66  * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
  67  * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
  68  */
  69 #define Index_Writeback_Inv_S   0x03
  70 #define Index_Load_Tag_S        0x07
  71 #define Index_Store_Tag_S       0x0B
  72 #define Hit_Invalidate_S        0x13
  73 #define Cache_Barrier           0x14
  74 #define Hit_Writeback_Inv_S     0x17
  75 #define Index_Load_Data_I       0x18
  76 #define Index_Load_Data_D       0x19
  77 #define Index_Load_Data_S       0x1b
  78 #define Index_Store_Data_I      0x1c
  79 #define Index_Store_Data_D      0x1d
  80 #define Index_Store_Data_S      0x1f
  81
  82 #endif  /* __ASM_CACHEOPS_H */