target/linux/brcm2708/patches-3.10/0114-dmaengine-Add-support-for-BCM2708.patch

   1 From f7a2665c5c7690e769a6010a88e2aca3477e5b1f Mon Sep 17 00:00:00 2001
   2 From: Florian Meier <florian.meier@koalo.de>
   3 Date: Fri, 22 Nov 2013 14:22:53 +0100
   4 Subject: [PATCH 114/196] dmaengine: Add support for BCM2708
   5
   6 Add support for DMA controller of BCM2708 as used in the Raspberry Pi.
   7 Currently it only supports cyclic DMA.
   8
   9 Signed-off-by: Florian Meier <florian.meier@koalo.de>
  10 ---
  11  drivers/dma/Kconfig             |   6 +
  12  drivers/dma/Makefile            |   1 +
  13  drivers/dma/bcm2708-dmaengine.c | 588 ++++++++++++++++++++++++++++++++++++++++
  14  3 files changed, 595 insertions(+)
  15  create mode 100644 drivers/dma/bcm2708-dmaengine.c
  16
  17 diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
  18 index 0ba5a95..9a99add 100644
  19 --- a/drivers/dma/Kconfig
  20 +++ b/drivers/dma/Kconfig
  21 @@ -305,6 +305,12 @@ config DMA_OMAP
  22         select DMA_ENGINE
  23         select DMA_VIRTUAL_CHANNELS
  24
  25 +config DMA_BCM2708
  26 +       tristate "BCM2708 DMA engine support"
  27 +       depends on MACH_BCM2708
  28 +       select DMA_ENGINE
  29 +       select DMA_VIRTUAL_CHANNELS
  30 +
  31  config MMP_PDMA
  32         bool "MMP PDMA support"
  33         depends on (ARCH_MMP || ARCH_PXA)
  34 diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
  35 index a2b0df5..d0f5b32 100644
  36 --- a/drivers/dma/Makefile
  37 +++ b/drivers/dma/Makefile
  38 @@ -37,4 +37,5 @@ obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
  39  obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
  40  obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
  41  obj-$(CONFIG_DMA_OMAP) += omap-dma.o
  42 +obj-$(CONFIG_DMA_BCM2708) += bcm2708-dmaengine.o
  43  obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
  44 diff --git a/drivers/dma/bcm2708-dmaengine.c b/drivers/dma/bcm2708-dmaengine.c
  45 new file mode 100644
  46 index 0000000..3ba3cec
  47 --- /dev/null
  48 +++ b/drivers/dma/bcm2708-dmaengine.c
  49 @@ -0,0 +1,588 @@
  50 +/*
  51 + * BCM2708 DMA engine support
  52 + *
  53 + * This driver only supports cyclic DMA transfers
  54 + * as needed for the I2S module.
  55 + *
  56 + * Author:      Florian Meier <florian.meier@koalo.de>
  57 + *              Copyright 2013
  58 + *
  59 + * Based on
  60 + *     OMAP DMAengine support by Russell King
  61 + *
  62 + *     BCM2708 DMA Driver
  63 + *     Copyright (C) 2010 Broadcom
  64 + *
  65 + *     Raspberry Pi PCM I2S ALSA Driver
  66 + *     Copyright (c) by Phil Poole 2013
  67 + *
  68 + *     MARVELL MMP Peripheral DMA Driver
  69 + *     Copyright 2012 Marvell International Ltd.
  70 + *
  71 + * This program is free software; you can redistribute it and/or modify
  72 + * it under the terms of the GNU General Public License as published by
  73 + * the Free Software Foundation; either version 2 of the License, or
  74 + * (at your option) any later version.
  75 + *
  76 + * This program is distributed in the hope that it will be useful,
  77 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  78 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  79 + * GNU General Public License for more details.
  80 + */
  81 +#include <linux/dmaengine.h>
  82 +#include <linux/dma-mapping.h>
  83 +#include <linux/err.h>
  84 +#include <linux/init.h>
  85 +#include <linux/interrupt.h>
  86 +#include <linux/list.h>
  87 +#include <linux/module.h>
  88 +#include <linux/platform_device.h>
  89 +#include <linux/slab.h>
  90 +#include <linux/io.h>
  91 +#include <linux/spinlock.h>
  92 +#include <linux/irq.h>
  93 +
  94 +#include "virt-dma.h"
  95 +
  96 +#include <mach/dma.h>
  97 +#include <mach/irqs.h>
  98 +
  99 +struct bcm2708_dmadev {
 100 +       struct dma_device ddev;
 101 +       spinlock_t lock;
 102 +       void __iomem *base;
 103 +       struct device_dma_parameters dma_parms;
 104 +};
 105 +
 106 +struct bcm2708_chan {
 107 +       struct virt_dma_chan vc;
 108 +       struct list_head node;
 109 +
 110 +       struct dma_slave_config cfg;
 111 +       bool cyclic;
 112 +
 113 +       int ch;
 114 +       struct bcm2708_desc *desc;
 115 +
 116 +       void __iomem *chan_base;
 117 +       int irq_number;
 118 +};
 119 +
 120 +struct bcm2708_desc {
 121 +       struct virt_dma_desc vd;
 122 +       enum dma_transfer_direction dir;
 123 +
 124 +       unsigned int control_block_size;
 125 +       struct bcm2708_dma_cb *control_block_base;
 126 +       dma_addr_t control_block_base_phys;
 127 +
 128 +       unsigned frames;
 129 +       size_t size;
 130 +};
 131 +
 132 +#define BCM2708_DMA_DATA_TYPE_S8       1
 133 +#define BCM2708_DMA_DATA_TYPE_S16      2
 134 +#define BCM2708_DMA_DATA_TYPE_S32      4
 135 +#define BCM2708_DMA_DATA_TYPE_S128     16
 136 +
 137 +static inline struct bcm2708_dmadev *to_bcm2708_dma_dev(struct dma_device *d)
 138 +{
 139 +       return container_of(d, struct bcm2708_dmadev, ddev);
 140 +}
 141 +
 142 +static inline struct bcm2708_chan *to_bcm2708_dma_chan(struct dma_chan *c)
 143 +{
 144 +       return container_of(c, struct bcm2708_chan, vc.chan);
 145 +}
 146 +
 147 +static inline struct bcm2708_desc *to_bcm2708_dma_desc(
 148 +               struct dma_async_tx_descriptor *t)
 149 +{
 150 +       return container_of(t, struct bcm2708_desc, vd.tx);
 151 +}
 152 +
 153 +static void bcm2708_dma_desc_free(struct virt_dma_desc *vd)
 154 +{
 155 +       struct bcm2708_desc *desc = container_of(vd, struct bcm2708_desc, vd);
 156 +       dma_free_coherent(desc->vd.tx.chan->device->dev,
 157 +                       desc->control_block_size,
 158 +                       desc->control_block_base,
 159 +                       desc->control_block_base_phys);
 160 +       kfree(desc);
 161 +}
 162 +
 163 +static void bcm2708_dma_start_desc(struct bcm2708_chan *c)
 164 +{
 165 +       struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
 166 +       struct bcm2708_desc *d;
 167 +
 168 +       if (!vd) {
 169 +               c->desc = NULL;
 170 +               return;
 171 +       }
 172 +
 173 +       list_del(&vd->node);
 174 +
 175 +       c->desc = d = to_bcm2708_dma_desc(&vd->tx);
 176 +
 177 +       bcm_dma_start(c->chan_base, d->control_block_base_phys);
 178 +}
 179 +
 180 +static irqreturn_t bcm2708_dma_callback(int irq, void *data)
 181 +{
 182 +       struct bcm2708_chan *c = data;
 183 +       struct bcm2708_desc *d;
 184 +       unsigned long flags;
 185 +
 186 +       spin_lock_irqsave(&c->vc.lock, flags);
 187 +
 188 +       /* Acknowledge interrupt */
 189 +       writel(BCM2708_DMA_INT, c->chan_base + BCM2708_DMA_CS);
 190 +
 191 +       d = c->desc;
 192 +
 193 +       if (d) {
 194 +               /* TODO Only works for cyclic DMA */
 195 +               vchan_cyclic_callback(&d->vd);
 196 +       }
 197 +
 198 +       /* Keep the DMA engine running */
 199 +       dsb(); /* ARM synchronization barrier */
 200 +       writel(BCM2708_DMA_ACTIVE, c->chan_base + BCM2708_DMA_CS);
 201 +
 202 +       spin_unlock_irqrestore(&c->vc.lock, flags);
 203 +
 204 +       return IRQ_HANDLED;
 205 +}
 206 +
 207 +static int bcm2708_dma_alloc_chan_resources(struct dma_chan *chan)
 208 +{
 209 +       struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
 210 +
 211 +       return request_irq(c->irq_number,
 212 +                       bcm2708_dma_callback, 0, "DMA IRQ", c);
 213 +}
 214 +
 215 +static void bcm2708_dma_free_chan_resources(struct dma_chan *chan)
 216 +{
 217 +       struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
 218 +
 219 +       vchan_free_chan_resources(&c->vc);
 220 +       free_irq(c->irq_number, c);
 221 +
 222 +       dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->ch);
 223 +}
 224 +
 225 +static size_t bcm2708_dma_desc_size(struct bcm2708_desc *d)
 226 +{
 227 +       return d->size;
 228 +}
 229 +
 230 +static size_t bcm2708_dma_desc_size_pos(struct bcm2708_desc *d, dma_addr_t addr)
 231 +{
 232 +       unsigned i;
 233 +       size_t size;
 234 +
 235 +       for (size = i = 0; i < d->frames; i++) {
 236 +               struct bcm2708_dma_cb *control_block =
 237 +                       &d->control_block_base[i];
 238 +               size_t this_size = control_block->length;
 239 +               dma_addr_t dma;
 240 +
 241 +               if (d->dir == DMA_DEV_TO_MEM)
 242 +                       dma = control_block->dst;
 243 +               else
 244 +                       dma = control_block->src;
 245 +
 246 +               if (size)
 247 +                       size += this_size;
 248 +               else if (addr >= dma && addr < dma + this_size)
 249 +                       size += dma + this_size - addr;
 250 +       }
 251 +
 252 +       return size;
 253 +}
 254 +
 255 +static enum dma_status bcm2708_dma_tx_status(struct dma_chan *chan,
 256 +       dma_cookie_t cookie, struct dma_tx_state *txstate)
 257 +{
 258 +       struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
 259 +       struct virt_dma_desc *vd;
 260 +       enum dma_status ret;
 261 +       unsigned long flags;
 262 +
 263 +       ret = dma_cookie_status(chan, cookie, txstate);
 264 +       if (ret == DMA_SUCCESS || !txstate)
 265 +               return ret;
 266 +
 267 +       spin_lock_irqsave(&c->vc.lock, flags);
 268 +       vd = vchan_find_desc(&c->vc, cookie);
 269 +       if (vd) {
 270 +               txstate->residue =
 271 +                       bcm2708_dma_desc_size(to_bcm2708_dma_desc(&vd->tx));
 272 +       } else if (c->desc && c->desc->vd.tx.cookie == cookie) {
 273 +               struct bcm2708_desc *d = c->desc;
 274 +               dma_addr_t pos;
 275 +
 276 +               if (d->dir == DMA_MEM_TO_DEV)
 277 +                       pos = readl(c->chan_base + BCM2708_DMA_SOURCE_AD);
 278 +               else if (d->dir == DMA_DEV_TO_MEM)
 279 +                       pos = readl(c->chan_base + BCM2708_DMA_DEST_AD);
 280 +               else
 281 +                       pos = 0;
 282 +
 283 +               txstate->residue = bcm2708_dma_desc_size_pos(d, pos);
 284 +       } else {
 285 +               txstate->residue = 0;
 286 +       }
 287 +
 288 +       spin_unlock_irqrestore(&c->vc.lock, flags);
 289 +
 290 +       return ret;
 291 +}
 292 +
 293 +static void bcm2708_dma_issue_pending(struct dma_chan *chan)
 294 +{
 295 +       struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
 296 +       unsigned long flags;
 297 +
 298 +       c->cyclic = true; /* Nothing else is implemented */
 299 +
 300 +       spin_lock_irqsave(&c->vc.lock, flags);
 301 +       if (vchan_issue_pending(&c->vc) && !c->desc)
 302 +               bcm2708_dma_start_desc(c);
 303 +
 304 +       spin_unlock_irqrestore(&c->vc.lock, flags);
 305 +}
 306 +
 307 +static struct dma_async_tx_descriptor *bcm2708_dma_prep_dma_cyclic(
 308 +       struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
 309 +       size_t period_len, enum dma_transfer_direction direction,
 310 +       unsigned long flags, void *context)
 311 +{
 312 +       struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
 313 +       enum dma_slave_buswidth dev_width;
 314 +       struct bcm2708_desc *d;
 315 +       dma_addr_t dev_addr;
 316 +       unsigned es, sync_type;
 317 +       unsigned frame;
 318 +
 319 +       /* Grab configuration */
 320 +       if (direction == DMA_DEV_TO_MEM) {
 321 +               dev_addr = c->cfg.src_addr;
 322 +               dev_width = c->cfg.src_addr_width;
 323 +               sync_type = BCM2708_DMA_S_DREQ;
 324 +       } else if (direction == DMA_MEM_TO_DEV) {
 325 +               dev_addr = c->cfg.dst_addr;
 326 +               dev_width = c->cfg.dst_addr_width;
 327 +               sync_type = BCM2708_DMA_D_DREQ;
 328 +       } else {
 329 +               dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
 330 +               return NULL;
 331 +       }
 332 +
 333 +       /* Bus width translates to the element size (ES) */
 334 +       switch (dev_width) {
 335 +       case DMA_SLAVE_BUSWIDTH_4_BYTES:
 336 +               es = BCM2708_DMA_DATA_TYPE_S32;
 337 +               break;
 338 +       default:
 339 +               return NULL;
 340 +       }
 341 +
 342 +       /* Now allocate and setup the descriptor. */
 343 +       d = kzalloc(sizeof(*d), GFP_NOWAIT);
 344 +       if (!d)
 345 +               return NULL;
 346 +
 347 +       d->dir = direction;
 348 +       d->frames = buf_len / period_len;
 349 +
 350 +       /* Allocate memory for control blocks */
 351 +       d->control_block_size = d->frames * sizeof(struct bcm2708_dma_cb);
 352 +       d->control_block_base = dma_zalloc_coherent(chan->device->dev,
 353 +                       d->control_block_size, &d->control_block_base_phys,
 354 +                       GFP_NOWAIT);
 355 +
 356 +       if (!d->control_block_base) {
 357 +               kfree(d);
 358 +               return NULL;
 359 +       }
 360 +
 361 +       /*
 362 +        * Iterate over all frames, create a control block
 363 +        * for each frame and link them together.
 364 +        */
 365 +       for (frame = 0; frame < d->frames; frame++) {
 366 +               struct bcm2708_dma_cb *control_block =
 367 +                       &d->control_block_base[frame];
 368 +
 369 +               /* Setup adresses */
 370 +               if (d->dir == DMA_DEV_TO_MEM) {
 371 +                       control_block->info = BCM2708_DMA_D_INC;
 372 +                       control_block->src = dev_addr;
 373 +                       control_block->dst = buf_addr + frame * period_len;
 374 +               } else {
 375 +                       control_block->info = BCM2708_DMA_S_INC;
 376 +                       control_block->src = buf_addr + frame * period_len;
 377 +                       control_block->dst = dev_addr;
 378 +               }
 379 +
 380 +               /* Enable interrupt */
 381 +               control_block->info |= BCM2708_DMA_INT_EN;
 382 +
 383 +               /* Setup synchronization */
 384 +               if (sync_type != 0)
 385 +                       control_block->info |= sync_type;
 386 +
 387 +               /* Setup DREQ channel */
 388 +               if (c->cfg.slave_id != 0)
 389 +                       control_block->info |=
 390 +                               BCM2708_DMA_PER_MAP(c->cfg.slave_id);
 391 +
 392 +               /* Length of a frame */
 393 +               control_block->length = period_len;
 394 +               d->size += control_block->length;
 395 +
 396 +               /*
 397 +                * Next block is the next frame.
 398 +                * This DMA engine driver currently only supports cyclic DMA.
 399 +                * Therefore, wrap around at number of frames.
 400 +                */
 401 +               control_block->next = d->control_block_base_phys +
 402 +                       sizeof(struct bcm2708_dma_cb)
 403 +                       * ((frame + 1) % d->frames);
 404 +       }
 405 +
 406 +       return vchan_tx_prep(&c->vc, &d->vd, flags);
 407 +}
 408 +
 409 +static int bcm2708_dma_slave_config(struct bcm2708_chan *c,
 410 +               struct dma_slave_config *cfg)
 411 +{
 412 +       if ((cfg->direction == DMA_DEV_TO_MEM &&
 413 +            cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
 414 +           (cfg->direction == DMA_MEM_TO_DEV &&
 415 +            cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
 416 +           !is_slave_direction(cfg->direction)) {
 417 +               return -EINVAL;
 418 +       }
 419 +
 420 +       c->cfg = *cfg;
 421 +
 422 +       return 0;
 423 +}
 424 +
 425 +static int bcm2708_dma_terminate_all(struct bcm2708_chan *c)
 426 +{
 427 +       struct bcm2708_dmadev *d = to_bcm2708_dma_dev(c->vc.chan.device);
 428 +       unsigned long flags;
 429 +       int timeout = 10000;
 430 +       LIST_HEAD(head);
 431 +
 432 +       spin_lock_irqsave(&c->vc.lock, flags);
 433 +
 434 +       /* Prevent this channel being scheduled */
 435 +       spin_lock(&d->lock);
 436 +       list_del_init(&c->node);
 437 +       spin_unlock(&d->lock);
 438 +
 439 +       /*
 440 +        * Stop DMA activity: we assume the callback will not be called
 441 +        * after bcm_dma_abort() returns (even if it does, it will see
 442 +        * c->desc is NULL and exit.)
 443 +        */
 444 +       if (c->desc) {
 445 +               c->desc = NULL;
 446 +               bcm_dma_abort(c->chan_base);
 447 +
 448 +               /* Wait for stopping */
 449 +               while (timeout > 0) {
 450 +                       timeout--;
 451 +                       if (!(readl(c->chan_base + BCM2708_DMA_CS) &
 452 +                                               BCM2708_DMA_ACTIVE))
 453 +                               break;
 454 +
 455 +                       cpu_relax();
 456 +               }
 457 +
 458 +               if (timeout <= 0)
 459 +                       dev_err(d->ddev.dev, "DMA transfer could not be terminated\n");
 460 +       }
 461 +
 462 +       vchan_get_all_descriptors(&c->vc, &head);
 463 +       spin_unlock_irqrestore(&c->vc.lock, flags);
 464 +       vchan_dma_desc_free_list(&c->vc, &head);
 465 +
 466 +       return 0;
 467 +}
 468 +
 469 +static int bcm2708_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 470 +       unsigned long arg)
 471 +{
 472 +       struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
 473 +
 474 +       switch (cmd) {
 475 +       case DMA_SLAVE_CONFIG:
 476 +               return bcm2708_dma_slave_config(c,
 477 +                               (struct dma_slave_config *)arg);
 478 +
 479 +       case DMA_TERMINATE_ALL:
 480 +               return bcm2708_dma_terminate_all(c);
 481 +
 482 +       default:
 483 +               return -ENXIO;
 484 +       }
 485 +}
 486 +
 487 +static int bcm2708_dma_chan_init(struct bcm2708_dmadev *d, void __iomem* chan_base,
 488 +                                                                       int chan_id, int irq)
 489 +{
 490 +       struct bcm2708_chan *c;
 491 +
 492 +       c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL);
 493 +       if (!c)
 494 +               return -ENOMEM;
 495 +
 496 +       c->vc.desc_free = bcm2708_dma_desc_free;
 497 +       vchan_init(&c->vc, &d->ddev);
 498 +       INIT_LIST_HEAD(&c->node);
 499 +
 500 +       d->ddev.chancnt++;
 501 +
 502 +       c->chan_base = chan_base;
 503 +       c->ch = chan_id;
 504 +       c->irq_number = irq;
 505 +
 506 +       return 0;
 507 +}
 508 +
 509 +static void bcm2708_dma_free(struct bcm2708_dmadev *od)
 510 +{
 511 +       while (!list_empty(&od->ddev.channels)) {
 512 +               struct bcm2708_chan *c = list_first_entry(&od->ddev.channels,
 513 +                       struct bcm2708_chan, vc.chan.device_node);
 514 +
 515 +               list_del(&c->vc.chan.device_node);
 516 +               tasklet_kill(&c->vc.task);
 517 +       }
 518 +}
 519 +
 520 +static int bcm2708_dma_probe(struct platform_device *pdev)
 521 +{
 522 +       struct bcm2708_dmadev *od;
 523 +       int rc, i;
 524 +
 525 +       if (!pdev->dev.dma_mask)
 526 +               pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
 527 +
 528 +       rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
 529 +       if (rc)
 530 +               return rc;
 531 +       dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
 532 +
 533 +       od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
 534 +       if (!od)
 535 +               return -ENOMEM;
 536 +
 537 +       pdev->dev.dma_parms = &od->dma_parms;
 538 +       dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);
 539 +
 540 +       dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
 541 +       dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
 542 +       od->ddev.device_alloc_chan_resources = bcm2708_dma_alloc_chan_resources;
 543 +       od->ddev.device_free_chan_resources = bcm2708_dma_free_chan_resources;
 544 +       od->ddev.device_tx_status = bcm2708_dma_tx_status;
 545 +       od->ddev.device_issue_pending = bcm2708_dma_issue_pending;
 546 +       od->ddev.device_prep_dma_cyclic = bcm2708_dma_prep_dma_cyclic;
 547 +       od->ddev.device_control = bcm2708_dma_control;
 548 +       od->ddev.dev = &pdev->dev;
 549 +       INIT_LIST_HEAD(&od->ddev.channels);
 550 +       spin_lock_init(&od->lock);
 551 +
 552 +       platform_set_drvdata(pdev, od);
 553 +
 554 +       for (i = 0; i < 16; i++) {
 555 +               void __iomem* chan_base;
 556 +               int chan_id, irq;
 557 +
 558 +               chan_id = bcm_dma_chan_alloc(BCM_DMA_FEATURE_FAST,
 559 +                       &chan_base,
 560 +                       &irq);
 561 +
 562 +               if (chan_id < 0)
 563 +                       break;
 564 +
 565 +               rc = bcm2708_dma_chan_init(od, chan_base, chan_id, irq);
 566 +               if (rc) {
 567 +                       bcm2708_dma_free(od);
 568 +                       return rc;
 569 +               }
 570 +       }
 571 +
 572 +       rc = dma_async_device_register(&od->ddev);
 573 +       if (rc) {
 574 +               dev_err(&pdev->dev,
 575 +                       "Failed to register slave DMA engine device: %d\n", rc);
 576 +               bcm2708_dma_free(od);
 577 +               return rc;
 578 +       }
 579 +
 580 +       dev_dbg(&pdev->dev, "Load BCM2708 DMA engine driver\n");
 581 +
 582 +       return rc;
 583 +}
 584 +
 585 +static int bcm2708_dma_remove(struct platform_device *pdev)
 586 +{
 587 +       struct bcm2708_dmadev *od = platform_get_drvdata(pdev);
 588 +
 589 +       dma_async_device_unregister(&od->ddev);
 590 +       bcm2708_dma_free(od);
 591 +
 592 +       return 0;
 593 +}
 594 +
 595 +static struct platform_driver bcm2708_dma_driver = {
 596 +       .probe  = bcm2708_dma_probe,
 597 +       .remove = bcm2708_dma_remove,
 598 +       .driver = {
 599 +               .name = "bcm2708-dmaengine",
 600 +               .owner = THIS_MODULE,
 601 +       },
 602 +};
 603 +
 604 +static struct platform_device *pdev;
 605 +
 606 +static const struct platform_device_info bcm2708_dma_dev_info = {
 607 +       .name = "bcm2708-dmaengine",
 608 +       .id = -1,
 609 +};
 610 +
 611 +static int bcm2708_dma_init(void)
 612 +{
 613 +       int rc = platform_driver_register(&bcm2708_dma_driver);
 614 +
 615 +       if (rc == 0) {
 616 +               pdev = platform_device_register_full(&bcm2708_dma_dev_info);
 617 +               if (IS_ERR(pdev)) {
 618 +                       platform_driver_unregister(&bcm2708_dma_driver);
 619 +                       rc = PTR_ERR(pdev);
 620 +               }
 621 +       }
 622 +
 623 +       return rc;
 624 +}
 625 +subsys_initcall(bcm2708_dma_init);
 626 +
 627 +static void __exit bcm2708_dma_exit(void)
 628 +{
 629 +       platform_device_unregister(pdev);
 630 +       platform_driver_unregister(&bcm2708_dma_driver);
 631 +}
 632 +module_exit(bcm2708_dma_exit);
 633 +
 634 +MODULE_ALIAS("platform:bcm2708-dma");
 635 +MODULE_DESCRIPTION("BCM2708 DMA engine driver");
 636 +MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
 637 +MODULE_LICENSE("GPL v2");
 638 --
 639 1.9.1
 640