1 From 568b7292b8e7e1fe3d852db8b463d989d06b5adf Mon Sep 17 00:00:00 2001
2 From: Florian Meier <florian.meier@koalo.de>
3 Date: Fri, 22 Nov 2013 14:22:53 +0100
4 Subject: [PATCH 33/54] dmaengine: Add support for BCM2708
6 Add support for DMA controller of BCM2708 as used in the Raspberry Pi.
7 Currently it only supports cyclic DMA.
9 Signed-off-by: Florian Meier <florian.meier@koalo.de>
11 drivers/dma/Kconfig | 6 +
12 drivers/dma/Makefile | 1 +
13 drivers/dma/bcm2708-dmaengine.c | 588 ++++++++++++++++++++++++++++++++++++++++
14 3 files changed, 595 insertions(+)
15 create mode 100644 drivers/dma/bcm2708-dmaengine.c
17 diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
18 index 605b016..edd5842 100644
19 --- a/drivers/dma/Kconfig
20 +++ b/drivers/dma/Kconfig
21 @@ -312,6 +312,12 @@ config DMA_BCM2835
23 select DMA_VIRTUAL_CHANNELS
26 + tristate "BCM2708 DMA engine support"
27 + depends on MACH_BCM2708
29 + select DMA_VIRTUAL_CHANNELS
32 tristate "AM33xx CPPI41 DMA support"
34 diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
35 index a029d0f4..f4d9516 100644
36 --- a/drivers/dma/Makefile
37 +++ b/drivers/dma/Makefile
38 @@ -39,6 +39,7 @@ obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
39 obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
40 obj-$(CONFIG_DMA_OMAP) += omap-dma.o
41 obj-$(CONFIG_DMA_BCM2835) += bcm2835-dma.o
42 +obj-$(CONFIG_DMA_BCM2708) += bcm2708-dmaengine.o
43 obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
44 obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o
45 obj-$(CONFIG_TI_CPPI41) += cppi41.o
46 diff --git a/drivers/dma/bcm2708-dmaengine.c b/drivers/dma/bcm2708-dmaengine.c
48 index 0000000..b244293
50 +++ b/drivers/dma/bcm2708-dmaengine.c
53 + * BCM2708 DMA engine support
55 + * This driver only supports cyclic DMA transfers
56 + * as needed for the I2S module.
58 + * Author: Florian Meier <florian.meier@koalo.de>
62 + * OMAP DMAengine support by Russell King
64 + * BCM2708 DMA Driver
65 + * Copyright (C) 2010 Broadcom
67 + * Raspberry Pi PCM I2S ALSA Driver
68 + * Copyright (c) by Phil Poole 2013
70 + * MARVELL MMP Peripheral DMA Driver
71 + * Copyright 2012 Marvell International Ltd.
73 + * This program is free software; you can redistribute it and/or modify
74 + * it under the terms of the GNU General Public License as published by
75 + * the Free Software Foundation; either version 2 of the License, or
76 + * (at your option) any later version.
78 + * This program is distributed in the hope that it will be useful,
79 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
80 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
81 + * GNU General Public License for more details.
83 +#include <linux/dmaengine.h>
84 +#include <linux/dma-mapping.h>
85 +#include <linux/err.h>
86 +#include <linux/init.h>
87 +#include <linux/interrupt.h>
88 +#include <linux/list.h>
89 +#include <linux/module.h>
90 +#include <linux/platform_device.h>
91 +#include <linux/slab.h>
92 +#include <linux/io.h>
93 +#include <linux/spinlock.h>
94 +#include <linux/irq.h>
96 +#include "virt-dma.h"
98 +#include <mach/dma.h>
99 +#include <mach/irqs.h>
101 +struct bcm2708_dmadev {
102 + struct dma_device ddev;
104 + void __iomem *base;
105 + struct device_dma_parameters dma_parms;
108 +struct bcm2708_chan {
109 + struct virt_dma_chan vc;
110 + struct list_head node;
112 + struct dma_slave_config cfg;
116 + struct bcm2708_desc *desc;
118 + void __iomem *chan_base;
122 +struct bcm2708_desc {
123 + struct virt_dma_desc vd;
124 + enum dma_transfer_direction dir;
126 + unsigned int control_block_size;
127 + struct bcm2708_dma_cb *control_block_base;
128 + dma_addr_t control_block_base_phys;
134 +#define BCM2708_DMA_DATA_TYPE_S8 1
135 +#define BCM2708_DMA_DATA_TYPE_S16 2
136 +#define BCM2708_DMA_DATA_TYPE_S32 4
137 +#define BCM2708_DMA_DATA_TYPE_S128 16
139 +static inline struct bcm2708_dmadev *to_bcm2708_dma_dev(struct dma_device *d)
141 + return container_of(d, struct bcm2708_dmadev, ddev);
144 +static inline struct bcm2708_chan *to_bcm2708_dma_chan(struct dma_chan *c)
146 + return container_of(c, struct bcm2708_chan, vc.chan);
149 +static inline struct bcm2708_desc *to_bcm2708_dma_desc(
150 + struct dma_async_tx_descriptor *t)
152 + return container_of(t, struct bcm2708_desc, vd.tx);
155 +static void bcm2708_dma_desc_free(struct virt_dma_desc *vd)
157 + struct bcm2708_desc *desc = container_of(vd, struct bcm2708_desc, vd);
158 + dma_free_coherent(desc->vd.tx.chan->device->dev,
159 + desc->control_block_size,
160 + desc->control_block_base,
161 + desc->control_block_base_phys);
165 +static void bcm2708_dma_start_desc(struct bcm2708_chan *c)
167 + struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
168 + struct bcm2708_desc *d;
175 + list_del(&vd->node);
177 + c->desc = d = to_bcm2708_dma_desc(&vd->tx);
179 + bcm_dma_start(c->chan_base, d->control_block_base_phys);
182 +static irqreturn_t bcm2708_dma_callback(int irq, void *data)
184 + struct bcm2708_chan *c = data;
185 + struct bcm2708_desc *d;
186 + unsigned long flags;
188 + spin_lock_irqsave(&c->vc.lock, flags);
190 + /* Acknowledge interrupt */
191 + writel(BCM2708_DMA_INT, c->chan_base + BCM2708_DMA_CS);
196 + /* TODO Only works for cyclic DMA */
197 + vchan_cyclic_callback(&d->vd);
200 + /* Keep the DMA engine running */
201 + dsb(); /* ARM synchronization barrier */
202 + writel(BCM2708_DMA_ACTIVE, c->chan_base + BCM2708_DMA_CS);
204 + spin_unlock_irqrestore(&c->vc.lock, flags);
206 + return IRQ_HANDLED;
209 +static int bcm2708_dma_alloc_chan_resources(struct dma_chan *chan)
211 + struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
213 + return request_irq(c->irq_number,
214 + bcm2708_dma_callback, 0, "DMA IRQ", c);
217 +static void bcm2708_dma_free_chan_resources(struct dma_chan *chan)
219 + struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
221 + vchan_free_chan_resources(&c->vc);
222 + free_irq(c->irq_number, c);
224 + dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->ch);
227 +static size_t bcm2708_dma_desc_size(struct bcm2708_desc *d)
232 +static size_t bcm2708_dma_desc_size_pos(struct bcm2708_desc *d, dma_addr_t addr)
237 + for (size = i = 0; i < d->frames; i++) {
238 + struct bcm2708_dma_cb *control_block =
239 + &d->control_block_base[i];
240 + size_t this_size = control_block->length;
243 + if (d->dir == DMA_DEV_TO_MEM)
244 + dma = control_block->dst;
246 + dma = control_block->src;
250 + else if (addr >= dma && addr < dma + this_size)
251 + size += dma + this_size - addr;
257 +static enum dma_status bcm2708_dma_tx_status(struct dma_chan *chan,
258 + dma_cookie_t cookie, struct dma_tx_state *txstate)
260 + struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
261 + struct virt_dma_desc *vd;
262 + enum dma_status ret;
263 + unsigned long flags;
265 + ret = dma_cookie_status(chan, cookie, txstate);
266 + if (ret == DMA_COMPLETE || !txstate)
269 + spin_lock_irqsave(&c->vc.lock, flags);
270 + vd = vchan_find_desc(&c->vc, cookie);
273 + bcm2708_dma_desc_size(to_bcm2708_dma_desc(&vd->tx));
274 + } else if (c->desc && c->desc->vd.tx.cookie == cookie) {
275 + struct bcm2708_desc *d = c->desc;
278 + if (d->dir == DMA_MEM_TO_DEV)
279 + pos = readl(c->chan_base + BCM2708_DMA_SOURCE_AD);
280 + else if (d->dir == DMA_DEV_TO_MEM)
281 + pos = readl(c->chan_base + BCM2708_DMA_DEST_AD);
285 + txstate->residue = bcm2708_dma_desc_size_pos(d, pos);
287 + txstate->residue = 0;
290 + spin_unlock_irqrestore(&c->vc.lock, flags);
295 +static void bcm2708_dma_issue_pending(struct dma_chan *chan)
297 + struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
298 + unsigned long flags;
300 + c->cyclic = true; /* Nothing else is implemented */
302 + spin_lock_irqsave(&c->vc.lock, flags);
303 + if (vchan_issue_pending(&c->vc) && !c->desc)
304 + bcm2708_dma_start_desc(c);
306 + spin_unlock_irqrestore(&c->vc.lock, flags);
309 +static struct dma_async_tx_descriptor *bcm2708_dma_prep_dma_cyclic(
310 + struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
311 + size_t period_len, enum dma_transfer_direction direction,
312 + unsigned long flags, void *context)
314 + struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
315 + enum dma_slave_buswidth dev_width;
316 + struct bcm2708_desc *d;
317 + dma_addr_t dev_addr;
318 + unsigned es, sync_type;
321 + /* Grab configuration */
322 + if (direction == DMA_DEV_TO_MEM) {
323 + dev_addr = c->cfg.src_addr;
324 + dev_width = c->cfg.src_addr_width;
325 + sync_type = BCM2708_DMA_S_DREQ;
326 + } else if (direction == DMA_MEM_TO_DEV) {
327 + dev_addr = c->cfg.dst_addr;
328 + dev_width = c->cfg.dst_addr_width;
329 + sync_type = BCM2708_DMA_D_DREQ;
331 + dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
335 + /* Bus width translates to the element size (ES) */
336 + switch (dev_width) {
337 + case DMA_SLAVE_BUSWIDTH_4_BYTES:
338 + es = BCM2708_DMA_DATA_TYPE_S32;
344 + /* Now allocate and setup the descriptor. */
345 + d = kzalloc(sizeof(*d), GFP_NOWAIT);
349 + d->dir = direction;
350 + d->frames = buf_len / period_len;
352 + /* Allocate memory for control blocks */
353 + d->control_block_size = d->frames * sizeof(struct bcm2708_dma_cb);
354 + d->control_block_base = dma_zalloc_coherent(chan->device->dev,
355 + d->control_block_size, &d->control_block_base_phys,
358 + if (!d->control_block_base) {
364 + * Iterate over all frames, create a control block
365 + * for each frame and link them together.
367 + for (frame = 0; frame < d->frames; frame++) {
368 + struct bcm2708_dma_cb *control_block =
369 + &d->control_block_base[frame];
371 + /* Setup adresses */
372 + if (d->dir == DMA_DEV_TO_MEM) {
373 + control_block->info = BCM2708_DMA_D_INC;
374 + control_block->src = dev_addr;
375 + control_block->dst = buf_addr + frame * period_len;
377 + control_block->info = BCM2708_DMA_S_INC;
378 + control_block->src = buf_addr + frame * period_len;
379 + control_block->dst = dev_addr;
382 + /* Enable interrupt */
383 + control_block->info |= BCM2708_DMA_INT_EN;
385 + /* Setup synchronization */
386 + if (sync_type != 0)
387 + control_block->info |= sync_type;
389 + /* Setup DREQ channel */
390 + if (c->cfg.slave_id != 0)
391 + control_block->info |=
392 + BCM2708_DMA_PER_MAP(c->cfg.slave_id);
394 + /* Length of a frame */
395 + control_block->length = period_len;
396 + d->size += control_block->length;
399 + * Next block is the next frame.
400 + * This DMA engine driver currently only supports cyclic DMA.
401 + * Therefore, wrap around at number of frames.
403 + control_block->next = d->control_block_base_phys +
404 + sizeof(struct bcm2708_dma_cb)
405 + * ((frame + 1) % d->frames);
408 + return vchan_tx_prep(&c->vc, &d->vd, flags);
411 +static int bcm2708_dma_slave_config(struct bcm2708_chan *c,
412 + struct dma_slave_config *cfg)
414 + if ((cfg->direction == DMA_DEV_TO_MEM &&
415 + cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
416 + (cfg->direction == DMA_MEM_TO_DEV &&
417 + cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
418 + !is_slave_direction(cfg->direction)) {
427 +static int bcm2708_dma_terminate_all(struct bcm2708_chan *c)
429 + struct bcm2708_dmadev *d = to_bcm2708_dma_dev(c->vc.chan.device);
430 + unsigned long flags;
431 + int timeout = 10000;
434 + spin_lock_irqsave(&c->vc.lock, flags);
436 + /* Prevent this channel being scheduled */
437 + spin_lock(&d->lock);
438 + list_del_init(&c->node);
439 + spin_unlock(&d->lock);
442 + * Stop DMA activity: we assume the callback will not be called
443 + * after bcm_dma_abort() returns (even if it does, it will see
444 + * c->desc is NULL and exit.)
448 + bcm_dma_abort(c->chan_base);
450 + /* Wait for stopping */
451 + while (timeout > 0) {
453 + if (!(readl(c->chan_base + BCM2708_DMA_CS) &
454 + BCM2708_DMA_ACTIVE))
461 + dev_err(d->ddev.dev, "DMA transfer could not be terminated\n");
464 + vchan_get_all_descriptors(&c->vc, &head);
465 + spin_unlock_irqrestore(&c->vc.lock, flags);
466 + vchan_dma_desc_free_list(&c->vc, &head);
471 +static int bcm2708_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
474 + struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
477 + case DMA_SLAVE_CONFIG:
478 + return bcm2708_dma_slave_config(c,
479 + (struct dma_slave_config *)arg);
481 + case DMA_TERMINATE_ALL:
482 + return bcm2708_dma_terminate_all(c);
489 +static int bcm2708_dma_chan_init(struct bcm2708_dmadev *d, void __iomem* chan_base,
490 + int chan_id, int irq)
492 + struct bcm2708_chan *c;
494 + c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL);
498 + c->vc.desc_free = bcm2708_dma_desc_free;
499 + vchan_init(&c->vc, &d->ddev);
500 + INIT_LIST_HEAD(&c->node);
504 + c->chan_base = chan_base;
506 + c->irq_number = irq;
511 +static void bcm2708_dma_free(struct bcm2708_dmadev *od)
513 + while (!list_empty(&od->ddev.channels)) {
514 + struct bcm2708_chan *c = list_first_entry(&od->ddev.channels,
515 + struct bcm2708_chan, vc.chan.device_node);
517 + list_del(&c->vc.chan.device_node);
518 + tasklet_kill(&c->vc.task);
522 +static int bcm2708_dma_probe(struct platform_device *pdev)
524 + struct bcm2708_dmadev *od;
527 + if (!pdev->dev.dma_mask)
528 + pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
530 + rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
533 + dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
535 + od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
539 + pdev->dev.dma_parms = &od->dma_parms;
540 + dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);
542 + dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
543 + dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
544 + od->ddev.device_alloc_chan_resources = bcm2708_dma_alloc_chan_resources;
545 + od->ddev.device_free_chan_resources = bcm2708_dma_free_chan_resources;
546 + od->ddev.device_tx_status = bcm2708_dma_tx_status;
547 + od->ddev.device_issue_pending = bcm2708_dma_issue_pending;
548 + od->ddev.device_prep_dma_cyclic = bcm2708_dma_prep_dma_cyclic;
549 + od->ddev.device_control = bcm2708_dma_control;
550 + od->ddev.dev = &pdev->dev;
551 + INIT_LIST_HEAD(&od->ddev.channels);
552 + spin_lock_init(&od->lock);
554 + platform_set_drvdata(pdev, od);
556 + for (i = 0; i < 16; i++) {
557 + void __iomem* chan_base;
560 + chan_id = bcm_dma_chan_alloc(BCM_DMA_FEATURE_FAST,
567 + rc = bcm2708_dma_chan_init(od, chan_base, chan_id, irq);
569 + bcm2708_dma_free(od);
574 + rc = dma_async_device_register(&od->ddev);
576 + dev_err(&pdev->dev,
577 + "Failed to register slave DMA engine device: %d\n", rc);
578 + bcm2708_dma_free(od);
582 + dev_dbg(&pdev->dev, "Load BCM2708 DMA engine driver\n");
587 +static int bcm2708_dma_remove(struct platform_device *pdev)
589 + struct bcm2708_dmadev *od = platform_get_drvdata(pdev);
591 + dma_async_device_unregister(&od->ddev);
592 + bcm2708_dma_free(od);
597 +static struct platform_driver bcm2708_dma_driver = {
598 + .probe = bcm2708_dma_probe,
599 + .remove = bcm2708_dma_remove,
601 + .name = "bcm2708-dmaengine",
602 + .owner = THIS_MODULE,
606 +static struct platform_device *pdev;
608 +static const struct platform_device_info bcm2708_dma_dev_info = {
609 + .name = "bcm2708-dmaengine",
613 +static int bcm2708_dma_init(void)
615 + int rc = platform_driver_register(&bcm2708_dma_driver);
618 + pdev = platform_device_register_full(&bcm2708_dma_dev_info);
619 + if (IS_ERR(pdev)) {
620 + platform_driver_unregister(&bcm2708_dma_driver);
621 + rc = PTR_ERR(pdev);
627 +subsys_initcall(bcm2708_dma_init);
629 +static void __exit bcm2708_dma_exit(void)
631 + platform_device_unregister(pdev);
632 + platform_driver_unregister(&bcm2708_dma_driver);
634 +module_exit(bcm2708_dma_exit);
636 +MODULE_ALIAS("platform:bcm2708-dma");
637 +MODULE_DESCRIPTION("BCM2708 DMA engine driver");
638 +MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
639 +MODULE_LICENSE("GPL v2");