1 From 957ccf05060d65da074d019679ec7f486477e412 Mon Sep 17 00:00:00 2001
2 From: Annaliese McDermond <nh6z@nh6z.net>
3 Date: Thu, 21 Mar 2019 17:58:45 -0700
4 Subject: [PATCH 399/806] ASoC: tlv320aic32x4: Model PLL in CCF
6 commit 514b044cba667e4b7c383ec79b42b997e624b91d upstream.
8 Model and manage the on-board PLL as a component in the Core
9 Clock Framework. This should allow us to do some more complex
10 clock management and power control. Also, some of the
11 on-board chip clocks can be exposed to the outside, and this
12 change will make those clocks easier to consume by other
15 Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
16 Signed-off-by: Mark Brown <broonie@kernel.org>
18 sound/soc/codecs/Kconfig | 1 +
19 sound/soc/codecs/Makefile | 2 +-
20 sound/soc/codecs/tlv320aic32x4-clk.c | 323 +++++++++++++++++++++++++++
21 sound/soc/codecs/tlv320aic32x4.c | 195 ++++++++--------
22 sound/soc/codecs/tlv320aic32x4.h | 5 +
23 5 files changed, 431 insertions(+), 95 deletions(-)
24 create mode 100644 sound/soc/codecs/tlv320aic32x4-clk.c
26 --- a/sound/soc/codecs/Kconfig
27 +++ b/sound/soc/codecs/Kconfig
28 @@ -1025,6 +1025,7 @@ config SND_SOC_TLV320AIC31XX
30 config SND_SOC_TLV320AIC32X4
32 + depends on COMMON_CLK
34 config SND_SOC_TLV320AIC32X4_I2C
35 tristate "Texas Instruments TLV320AIC32x4 audio CODECs - I2C"
36 --- a/sound/soc/codecs/Makefile
37 +++ b/sound/soc/codecs/Makefile
38 @@ -182,7 +182,7 @@ snd-soc-tlv320aic23-i2c-objs := tlv320ai
39 snd-soc-tlv320aic23-spi-objs := tlv320aic23-spi.o
40 snd-soc-tlv320aic26-objs := tlv320aic26.o
41 snd-soc-tlv320aic31xx-objs := tlv320aic31xx.o
42 -snd-soc-tlv320aic32x4-objs := tlv320aic32x4.o
43 +snd-soc-tlv320aic32x4-objs := tlv320aic32x4.o tlv320aic32x4-clk.o
44 snd-soc-tlv320aic32x4-i2c-objs := tlv320aic32x4-i2c.o
45 snd-soc-tlv320aic32x4-spi-objs := tlv320aic32x4-spi.o
46 snd-soc-tlv320aic3x-objs := tlv320aic3x.o
48 +++ b/sound/soc/codecs/tlv320aic32x4-clk.c
50 +/* SPDX-License-Identifier: GPL-2.0
52 + * Clock Tree for the Texas Instruments TLV320AIC32x4
54 + * Copyright 2019 Annaliese McDermond
56 + * Author: Annaliese McDermond <nh6z@nh6z.net>
59 +#include <linux/clk-provider.h>
60 +#include <linux/clkdev.h>
61 +#include <linux/regmap.h>
62 +#include <linux/device.h>
64 +#include "tlv320aic32x4.h"
66 +#define to_clk_aic32x4(_hw) container_of(_hw, struct clk_aic32x4, hw)
70 + struct regmap *regmap;
75 + * struct clk_aic32x4_pll_muldiv - Multiplier/divider settings
77 + * @r: first multiplier
78 + * @j: integer part of second multiplier
79 + * @d: decimal part of second multiplier
81 +struct clk_aic32x4_pll_muldiv {
88 +struct aic32x4_clkdesc {
90 + const char * const *parent_names;
91 + unsigned int num_parents;
92 + const struct clk_ops *ops;
96 +static int clk_aic32x4_pll_prepare(struct clk_hw *hw)
98 + struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
100 + return regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
101 + AIC32X4_PLLEN, AIC32X4_PLLEN);
104 +static void clk_aic32x4_pll_unprepare(struct clk_hw *hw)
106 + struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
108 + regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
112 +static int clk_aic32x4_pll_is_prepared(struct clk_hw *hw)
114 + struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
119 + ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val);
123 + return !!(val & AIC32X4_PLLEN);
126 +static int clk_aic32x4_pll_get_muldiv(struct clk_aic32x4 *pll,
127 + struct clk_aic32x4_pll_muldiv *settings)
129 + /* Change to use regmap_bulk_read? */
133 + ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val);
136 + settings->r = val & AIC32X4_PLL_R_MASK;
137 + settings->p = (val & AIC32X4_PLL_P_MASK) >> AIC32X4_PLL_P_SHIFT;
139 + ret = regmap_read(pll->regmap, AIC32X4_PLLJ, &val);
144 + ret = regmap_read(pll->regmap, AIC32X4_PLLDMSB, &val);
147 + settings->d = val << 8;
149 + ret = regmap_read(pll->regmap, AIC32X4_PLLDLSB, &val);
152 + settings->d |= val;
157 +static int clk_aic32x4_pll_set_muldiv(struct clk_aic32x4 *pll,
158 + struct clk_aic32x4_pll_muldiv *settings)
161 + /* Change to use regmap_bulk_write for some if not all? */
163 + ret = regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
164 + AIC32X4_PLL_R_MASK, settings->r);
168 + ret = regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
169 + AIC32X4_PLL_P_MASK,
170 + settings->p << AIC32X4_PLL_P_SHIFT);
174 + ret = regmap_write(pll->regmap, AIC32X4_PLLJ, settings->j);
178 + ret = regmap_write(pll->regmap, AIC32X4_PLLDMSB, (settings->d >> 8));
181 + ret = regmap_write(pll->regmap, AIC32X4_PLLDLSB, (settings->d & 0xff));
188 +static unsigned long clk_aic32x4_pll_calc_rate(
189 + struct clk_aic32x4_pll_muldiv *settings,
190 + unsigned long parent_rate)
194 + * We scale j by 10000 to account for the decimal part of P and divide
195 + * it back out later.
197 + rate = (u64) parent_rate * settings->r *
198 + ((settings->j * 10000) + settings->d);
200 + return (unsigned long) DIV_ROUND_UP_ULL(rate, settings->p * 10000);
203 +static int clk_aic32x4_pll_calc_muldiv(struct clk_aic32x4_pll_muldiv *settings,
204 + unsigned long rate, unsigned long parent_rate)
208 + settings->p = parent_rate / AIC32X4_MAX_PLL_CLKIN + 1;
209 + if (settings->p > 8)
213 + * We scale this figure by 10000 so that we can get the decimal part
214 + * of the multiplier. This is because we can't do floating point
215 + * math in the kernel.
217 + multiplier = (u64) rate * settings->p * 10000;
218 + do_div(multiplier, parent_rate);
221 + * J can't be over 64, so R can scale this.
222 + * R can't be greater than 4.
224 + settings->r = ((u32) multiplier / 640000) + 1;
225 + if (settings->r > 4)
227 + do_div(multiplier, settings->r);
232 + if (multiplier < 10000)
235 + /* Figure out the integer part, J, and the fractional part, D. */
236 + settings->j = (u32) multiplier / 10000;
237 + settings->d = (u32) multiplier % 10000;
242 +static unsigned long clk_aic32x4_pll_recalc_rate(struct clk_hw *hw,
243 + unsigned long parent_rate)
245 + struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
246 + struct clk_aic32x4_pll_muldiv settings;
249 + ret = clk_aic32x4_pll_get_muldiv(pll, &settings);
253 + return clk_aic32x4_pll_calc_rate(&settings, parent_rate);
256 +static long clk_aic32x4_pll_round_rate(struct clk_hw *hw,
257 + unsigned long rate,
258 + unsigned long *parent_rate)
260 + struct clk_aic32x4_pll_muldiv settings;
263 + ret = clk_aic32x4_pll_calc_muldiv(&settings, rate, *parent_rate);
267 + return clk_aic32x4_pll_calc_rate(&settings, *parent_rate);
270 +static int clk_aic32x4_pll_set_rate(struct clk_hw *hw,
271 + unsigned long rate,
272 + unsigned long parent_rate)
274 + struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
275 + struct clk_aic32x4_pll_muldiv settings;
278 + ret = clk_aic32x4_pll_calc_muldiv(&settings, rate, parent_rate);
282 + return clk_aic32x4_pll_set_muldiv(pll, &settings);
285 +static int clk_aic32x4_pll_set_parent(struct clk_hw *hw, u8 index)
287 + struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
289 + return regmap_update_bits(pll->regmap,
291 + AIC32X4_PLL_CLKIN_MASK,
292 + index << AIC32X4_PLL_CLKIN_SHIFT);
295 +static u8 clk_aic32x4_pll_get_parent(struct clk_hw *hw)
297 + struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
300 + regmap_read(pll->regmap, AIC32X4_PLLPR, &val);
302 + return (val & AIC32X4_PLL_CLKIN_MASK) >> AIC32X4_PLL_CLKIN_SHIFT;
306 +static const struct clk_ops aic32x4_pll_ops = {
307 + .prepare = clk_aic32x4_pll_prepare,
308 + .unprepare = clk_aic32x4_pll_unprepare,
309 + .is_prepared = clk_aic32x4_pll_is_prepared,
310 + .recalc_rate = clk_aic32x4_pll_recalc_rate,
311 + .round_rate = clk_aic32x4_pll_round_rate,
312 + .set_rate = clk_aic32x4_pll_set_rate,
313 + .set_parent = clk_aic32x4_pll_set_parent,
314 + .get_parent = clk_aic32x4_pll_get_parent,
317 +static struct aic32x4_clkdesc aic32x4_clkdesc_array[] = {
321 + (const char* []) { "mclk", "bclk", "gpio", "din" },
323 + .ops = &aic32x4_pll_ops,
328 +static struct clk *aic32x4_register_clk(struct device *dev,
329 + struct aic32x4_clkdesc *desc)
331 + struct clk_init_data init;
332 + struct clk_aic32x4 *priv;
333 + const char *devname = dev_name(dev);
335 + init.ops = desc->ops;
336 + init.name = desc->name;
337 + init.parent_names = desc->parent_names;
338 + init.num_parents = desc->num_parents;
341 + priv = devm_kzalloc(dev, sizeof(struct clk_aic32x4), GFP_KERNEL);
343 + return (struct clk *) -ENOMEM;
346 + priv->hw.init = &init;
347 + priv->regmap = dev_get_regmap(dev, NULL);
348 + priv->reg = desc->reg;
350 + clk_hw_register_clkdev(&priv->hw, desc->name, devname);
351 + return devm_clk_register(dev, &priv->hw);
354 +int aic32x4_register_clocks(struct device *dev, const char *mclk_name)
359 + * These lines are here to preserve the current functionality of
360 + * the driver with regard to the DT. These should eventually be set
361 + * by DT nodes so that the connections can be set up in configuration
362 + * rather than code.
364 + aic32x4_clkdesc_array[0].parent_names =
365 + (const char* []) { mclk_name, "bclk", "gpio", "din" };
367 + for (i = 0; i < ARRAY_SIZE(aic32x4_clkdesc_array); ++i)
368 + aic32x4_register_clk(dev, &aic32x4_clkdesc_array[i]);
372 +EXPORT_SYMBOL_GPL(aic32x4_register_clocks);
373 --- a/sound/soc/codecs/tlv320aic32x4.c
374 +++ b/sound/soc/codecs/tlv320aic32x4.c
377 * This program is distributed in the hope that it will be useful,
378 * but WITHOUT ANY WARRANTY; without even the implied warranty of
379 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
380 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
381 * GNU General Public License for more details.
383 * You should have received a copy of the GNU General Public License
385 #include <linux/cdev.h>
386 #include <linux/slab.h>
387 #include <linux/clk.h>
388 +#include <linux/of_clk.h>
389 #include <linux/regulator/consumer.h>
391 #include <sound/tlv320aic32x4.h>
393 struct aic32x4_rate_divs {
399 + unsigned long pll_rate;
403 @@ -71,6 +70,7 @@ struct aic32x4_priv {
407 + const char *mclk_name;
409 struct regulator *supply_ldo;
410 struct regulator *supply_iov;
411 @@ -309,34 +309,34 @@ static const struct snd_kcontrol_new aic
413 static const struct aic32x4_rate_divs aic32x4_divs[] = {
415 - {12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24, 1, 1},
416 - {24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24, 1, 1},
417 - {25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24, 1, 1},
418 + { 12000000, 8000, 57120000, 768, 5, 3, 128, 5, 18, 24, 1, 1 },
419 + { 24000000, 8000, 57120000, 768, 15, 1, 64, 45, 4, 24, 1, 1 },
420 + { 25000000, 8000, 32620000, 768, 15, 1, 64, 45, 4, 24, 1, 1 },
422 - {12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16, 1, 1},
423 - {24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16, 1, 1},
424 + { 12000000, 11025, 44217600, 512, 8, 2, 128, 8, 8, 16, 1, 1 },
425 + { 24000000, 11025, 44217600, 512, 16, 1, 64, 32, 4, 16, 1, 1 },
427 - {12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12, 1, 1},
428 - {24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12, 1, 1},
429 - {25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12, 1, 1},
430 + { 12000000, 16000, 57120000, 384, 5, 3, 128, 5, 9, 12, 1, 1 },
431 + { 24000000, 16000, 57120000, 384, 15, 1, 64, 18, 5, 12, 1, 1 },
432 + { 25000000, 16000, 32620000, 384, 15, 1, 64, 18, 5, 12, 1, 1 },
434 - {12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8, 1, 1},
435 - {24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8, 1, 1},
436 - {25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8, 1, 1},
437 + { 12000000, 22050, 44217600, 256, 4, 4, 128, 4, 8, 8, 1, 1 },
438 + { 24000000, 22050, 44217600, 256, 16, 1, 64, 16, 4, 8, 1, 1 },
439 + { 25000000, 22050, 19713750, 256, 16, 1, 64, 16, 4, 8, 1, 1 },
441 - {12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6, 1, 1},
442 - {24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6, 1, 1},
443 + { 12000000, 32000, 14112000, 192, 2, 7, 64, 2, 21, 6, 1, 1 },
444 + { 24000000, 32000, 14112000, 192, 7, 2, 64, 7, 6, 6, 1, 1 },
446 - {12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4, 1, 1},
447 - {24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4, 1, 1},
448 - {25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4, 1, 1},
449 + { 12000000, 44100, 44217600, 128, 2, 8, 128, 2, 8, 4, 1, 1 },
450 + { 24000000, 44100, 44217600, 128, 8, 2, 64, 8, 4, 4, 1, 1 },
451 + { 25000000, 44100, 19713750, 128, 8, 2, 64, 8, 4, 4, 1, 1 },
453 - {12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4, 1, 1},
454 - {24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4, 1, 1},
455 - {25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4, 1, 1},
456 + { 12000000, 48000, 18432000, 128, 2, 8, 128, 2, 8, 4, 1, 1 },
457 + { 24000000, 48000, 18432000, 128, 8, 2, 64, 8, 4, 4, 1, 1 },
458 + { 25000000, 48000, 75626250, 128, 8, 2, 64, 8, 4, 4, 1, 1 },
461 - {25000000, 96000, 2, 7, 8643, 64, 4, 4, 64, 4, 4, 1, 1, 9},
462 + { 25000000, 96000, 75626250, 64, 4, 4, 64, 4, 4, 1, 1, 9 },
465 static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
466 @@ -393,7 +393,7 @@ static const struct snd_kcontrol_new in3
467 SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum),
470 -/* Right mixer pins */
471 +/* Right mixer pins */
472 static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text);
473 static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text);
474 static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text);
475 @@ -597,7 +597,7 @@ static const struct snd_soc_dapm_route a
476 static const struct regmap_range_cfg aic32x4_regmap_pages[] = {
479 - .selector_mask = 0xff,
480 + .selector_mask = 0xff,
484 @@ -618,7 +618,7 @@ static inline int aic32x4_get_divs(int m
486 for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) {
487 if ((aic32x4_divs[i].rate == rate)
488 - && (aic32x4_divs[i].mclk == mclk)) {
489 + && (aic32x4_divs[i].mclk == mclk)) {
493 @@ -690,12 +690,12 @@ static int aic32x4_set_dai_fmt(struct sn
496 snd_soc_component_update_bits(component, AIC32X4_IFACE1,
497 - AIC32X4_IFACE1_DATATYPE_MASK |
498 - AIC32X4_IFACE1_MASTER_MASK, iface_reg_1);
499 + AIC32X4_IFACE1_DATATYPE_MASK |
500 + AIC32X4_IFACE1_MASTER_MASK, iface_reg_1);
501 snd_soc_component_update_bits(component, AIC32X4_IFACE2,
502 - AIC32X4_DATA_OFFSET_MASK, iface_reg_2);
503 + AIC32X4_DATA_OFFSET_MASK, iface_reg_2);
504 snd_soc_component_update_bits(component, AIC32X4_IFACE3,
505 - AIC32X4_BCLKINV_MASK, iface_reg_3);
506 + AIC32X4_BCLKINV_MASK, iface_reg_3);
510 @@ -717,6 +717,11 @@ static int aic32x4_setup_clocks(struct s
511 unsigned int parent_rate)
516 + struct clk_bulk_data clocks[] = {
520 i = aic32x4_get_divs(parent_rate, sample_rate);
522 @@ -724,39 +729,29 @@ static int aic32x4_setup_clocks(struct s
526 + ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
530 + clk_set_rate(clocks[0].clk, sample_rate);
532 aic32x4_set_processing_blocks(component, aic32x4_divs[i].r_block, aic32x4_divs[i].p_block);
534 - /* MCLK as PLL_CLKIN */
535 - snd_soc_component_update_bits(component, AIC32X4_CLKMUX, AIC32X4_PLL_CLKIN_MASK,
536 - AIC32X4_PLL_CLKIN_MCLK << AIC32X4_PLL_CLKIN_SHIFT);
537 /* PLL as CODEC_CLKIN */
538 - snd_soc_component_update_bits(component, AIC32X4_CLKMUX, AIC32X4_CODEC_CLKIN_MASK,
539 - AIC32X4_CODEC_CLKIN_PLL << AIC32X4_CODEC_CLKIN_SHIFT);
540 + snd_soc_component_update_bits(component, AIC32X4_CLKMUX,
541 + AIC32X4_CODEC_CLKIN_MASK,
542 + AIC32X4_CODEC_CLKIN_PLL << AIC32X4_CODEC_CLKIN_SHIFT);
543 /* DAC_MOD_CLK as BDIV_CLKIN */
544 snd_soc_component_update_bits(component, AIC32X4_IFACE3, AIC32X4_BDIVCLK_MASK,
545 - AIC32X4_DACMOD2BCLK << AIC32X4_BDIVCLK_SHIFT);
547 - /* We will fix R value to 1 and will make P & J=K.D as variable */
548 - snd_soc_component_update_bits(component, AIC32X4_PLLPR, AIC32X4_PLL_R_MASK, 0x01);
551 - snd_soc_component_update_bits(component, AIC32X4_PLLPR, AIC32X4_PLL_P_MASK,
552 - aic32x4_divs[i].p_val << AIC32X4_PLL_P_SHIFT);
555 - snd_soc_component_write(component, AIC32X4_PLLJ, aic32x4_divs[i].pll_j);
558 - snd_soc_component_write(component, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8));
559 - snd_soc_component_write(component, AIC32X4_PLLDLSB, (aic32x4_divs[i].pll_d & 0xff));
560 + AIC32X4_DACMOD2BCLK << AIC32X4_BDIVCLK_SHIFT);
562 /* NDAC divider value */
563 snd_soc_component_update_bits(component, AIC32X4_NDAC,
564 - AIC32X4_NDAC_MASK, aic32x4_divs[i].ndac);
565 + AIC32X4_NDAC_MASK, aic32x4_divs[i].ndac);
567 /* MDAC divider value */
568 snd_soc_component_update_bits(component, AIC32X4_MDAC,
569 - AIC32X4_MDAC_MASK, aic32x4_divs[i].mdac);
570 + AIC32X4_MDAC_MASK, aic32x4_divs[i].mdac);
572 /* DOSR MSB & LSB values */
573 snd_soc_component_write(component, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8);
574 @@ -764,18 +759,18 @@ static int aic32x4_setup_clocks(struct s
576 /* NADC divider value */
577 snd_soc_component_update_bits(component, AIC32X4_NADC,
578 - AIC32X4_NADC_MASK, aic32x4_divs[i].nadc);
579 + AIC32X4_NADC_MASK, aic32x4_divs[i].nadc);
581 /* MADC divider value */
582 snd_soc_component_update_bits(component, AIC32X4_MADC,
583 - AIC32X4_MADC_MASK, aic32x4_divs[i].madc);
584 + AIC32X4_MADC_MASK, aic32x4_divs[i].madc);
587 snd_soc_component_write(component, AIC32X4_AOSR, aic32x4_divs[i].aosr);
590 snd_soc_component_update_bits(component, AIC32X4_BCLKN,
591 - AIC32X4_BCLK_MASK, aic32x4_divs[i].blck_N);
592 + AIC32X4_BCLK_MASK, aic32x4_divs[i].blck_N);
596 @@ -794,23 +789,23 @@ static int aic32x4_hw_params(struct snd_
597 switch (params_width(params)) {
599 iface1_reg |= (AIC32X4_WORD_LEN_16BITS <<
600 - AIC32X4_IFACE1_DATALEN_SHIFT);
601 + AIC32X4_IFACE1_DATALEN_SHIFT);
604 iface1_reg |= (AIC32X4_WORD_LEN_20BITS <<
605 - AIC32X4_IFACE1_DATALEN_SHIFT);
606 + AIC32X4_IFACE1_DATALEN_SHIFT);
609 iface1_reg |= (AIC32X4_WORD_LEN_24BITS <<
610 - AIC32X4_IFACE1_DATALEN_SHIFT);
611 + AIC32X4_IFACE1_DATALEN_SHIFT);
614 iface1_reg |= (AIC32X4_WORD_LEN_32BITS <<
615 - AIC32X4_IFACE1_DATALEN_SHIFT);
616 + AIC32X4_IFACE1_DATALEN_SHIFT);
619 snd_soc_component_update_bits(component, AIC32X4_IFACE1,
620 - AIC32X4_IFACE1_DATALEN_MASK, iface1_reg);
621 + AIC32X4_IFACE1_DATALEN_MASK, iface1_reg);
623 if (params_channels(params) == 1) {
624 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN;
625 @@ -821,7 +816,7 @@ static int aic32x4_hw_params(struct snd_
626 dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
628 snd_soc_component_update_bits(component, AIC32X4_DACSETUP,
629 - AIC32X4_DAC_CHAN_MASK, dacsetup_reg);
630 + AIC32X4_DAC_CHAN_MASK, dacsetup_reg);
634 @@ -831,7 +826,7 @@ static int aic32x4_mute(struct snd_soc_d
635 struct snd_soc_component *component = dai->component;
637 snd_soc_component_update_bits(component, AIC32X4_DACMUTE,
638 - AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0);
639 + AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0);
643 @@ -853,27 +848,27 @@ static int aic32x4_set_bias_level(struct
646 snd_soc_component_update_bits(component, AIC32X4_PLLPR,
647 - AIC32X4_PLLEN, AIC32X4_PLLEN);
648 + AIC32X4_PLLEN, AIC32X4_PLLEN);
650 /* Switch on NDAC Divider */
651 snd_soc_component_update_bits(component, AIC32X4_NDAC,
652 - AIC32X4_NDACEN, AIC32X4_NDACEN);
653 + AIC32X4_NDACEN, AIC32X4_NDACEN);
655 /* Switch on MDAC Divider */
656 snd_soc_component_update_bits(component, AIC32X4_MDAC,
657 - AIC32X4_MDACEN, AIC32X4_MDACEN);
658 + AIC32X4_MDACEN, AIC32X4_MDACEN);
660 /* Switch on NADC Divider */
661 snd_soc_component_update_bits(component, AIC32X4_NADC,
662 - AIC32X4_NADCEN, AIC32X4_NADCEN);
663 + AIC32X4_NADCEN, AIC32X4_NADCEN);
665 /* Switch on MADC Divider */
666 snd_soc_component_update_bits(component, AIC32X4_MADC,
667 - AIC32X4_MADCEN, AIC32X4_MADCEN);
668 + AIC32X4_MADCEN, AIC32X4_MADCEN);
670 /* Switch on BCLK_N Divider */
671 snd_soc_component_update_bits(component, AIC32X4_BCLKN,
672 - AIC32X4_BCLKEN, AIC32X4_BCLKEN);
673 + AIC32X4_BCLKEN, AIC32X4_BCLKEN);
675 case SND_SOC_BIAS_PREPARE:
677 @@ -884,27 +879,27 @@ static int aic32x4_set_bias_level(struct
679 /* Switch off BCLK_N Divider */
680 snd_soc_component_update_bits(component, AIC32X4_BCLKN,
681 - AIC32X4_BCLKEN, 0);
682 + AIC32X4_BCLKEN, 0);
684 /* Switch off MADC Divider */
685 snd_soc_component_update_bits(component, AIC32X4_MADC,
686 - AIC32X4_MADCEN, 0);
687 + AIC32X4_MADCEN, 0);
689 /* Switch off NADC Divider */
690 snd_soc_component_update_bits(component, AIC32X4_NADC,
691 - AIC32X4_NADCEN, 0);
692 + AIC32X4_NADCEN, 0);
694 /* Switch off MDAC Divider */
695 snd_soc_component_update_bits(component, AIC32X4_MDAC,
696 - AIC32X4_MDACEN, 0);
697 + AIC32X4_MDACEN, 0);
699 /* Switch off NDAC Divider */
700 snd_soc_component_update_bits(component, AIC32X4_NDAC,
701 - AIC32X4_NDACEN, 0);
702 + AIC32X4_NDACEN, 0);
705 snd_soc_component_update_bits(component, AIC32X4_PLLPR,
709 /* Switch off master clock */
710 clk_disable_unprepare(aic32x4->mclk);
711 @@ -916,7 +911,7 @@ static int aic32x4_set_bias_level(struct
714 #define AIC32X4_RATES SNDRV_PCM_RATE_8000_96000
715 -#define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
716 +#define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
717 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
719 static const struct snd_soc_dai_ops aic32x4_ops = {
720 @@ -929,17 +924,17 @@ static const struct snd_soc_dai_ops aic3
721 static struct snd_soc_dai_driver aic32x4_dai = {
722 .name = "tlv320aic32x4-hifi",
724 - .stream_name = "Playback",
727 - .rates = AIC32X4_RATES,
728 - .formats = AIC32X4_FORMATS,},
729 + .stream_name = "Playback",
732 + .rates = AIC32X4_RATES,
733 + .formats = AIC32X4_FORMATS,},
735 - .stream_name = "Capture",
738 - .rates = AIC32X4_RATES,
739 - .formats = AIC32X4_FORMATS,},
740 + .stream_name = "Capture",
743 + .rates = AIC32X4_RATES,
744 + .formats = AIC32X4_FORMATS,},
746 .symmetric_rates = 1,
748 @@ -952,7 +947,7 @@ static void aic32x4_setup_gpios(struct s
750 if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) {
751 snd_soc_component_write(component, AIC32X4_DINCTL,
752 - aic32x4->setup->gpio_func[0]);
753 + aic32x4->setup->gpio_func[0]);
754 snd_soc_add_component_controls(component, aic32x4_mfp1,
755 ARRAY_SIZE(aic32x4_mfp1));
757 @@ -960,7 +955,7 @@ static void aic32x4_setup_gpios(struct s
759 if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) {
760 snd_soc_component_write(component, AIC32X4_DOUTCTL,
761 - aic32x4->setup->gpio_func[1]);
762 + aic32x4->setup->gpio_func[1]);
763 snd_soc_add_component_controls(component, aic32x4_mfp2,
764 ARRAY_SIZE(aic32x4_mfp2));
766 @@ -968,7 +963,7 @@ static void aic32x4_setup_gpios(struct s
768 if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) {
769 snd_soc_component_write(component, AIC32X4_SCLKCTL,
770 - aic32x4->setup->gpio_func[2]);
771 + aic32x4->setup->gpio_func[2]);
772 snd_soc_add_component_controls(component, aic32x4_mfp3,
773 ARRAY_SIZE(aic32x4_mfp3));
775 @@ -976,7 +971,7 @@ static void aic32x4_setup_gpios(struct s
777 if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) {
778 snd_soc_component_write(component, AIC32X4_MISOCTL,
779 - aic32x4->setup->gpio_func[3]);
780 + aic32x4->setup->gpio_func[3]);
781 snd_soc_add_component_controls(component, aic32x4_mfp4,
782 ARRAY_SIZE(aic32x4_mfp4));
784 @@ -984,7 +979,7 @@ static void aic32x4_setup_gpios(struct s
786 if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) {
787 snd_soc_component_write(component, AIC32X4_GPIOCTL,
788 - aic32x4->setup->gpio_func[4]);
789 + aic32x4->setup->gpio_func[4]);
790 snd_soc_add_component_controls(component, aic32x4_mfp5,
791 ARRAY_SIZE(aic32x4_mfp5));
793 @@ -1007,8 +1002,8 @@ static int aic32x4_component_probe(struc
795 /* Power platform configuration */
796 if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
797 - snd_soc_component_write(component, AIC32X4_MICBIAS, AIC32X4_MICBIAS_LDOIN |
798 - AIC32X4_MICBIAS_2075V);
799 + snd_soc_component_write(component, AIC32X4_MICBIAS,
800 + AIC32X4_MICBIAS_LDOIN | AIC32X4_MICBIAS_2075V);
802 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
803 snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
804 @@ -1071,12 +1066,18 @@ static int aic32x4_parse_dt(struct aic32
805 struct device_node *np)
807 struct aic32x4_setup_data *aic32x4_setup;
810 aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup),
815 + ret = of_property_match_string(np, "clock-names", "mclk");
818 + aic32x4->mclk_name = of_clk_get_parent_name(np, ret);
820 aic32x4->swapdacs = false;
821 aic32x4->micpga_routing = 0;
822 aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0);
823 @@ -1198,7 +1199,7 @@ int aic32x4_probe(struct device *dev, st
824 return PTR_ERR(regmap);
826 aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv),
832 @@ -1210,6 +1211,7 @@ int aic32x4_probe(struct device *dev, st
833 aic32x4->swapdacs = pdata->swapdacs;
834 aic32x4->micpga_routing = pdata->micpga_routing;
835 aic32x4->rstn_gpio = pdata->rstn_gpio;
836 + aic32x4->mclk_name = "mclk";
838 ret = aic32x4_parse_dt(aic32x4, np);
840 @@ -1221,6 +1223,7 @@ int aic32x4_probe(struct device *dev, st
841 aic32x4->swapdacs = false;
842 aic32x4->micpga_routing = 0;
843 aic32x4->rstn_gpio = -1;
844 + aic32x4->mclk_name = "mclk";
847 aic32x4->mclk = devm_clk_get(dev, "mclk");
848 @@ -1229,6 +1232,10 @@ int aic32x4_probe(struct device *dev, st
849 return PTR_ERR(aic32x4->mclk);
852 + ret = aic32x4_register_clocks(dev, aic32x4->mclk_name);
856 if (gpio_is_valid(aic32x4->rstn_gpio)) {
857 ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio,
858 GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn");
859 --- a/sound/soc/codecs/tlv320aic32x4.h
860 +++ b/sound/soc/codecs/tlv320aic32x4.h
861 @@ -16,6 +16,7 @@ struct regmap_config;
862 extern const struct regmap_config aic32x4_regmap_config;
863 int aic32x4_probe(struct device *dev, struct regmap *regmap);
864 int aic32x4_remove(struct device *dev);
865 +int aic32x4_register_clocks(struct device *dev, const char *mclk_name);
867 /* tlv320aic32x4 register space (in decimal to match datasheet) */
869 @@ -205,4 +206,8 @@ int aic32x4_remove(struct device *dev);
870 #define AIC32X4_RMICPGANIN_IN1L_10K 0x10
871 #define AIC32X4_RMICPGANIN_CM1R_10K 0x40
874 +#define AIC32X4_MAX_PLL_CLKIN 20000000
877 #endif /* _TLV320AIC32X4_H */