1 From 3e62c56daa1c799bb2a1d954ecfb88e8d37421bb Mon Sep 17 00:00:00 2001
2 From: Annaliese McDermond <nh6z@nh6z.net>
3 Date: Thu, 21 Mar 2019 17:58:51 -0700
4 Subject: [PATCH 405/806] ASoC: tlv320aic32x4: Dynamically Determine Clocking
6 commit 96c3bb00239de4fb5f4ddca42c1f90d6d9b3c697 upstream.
8 The existing code uses a static lookup table to determine the
9 settings of the various clock devices on board the chip. This is
10 limiting in a couple of ways. First, this doesn't allow for any
11 master clock rates other than the three that have been
12 precalculated. Additionally, new sample rates are difficult to
13 add to the table. Witness that the chip is capable of 192000 Hz
14 sampling, but it is not provided by this driver. Last, if the
15 driver is clocked by something that isn't a crystal, the
16 upstream clock may not be able to achieve exactly the rate
17 requested in the driver. This will mean that clocking will be
18 slightly off for the sampling clock or that it won't work at all.
20 This patch determines the settings for all of the clocks at
21 runtime considering the real conditions of the clocks in the
22 system. The rules for the clocks are in TI's SLAA557 application
23 guide on pages 37, 51 and 77.
25 Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
26 Signed-off-by: Mark Brown <broonie@kernel.org>
28 sound/soc/codecs/tlv320aic32x4.c | 190 ++++++++++++++-----------------
29 sound/soc/codecs/tlv320aic32x4.h | 4 +-
30 2 files changed, 90 insertions(+), 104 deletions(-)
32 --- a/sound/soc/codecs/tlv320aic32x4.c
33 +++ b/sound/soc/codecs/tlv320aic32x4.c
36 #include "tlv320aic32x4.h"
38 -struct aic32x4_rate_divs {
41 - unsigned long pll_rate;
43 - unsigned long ndac_rate;
44 - unsigned long mdac_rate;
46 - unsigned long nadc_rate;
47 - unsigned long madc_rate;
48 - unsigned long bdiv_rate;
54 struct regmap *regmap;
56 @@ -307,58 +292,6 @@ static const struct snd_kcontrol_new aic
60 -static const struct aic32x4_rate_divs aic32x4_divs[] = {
62 - { 12000000, 8000, 57120000, 768, 18432000, 6144000, 128, 18432000,
63 - 1024000, 256000, 1, 1 },
64 - { 24000000, 8000, 57120000, 768, 6144000, 6144000, 64, 2048000,
65 - 512000, 256000, 1, 1 },
66 - { 25000000, 8000, 32620000, 768, 6144000, 6144000, 64, 2048000,
67 - 512000, 256000, 1, 1 },
69 - { 12000000, 11025, 44217600, 512, 11289600, 5644800, 128, 11289600,
70 - 1411200, 352800, 1, 1 },
71 - { 24000000, 11025, 44217600, 512, 5644800, 5644800, 64, 2822400,
72 - 705600, 352800, 1, 1 },
74 - { 12000000, 16000, 57120000, 384, 18432000, 6144000, 128, 18432000,
75 - 2048000, 512000, 1, 1 },
76 - { 24000000, 16000, 57120000, 384, 6144000, 6144000, 64, 5120000,
77 - 1024000, 512000, 1, 1 },
78 - { 25000000, 16000, 32620000, 384, 6144000, 6144000, 64, 5120000,
79 - 1024000, 512000, 1, 1 },
81 - { 12000000, 22050, 44217600, 256, 22579200, 5644800, 128, 22579200,
82 - 2822400, 705600, 1, 1 },
83 - { 24000000, 22050, 44217600, 256, 5644800, 5644800, 64, 5644800,
84 - 1411200, 705600, 1, 1 },
85 - { 25000000, 22050, 19713750, 256, 5644800, 5644800, 64, 5644800,
86 - 1411200, 705600, 1, 1 },
88 - { 12000000, 32000, 14112000, 192, 43008000, 6144000, 64, 43008000,
89 - 2048000, 1024000, 1, 1 },
90 - { 24000000, 32000, 14112000, 192, 12288000, 6144000, 64, 12288000,
91 - 2048000, 1024000, 1, 1 },
93 - { 12000000, 44100, 44217600, 128, 45158400, 5644800, 128, 45158400,
94 - 5644800, 1411200, 1, 1 },
95 - { 24000000, 44100, 44217600, 128, 11289600, 5644800, 64, 11289600,
96 - 2822400, 1411200, 1, 1 },
97 - { 25000000, 44100, 19713750, 128, 11289600, 5644800, 64, 11289600,
98 - 2822400, 1411200, 1, 1 },
100 - { 12000000, 48000, 18432000, 128, 49152000, 6144000, 128, 49152000,
101 - 6144000, 1536000, 1, 1 },
102 - { 24000000, 48000, 18432000, 128, 12288000, 6144000, 64, 12288000,
103 - 3072000, 1536000, 1, 1 },
104 - { 25000000, 48000, 75626250, 128, 12288000, 6144000, 64, 12288000,
105 - 3072000, 1536000, 1, 1 },
108 - { 25000000, 96000, 75626250, 64, 24576000, 6144000, 64, 24576000,
109 - 6144000, 3072000, 1, 9 },
112 static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
113 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
114 SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
115 @@ -632,20 +565,6 @@ const struct regmap_config aic32x4_regma
117 EXPORT_SYMBOL(aic32x4_regmap_config);
119 -static inline int aic32x4_get_divs(int mclk, int rate)
123 - for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) {
124 - if ((aic32x4_divs[i].rate == rate)
125 - && (aic32x4_divs[i].mclk == mclk)) {
129 - printk(KERN_ERR "aic32x4: master clock and sample rate is not supported\n");
133 static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
134 int clk_id, unsigned int freq, int dir)
136 @@ -747,11 +666,17 @@ static int aic32x4_set_processing_blocks
139 static int aic32x4_setup_clocks(struct snd_soc_component *component,
140 - unsigned int sample_rate,
141 - unsigned int parent_rate)
142 + unsigned int sample_rate)
147 + u8 adc_resource_class, dac_resource_class;
148 + u8 madc, nadc, mdac, ndac, max_nadc, min_mdac, max_ndac;
150 + u16 max_dosr, min_dosr;
151 + unsigned long mclk_rate, adc_clock_rate, dac_clock_rate;
155 struct clk_bulk_data clocks[] = {
157 @@ -761,30 +686,89 @@ static int aic32x4_setup_clocks(struct s
162 - i = aic32x4_get_divs(parent_rate, sample_rate);
164 - printk(KERN_ERR "aic32x4: sampling rate not supported\n");
168 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
172 - clk_set_rate(clocks[0].clk, aic32x4_divs[i].pll_rate);
173 - clk_set_rate(clocks[1].clk, aic32x4_divs[i].nadc_rate);
174 - clk_set_rate(clocks[2].clk, aic32x4_divs[i].madc_rate);
175 - clk_set_rate(clocks[3].clk, aic32x4_divs[i].ndac_rate);
176 - clk_set_rate(clocks[4].clk, aic32x4_divs[i].mdac_rate);
177 - clk_set_rate(clocks[5].clk, aic32x4_divs[i].bdiv_rate);
178 + mclk = clk_get_parent(clocks[1].clk);
179 + mclk_rate = clk_get_rate(mclk);
181 - aic32x4_set_aosr(component, aic32x4_divs[i].aosr);
182 - aic32x4_set_dosr(component, aic32x4_divs[i].dosr);
183 + if (sample_rate <= 48000) {
185 + adc_resource_class = 6;
186 + dac_resource_class = 8;
187 + dosr_increment = 8;
188 + aic32x4_set_processing_blocks(component, 1, 1);
189 + } else if (sample_rate <= 96000) {
191 + adc_resource_class = 6;
192 + dac_resource_class = 8;
193 + dosr_increment = 4;
194 + aic32x4_set_processing_blocks(component, 1, 9);
195 + } else if (sample_rate == 192000) {
197 + adc_resource_class = 3;
198 + dac_resource_class = 4;
199 + dosr_increment = 2;
200 + aic32x4_set_processing_blocks(component, 13, 19);
202 + dev_err(component->dev, "Sampling rate not supported\n");
206 - aic32x4_set_processing_blocks(component, aic32x4_divs[i].r_block, aic32x4_divs[i].p_block);
207 + madc = DIV_ROUND_UP((32 * adc_resource_class), aosr);
208 + max_dosr = (AIC32X4_MAX_DOSR_FREQ / sample_rate / dosr_increment) *
210 + min_dosr = (AIC32X4_MIN_DOSR_FREQ / sample_rate / dosr_increment) *
212 + max_nadc = AIC32X4_MAX_CODEC_CLKIN_FREQ / (madc * aosr * sample_rate);
214 + for (nadc = max_nadc; nadc > 0; --nadc) {
215 + adc_clock_rate = nadc * madc * aosr * sample_rate;
216 + for (dosr = max_dosr; dosr >= min_dosr;
217 + dosr -= dosr_increment) {
218 + min_mdac = DIV_ROUND_UP((32 * dac_resource_class), dosr);
219 + max_ndac = AIC32X4_MAX_CODEC_CLKIN_FREQ /
220 + (min_mdac * dosr * sample_rate);
221 + for (mdac = min_mdac; mdac <= 128; ++mdac) {
222 + for (ndac = max_ndac; ndac > 0; --ndac) {
223 + dac_clock_rate = ndac * mdac * dosr *
225 + if (dac_clock_rate == adc_clock_rate) {
226 + if (clk_round_rate(clocks[0].clk, dac_clock_rate) == 0)
229 + clk_set_rate(clocks[0].clk,
232 + clk_set_rate(clocks[1].clk,
233 + sample_rate * aosr *
235 + clk_set_rate(clocks[2].clk,
236 + sample_rate * aosr);
237 + aic32x4_set_aosr(component,
240 + clk_set_rate(clocks[3].clk,
241 + sample_rate * dosr *
243 + clk_set_rate(clocks[4].clk,
244 + sample_rate * dosr);
245 + aic32x4_set_dosr(component,
248 + clk_set_rate(clocks[5].clk,
258 + dev_err(component->dev,
259 + "Could not set clocks to support sample rate.\n");
263 static int aic32x4_hw_params(struct snd_pcm_substream *substream,
264 @@ -796,7 +780,7 @@ static int aic32x4_hw_params(struct snd_
268 - aic32x4_setup_clocks(component, params_rate(params), aic32x4->sysclk);
269 + aic32x4_setup_clocks(component, params_rate(params));
271 switch (params_width(params)) {
273 --- a/sound/soc/codecs/tlv320aic32x4.h
274 +++ b/sound/soc/codecs/tlv320aic32x4.h
275 @@ -211,7 +211,9 @@ int aic32x4_register_clocks(struct devic
276 #define AIC32X4_DIV_MASK GENMASK(6, 0)
279 +#define AIC32X4_MAX_DOSR_FREQ 6200000
280 +#define AIC32X4_MIN_DOSR_FREQ 2800000
281 +#define AIC32X4_MAX_CODEC_CLKIN_FREQ 110000000
282 #define AIC32X4_MAX_PLL_CLKIN 20000000
285 #endif /* _TLV320AIC32X4_H */