1 From ffbb6cc14b8fb1876b249048284a5fe30f48c693 Mon Sep 17 00:00:00 2001
2 From: Annaliese McDermond <nh6z@nh6z.net>
3 Date: Sat, 8 Jun 2019 10:14:43 -0700
4 Subject: [PATCH] i2c: bcm2835: Model Divider in CCF
6 Commit bebff81fb8b9216eb4fba22cf910553621ae3477 upstream.
8 Model the I2C bus clock divider as a part of the Core Clock Framework.
9 Primarily this removes the clk_get_rate() call from each transfer.
10 This call causes problems for slave drivers that themselves have
11 internal clock components that are controlled by an I2C interface.
12 When the slave's internal clock component is prepared, the prepare
13 lock is obtained, and it makes calls to the I2C subsystem to
14 command the hardware to activate the clock. In order to perform
15 the I2C transfer, this driver sets the divider, which requires
16 it to get the parent clock rate, which it does with clk_get_rate().
17 Unfortunately, this function will try to take the clock prepare
18 lock, which is already held by the slave's internal clock calls
21 Modeling the divider in the CCF natively removes this dependency
22 and the divider value is only set upon changing the bus clock
23 frequency or changes in the parent clock that cascade down to this
24 divisor. This obviates the need to set the divider with every
25 transfer and avoids the deadlock described above. It also should
26 provide better clock debugging and save a few cycles on each
27 transfer due to not having to recalcuate the divider value.
29 Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
30 Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
31 Reviewed-by: Eric Anholt <eric@anholt.net>
32 Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
34 drivers/i2c/busses/i2c-bcm2835.c | 145 ++++++++++++++++++++++++-------
35 1 file changed, 114 insertions(+), 31 deletions(-)
37 --- a/drivers/i2c/busses/i2c-bcm2835.c
38 +++ b/drivers/i2c/busses/i2c-bcm2835.c
42 #include <linux/clk.h>
43 +#include <linux/clkdev.h>
44 +#include <linux/clk-provider.h>
45 #include <linux/completion.h>
46 #include <linux/err.h>
47 #include <linux/i2c.h>
48 @@ -71,9 +73,7 @@ struct bcm2835_debug {
49 struct bcm2835_i2c_dev {
55 struct i2c_adapter adapter;
56 struct completion completion;
57 struct i2c_msg *curr_msg;
58 @@ -164,12 +164,17 @@ static inline u32 bcm2835_i2c_readl(stru
59 return readl(i2c_dev->regs + reg);
62 -static int bcm2835_i2c_set_divider(struct bcm2835_i2c_dev *i2c_dev)
63 +#define to_clk_bcm2835_i2c(_hw) container_of(_hw, struct clk_bcm2835_i2c, hw)
64 +struct clk_bcm2835_i2c {
66 + struct bcm2835_i2c_dev *i2c_dev;
69 +static int clk_bcm2835_i2c_calc_divider(unsigned long rate,
70 + unsigned long parent_rate)
72 - u32 divider, redl, fedl;
73 + u32 divider = DIV_ROUND_UP(parent_rate, rate);
75 - divider = DIV_ROUND_UP(clk_get_rate(i2c_dev->clk),
76 - i2c_dev->bus_clk_rate);
78 * Per the datasheet, the register is always interpreted as an even
79 * number, by rounding down. In other words, the LSB is ignored. So,
80 @@ -178,12 +183,23 @@ static int bcm2835_i2c_set_divider(struc
83 if ((divider < BCM2835_I2C_CDIV_MIN) ||
84 - (divider > BCM2835_I2C_CDIV_MAX)) {
85 - dev_err_ratelimited(i2c_dev->dev, "Invalid clock-frequency\n");
86 + (divider > BCM2835_I2C_CDIV_MAX))
90 - bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DIV, divider);
94 +static int clk_bcm2835_i2c_set_rate(struct clk_hw *hw, unsigned long rate,
95 + unsigned long parent_rate)
97 + struct clk_bcm2835_i2c *div = to_clk_bcm2835_i2c(hw);
99 + u32 divider = clk_bcm2835_i2c_calc_divider(rate, parent_rate);
101 + if (divider == -EINVAL)
104 + bcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DIV, divider);
107 * Number of core clocks to wait after falling edge before
108 @@ -198,12 +214,62 @@ static int bcm2835_i2c_set_divider(struc
110 redl = max(divider / 4, 1u);
112 - bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DEL,
113 + bcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DEL,
114 (fedl << BCM2835_I2C_FEDL_SHIFT) |
115 (redl << BCM2835_I2C_REDL_SHIFT));
119 +static long clk_bcm2835_i2c_round_rate(struct clk_hw *hw, unsigned long rate,
120 + unsigned long *parent_rate)
122 + u32 divider = clk_bcm2835_i2c_calc_divider(rate, *parent_rate);
124 + return DIV_ROUND_UP(*parent_rate, divider);
127 +static unsigned long clk_bcm2835_i2c_recalc_rate(struct clk_hw *hw,
128 + unsigned long parent_rate)
130 + struct clk_bcm2835_i2c *div = to_clk_bcm2835_i2c(hw);
131 + u32 divider = bcm2835_i2c_readl(div->i2c_dev, BCM2835_I2C_DIV);
133 + return DIV_ROUND_UP(parent_rate, divider);
136 +static const struct clk_ops clk_bcm2835_i2c_ops = {
137 + .set_rate = clk_bcm2835_i2c_set_rate,
138 + .round_rate = clk_bcm2835_i2c_round_rate,
139 + .recalc_rate = clk_bcm2835_i2c_recalc_rate,
142 +static struct clk *bcm2835_i2c_register_div(struct device *dev,
143 + const char *mclk_name,
144 + struct bcm2835_i2c_dev *i2c_dev)
146 + struct clk_init_data init;
147 + struct clk_bcm2835_i2c *priv;
150 + snprintf(name, sizeof(name), "%s_div", dev_name(dev));
152 + init.ops = &clk_bcm2835_i2c_ops;
154 + init.parent_names = (const char* []) { mclk_name };
155 + init.num_parents = 1;
158 + priv = devm_kzalloc(dev, sizeof(struct clk_bcm2835_i2c), GFP_KERNEL);
160 + return ERR_PTR(-ENOMEM);
162 + priv->hw.init = &init;
163 + priv->i2c_dev = i2c_dev;
165 + clk_hw_register_clkdev(&priv->hw, "div", dev_name(dev));
166 + return devm_clk_register(dev, &priv->hw);
169 static void bcm2835_fill_txfifo(struct bcm2835_i2c_dev *i2c_dev)
172 @@ -363,7 +429,7 @@ static int bcm2835_i2c_xfer(struct i2c_a
174 struct bcm2835_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
175 unsigned long time_left;
180 i2c_dev->debug_num_msgs = num;
181 @@ -379,10 +445,6 @@ static int bcm2835_i2c_xfer(struct i2c_a
185 - ret = bcm2835_i2c_set_divider(i2c_dev);
189 i2c_dev->curr_msg = msgs;
190 i2c_dev->num_msgs = num;
191 reinit_completion(&i2c_dev->completion);
192 @@ -443,6 +505,9 @@ static int bcm2835_i2c_probe(struct plat
193 struct resource *mem, *irq;
195 struct i2c_adapter *adap;
196 + const char *mclk_name;
197 + struct clk *bus_clk;
200 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
202 @@ -456,21 +521,6 @@ static int bcm2835_i2c_probe(struct plat
203 if (IS_ERR(i2c_dev->regs))
204 return PTR_ERR(i2c_dev->regs);
206 - i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
207 - if (IS_ERR(i2c_dev->clk)) {
208 - if (PTR_ERR(i2c_dev->clk) != -EPROBE_DEFER)
209 - dev_err(&pdev->dev, "Could not get clock\n");
210 - return PTR_ERR(i2c_dev->clk);
213 - ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
214 - &i2c_dev->bus_clk_rate);
216 - dev_warn(&pdev->dev,
217 - "Could not read clock-frequency property\n");
218 - i2c_dev->bus_clk_rate = 100000;
221 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
223 dev_err(&pdev->dev, "No IRQ resource\n");
224 @@ -485,6 +535,35 @@ static int bcm2835_i2c_probe(struct plat
228 + mclk_name = of_clk_get_parent_name(pdev->dev.of_node, 0);
230 + bus_clk = bcm2835_i2c_register_div(&pdev->dev, mclk_name, i2c_dev);
232 + if (IS_ERR(bus_clk)) {
233 + dev_err(&pdev->dev, "Could not register clock\n");
234 + return PTR_ERR(bus_clk);
237 + ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
240 + dev_warn(&pdev->dev,
241 + "Could not read clock-frequency property\n");
242 + bus_clk_rate = 100000;
245 + ret = clk_set_rate_exclusive(bus_clk, bus_clk_rate);
247 + dev_err(&pdev->dev, "Could not set clock frequency\n");
251 + ret = clk_prepare_enable(bus_clk);
253 + dev_err(&pdev->dev, "Couldn't prepare clock");
257 adap = &i2c_dev->adapter;
258 i2c_set_adapdata(adap, i2c_dev);
259 adap->owner = THIS_MODULE;
260 @@ -507,6 +586,10 @@ static int bcm2835_i2c_probe(struct plat
261 static int bcm2835_i2c_remove(struct platform_device *pdev)
263 struct bcm2835_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
264 + struct clk *bus_clk = devm_clk_get(i2c_dev->dev, "div");
266 + clk_rate_exclusive_put(bus_clk);
267 + clk_disable_unprepare(bus_clk);
269 free_irq(i2c_dev->irq, i2c_dev);
270 i2c_del_adapter(&i2c_dev->adapter);