1 From a4ea446a07d7ba010c3c32286a22dc89cffa1e54 Mon Sep 17 00:00:00 2001
2 From: Martin Sperl <kernel@martin.sperl.org>
3 Date: Sun, 12 May 2019 16:17:08 +0000
4 Subject: [PATCH] spi: devicetree: add overlays for spi 3 to 6
6 Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
8 arch/arm/boot/dts/overlays/Makefile | 8 ++
9 arch/arm/boot/dts/overlays/README | 104 ++++++++++++++++++
10 .../boot/dts/overlays/spi3-1cs-overlay.dts | 44 ++++++++
11 .../boot/dts/overlays/spi3-2cs-overlay.dts | 56 ++++++++++
12 .../boot/dts/overlays/spi4-1cs-overlay.dts | 44 ++++++++
13 .../boot/dts/overlays/spi4-2cs-overlay.dts | 56 ++++++++++
14 .../boot/dts/overlays/spi5-1cs-overlay.dts | 44 ++++++++
15 .../boot/dts/overlays/spi5-2cs-overlay.dts | 56 ++++++++++
16 .../boot/dts/overlays/spi6-1cs-overlay.dts | 44 ++++++++
17 .../boot/dts/overlays/spi6-2cs-overlay.dts | 56 ++++++++++
18 10 files changed, 512 insertions(+)
19 create mode 100644 arch/arm/boot/dts/overlays/spi3-1cs-overlay.dts
20 create mode 100644 arch/arm/boot/dts/overlays/spi3-2cs-overlay.dts
21 create mode 100644 arch/arm/boot/dts/overlays/spi4-1cs-overlay.dts
22 create mode 100644 arch/arm/boot/dts/overlays/spi4-2cs-overlay.dts
23 create mode 100644 arch/arm/boot/dts/overlays/spi5-1cs-overlay.dts
24 create mode 100644 arch/arm/boot/dts/overlays/spi5-2cs-overlay.dts
25 create mode 100644 arch/arm/boot/dts/overlays/spi6-1cs-overlay.dts
26 create mode 100644 arch/arm/boot/dts/overlays/spi6-2cs-overlay.dts
28 --- a/arch/arm/boot/dts/overlays/Makefile
29 +++ b/arch/arm/boot/dts/overlays/Makefile
30 @@ -144,6 +144,14 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
43 superaudioboard.dtbo \
45 --- a/arch/arm/boot/dts/overlays/README
46 +++ b/arch/arm/boot/dts/overlays/README
47 @@ -2085,6 +2085,110 @@ Params: cs0_pin GPIO pin
48 is 'okay' or enabled).
52 +Info: Enables spi3 with a single chip select (CS) line and associated spidev
53 + dev node. The gpio pin number for the CS line and spidev device node
54 + creation are configurable.
55 +Load: dtoverlay=spi3-1cs,<param>=<val>
56 +Params: cs0_pin GPIO pin for CS0 (default 0 - BCM SPI3_CE0).
57 + cs0_spidev Set to 'off' to prevent the creation of a
58 + userspace device node /dev/spidev3.0 (default
59 + is 'on' or enabled).
63 +Info: Enables spi3 with two chip select (CS) lines and associated spidev
64 + dev nodes. The gpio pin numbers for the CS lines and spidev device node
65 + creation are configurable.
66 +Load: dtoverlay=spi3-2cs,<param>=<val>
67 +Params: cs0_pin GPIO pin for CS0 (default 0 - BCM SPI3_CE0).
68 + cs1_pin GPIO pin for CS1 (default 24 - BCM SPI3_CE1).
69 + cs0_spidev Set to 'off' to prevent the creation of a
70 + userspace device node /dev/spidev3.0 (default
71 + is 'on' or enabled).
72 + cs1_spidev Set to 'off' to prevent the creation of a
73 + userspace device node /dev/spidev3.1 (default
74 + is 'on' or enabled).
78 +Info: Enables spi4 with a single chip select (CS) line and associated spidev
79 + dev node. The gpio pin number for the CS line and spidev device node
80 + creation are configurable.
81 +Load: dtoverlay=spi4-1cs,<param>=<val>
82 +Params: cs0_pin GPIO pin for CS0 (default 4 - BCM SPI4_CE0).
83 + cs0_spidev Set to 'off' to prevent the creation of a
84 + userspace device node /dev/spidev4.0 (default
85 + is 'on' or enabled).
89 +Info: Enables spi4 with two chip select (CS) lines and associated spidev
90 + dev nodes. The gpio pin numbers for the CS lines and spidev device node
91 + creation are configurable.
92 +Load: dtoverlay=spi4-2cs,<param>=<val>
93 +Params: cs0_pin GPIO pin for CS0 (default 4 - BCM SPI4_CE0).
94 + cs1_pin GPIO pin for CS1 (default 25 - BCM SPI4_CE1).
95 + cs0_spidev Set to 'off' to prevent the creation of a
96 + userspace device node /dev/spidev4.0 (default
97 + is 'on' or enabled).
98 + cs1_spidev Set to 'off' to prevent the creation of a
99 + userspace device node /dev/spidev4.1 (default
100 + is 'on' or enabled).
104 +Info: Enables spi5 with a single chip select (CS) line and associated spidev
105 + dev node. The gpio pin numbers for the CS lines and spidev device node
106 + creation are configurable.
107 +Load: dtoverlay=spi5-1cs,<param>=<val>
108 +Params: cs0_pin GPIO pin for CS0 (default 12 - BCM SPI5_CE0).
109 + cs0_spidev Set to 'off' to prevent the creation of a
110 + userspace device node /dev/spidev5.0 (default
111 + is 'on' or enabled).
115 +Info: Enables spi5 with two chip select (CS) lines and associated spidev
116 + dev nodes. The gpio pin numbers for the CS lines and spidev device node
117 + creation are configurable.
118 +Load: dtoverlay=spi5-2cs,<param>=<val>
119 +Params: cs0_pin GPIO pin for CS0 (default 12 - BCM SPI5_CE0).
120 + cs1_pin GPIO pin for CS1 (default 26 - BCM SPI5_CE1).
121 + cs0_spidev Set to 'off' to prevent the creation of a
122 + userspace device node /dev/spidev5.0 (default
123 + is 'on' or enabled).
124 + cs1_spidev Set to 'off' to prevent the creation of a
125 + userspace device node /dev/spidev5.1 (default
126 + is 'on' or enabled).
130 +Info: Enables spi6 with a single chip select (CS) line and associated spidev
131 + dev node. The gpio pin number for the CS line and spidev device node
132 + creation are configurable.
133 +Load: dtoverlay=spi6-1cs,<param>=<val>
134 +Params: cs0_pin GPIO pin for CS0 (default 18 - BCM SPI6_CE0).
135 + cs0_spidev Set to 'off' to prevent the creation of a
136 + userspace device node /dev/spidev6.0 (default
137 + is 'on' or enabled).
141 +Info: Enables spi6 with two chip select (CS) lines and associated spidev
142 + dev nodes. The gpio pin numbers for the CS lines and spidev device node
143 + creation are configurable.
144 +Load: dtoverlay=spi6-2cs,<param>=<val>
145 +Params: cs0_pin GPIO pin for CS0 (default 18 - BCM SPI6_CE0).
146 + cs1_pin GPIO pin for CS1 (default 27 - BCM SPI6_CE1).
147 + cs0_spidev Set to 'off' to prevent the creation of a
148 + userspace device node /dev/spidev6.0 (default
149 + is 'on' or enabled).
150 + cs1_spidev Set to 'off' to prevent the creation of a
151 + userspace device node /dev/spidev6.1 (default
152 + is 'on' or enabled).
156 Info: Overlay for activation of SSD1306 over I2C OLED display framebuffer.
157 Load: dtoverlay=ssd1306,<param>=<val>
159 +++ b/arch/arm/boot/dts/overlays/spi3-1cs-overlay.dts
166 + compatible = "brcm,bcm2838";
169 + target = <&spi3_cs_pins>;
170 + frag0: __overlay__ {
172 + brcm,function = <1>; /* output */
178 + frag1: __overlay__ {
179 + /* needed to avoid dtc warning */
180 + #address-cells = <1>;
183 + pinctrl-names = "default";
184 + pinctrl-0 = <&spi3_pins &spi3_cs_pins>;
185 + cs-gpios = <&gpio 0 1>;
188 + spidev3_0: spidev@0 {
189 + compatible = "spidev";
190 + reg = <0>; /* CE0 */
191 + #address-cells = <1>;
193 + spi-max-frequency = <125000000>;
200 + cs0_pin = <&frag0>,"brcm,pins:0",
201 + <&frag1>,"cs-gpios:4";
202 + cs0_spidev = <&spidev3_0>,"status";
206 +++ b/arch/arm/boot/dts/overlays/spi3-2cs-overlay.dts
213 + compatible = "brcm,bcm2838";
216 + target = <&spi3_cs_pins>;
217 + frag0: __overlay__ {
218 + brcm,pins = <0 24>;
219 + brcm,function = <1>; /* output */
225 + frag1: __overlay__ {
226 + /* needed to avoid dtc warning */
227 + #address-cells = <1>;
230 + pinctrl-names = "default";
231 + pinctrl-0 = <&spi3_pins &spi3_cs_pins>;
232 + cs-gpios = <&gpio 0 1>, <&gpio 24 1>;
235 + spidev3_0: spidev@0 {
236 + compatible = "spidev";
237 + reg = <0>; /* CE0 */
238 + #address-cells = <1>;
240 + spi-max-frequency = <125000000>;
244 + spidev3_1: spidev@1 {
245 + compatible = "spidev";
246 + reg = <1>; /* CE1 */
247 + #address-cells = <1>;
249 + spi-max-frequency = <125000000>;
256 + cs0_pin = <&frag0>,"brcm,pins:0",
257 + <&frag1>,"cs-gpios:4";
258 + cs1_pin = <&frag0>,"brcm,pins:4",
259 + <&frag1>,"cs-gpios:16";
260 + cs0_spidev = <&spidev3_0>,"status";
261 + cs1_spidev = <&spidev3_1>,"status";
265 +++ b/arch/arm/boot/dts/overlays/spi4-1cs-overlay.dts
272 + compatible = "brcm,bcm2838";
275 + target = <&spi4_cs_pins>;
276 + frag0: __overlay__ {
278 + brcm,function = <1>; /* output */
284 + frag1: __overlay__ {
285 + /* needed to avoid dtc warning */
286 + #address-cells = <1>;
289 + pinctrl-names = "default";
290 + pinctrl-0 = <&spi4_pins &spi4_cs_pins>;
291 + cs-gpios = <&gpio 4 1>;
294 + spidev4_0: spidev@0 {
295 + compatible = "spidev";
296 + reg = <0>; /* CE0 */
297 + #address-cells = <1>;
299 + spi-max-frequency = <125000000>;
306 + cs0_pin = <&frag0>,"brcm,pins:0",
307 + <&frag1>,"cs-gpios:4";
308 + cs0_spidev = <&spidev4_0>,"status";
312 +++ b/arch/arm/boot/dts/overlays/spi4-2cs-overlay.dts
319 + compatible = "brcm,bcm2838";
322 + target = <&spi4_cs_pins>;
323 + frag0: __overlay__ {
324 + brcm,pins = <4 25>;
325 + brcm,function = <1>; /* output */
331 + frag1: __overlay__ {
332 + /* needed to avoid dtc warning */
333 + #address-cells = <1>;
336 + pinctrl-names = "default";
337 + pinctrl-0 = <&spi4_pins &spi4_cs_pins>;
338 + cs-gpios = <&gpio 4 1>, <&gpio 25 1>;
341 + spidev4_0: spidev@0 {
342 + compatible = "spidev";
343 + reg = <0>; /* CE0 */
344 + #address-cells = <1>;
346 + spi-max-frequency = <125000000>;
350 + spidev4_1: spidev@1 {
351 + compatible = "spidev";
352 + reg = <1>; /* CE1 */
353 + #address-cells = <1>;
355 + spi-max-frequency = <125000000>;
362 + cs0_pin = <&frag0>,"brcm,pins:0",
363 + <&frag1>,"cs-gpios:4";
364 + cs1_pin = <&frag0>,"brcm,pins:4",
365 + <&frag1>,"cs-gpios:16";
366 + cs0_spidev = <&spidev4_0>,"status";
367 + cs1_spidev = <&spidev4_1>,"status";
371 +++ b/arch/arm/boot/dts/overlays/spi5-1cs-overlay.dts
378 + compatible = "brcm,bcm2838";
381 + target = <&spi5_cs_pins>;
382 + frag0: __overlay__ {
384 + brcm,function = <1>; /* output */
390 + frag1: __overlay__ {
391 + /* needed to avoid dtc warning */
392 + #address-cells = <1>;
395 + pinctrl-names = "default";
396 + pinctrl-0 = <&spi5_pins &spi5_cs_pins>;
397 + cs-gpios = <&gpio 12 1>;
400 + spidev5_0: spidev@0 {
401 + compatible = "spidev";
402 + reg = <0>; /* CE0 */
403 + #address-cells = <1>;
405 + spi-max-frequency = <125000000>;
412 + cs0_pin = <&frag0>,"brcm,pins:0",
413 + <&frag1>,"cs-gpios:4";
414 + cs0_spidev = <&spidev5_0>,"status";
418 +++ b/arch/arm/boot/dts/overlays/spi5-2cs-overlay.dts
425 + compatible = "brcm,bcm2838";
428 + target = <&spi5_cs_pins>;
429 + frag0: __overlay__ {
430 + brcm,pins = <12 26>;
431 + brcm,function = <1>; /* output */
437 + frag1: __overlay__ {
438 + /* needed to avoid dtc warning */
439 + #address-cells = <1>;
442 + pinctrl-names = "default";
443 + pinctrl-0 = <&spi5_pins &spi5_cs_pins>;
444 + cs-gpios = <&gpio 12 1>, <&gpio 26 1>;
447 + spidev5_0: spidev@0 {
448 + compatible = "spidev";
449 + reg = <0>; /* CE0 */
450 + #address-cells = <1>;
452 + spi-max-frequency = <125000000>;
456 + spidev5_1: spidev@1 {
457 + compatible = "spidev";
458 + reg = <1>; /* CE1 */
459 + #address-cells = <1>;
461 + spi-max-frequency = <125000000>;
468 + cs0_pin = <&frag0>,"brcm,pins:0",
469 + <&frag1>,"cs-gpios:4";
470 + cs1_pin = <&frag0>,"brcm,pins:4",
471 + <&frag1>,"cs-gpios:16";
472 + cs0_spidev = <&spidev5_0>,"status";
473 + cs1_spidev = <&spidev5_1>,"status";
477 +++ b/arch/arm/boot/dts/overlays/spi6-1cs-overlay.dts
484 + compatible = "brcm,bcm2838";
487 + target = <&spi6_cs_pins>;
488 + frag0: __overlay__ {
490 + brcm,function = <1>; /* output */
496 + frag1: __overlay__ {
497 + /* needed to avoid dtc warning */
498 + #address-cells = <1>;
501 + pinctrl-names = "default";
502 + pinctrl-0 = <&spi6_pins &spi6_cs_pins>;
503 + cs-gpios = <&gpio 18 1>;
506 + spidev6_0: spidev@0 {
507 + compatible = "spidev";
508 + reg = <0>; /* CE0 */
509 + #address-cells = <1>;
511 + spi-max-frequency = <125000000>;
518 + cs0_pin = <&frag0>,"brcm,pins:0",
519 + <&frag1>,"cs-gpios:4";
520 + cs0_spidev = <&spidev6_0>,"status";
524 +++ b/arch/arm/boot/dts/overlays/spi6-2cs-overlay.dts
531 + compatible = "brcm,bcm2838";
534 + target = <&spi6_cs_pins>;
535 + frag0: __overlay__ {
536 + brcm,pins = <18 27>;
537 + brcm,function = <1>; /* output */
543 + frag1: __overlay__ {
544 + /* needed to avoid dtc warning */
545 + #address-cells = <1>;
548 + pinctrl-names = "default";
549 + pinctrl-0 = <&spi6_pins &spi6_cs_pins>;
550 + cs-gpios = <&gpio 18 1>, <&gpio 27 1>;
553 + spidev6_0: spidev@0 {
554 + compatible = "spidev";
555 + reg = <0>; /* CE0 */
556 + #address-cells = <1>;
558 + spi-max-frequency = <125000000>;
562 + spidev6_1: spidev@1 {
563 + compatible = "spidev";
564 + reg = <1>; /* CE1 */
565 + #address-cells = <1>;
567 + spi-max-frequency = <125000000>;
574 + cs0_pin = <&frag0>,"brcm,pins:0",
575 + <&frag1>,"cs-gpios:4";
576 + cs1_pin = <&frag0>,"brcm,pins:4",
577 + <&frag1>,"cs-gpios:16";
578 + cs0_spidev = <&spidev6_0>,"status";
579 + cs1_spidev = <&spidev6_1>,"status";