1 --- a/arch/mips/bcm47xx/nvram.c
2 +++ b/arch/mips/bcm47xx/nvram.c
3 @@ -210,3 +210,30 @@ int bcm47xx_nvram_gpio_pin(const char *n
6 EXPORT_SYMBOL(bcm47xx_nvram_gpio_pin);
8 +char *nvram_get(const char *name)
10 + char *var, *value, *end, *eq;
18 + /* Look for name=value and return value */
19 + var = &nvram_buf[sizeof(struct nvram_header)];
20 + end = nvram_buf + sizeof(nvram_buf) - 2;
21 + end[0] = end[1] = '\0';
22 + for (; *var; var = value + strlen(value) + 1) {
23 + eq = strchr(var, '=');
27 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
33 +EXPORT_SYMBOL(nvram_get);
34 --- a/arch/mips/bcm47xx/Makefile
35 +++ b/arch/mips/bcm47xx/Makefile
38 obj-y += irq.o nvram.o prom.o serial.o setup.o time.o sprom.o
39 obj-y += board.o buttons.o leds.o workarounds.o
42 +++ b/arch/mips/bcm47xx/gpio.c
45 + * This file is subject to the terms and conditions of the GNU General Public
46 + * License. See the file "COPYING" in the main directory of this archive
49 + * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
50 + * Copyright (C) 2012 Hauke Mehrtens <hauke@hauke-m.de>
52 + * Parts of this file are based on Atheros AR71XX/AR724X/AR913X GPIO
55 +#include <linux/export.h>
56 +#include <linux/gpio.h>
57 +#include <linux/ssb/ssb_embedded.h>
58 +#include <linux/bcma/bcma.h>
62 +/* low level BCM47xx gpio api */
63 +u32 bcm47xx_gpio_in(u32 mask)
65 + switch (bcm47xx_bus_type) {
66 +#ifdef CONFIG_BCM47XX_SSB
67 + case BCM47XX_BUS_TYPE_SSB:
68 + return ssb_gpio_in(&bcm47xx_bus.ssb, mask);
70 +#ifdef CONFIG_BCM47XX_BCMA
71 + case BCM47XX_BUS_TYPE_BCMA:
72 + return bcma_chipco_gpio_in(&bcm47xx_bus.bcma.bus.drv_cc, mask);
77 +EXPORT_SYMBOL(bcm47xx_gpio_in);
79 +u32 bcm47xx_gpio_out(u32 mask, u32 value)
81 + switch (bcm47xx_bus_type) {
82 +#ifdef CONFIG_BCM47XX_SSB
83 + case BCM47XX_BUS_TYPE_SSB:
84 + return ssb_gpio_out(&bcm47xx_bus.ssb, mask, value);
86 +#ifdef CONFIG_BCM47XX_BCMA
87 + case BCM47XX_BUS_TYPE_BCMA:
88 + return bcma_chipco_gpio_out(&bcm47xx_bus.bcma.bus.drv_cc, mask,
94 +EXPORT_SYMBOL(bcm47xx_gpio_out);
96 +u32 bcm47xx_gpio_outen(u32 mask, u32 value)
98 + switch (bcm47xx_bus_type) {
99 +#ifdef CONFIG_BCM47XX_SSB
100 + case BCM47XX_BUS_TYPE_SSB:
101 + return ssb_gpio_outen(&bcm47xx_bus.ssb, mask, value);
103 +#ifdef CONFIG_BCM47XX_BCMA
104 + case BCM47XX_BUS_TYPE_BCMA:
105 + return bcma_chipco_gpio_outen(&bcm47xx_bus.bcma.bus.drv_cc,
111 +EXPORT_SYMBOL(bcm47xx_gpio_outen);
113 +u32 bcm47xx_gpio_control(u32 mask, u32 value)
115 + switch (bcm47xx_bus_type) {
116 +#ifdef CONFIG_BCM47XX_SSB
117 + case BCM47XX_BUS_TYPE_SSB:
118 + return ssb_gpio_control(&bcm47xx_bus.ssb, mask, value);
120 +#ifdef CONFIG_BCM47XX_BCMA
121 + case BCM47XX_BUS_TYPE_BCMA:
122 + return bcma_chipco_gpio_control(&bcm47xx_bus.bcma.bus.drv_cc,
128 +EXPORT_SYMBOL(bcm47xx_gpio_control);
130 +u32 bcm47xx_gpio_intmask(u32 mask, u32 value)
132 + switch (bcm47xx_bus_type) {
133 +#ifdef CONFIG_BCM47XX_SSB
134 + case BCM47XX_BUS_TYPE_SSB:
135 + return ssb_gpio_intmask(&bcm47xx_bus.ssb, mask, value);
137 +#ifdef CONFIG_BCM47XX_BCMA
138 + case BCM47XX_BUS_TYPE_BCMA:
139 + return bcma_chipco_gpio_intmask(&bcm47xx_bus.bcma.bus.drv_cc,
145 +EXPORT_SYMBOL(bcm47xx_gpio_intmask);
147 +u32 bcm47xx_gpio_polarity(u32 mask, u32 value)
149 + switch (bcm47xx_bus_type) {
150 +#ifdef CONFIG_BCM47XX_SSB
151 + case BCM47XX_BUS_TYPE_SSB:
152 + return ssb_gpio_polarity(&bcm47xx_bus.ssb, mask, value);
154 +#ifdef CONFIG_BCM47XX_BCMA
155 + case BCM47XX_BUS_TYPE_BCMA:
156 + return bcma_chipco_gpio_polarity(&bcm47xx_bus.bcma.bus.drv_cc,
162 +EXPORT_SYMBOL(bcm47xx_gpio_polarity);
163 --- a/arch/mips/include/asm/mach-bcm47xx/gpio.h
164 +++ b/arch/mips/include/asm/mach-bcm47xx/gpio.h
165 @@ -14,4 +14,11 @@ static inline int irq_to_gpio(unsigned i
169 +u32 bcm47xx_gpio_in(u32 mask);
170 +u32 bcm47xx_gpio_out(u32 mask, u32 value);
171 +u32 bcm47xx_gpio_outen(u32 mask, u32 value);
172 +u32 bcm47xx_gpio_control(u32 mask, u32 value);
173 +u32 bcm47xx_gpio_intmask(u32 mask, u32 value);
174 +u32 bcm47xx_gpio_polarity(u32 mask, u32 value);