4 #include <linux/types.h>
5 #include <linux/init.h>
7 #include <bcm63xx_regs.h>
10 * Macro to fetch bcm63xx cpu id and revision, should be optimized at
11 * compile time if only one CPU support is enabled (idea stolen from
14 #define BCM6338_CPU_ID 0x6338
15 #define BCM6345_CPU_ID 0x6345
16 #define BCM6348_CPU_ID 0x6348
17 #define BCM6358_CPU_ID 0x6358
19 void __init
bcm63xx_cpu_init(void);
20 u16
__bcm63xx_get_cpu_id(void);
21 u16
bcm63xx_get_cpu_rev(void);
22 unsigned int bcm63xx_get_cpu_freq(void);
24 #ifdef CONFIG_BCM63XX_CPU_6338
25 # ifdef bcm63xx_get_cpu_id
26 # undef bcm63xx_get_cpu_id
27 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
28 # define BCMCPU_RUNTIME_DETECT
30 # define bcm63xx_get_cpu_id() BCM6338_CPU_ID
32 # define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
34 # define BCMCPU_IS_6338() (0)
37 #ifdef CONFIG_BCM63XX_CPU_6345
38 # ifdef bcm63xx_get_cpu_id
39 # undef bcm63xx_get_cpu_id
40 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
41 # define BCMCPU_RUNTIME_DETECT
43 # define bcm63xx_get_cpu_id() BCM6345_CPU_ID
45 # define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
47 # define BCMCPU_IS_6345() (0)
50 #ifdef CONFIG_BCM63XX_CPU_6348
51 # ifdef bcm63xx_get_cpu_id
52 # undef bcm63xx_get_cpu_id
53 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
54 # define BCMCPU_RUNTIME_DETECT
56 # define bcm63xx_get_cpu_id() BCM6348_CPU_ID
58 # define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
60 # define BCMCPU_IS_6348() (0)
63 #ifdef CONFIG_BCM63XX_CPU_6358
64 # ifdef bcm63xx_get_cpu_id
65 # undef bcm63xx_get_cpu_id
66 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
67 # define BCMCPU_RUNTIME_DETECT
69 # define bcm63xx_get_cpu_id() BCM6358_CPU_ID
71 # define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
73 # define BCMCPU_IS_6358() (0)
76 #ifndef bcm63xx_get_cpu_id
77 #error "No CPU support configured"
81 * While registers sets are (mostly) the same across 63xx CPU, base
82 * address of these sets do change.
84 enum bcm63xx_regs_set
{
108 #define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
109 #define RSET_DSL_SIZE 4096
110 #define RSET_WDT_SIZE 12
111 #define RSET_ENET_SIZE 2048
112 #define RSET_ENETDMA_SIZE 2048
113 #define RSET_UART_SIZE 24
114 #define RSET_SPI_SIZE 256
115 #define RSET_UDC_SIZE 256
116 #define RSET_OHCI_SIZE 256
117 #define RSET_EHCI_SIZE 256
118 #define RSET_PCMCIA_SIZE 12
121 * 6338 register sets base address
124 #define BCM_6338_DSL_LMEM_BASE (0xfff00000)
125 #define BCM_6338_PERF_BASE (0xfffe0000)
126 #define BCM_6338_BB_BASE (0xfffe0100)
127 #define BCM_6338_TIMER_BASE (0xfffe0200)
128 #define BCM_6338_WDT_BASE (0xfffe021c)
129 #define BCM_6338_UART0_BASE (0xfffe0300)
130 #define BCM_6338_GPIO_BASE (0xfffe0400)
131 #define BCM_6338_SPI_BASE (0xfffe0c00)
132 #define BCM_6338_UDC0_BASE (0xdeadbeef)
133 #define BCM_6338_USBDMA_BASE (0xfffe2400)
134 #define BCM_6338_OHCI0_BASE (0xdeadbeef)
135 #define BCM_6338_OHCI_PRIV_BASE (0xfffe3000)
136 #define BCM_6338_USBH_PRIV_BASE (0xdeadbeef)
137 #define BCM_6338_MPI_BASE (0xfffe3160)
138 #define BCM_6338_PCMCIA_BASE (0xdeadbeef)
139 #define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
140 #define BCM_6338_DSL_BASE (0xfffe1000)
141 #define BCM_6338_SAR_BASE (0xfffe2000)
142 #define BCM_6338_UBUS_BASE (0xdeadbeef)
143 #define BCM_6338_ENET0_BASE (0xfffe2800)
144 #define BCM_6338_ENET1_BASE (0xdeadbeef)
145 #define BCM_6338_ENETDMA_BASE (0xfffe2400)
146 #define BCM_6338_EHCI0_BASE (0xdeadbeef)
147 #define BCM_6338_SDRAM_BASE (0xfffe3100)
148 #define BCM_6338_MEMC_BASE (0xdeadbeef)
149 #define BCM_6338_DDR_BASE (0xdeadbeef)
152 * 6345 register sets base address
154 #define BCM_6345_DSL_LMEM_BASE (0xfff00000)
155 #define BCM_6345_PERF_BASE (0xfffe0000)
156 #define BCM_6345_BB_BASE (0xfffe0100)
157 #define BCM_6345_TIMER_BASE (0xfffe0200)
158 #define BCM_6345_WDT_BASE (0xfffe021c)
159 #define BCM_6345_UART0_BASE (0xfffe0300)
160 #define BCM_6345_GPIO_BASE (0xfffe0400)
161 #define BCM_6345_SPI_BASE (0xdeadbeef)
162 #define BCM_6345_UDC0_BASE (0xdeadbeef)
163 #define BCM_6345_USBDMA_BASE (0xfffe2800)
164 #define BCM_6345_ENET0_BASE (0xfffe1800)
165 #define BCM_6345_ENETDMA_BASE (0xfffe2800)
166 #define BCM_6345_PCMCIA_BASE (0xfffe2028)
167 #define BCM_6345_MPI_BASE (0xdeadbeef)
168 #define BCM_6345_OHCI0_BASE (0xfffe2100)
169 #define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
170 #define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
171 #define BCM_6345_SDRAM_REGS_BASE (0xfffe2300)
172 #define BCM_6345_DSL_BASE (0xdeadbeef)
173 #define BCM_6345_SAR_BASE (0xdeadbeef)
174 #define BCM_6345_UBUS_BASE (0xdeadbeef)
175 #define BCM_6345_ENET1_BASE (0xdeadbeef)
176 #define BCM_6345_EHCI0_BASE (0xdeadbeef)
177 #define BCM_6345_SDRAM_BASE (0xfffe2300)
178 #define BCM_6345_MEMC_BASE (0xdeadbeef)
179 #define BCM_6345_DDR_BASE (0xdeadbeef)
182 * 6348 register sets base address
184 #define BCM_6348_DSL_LMEM_BASE (0xfff00000)
185 #define BCM_6348_PERF_BASE (0xfffe0000)
186 #define BCM_6348_BB_BASE (0xfffe0100)
187 #define BCM_6348_TIMER_BASE (0xfffe0200)
188 #define BCM_6348_WDT_BASE (0xfffe021c)
189 #define BCM_6348_UART0_BASE (0xfffe0300)
190 #define BCM_6348_GPIO_BASE (0xfffe0400)
191 #define BCM_6348_SPI_BASE (0xfffe0c00)
192 #define BCM_6348_UDC0_BASE (0xfffe1000)
193 #define BCM_6348_USBDMA_BASE (0xfffe1400)
194 #define BCM_6348_OHCI0_BASE (0xfffe1b00)
195 #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
196 #define BCM_6348_USBH_PRIV_BASE (0xdeadbeef)
197 #define BCM_6348_MPI_BASE (0xfffe2000)
198 #define BCM_6348_PCMCIA_BASE (0xfffe2054)
199 #define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
200 #define BCM_6348_DSL_BASE (0xfffe3000)
201 #define BCM_6348_SAR_BASE (0xfffe4000)
202 #define BCM_6348_UBUS_BASE (0xfffe5000)
203 #define BCM_6348_ENET0_BASE (0xfffe6000)
204 #define BCM_6348_ENET1_BASE (0xfffe6800)
205 #define BCM_6348_ENETDMA_BASE (0xfffe7000)
206 #define BCM_6348_EHCI0_BASE (0xdeadbeef)
207 #define BCM_6348_SDRAM_BASE (0xfffe2300)
208 #define BCM_6348_MEMC_BASE (0xdeadbeef)
209 #define BCM_6348_DDR_BASE (0xdeadbeef)
212 * 6358 register sets base address
214 #define BCM_6358_DSL_LMEM_BASE (0xfff00000)
215 #define BCM_6358_PERF_BASE (0xfffe0000)
216 #define BCM_6358_TIMER_BASE (0xfffe0040)
217 #define BCM_6358_WDT_BASE (0xfffe005c)
218 #define BCM_6358_GPIO_BASE (0xfffe0080)
219 #define BCM_6358_UART0_BASE (0xfffe0100)
220 #define BCM_6358_UDC0_BASE (0xfffe0400)
221 #define BCM_6358_SPI_BASE (0xfffe0800)
222 #define BCM_6358_MPI_BASE (0xfffe1000)
223 #define BCM_6358_PCMCIA_BASE (0xfffe1054)
224 #define BCM_6358_OHCI0_BASE (0xfffe1400)
225 #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
226 #define BCM_6358_USBH_PRIV_BASE (0xfffe1500)
227 #define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
228 #define BCM_6358_DSL_BASE (0xfffe3000)
229 #define BCM_6358_ENET0_BASE (0xfffe4000)
230 #define BCM_6358_ENET1_BASE (0xfffe4800)
231 #define BCM_6358_ENETDMA_BASE (0xfffe5000)
232 #define BCM_6358_EHCI0_BASE (0xfffe1300)
233 #define BCM_6358_SDRAM_BASE (0xdeadbeef)
234 #define BCM_6358_MEMC_BASE (0xfffe1200)
235 #define BCM_6358_DDR_BASE (0xfffe12a0)
238 extern const unsigned long *bcm63xx_regs_base
;
240 static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set
)
242 #ifdef BCMCPU_RUNTIME_DETECT
243 return bcm63xx_regs_base
[set
];
245 #ifdef CONFIG_BCM63XX_CPU_6338
248 return BCM_6338_DSL_LMEM_BASE
;
250 return BCM_6338_PERF_BASE
;
252 return BCM_6338_TIMER_BASE
;
254 return BCM_6338_WDT_BASE
;
256 return BCM_6338_UART0_BASE
;
258 return BCM_6338_GPIO_BASE
;
260 return BCM_6338_SPI_BASE
;
262 return BCM_6338_UDC0_BASE
;
264 return BCM_6338_OHCI0_BASE
;
266 return BCM_6338_OHCI_PRIV_BASE
;
268 return BCM_6338_USBH_PRIV_BASE
;
270 return BCM_6338_MPI_BASE
;
272 return BCM_6338_PCMCIA_BASE
;
274 return BCM_6338_DSL_BASE
;
276 return BCM_6338_ENET0_BASE
;
278 return BCM_6338_ENET1_BASE
;
280 return BCM_6338_ENETDMA_BASE
;
282 return BCM_6338_EHCI0_BASE
;
284 return BCM_6338_SDRAM_BASE
;
286 return BCM_6338_MEMC_BASE
;
288 return BCM_6338_DDR_BASE
;
291 #ifdef CONFIG_BCM63XX_CPU_6345
294 return BCM_6345_DSL_LMEM_BASE
;
296 return BCM_6345_PERF_BASE
;
298 return BCM_6345_TIMER_BASE
;
300 return BCM_6345_WDT_BASE
;
302 return BCM_6345_UART0_BASE
;
304 return BCM_6345_GPIO_BASE
;
306 return BCM_6345_SPI_BASE
;
308 return BCM_6345_UDC0_BASE
;
310 return BCM_6345_OHCI0_BASE
;
312 return BCM_6345_OHCI_PRIV_BASE
;
314 return BCM_6345_USBH_PRIV_BASE
;
316 return BCM_6345_MPI_BASE
;
318 return BCM_6345_PCMCIA_BASE
;
320 return BCM_6345_DSL_BASE
;
322 return BCM_6345_ENET0_BASE
;
324 return BCM_6345_ENETDMA_BASE
;
326 return BCM_6345_EHCI0_BASE
;
328 return BCM_6345_SDRAM_BASE
;
330 return BCM_6345_MEMC_BASE
;
332 return BCM_6345_DDR_BASE
;
335 #ifdef CONFIG_BCM63XX_CPU_6348
338 return BCM_6348_DSL_LMEM_BASE
;
340 return BCM_6348_PERF_BASE
;
342 return BCM_6348_TIMER_BASE
;
344 return BCM_6348_WDT_BASE
;
346 return BCM_6348_UART0_BASE
;
348 return BCM_6348_GPIO_BASE
;
350 return BCM_6348_SPI_BASE
;
352 return BCM_6348_UDC0_BASE
;
354 return BCM_6348_OHCI0_BASE
;
356 return BCM_6348_OHCI_PRIV_BASE
;
358 return BCM_6348_USBH_PRIV_BASE
;
360 return BCM_6348_MPI_BASE
;
362 return BCM_6348_PCMCIA_BASE
;
364 return BCM_6348_DSL_BASE
;
366 return BCM_6348_ENET0_BASE
;
368 return BCM_6348_ENET1_BASE
;
370 return BCM_6348_ENETDMA_BASE
;
372 return BCM_6348_EHCI0_BASE
;
374 return BCM_6348_SDRAM_BASE
;
376 return BCM_6348_MEMC_BASE
;
378 return BCM_6348_DDR_BASE
;
381 #ifdef CONFIG_BCM63XX_CPU_6358
384 return BCM_6358_DSL_LMEM_BASE
;
386 return BCM_6358_PERF_BASE
;
388 return BCM_6358_TIMER_BASE
;
390 return BCM_6358_WDT_BASE
;
392 return BCM_6358_UART0_BASE
;
394 return BCM_6358_GPIO_BASE
;
396 return BCM_6358_SPI_BASE
;
398 return BCM_6358_UDC0_BASE
;
400 return BCM_6358_OHCI0_BASE
;
402 return BCM_6358_OHCI_PRIV_BASE
;
404 return BCM_6358_USBH_PRIV_BASE
;
406 return BCM_6358_MPI_BASE
;
408 return BCM_6358_PCMCIA_BASE
;
410 return BCM_6358_ENET0_BASE
;
412 return BCM_6358_ENET1_BASE
;
414 return BCM_6358_ENETDMA_BASE
;
416 return BCM_6358_DSL_BASE
;
418 return BCM_6358_EHCI0_BASE
;
420 return BCM_6358_SDRAM_BASE
;
422 return BCM_6358_MEMC_BASE
;
424 return BCM_6358_DDR_BASE
;
433 * SPI register layout is not compatible
434 * accross CPU versions but it is software
438 enum bcm63xx_regs_spi
{
453 extern const unsigned long *bcm63xx_regs_spi
;
455 static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg
)
457 #ifdef BCMCPU_RUNTIME_DETECT
458 return bcm63xx_regs_spi
[reg
];
460 #ifdef CONFIG_BCM63XX_CPU_6338
463 return SPI_BCM_6338_SPI_CMD
;
465 return SPI_BCM_6338_SPI_INT_STATUS
;
466 case SPI_INT_MASK_ST
:
467 return SPI_BCM_6338_SPI_MASK_INT_ST
;
469 return SPI_BCM_6338_SPI_INT_MASK
;
471 return SPI_BCM_6338_SPI_ST
;
473 return SPI_BCM_6338_SPI_CLK_CFG
;
475 return SPI_BCM_6338_SPI_FILL_BYTE
;
477 return SPI_BCM_6338_SPI_MSG_TAIL
;
479 return SPI_BCM_6338_SPI_RX_TAIL
;
481 return SPI_BCM_6338_SPI_MSG_CTL
;
483 return SPI_BCM_6338_SPI_MSG_DATA
;
485 return SPI_BCM_6338_SPI_RX_DATA
;
488 #ifdef CONFIG_BCM63XX_CPU_6348
491 return SPI_BCM_6348_SPI_CMD
;
492 case SPI_INT_MASK_ST
:
493 return SPI_BCM_6348_SPI_MASK_INT_ST
;
495 return SPI_BCM_6348_SPI_INT_MASK
;
497 return SPI_BCM_6348_SPI_INT_STATUS
;
499 return SPI_BCM_6348_SPI_ST
;
501 return SPI_BCM_6348_SPI_CLK_CFG
;
503 return SPI_BCM_6348_SPI_FILL_BYTE
;
505 return SPI_BCM_6348_SPI_MSG_TAIL
;
507 return SPI_BCM_6348_SPI_RX_TAIL
;
509 return SPI_BCM_6348_SPI_MSG_CTL
;
511 return SPI_BCM_6348_SPI_MSG_DATA
;
513 return SPI_BCM_6348_SPI_RX_DATA
;
516 #ifdef CONFIG_BCM63XX_CPU_6358
519 return SPI_BCM_6358_SPI_CMD
;
521 return SPI_BCM_6358_SPI_INT_STATUS
;
522 case SPI_INT_MASK_ST
:
523 return SPI_BCM_6358_SPI_MASK_INT_ST
;
525 return SPI_BCM_6358_SPI_INT_MASK
;
527 return SPI_BCM_6358_SPI_STATUS
;
529 return SPI_BCM_6358_SPI_CLK_CFG
;
531 return SPI_BCM_6358_SPI_FILL_BYTE
;
533 return SPI_BCM_6358_SPI_MSG_TAIL
;
535 return SPI_BCM_6358_SPI_RX_TAIL
;
537 return SPI_BCM_6358_MSG_CTL
;
539 return SPI_BCM_6358_SPI_MSG_DATA
;
541 return SPI_BCM_6358_SPI_RX_DATA
;
549 * IRQ number changes across CPU too
574 #define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
575 #define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
576 #define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
577 #define BCM_6338_DG_IRQ (IRQ_INTERNAL_BASE + 4)
578 #define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
579 #define BCM_6338_ATM_IRQ (IRQ_INTERNAL_BASE + 6)
580 #define BCM_6338_UDC0_IRQ (IRQ_INTERNAL_BASE + 7)
581 #define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
582 #define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
583 #define BCM_6338_SDRAM_IRQ (IRQ_INTERNAL_BASE + 10)
584 #define BCM_6338_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 11)
585 #define BCM_6338_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 12)
586 #define BCM_6338_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13)
587 #define BCM_6338_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 14)
588 #define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
589 #define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
590 #define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17)
595 #define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
596 #define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
597 #define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)
598 #define BCM_6345_ATM_IRQ (IRQ_INTERNAL_BASE + 4)
599 #define BCM_6345_USB_IRQ (IRQ_INTERNAL_BASE + 5)
600 #define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
601 #define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
602 #define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1)
603 #define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2)
608 #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
609 #define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
610 #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
611 #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
612 #define BCM_6348_UDC0_IRQ (IRQ_INTERNAL_BASE + 6)
613 #define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
614 #define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
615 #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
616 #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
617 #define BCM_6348_USB_CNTL_RX_DMA (IRQ_INTERNAL_BASE + 14)
618 #define BCM_6348_USB_CNTL_TX_DMA (IRQ_INTERNAL_BASE + 15)
619 #define BCM_6348_USB_BULK_RX_DMA (IRQ_INTERNAL_BASE + 16)
620 #define BCM_6348_USB_BULK_TX_DMA (IRQ_INTERNAL_BASE + 17)
621 #define BCM_6348_USB_ISO_RX_DMA (IRQ_INTERNAL_BASE + 18)
622 #define BCM_6348_USB_ISO_TX_DMA (IRQ_INTERNAL_BASE + 19)
623 #define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
624 #define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)
625 #define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)
626 #define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)
627 #define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
628 #define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)
633 #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
634 #define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
635 #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
636 #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
637 #define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
638 #define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
639 #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
640 #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
641 #define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
642 #define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
643 #define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
644 #define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
645 #define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
646 #define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
647 #define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
649 extern const int *bcm63xx_irqs
;
651 static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq
)
653 return bcm63xx_irqs
[irq
];
657 * return installed memory size
659 unsigned int bcm63xx_get_memory_size(void);
661 #endif /* !BCM63XX_CPU_H_ */