1 From 4d3886359d6f6ac475e143d5f3e3b389542a0510 Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jogo@openwrt.org>
3 Date: Sun, 30 Nov 2014 14:53:12 +0100
4 Subject: [PATCH 17/20] irqchip: add support for bcm6345-style l2 irq
7 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
9 .../interrupt-controller/brcm,bcm6345-l2-intc.txt | 25 ++
10 drivers/irqchip/Kconfig | 4 +
11 drivers/irqchip/Makefile | 1 +
12 drivers/irqchip/irq-bcm6345-l2.c | 320 ++++++++++++++++++++
13 include/linux/irqchip/irq-bcm6345-l2-intc.h | 16 +
14 5 files changed, 366 insertions(+)
15 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-l2-intc.txt
16 create mode 100644 drivers/irqchip/irq-bcm6345-l2.c
17 create mode 100644 include/linux/irqchip/irq-bcm6345-l2-intc.h
20 +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-l2-intc.txt
22 +Broadcom BCM6345 Level 2 interrupt controller
26 +- compatible: should be "brcm,bcm6345-l2-intc"
27 +- reg: specifies the base physical address and size of the registers;
28 + multiple regs may be specified, and must match the amount of parent interrupts
29 +- interrupt-controller: identifies the node as an interrupt controller
30 +- #interrupt-cells: specifies the number of cells needed to encode an interrupt
32 +- interrupt-parent: specifies the phandle to the parent interrupt controller
33 + this one is cascaded from
34 +- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
35 + node, valid values depend on the type of parent interrupt controller
39 +periph_intc: interrupt-controller@f0406800 {
40 + compatible = "brcm,bcm6345-l2-intc";
41 + interrupt-parent = <&mips_intc>;
42 + #interrupt-cells = <1>;
43 + reg = <0x10000020 0x10> <0x10000030 0x10>;
44 + interrupt-controller;
45 + interrupts = <2>, <3>;
47 --- a/drivers/irqchip/Kconfig
48 +++ b/drivers/irqchip/Kconfig
49 @@ -30,6 +30,10 @@ config ARM_VIC_NR
50 The maximum number of VICs available in the system, for
53 +config BCM6345_L2_IRQ
60 --- a/drivers/irqchip/Makefile
61 +++ b/drivers/irqchip/Makefile
62 @@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
63 obj-$(CONFIG_ARCH_MVEBU) += irq-armada-370-xp.o
64 obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
65 obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
66 +obj-$(CONFIG_BCM6345_L2_IRQ) += irq-bcm6345-l2.o
67 obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
68 obj-$(CONFIG_METAG) += irq-metag-ext.o
69 obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
71 +++ b/drivers/irqchip/irq-bcm6345-l2.c
74 + * This file is subject to the terms and conditions of the GNU General Public
75 + * License. See the file "COPYING" in the main directory of this archive
78 + * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>
81 +#include <linux/ioport.h>
82 +#include <linux/irq.h>
83 +#include <linux/irqchip/chained_irq.h>
84 +#include <linux/irqchip/irq-bcm6345-l2-intc.h>
85 +#include <linux/kernel.h>
86 +#include <linux/of.h>
87 +#include <linux/of_irq.h>
88 +#include <linux/of_address.h>
89 +#include <linux/slab.h>
90 +#include <linux/spinlock.h>
92 +#ifdef CONFIG_BCM63XX
93 +#include <asm/mach-bcm63xx/bcm63xx_irq.h>
95 +#define VIRQ_BASE IRQ_INTERNAL_BASE
100 +#include "irqchip.h"
103 +#define MAX_PARENT_IRQS 2
104 +#define IRQS_PER_WORD 32
108 + void __iomem *base;
109 + void __iomem *en_reg[MAX_WORDS];
110 + void __iomem *status_reg[MAX_WORDS];
111 + u32 mask_cache[MAX_WORDS];
115 + struct irq_chip chip;
116 + struct intc_block block[MAX_PARENT_IRQS];
120 + struct irq_domain *domain;
124 +static void bcm6345_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
126 + struct intc_data *data = irq_desc_get_handler_data(desc);
127 + struct irq_chip *chip = irq_desc_get_chip(desc);
128 + struct intc_block *block;
131 + chained_irq_enter(chip, desc);
133 + for (idx = 0; idx < MAX_PARENT_IRQS; idx++)
134 + if (irq == data->block[idx].parent_irq)
135 + block = &data->block[idx];
137 + for (idx = 0; idx < data->num_words; idx++) {
138 + int base = idx * IRQS_PER_WORD;
139 + unsigned long pending;
142 + raw_spin_lock(data->lock);
143 + pending = __raw_readl(block->en_reg[idx]) &
144 + __raw_readl(block->status_reg[idx]);
145 + raw_spin_unlock(data->lock);
147 + for_each_set_bit(hw_irq, &pending, IRQS_PER_WORD) {
148 + generic_handle_irq(irq_find_mapping(data->domain, base + hw_irq));
152 + chained_irq_exit(chip, desc);
155 +static void bcm6345_l2_intc_irq_mask(struct irq_data *data)
157 + unsigned int i, reg, bit;
158 + struct intc_data *priv = data->domain->host_data;
159 + irq_hw_number_t hwirq = irqd_to_hwirq(data);
161 + reg = hwirq / IRQS_PER_WORD;
162 + bit = hwirq % IRQS_PER_WORD;
164 + raw_spin_lock(priv->lock);
165 + for (i = 0; i < MAX_PARENT_IRQS; i++) {
166 + struct intc_block *block = &priv->block[i];
169 + if (!block->parent_irq)
172 + val = __raw_readl(block->en_reg[reg]);
173 + __raw_writel(val & ~BIT(bit), block->en_reg[reg]);
175 + raw_spin_unlock(priv->lock);
178 +static void bcm6345_l2_intc_irq_unmask(struct irq_data *data)
180 + unsigned int i, reg, bit;
181 + struct intc_data *priv = data->domain->host_data;
182 + irq_hw_number_t hwirq = irqd_to_hwirq(data);
184 + reg = hwirq / IRQS_PER_WORD;
185 + bit = hwirq % IRQS_PER_WORD;
187 + raw_spin_lock(priv->lock);
188 + for (i = 0; i < MAX_PARENT_IRQS; i++) {
189 + struct intc_block *block = &priv->block[i];
192 + if (!block->parent_irq)
195 + val = __raw_readl(block->en_reg[reg]);
197 + if (block->mask_cache[reg] & BIT(bit))
202 + __raw_writel(val, block->en_reg[reg]);
205 + raw_spin_unlock(priv->lock);
209 +static int bcm6345_l2_intc_set_affinity(struct irq_data *data,
210 + const struct cpumask *mask,
213 + irq_hw_number_t hwirq = irqd_to_hwirq(data);
214 + struct intc_data *priv = data->domain->host_data;
215 + unsigned int i, reg, bit;
218 + reg = hwirq / IRQS_PER_WORD;
219 + bit = hwirq % IRQS_PER_WORD;
221 + /* we could route to more than one cpu, but performance
222 + suffers, so fix it to one.
224 + cpu = cpumask_any_and(mask, cpu_online_mask);
225 + if (cpu >= nr_cpu_ids)
228 + if (cpu >= MAX_PARENT_IRQS)
231 + if (!priv->block[cpu].parent_irq)
234 + raw_spin_lock(priv->lock);
235 + for (i = 0; i < MAX_PARENT_IRQS; i++) {
237 + priv->block[i].mask_cache[reg] |= BIT(bit);
239 + priv->block[i].mask_cache[reg] &= ~BIT(bit);
241 + raw_spin_unlock(priv->lock);
247 +static int bcm6345_l2_map(struct irq_domain *d, unsigned int irq,
248 + irq_hw_number_t hw)
250 + struct intc_data *priv = d->host_data;
252 + irq_set_chip_and_handler(irq, &priv->chip, handle_level_irq);
257 +static const struct irq_domain_ops bcm6345_l2_domain_ops = {
258 + .xlate = irq_domain_xlate_onecell,
259 + .map = bcm6345_l2_map,
262 +static int __init __bcm6345_l2_intc_init(struct device_node *node,
263 + int num_blocks, int *irq,
264 + void __iomem **base, int num_words)
266 + struct intc_data *data;
267 + unsigned int i, w, status_offset;
269 + data = kzalloc(sizeof(*data), GFP_KERNEL);
273 + status_offset = num_words * sizeof(u32);
275 + for (i = 0; i < num_blocks; i++) {
276 + struct intc_block *block = &data->block[i];
278 + block->parent_irq = irq[i];
279 + block->base = base[i];
281 + for (w = 0; w < num_words; w++) {
282 + int word_offset = sizeof(u32) * ((num_words - w) - 1);
284 + block->en_reg[w] = base[i] + word_offset;
285 + block->status_reg[w] = base[i] + status_offset;
286 + block->status_reg[w] += word_offset;
288 + /* route all interrups to line 0 by default */
290 + block->mask_cache[w] = 0xffffffff;
293 + irq_set_handler_data(block->parent_irq, data);
294 + irq_set_chained_handler(block->parent_irq,
295 + bcm6345_l2_intc_irq_handle);
298 + data->num_words = num_words;
300 + data->chip.name = "bcm6345-l2-intc";
301 + data->chip.irq_mask = bcm6345_l2_intc_irq_mask;
302 + data->chip.irq_unmask = bcm6345_l2_intc_irq_unmask;
305 + if (num_blocks > 1)
306 + data->chip.set_affinity = bcm6345_l2_intc_set_affinity;
309 + data->domain = irq_domain_add_simple(node, IRQS_PER_WORD * num_words,
310 + VIRQ_BASE, &bcm6345_l2_domain_ops,
312 + if (!data->domain) {
320 +void __init bcm6345_l2_intc_init(int num_blocks, int *irq, void __iomem **base,
323 + __bcm6345_l2_intc_init(NULL, num_blocks, irq, base, num_words);
327 +static int __init bcm6345_l2_intc_of_init(struct device_node *node,
328 + struct device_node *parent)
330 + struct resource res;
331 + int num_irqs, ret = -EINVAL;
332 + int irqs[MAX_PARENT_IRQS] = { 0 };
333 + void __iomem *bases[MAX_PARENT_IRQS] = { NULL };
337 + num_irqs = of_irq_count(node);
339 + if (num_irqs < 1 || num_irqs > MAX_PARENT_IRQS)
342 + for (i = 0; i < num_irqs; i++) {
343 + resource_size_t size;
345 + irqs[i] = irq_of_parse_and_map(node, i);
349 + if (of_address_to_resource(node, i, &res)) {
353 + size = resource_size(&res);
364 + if (words && words != size) {
370 + bases[i] = of_iomap(node, i);
377 + ret = __bcm6345_l2_intc_init(node, num_irqs, irqs, bases, words);
382 + for (i = 0; i < num_irqs; i++) {
384 + irq_dispose_mapping(irqs[i]);
390 +IRQCHIP_DECLARE(bcm6345_l2_intc, "brcm,bcm6345-l2-intc",
391 + bcm6345_l2_intc_of_init);
394 +++ b/include/linux/irqchip/irq-bcm6345-l2-intc.h
397 + * This file is subject to the terms and conditions of the GNU General Public
398 + * License. See the file "COPYING" in the main directory of this archive
399 + * for more details.
401 + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
402 + * Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr>
405 +#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_L2_INTC_H
406 +#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_L2_INTC_H
408 +void bcm6345_l2_intc_init(int num_blocks, int *irq, void __iomem **base,
411 +#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_L2_INTC_H */