1 From 96ce0a9d195b2781d6f8d919dea8056b1c409703 Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jogo@openwrt.org>
3 Date: Thu, 25 Apr 2013 00:24:06 +0200
4 Subject: [PATCH 04/10] MIPS: BCM63XX: append irq line to irq_{stat,mask}*
6 The SMP capable irq controllers have two interrupt output pins which are
7 controlled through separate registers, so make the variables arrays.
9 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
11 arch/mips/bcm63xx/irq.c | 51 ++++++++++++-----------
12 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 16 +++----
13 2 files changed, 34 insertions(+), 33 deletions(-)
15 --- a/arch/mips/bcm63xx/irq.c
16 +++ b/arch/mips/bcm63xx/irq.c
18 #include <bcm63xx_io.h>
19 #include <bcm63xx_irq.h>
21 -static u32 irq_stat_addr, irq_mask_addr;
22 +static u32 irq_stat_addr[2];
23 +static u32 irq_mask_addr[2];
24 static void (*dispatch_internal)(void);
25 static int is_ext_irq_cascaded;
26 static unsigned int ext_irq_count;
27 @@ -64,8 +65,8 @@ void __dispatch_internal_##width(void)
28 for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
31 - val = bcm_readl(irq_stat_addr + src * sizeof(u32)); \
32 - val &= bcm_readl(irq_mask_addr + src * sizeof(u32)); \
33 + val = bcm_readl(irq_stat_addr[0] + src * sizeof(u32)); \
34 + val &= bcm_readl(irq_mask_addr[0] + src * sizeof(u32)); \
35 pending[--tgt] = val; \
38 @@ -92,9 +93,9 @@ static void __internal_irq_mask_##width(
39 unsigned reg = (irq / 32) ^ (width/32 - 1); \
40 unsigned bit = irq & 0x1f; \
42 - val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
43 + val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \
45 - bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
46 + bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \
49 static void __internal_irq_unmask_##width(unsigned int irq) \
50 @@ -103,9 +104,9 @@ static void __internal_irq_unmask_##widt
51 unsigned reg = (irq / 32) ^ (width/32 - 1); \
52 unsigned bit = irq & 0x1f; \
54 - val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
55 + val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \
57 - bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
58 + bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \
61 BUILD_IPIC_INTERNAL(32);
62 @@ -339,20 +340,20 @@ static void bcm63xx_init_irq(void)
66 - irq_stat_addr = bcm63xx_regset_address(RSET_PERF);
67 - irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
68 + irq_stat_addr[0] = bcm63xx_regset_address(RSET_PERF);
69 + irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF);
71 switch (bcm63xx_get_cpu_id()) {
73 - irq_stat_addr += PERF_IRQSTAT_3368_REG;
74 - irq_mask_addr += PERF_IRQMASK_3368_REG;
75 + irq_stat_addr[0] += PERF_IRQSTAT_3368_REG;
76 + irq_mask_addr[0] += PERF_IRQMASK_3368_REG;
79 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
82 - irq_stat_addr += PERF_IRQSTAT_6328_REG;
83 - irq_mask_addr += PERF_IRQMASK_6328_REG;
84 + irq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0);
85 + irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0);
88 is_ext_irq_cascaded = 1;
89 @@ -361,29 +362,29 @@ static void bcm63xx_init_irq(void)
90 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
93 - irq_stat_addr += PERF_IRQSTAT_6338_REG;
94 - irq_mask_addr += PERF_IRQMASK_6338_REG;
95 + irq_stat_addr[0] += PERF_IRQSTAT_6338_REG;
96 + irq_mask_addr[0] += PERF_IRQMASK_6338_REG;
99 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
102 - irq_stat_addr += PERF_IRQSTAT_6345_REG;
103 - irq_mask_addr += PERF_IRQMASK_6345_REG;
104 + irq_stat_addr[0] += PERF_IRQSTAT_6345_REG;
105 + irq_mask_addr[0] += PERF_IRQMASK_6345_REG;
108 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
111 - irq_stat_addr += PERF_IRQSTAT_6348_REG;
112 - irq_mask_addr += PERF_IRQMASK_6348_REG;
113 + irq_stat_addr[0] += PERF_IRQSTAT_6348_REG;
114 + irq_mask_addr[0] += PERF_IRQMASK_6348_REG;
117 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
120 - irq_stat_addr += PERF_IRQSTAT_6358_REG;
121 - irq_mask_addr += PERF_IRQMASK_6358_REG;
122 + irq_stat_addr[0] += PERF_IRQSTAT_6358_REG(0);
123 + irq_mask_addr[0] += PERF_IRQMASK_6358_REG(0);
126 is_ext_irq_cascaded = 1;
127 @@ -392,8 +393,8 @@ static void bcm63xx_init_irq(void)
128 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
131 - irq_stat_addr += PERF_IRQSTAT_6362_REG;
132 - irq_mask_addr += PERF_IRQMASK_6362_REG;
133 + irq_stat_addr[0] += PERF_IRQSTAT_6362_REG(0);
134 + irq_mask_addr[0] += PERF_IRQMASK_6362_REG(0);
137 is_ext_irq_cascaded = 1;
138 @@ -402,8 +403,8 @@ static void bcm63xx_init_irq(void)
139 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
142 - irq_stat_addr += PERF_IRQSTAT_6368_REG;
143 - irq_mask_addr += PERF_IRQMASK_6368_REG;
144 + irq_stat_addr[0] += PERF_IRQSTAT_6368_REG(0);
145 + irq_mask_addr[0] += PERF_IRQMASK_6368_REG(0);
148 is_ext_irq_cascaded = 1;
149 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
150 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
151 @@ -215,23 +215,23 @@
153 /* Interrupt Mask register */
154 #define PERF_IRQMASK_3368_REG 0xc
155 -#define PERF_IRQMASK_6328_REG 0x20
156 +#define PERF_IRQMASK_6328_REG(x) (0x20 + (x) * 0x10)
157 #define PERF_IRQMASK_6338_REG 0xc
158 #define PERF_IRQMASK_6345_REG 0xc
159 #define PERF_IRQMASK_6348_REG 0xc
160 -#define PERF_IRQMASK_6358_REG 0xc
161 -#define PERF_IRQMASK_6362_REG 0x20
162 -#define PERF_IRQMASK_6368_REG 0x20
163 +#define PERF_IRQMASK_6358_REG(x) (0xc + (x) * 0x2c)
164 +#define PERF_IRQMASK_6362_REG(x) (0x20 + (x) * 0x10)
165 +#define PERF_IRQMASK_6368_REG(x) (0x20 + (x) * 0x10)
167 /* Interrupt Status register */
168 #define PERF_IRQSTAT_3368_REG 0x10
169 -#define PERF_IRQSTAT_6328_REG 0x28
170 +#define PERF_IRQSTAT_6328_REG(x) (0x28 + (x) * 0x10)
171 #define PERF_IRQSTAT_6338_REG 0x10
172 #define PERF_IRQSTAT_6345_REG 0x10
173 #define PERF_IRQSTAT_6348_REG 0x10
174 -#define PERF_IRQSTAT_6358_REG 0x10
175 -#define PERF_IRQSTAT_6362_REG 0x28
176 -#define PERF_IRQSTAT_6368_REG 0x28
177 +#define PERF_IRQSTAT_6358_REG(x) (0x10 + (x) * 0x2c)
178 +#define PERF_IRQSTAT_6362_REG(x) (0x28 + (x) * 0x10)
179 +#define PERF_IRQSTAT_6368_REG(x) (0x28 + (x) * 0x10)
181 /* External Interrupt Configuration register */
182 #define PERF_EXTIRQ_CFG_REG_3368 0x14