2 * Gateworks Corporation Laguna Platform
4 * Copyright 2000 Deep Blue Solutions Ltd
5 * Copyright 2008 ARM Limited
6 * Copyright 2008 Cavium Networks
8 * Copyright 2010 MontaVista Software, LLC.
9 * Anton Vorontsov <avorontsov@mvista.com>
10 * Copyright 2011 Gateworks Corporation
11 * Chris Lang <clang@gateworks.com>
12 * Copyright 2012-2013 Gateworks Corporation
13 * Tim Harvey <tharvey@gateworks.com>
15 * This file is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License, Version 2, as
17 * published by the Free Software Foundation.
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/compiler.h>
24 #include <linux/gpio.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/serial_core.h>
27 #include <linux/serial_8250.h>
28 #include <linux/platform_device.h>
29 #include <linux/mtd/mtd.h>
30 #include <linux/mtd/physmap.h>
31 #include <linux/mtd/partitions.h>
32 #include <linux/leds.h>
33 #include <linux/i2c.h>
34 #include <linux/i2c/at24.h>
35 #include <linux/i2c/pca953x.h>
36 #include <linux/spi/spi.h>
37 #include <linux/spi/flash.h>
38 #include <linux/if_ether.h>
39 #include <linux/pps-gpio.h>
40 #include <linux/usb/ehci_pdriver.h>
41 #include <linux/usb/ohci_pdriver.h>
42 #include <asm/setup.h>
43 #include <asm/mach-types.h>
44 #include <asm/mach/arch.h>
45 #include <asm/mach/map.h>
46 #include <asm/mach/time.h>
47 #include <mach/cns3xxx.h>
48 #include <mach/irqs.h>
49 #include <mach/platform.h>
51 #include <mach/gpio.h>
52 #include <asm/hardware/gic.h>
56 #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
59 #define ETH0_LOAD BIT(0)
60 #define ETH1_LOAD BIT(1)
61 #define ETH2_LOAD BIT(2)
62 #define SATA0_LOAD BIT(3)
63 #define SATA1_LOAD BIT(4)
64 #define PCM_LOAD BIT(5)
65 #define I2S_LOAD BIT(6)
66 #define SPI0_LOAD BIT(7)
67 #define SPI1_LOAD BIT(8)
68 #define PCIE0_LOAD BIT(9)
69 #define PCIE1_LOAD BIT(10)
70 #define USB0_LOAD BIT(11)
71 #define USB1_LOAD BIT(12)
72 #define USB1_ROUTE BIT(13)
73 #define SD_LOAD BIT(14)
74 #define UART0_LOAD BIT(15)
75 #define UART1_LOAD BIT(16)
76 #define UART2_LOAD BIT(17)
77 #define MPCI0_LOAD BIT(18)
78 #define MPCI1_LOAD BIT(19)
79 #define MPCI2_LOAD BIT(20)
80 #define MPCI3_LOAD BIT(21)
81 #define FP_BUT_LOAD BIT(22)
82 #define FP_BUT_HEADER_LOAD BIT(23)
83 #define FP_LED_LOAD BIT(24)
84 #define FP_LED_HEADER_LOAD BIT(25)
85 #define FP_TAMPER_LOAD BIT(26)
86 #define HEADER_33V_LOAD BIT(27)
87 #define SATA_POWER_LOAD BIT(28)
88 #define FP_POWER_LOAD BIT(29)
89 #define GPIO_HEADER_LOAD BIT(30)
90 #define GSP_BAT_LOAD BIT(31)
93 #define FAN_LOAD BIT(0)
94 #define SPI_FLASH_LOAD BIT(1)
95 #define NOR_FLASH_LOAD BIT(2)
96 #define GPS_LOAD BIT(3)
97 #define SUPPLY_5V_LOAD BIT(6)
98 #define SUPPLY_33V_LOAD BIT(7)
100 struct laguna_board_info
{
108 static struct laguna_board_info laguna_info __initdata
;
113 static struct mtd_partition laguna_nor_partitions
[] = {
118 .mask_flags
= MTD_WRITEABLE
,
126 .offset
= SZ_256K
+ SZ_128K
,
129 .size
= SZ_16M
- SZ_256K
- SZ_128K
- SZ_2M
,
130 .offset
= SZ_256K
+ SZ_128K
+ SZ_2M
,
134 static struct physmap_flash_data laguna_nor_pdata
= {
136 .parts
= laguna_nor_partitions
,
137 .nr_parts
= ARRAY_SIZE(laguna_nor_partitions
),
140 static struct resource laguna_nor_res
= {
141 .start
= CNS3XXX_FLASH_BASE
,
142 .end
= CNS3XXX_FLASH_BASE
+ SZ_128M
- 1,
143 .flags
= IORESOURCE_MEM
| IORESOURCE_MEM_32BIT
,
146 static struct platform_device laguna_nor_pdev
= {
147 .name
= "physmap-flash",
149 .resource
= &laguna_nor_res
,
152 .platform_data
= &laguna_nor_pdata
,
159 static struct mtd_partition laguna_spi_partitions
[] = {
164 .mask_flags
= MTD_WRITEABLE
,
171 .size
= SZ_1M
+ SZ_512K
,
175 .size
= SZ_16M
- SZ_2M
,
180 static struct flash_platform_data laguna_spi_pdata
= {
181 .parts
= laguna_spi_partitions
,
182 .nr_parts
= ARRAY_SIZE(laguna_spi_partitions
),
185 static struct spi_board_info __initdata laguna_spi_devices
[] = {
187 .modalias
= "m25p80",
188 .platform_data
= &laguna_spi_pdata
,
189 .max_speed_hz
= 50000000,
195 static struct platform_device laguna_spi_controller
= {
196 .name
= "cns3xxx_spi",
202 static struct gpio_led laguna_gpio_leds
[] = {
204 .name
= "user1", /* Green Led */
208 .name
= "user2", /* Red Led */
212 .name
= "pwr1", /* Green Led */
216 .name
= "pwr2", /* Yellow Led */
220 .name
= "txd1", /* Green Led */
224 .name
= "txd2", /* Yellow Led */
228 .name
= "rxd1", /* Green Led */
232 .name
= "rxd2", /* Yellow Led */
236 .name
= "ser1", /* Green Led */
240 .name
= "ser2", /* Yellow Led */
244 .name
= "enet1", /* Green Led */
248 .name
= "enet2", /* Yellow Led */
252 .name
= "sig1_1", /* Green Led */
256 .name
= "sig1_2", /* Yellow Led */
260 .name
= "sig2_1", /* Green Led */
264 .name
= "sig2_2", /* Yellow Led */
268 .name
= "sig3_1", /* Green Led */
272 .name
= "sig3_2", /* Yellow Led */
276 .name
= "net1", /*Green Led */
280 .name
= "net2", /* Red Led */
284 .name
= "mod1", /* Green Led */
288 .name
= "mod2", /* Red Led */
294 static struct gpio_led_platform_data laguna_gpio_leds_data
= {
296 .leds
= laguna_gpio_leds
,
299 static struct platform_device laguna_gpio_leds_device
= {
302 .dev
.platform_data
= &laguna_gpio_leds_data
,
308 static struct cns3xxx_plat_info laguna_net_data
= {
317 static struct platform_device laguna_net_device
= {
318 .name
= "cns3xxx_eth",
320 .dev
.platform_data
= &laguna_net_data
,
326 static void __init
laguna_early_serial_setup(void)
328 #ifdef CONFIG_SERIAL_8250_CONSOLE
329 static struct uart_port laguna_serial_port
= {
330 .membase
= (void __iomem
*)CNS3XXX_UART0_BASE_VIRT
,
331 .mapbase
= CNS3XXX_UART0_BASE
,
332 .irq
= IRQ_CNS3XXX_UART0
,
334 .flags
= UPF_BOOT_AUTOCONF
| UPF_FIXED_TYPE
,
342 early_serial_setup(&laguna_serial_port
);
346 static struct resource laguna_uart_resources
[] = {
348 .start
= CNS3XXX_UART0_BASE
,
349 .end
= CNS3XXX_UART0_BASE
+ SZ_4K
- 1,
350 .flags
= IORESOURCE_MEM
352 .start
= CNS3XXX_UART2_BASE
,
353 .end
= CNS3XXX_UART2_BASE
+ SZ_4K
- 1,
354 .flags
= IORESOURCE_MEM
356 .start
= CNS3XXX_UART2_BASE
,
357 .end
= CNS3XXX_UART2_BASE
+ SZ_4K
- 1,
358 .flags
= IORESOURCE_MEM
362 static struct plat_serial8250_port laguna_uart_data
[] = {
364 .membase
= (char*) (CNS3XXX_UART0_BASE_VIRT
),
365 .mapbase
= (CNS3XXX_UART0_BASE
),
366 .irq
= IRQ_CNS3XXX_UART0
,
368 .flags
= UPF_BOOT_AUTOCONF
| UPF_FIXED_TYPE
| UPF_NO_TXEN_TEST
,
373 .membase
= (char*) (CNS3XXX_UART1_BASE_VIRT
),
374 .mapbase
= (CNS3XXX_UART1_BASE
),
375 .irq
= IRQ_CNS3XXX_UART1
,
377 .flags
= UPF_BOOT_AUTOCONF
| UPF_FIXED_TYPE
| UPF_NO_TXEN_TEST
,
382 .membase
= (char*) (CNS3XXX_UART2_BASE_VIRT
),
383 .mapbase
= (CNS3XXX_UART2_BASE
),
384 .irq
= IRQ_CNS3XXX_UART2
,
386 .flags
= UPF_BOOT_AUTOCONF
| UPF_FIXED_TYPE
| UPF_NO_TXEN_TEST
,
394 static struct platform_device laguna_uart
= {
395 .name
= "serial8250",
396 .id
= PLAT8250_DEV_PLATFORM
,
397 .dev
.platform_data
= laguna_uart_data
,
399 .resource
= laguna_uart_resources
405 static struct resource cns3xxx_usb_ehci_resources
[] = {
407 .start
= CNS3XXX_USB_BASE
,
408 .end
= CNS3XXX_USB_BASE
+ SZ_16M
- 1,
409 .flags
= IORESOURCE_MEM
,
412 .start
= IRQ_CNS3XXX_USB_EHCI
,
413 .flags
= IORESOURCE_IRQ
,
417 static u64 cns3xxx_usb_ehci_dma_mask
= DMA_BIT_MASK(32);
419 static int csn3xxx_usb_power_on(struct platform_device
*pdev
)
422 * EHCI and OHCI share the same clock and power,
423 * resetting twice would cause the 1st controller been reset.
424 * Therefore only do power up at the first up device, and
425 * power down at the last down device.
427 * Set USB AHB INCR length to 16
429 if (atomic_inc_return(&usb_pwr_ref
) == 1) {
430 cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB
);
431 cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST
);
432 cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST
);
433 __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG
) | (0X2 << 24)),
434 MISC_CHIP_CONFIG_REG
);
440 static void csn3xxx_usb_power_off(struct platform_device
*pdev
)
443 * EHCI and OHCI share the same clock and power,
444 * resetting twice would cause the 1st controller been reset.
445 * Therefore only do power up at the first up device, and
446 * power down at the last down device.
448 if (atomic_dec_return(&usb_pwr_ref
) == 0)
449 cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST
);
452 static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata
= {
453 .power_on
= csn3xxx_usb_power_on
,
454 .power_off
= csn3xxx_usb_power_off
,
457 static struct platform_device cns3xxx_usb_ehci_device
= {
458 .name
= "ehci-platform",
459 .num_resources
= ARRAY_SIZE(cns3xxx_usb_ehci_resources
),
460 .resource
= cns3xxx_usb_ehci_resources
,
462 .dma_mask
= &cns3xxx_usb_ehci_dma_mask
,
463 .coherent_dma_mask
= DMA_BIT_MASK(32),
464 .platform_data
= &cns3xxx_usb_ehci_pdata
,
468 static struct resource cns3xxx_usb_ohci_resources
[] = {
470 .start
= CNS3XXX_USB_OHCI_BASE
,
471 .end
= CNS3XXX_USB_OHCI_BASE
+ SZ_16M
- 1,
472 .flags
= IORESOURCE_MEM
,
475 .start
= IRQ_CNS3XXX_USB_OHCI
,
476 .flags
= IORESOURCE_IRQ
,
480 static u64 cns3xxx_usb_ohci_dma_mask
= DMA_BIT_MASK(32);
482 static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata
= {
484 .power_on
= csn3xxx_usb_power_on
,
485 .power_off
= csn3xxx_usb_power_off
,
488 static struct platform_device cns3xxx_usb_ohci_device
= {
489 .name
= "ohci-platform",
490 .num_resources
= ARRAY_SIZE(cns3xxx_usb_ohci_resources
),
491 .resource
= cns3xxx_usb_ohci_resources
,
493 .dma_mask
= &cns3xxx_usb_ohci_dma_mask
,
494 .coherent_dma_mask
= DMA_BIT_MASK(32),
495 .platform_data
= &cns3xxx_usb_ohci_pdata
,
499 static struct resource cns3xxx_usb_otg_resources
[] = {
501 .start
= CNS3XXX_USBOTG_BASE
,
502 .end
= CNS3XXX_USBOTG_BASE
+ SZ_16M
- 1,
503 .flags
= IORESOURCE_MEM
,
506 .start
= IRQ_CNS3XXX_USB_OTG
,
507 .flags
= IORESOURCE_IRQ
,
511 static u64 cns3xxx_usb_otg_dma_mask
= DMA_BIT_MASK(32);
513 static struct platform_device cns3xxx_usb_otg_device
= {
515 .num_resources
= ARRAY_SIZE(cns3xxx_usb_otg_resources
),
516 .resource
= cns3xxx_usb_otg_resources
,
518 .dma_mask
= &cns3xxx_usb_otg_dma_mask
,
519 .coherent_dma_mask
= DMA_BIT_MASK(32),
526 static struct resource laguna_i2c_resource
[] = {
528 .start
= CNS3XXX_SSP_BASE
+ 0x20,
530 .flags
= IORESOURCE_MEM
,
532 .start
= IRQ_CNS3XXX_I2C
,
533 .flags
= IORESOURCE_IRQ
,
537 static struct platform_device laguna_i2c_controller
= {
538 .name
= "cns3xxx-i2c",
540 .resource
= laguna_i2c_resource
,
543 static struct memory_accessor
*at24_mem_acc
;
545 static void at24_setup(struct memory_accessor
*mem_acc
, void *context
)
549 at24_mem_acc
= mem_acc
;
551 /* Read MAC addresses */
552 if (at24_mem_acc
->read(at24_mem_acc
, buf
, 0x100, 6) == 6)
553 memcpy(&laguna_net_data
.hwaddr
[0], buf
, ETH_ALEN
);
554 if (at24_mem_acc
->read(at24_mem_acc
, buf
, 0x106, 6) == 6)
555 memcpy(&laguna_net_data
.hwaddr
[1], buf
, ETH_ALEN
);
556 if (at24_mem_acc
->read(at24_mem_acc
, buf
, 0x10C, 6) == 6)
557 memcpy(&laguna_net_data
.hwaddr
[2], buf
, ETH_ALEN
);
558 if (at24_mem_acc
->read(at24_mem_acc
, buf
, 0x112, 6) == 6)
559 memcpy(&laguna_net_data
.hwaddr
[3], buf
, ETH_ALEN
);
561 /* Read out Model Information */
562 if (at24_mem_acc
->read(at24_mem_acc
, buf
, 0x130, 16) == 16)
563 memcpy(&laguna_info
.model
, buf
, 16);
564 if (at24_mem_acc
->read(at24_mem_acc
, buf
, 0x140, 1) == 1)
565 memcpy(&laguna_info
.nor_flash_size
, buf
, 1);
566 if (at24_mem_acc
->read(at24_mem_acc
, buf
, 0x141, 1) == 1)
567 memcpy(&laguna_info
.spi_flash_size
, buf
, 1);
568 if (at24_mem_acc
->read(at24_mem_acc
, buf
, 0x142, 4) == 4)
569 memcpy(&laguna_info
.config_bitmap
, buf
, 4);
570 if (at24_mem_acc
->read(at24_mem_acc
, buf
, 0x146, 4) == 4)
571 memcpy(&laguna_info
.config2_bitmap
, buf
, 4);
574 static struct at24_platform_data laguna_eeprom_info
= {
577 .flags
= AT24_FLAG_READONLY
,
581 static struct pca953x_platform_data laguna_pca_data
= {
586 static struct pca953x_platform_data laguna_pca2_data
= {
591 static struct i2c_board_info __initdata laguna_i2c_devices
[] = {
593 I2C_BOARD_INFO("pca9555", 0x23),
594 .platform_data
= &laguna_pca_data
,
596 I2C_BOARD_INFO("pca9555", 0x27),
597 .platform_data
= &laguna_pca2_data
,
599 I2C_BOARD_INFO("gsp", 0x29),
601 I2C_BOARD_INFO ("24c08",0x50),
602 .platform_data
= &laguna_eeprom_info
,
604 I2C_BOARD_INFO("ds1672", 0x68),
612 static struct resource laguna_watchdog_resources
[] = {
614 .start
= CNS3XXX_TC11MP_TWD_BASE
+ 0x100, // CPU0 watchdog
615 .end
= CNS3XXX_TC11MP_TWD_BASE
+ SZ_4K
- 1,
616 .flags
= IORESOURCE_MEM
,
620 static struct platform_device laguna_watchdog
= {
621 .name
= "mpcore_wdt",
623 .num_resources
= ARRAY_SIZE(laguna_watchdog_resources
),
624 .resource
= laguna_watchdog_resources
,
630 static struct pps_gpio_platform_data laguna_pps_data
= {
632 .gpio_label
= "GPS_PPS",
633 .assert_falling_edge
= 0,
637 static struct platform_device laguna_pps_device
= {
640 .dev
.platform_data
= &laguna_pps_data
,
647 static struct gpio laguna_gpio_gw2391
[] = {
648 { 0, GPIOF_IN
, "*GPS_PPS" },
649 { 1, GPIOF_IN
, "*GSC_IRQ#" },
650 { 2, GPIOF_IN
, "*USB_FAULT#" },
651 { 5, GPIOF_OUT_INIT_LOW
, "*USB0_PCI_SEL" },
652 { 6, GPIOF_OUT_INIT_HIGH
, "*USB_VBUS_EN" },
653 { 7, GPIOF_OUT_INIT_LOW
, "*USB1_PCI_SEL" },
654 { 8, GPIOF_OUT_INIT_HIGH
, "*PERST#" },
655 { 9, GPIOF_OUT_INIT_LOW
, "*FP_SER_EN#" },
656 { 100, GPIOF_IN
, "*USER_PB#" },
657 { 103, GPIOF_OUT_INIT_HIGH
, "*V5_EN" },
658 { 108, GPIOF_IN
, "DIO0" },
659 { 109, GPIOF_IN
, "DIO1" },
660 { 110, GPIOF_IN
, "DIO2" },
661 { 111, GPIOF_IN
, "DIO3" },
662 { 112, GPIOF_IN
, "DIO4" },
665 static struct gpio laguna_gpio_gw2388
[] = {
666 { 0, GPIOF_IN
, "*GPS_PPS" },
667 { 1, GPIOF_IN
, "*GSC_IRQ#" },
668 { 3, GPIOF_IN
, "*USB_FAULT#" },
669 { 6, GPIOF_OUT_INIT_HIGH
, "*USB_VBUS_EN" },
670 { 7, GPIOF_OUT_INIT_LOW
, "*GSM_SEL0" },
671 { 8, GPIOF_OUT_INIT_LOW
, "*GSM_SEL1" },
672 { 9, GPIOF_OUT_INIT_LOW
, "*FP_SER_EN" },
673 { 100, GPIOF_OUT_INIT_HIGH
, "*USER_PB#" },
674 { 108, GPIOF_IN
, "DIO0" },
675 { 109, GPIOF_IN
, "DIO1" },
676 { 110, GPIOF_IN
, "DIO2" },
677 { 111, GPIOF_IN
, "DIO3" },
678 { 112, GPIOF_IN
, "DIO4" },
681 static struct gpio laguna_gpio_gw2387
[] = {
682 { 0, GPIOF_IN
, "*GPS_PPS" },
683 { 1, GPIOF_IN
, "*GSC_IRQ#" },
684 { 2, GPIOF_IN
, "*USB_FAULT#" },
685 { 5, GPIOF_OUT_INIT_LOW
, "*USB_PCI_SEL" },
686 { 6, GPIOF_OUT_INIT_HIGH
, "*USB_VBUS_EN" },
687 { 7, GPIOF_OUT_INIT_LOW
, "*GSM_SEL0" },
688 { 8, GPIOF_OUT_INIT_LOW
, "*GSM_SEL1" },
689 { 9, GPIOF_OUT_INIT_LOW
, "*FP_SER_EN" },
690 { 100, GPIOF_IN
, "*USER_PB#" },
691 { 103, GPIOF_OUT_INIT_HIGH
, "*V5_EN" },
692 { 108, GPIOF_IN
, "DIO0" },
693 { 109, GPIOF_IN
, "DIO1" },
694 { 110, GPIOF_IN
, "DIO2" },
695 { 111, GPIOF_IN
, "DIO3" },
696 { 112, GPIOF_IN
, "DIO4" },
697 { 113, GPIOF_IN
, "DIO5" },
700 static struct gpio laguna_gpio_gw2384
[] = {
701 { 0, GPIOF_IN
, "*GSC_IRQ#" },
702 { 1, GPIOF_OUT_INIT_HIGH
, "*USB_HST_VBUS_EN" },
703 { 2, GPIOF_IN
, "*USB_HST_FAULT#" },
704 { 5, GPIOF_IN
, "*USB_OTG_FAULT#" },
705 { 6, GPIOF_OUT_INIT_LOW
, "*USB_HST_PCI_SEL" },
706 { 7, GPIOF_OUT_INIT_LOW
, "*GSM_SEL0" },
707 { 8, GPIOF_OUT_INIT_LOW
, "*GSM_SEL1" },
708 { 9, GPIOF_OUT_INIT_LOW
, "*FP_SER_EN" },
709 { 12, GPIOF_OUT_INIT_LOW
, "J10_DIOLED0" },
710 { 13, GPIOF_OUT_INIT_HIGH
, "*I2CMUX_RST#" },
711 { 14, GPIOF_OUT_INIT_LOW
, "J10_DIOLED1" },
712 { 15, GPIOF_OUT_INIT_LOW
, "J10_DIOLED2" },
713 { 100, GPIOF_IN
, "*USER_PB#" },
714 { 103, GPIOF_OUT_INIT_HIGH
, "V5_EN" },
715 { 108, GPIOF_IN
, "J9_DIOGSC0" },
718 static struct gpio laguna_gpio_gw2383
[] = {
719 { 0, GPIOF_IN
, "*GPS_PPS" },
720 { 1, GPIOF_IN
, "*GSC_IRQ#" },
721 { 2, GPIOF_OUT_INIT_HIGH
, "*PCIE_RST#" },
722 { 3, GPIOF_IN
, "GPIO0" },
723 { 8, GPIOF_IN
, "GPIO1" },
724 { 100, GPIOF_IN
, "DIO0" },
725 { 101, GPIOF_IN
, "DIO1" },
728 static struct gpio laguna_gpio_gw2382
[] = {
729 { 0, GPIOF_IN
, "*GPS_PPS" },
730 { 1, GPIOF_IN
, "*GSC_IRQ#" },
731 { 2, GPIOF_OUT_INIT_HIGH
, "*PCIE_RST#" },
732 { 3, GPIOF_IN
, "GPIO0" },
733 { 4, GPIOF_IN
, "GPIO1" },
734 { 9, GPIOF_OUT_INIT_HIGH
, "*USB_VBUS_EN" },
735 { 10, GPIOF_OUT_INIT_HIGH
, "*USB_PCI_SEL#" },
736 { 100, GPIOF_IN
, "DIO0" },
737 { 101, GPIOF_IN
, "DIO1" },
740 static struct gpio laguna_gpio_gw2380
[] = {
741 { 0, GPIOF_IN
, "*GPS_PPS" },
742 { 1, GPIOF_IN
, "*GSC_IRQ#" },
743 { 3, GPIOF_IN
, "GPIO0" },
744 { 8, GPIOF_IN
, "GPIO1" },
745 { 100, GPIOF_IN
, "DIO0" },
746 { 101, GPIOF_IN
, "DIO1" },
747 { 102, GPIOF_IN
, "DIO2" },
748 { 103, GPIOF_IN
, "DIO3" },
754 static void __init
laguna_init(void)
756 platform_device_register(&laguna_watchdog
);
758 platform_device_register(&laguna_i2c_controller
);
760 i2c_register_board_info(0, ARRAY_AND_SIZE(laguna_i2c_devices
));
762 pm_power_off
= cns3xxx_power_off
;
765 static struct map_desc laguna_io_desc
[] __initdata
= {
767 .virtual = CNS3XXX_UART0_BASE_VIRT
,
768 .pfn
= __phys_to_pfn(CNS3XXX_UART0_BASE
),
772 .virtual = CNS3XXX_UART1_BASE_VIRT
,
773 .pfn
= __phys_to_pfn(CNS3XXX_UART1_BASE
),
777 .virtual = CNS3XXX_UART2_BASE_VIRT
,
778 .pfn
= __phys_to_pfn(CNS3XXX_UART2_BASE
),
784 static void __init
laguna_map_io(void)
786 cns3xxx_common_init();
787 cns3xxx_pcie_iotable_init();
788 iotable_init(ARRAY_AND_SIZE(laguna_io_desc
));
789 laguna_early_serial_setup();
792 static int laguna_register_gpio(struct gpio
*array
, size_t num
)
797 for (i
= 0; i
< num
; i
++, array
++) {
798 const char *label
= array
->label
;
801 err
= gpio_request_one(array
->gpio
, array
->flags
, label
);
805 err
= gpio_export(array
->gpio
, array
->label
[0] != '*');
811 static int __init
laguna_pcie_init(void)
813 if (!machine_is_gw2388())
816 return cns3xxx_pcie_init();
818 subsys_initcall(laguna_pcie_init
);
820 static int __init
laguna_model_setup(void)
825 if (!machine_is_gw2388())
828 printk("Running on Gateworks Laguna %s\n", laguna_info
.model
);
829 cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT
, IRQ_CNS3XXX_GPIOA
,
831 cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT
, IRQ_CNS3XXX_GPIOB
,
832 NR_IRQS_CNS3XXX
+ 32);
834 if (strncmp(laguna_info
.model
, "GW", 2) == 0) {
835 if (laguna_info
.config_bitmap
& ETH0_LOAD
)
836 laguna_net_data
.ports
|= BIT(0);
837 if (laguna_info
.config_bitmap
& ETH1_LOAD
)
838 laguna_net_data
.ports
|= BIT(1);
839 if (laguna_info
.config_bitmap
& ETH2_LOAD
)
840 laguna_net_data
.ports
|= BIT(2);
841 if (laguna_net_data
.ports
)
842 platform_device_register(&laguna_net_device
);
844 if ((laguna_info
.config_bitmap
& SATA0_LOAD
) ||
845 (laguna_info
.config_bitmap
& SATA1_LOAD
))
848 if (laguna_info
.config_bitmap
& (USB0_LOAD
)) {
849 cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB
);
851 /* DRVVBUS pins share with GPIOA */
852 mem
= (void __iomem
*)(CNS3XXX_MISC_BASE_VIRT
+ 0x0014);
853 reg
= __raw_readl(mem
);
855 __raw_writel(reg
, mem
);
858 mem
= (void __iomem
*)(CNS3XXX_MISC_BASE_VIRT
+ 0x0808);
859 reg
= __raw_readl(mem
);
861 __raw_writel(reg
, mem
);
863 platform_device_register(&cns3xxx_usb_otg_device
);
866 if (laguna_info
.config_bitmap
& (USB1_LOAD
)) {
867 platform_device_register(&cns3xxx_usb_ehci_device
);
868 platform_device_register(&cns3xxx_usb_ohci_device
);
871 if (laguna_info
.config_bitmap
& (SD_LOAD
))
872 cns3xxx_sdhci_init();
874 if (laguna_info
.config_bitmap
& (UART0_LOAD
))
875 laguna_uart
.num_resources
= 1;
876 if (laguna_info
.config_bitmap
& (UART1_LOAD
))
877 laguna_uart
.num_resources
= 2;
878 if (laguna_info
.config_bitmap
& (UART2_LOAD
))
879 laguna_uart
.num_resources
= 3;
880 platform_device_register(&laguna_uart
);
882 if (laguna_info
.config2_bitmap
& (NOR_FLASH_LOAD
)) {
883 switch (laguna_info
.nor_flash_size
) {
885 laguna_nor_partitions
[3].size
= SZ_8M
- SZ_256K
- SZ_128K
- SZ_2M
;
886 laguna_nor_res
.end
= CNS3XXX_FLASH_BASE
+ SZ_8M
- 1;
889 laguna_nor_partitions
[3].size
= SZ_16M
- SZ_256K
- SZ_128K
- SZ_2M
;
890 laguna_nor_res
.end
= CNS3XXX_FLASH_BASE
+ SZ_16M
- 1;
893 laguna_nor_partitions
[3].size
= SZ_32M
- SZ_256K
- SZ_128K
- SZ_2M
;
894 laguna_nor_res
.end
= CNS3XXX_FLASH_BASE
+ SZ_32M
- 1;
897 laguna_nor_partitions
[3].size
= SZ_64M
- SZ_256K
- SZ_128K
- SZ_2M
;
898 laguna_nor_res
.end
= CNS3XXX_FLASH_BASE
+ SZ_64M
- 1;
901 laguna_nor_partitions
[3].size
= SZ_128M
- SZ_256K
- SZ_128K
- SZ_2M
;
902 laguna_nor_res
.end
= CNS3XXX_FLASH_BASE
+ SZ_128M
- 1;
905 platform_device_register(&laguna_nor_pdev
);
908 if (laguna_info
.config2_bitmap
& (SPI_FLASH_LOAD
)) {
909 switch (laguna_info
.spi_flash_size
) {
911 laguna_spi_partitions
[3].size
= SZ_4M
- SZ_2M
;
914 laguna_spi_partitions
[3].size
= SZ_8M
- SZ_2M
;
917 laguna_spi_partitions
[3].size
= SZ_16M
- SZ_2M
;
920 laguna_spi_partitions
[3].size
= SZ_32M
- SZ_2M
;
923 laguna_spi_partitions
[3].size
= SZ_64M
- SZ_2M
;
926 spi_register_board_info(ARRAY_AND_SIZE(laguna_spi_devices
));
929 if ((laguna_info
.config_bitmap
& SPI0_LOAD
) ||
930 (laguna_info
.config_bitmap
& SPI1_LOAD
))
931 platform_device_register(&laguna_spi_controller
);
933 if (laguna_info
.config2_bitmap
& GPS_LOAD
)
934 platform_device_register(&laguna_pps_device
);
937 * Do any model specific setup not known by the bitmap by matching
938 * the first 6 characters of the model name
941 if ( (strncmp(laguna_info
.model
, "GW2388", 6) == 0)
942 || (strncmp(laguna_info
.model
, "GW2389", 6) == 0) )
945 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2388
));
947 laguna_gpio_leds_data
.num_leds
= 2;
948 } else if (strncmp(laguna_info
.model
, "GW2387", 6) == 0) {
950 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2387
));
952 laguna_gpio_leds_data
.num_leds
= 2;
953 } else if (strncmp(laguna_info
.model
, "GW2384", 6) == 0) {
955 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2384
));
957 laguna_gpio_leds_data
.num_leds
= 1;
958 } else if (strncmp(laguna_info
.model
, "GW2383", 6) == 0) {
960 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2383
));
962 laguna_gpio_leds
[0].gpio
= 107;
963 laguna_gpio_leds_data
.num_leds
= 1;
964 } else if (strncmp(laguna_info
.model
, "GW2382", 6) == 0) {
966 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2382
));
968 laguna_gpio_leds
[0].gpio
= 107;
969 laguna_gpio_leds_data
.num_leds
= 1;
970 } else if (strncmp(laguna_info
.model
, "GW2380", 6) == 0) {
972 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2380
));
974 laguna_gpio_leds
[0].gpio
= 107;
975 laguna_gpio_leds
[1].gpio
= 106;
976 laguna_gpio_leds_data
.num_leds
= 2;
977 } else if (strncmp(laguna_info
.model
, "GW2391", 6) == 0) {
979 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2391
));
981 laguna_gpio_leds_data
.num_leds
= 2;
983 platform_device_register(&laguna_gpio_leds_device
);
985 // Do some defaults here, not sure what yet
989 late_initcall(laguna_model_setup
);
991 MACHINE_START(GW2388
, "Gateworks Corporation Laguna Platform")
992 .atag_offset
= 0x100,
993 .map_io
= laguna_map_io
,
994 .init_irq
= cns3xxx_init_irq
,
995 .timer
= &cns3xxx_timer
,
996 .handle_irq
= gic_handle_irq
,
997 .init_machine
= laguna_init
,
998 .restart
= cns3xxx_restart
,