2 * Cavium CNS3xxx Gigabit driver for Linux
4 * Copyright 2011 Gateworks Corporation
5 * Chris Lang <clang@gateworks.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License
9 * as published by the Free Software Foundation.
13 #include <linux/delay.h>
14 #include <linux/module.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/dmapool.h>
17 #include <linux/etherdevice.h>
18 #include <linux/interrupt.h>
20 #include <linux/kernel.h>
21 #include <linux/phy.h>
22 #include <linux/platform_device.h>
23 #include <linux/platform_data/cns3xxx.h>
24 #include <linux/skbuff.h>
26 #define DRV_NAME "cns3xxx_eth"
30 #define TX_DESC_RESERVE 20
32 #define RX_POOL_ALLOC_SIZE (sizeof(struct rx_desc) * RX_DESCS)
33 #define TX_POOL_ALLOC_SIZE (sizeof(struct tx_desc) * TX_DESCS)
36 #define RX_BUFFER_ALIGN 64
37 #define RX_BUFFER_ALIGN_MASK (~(RX_BUFFER_ALIGN - 1))
39 #define SKB_HEAD_ALIGN (((PAGE_SIZE - NET_SKB_PAD) % RX_BUFFER_ALIGN) + NET_SKB_PAD + NET_IP_ALIGN)
40 #define RX_SEGMENT_ALLOC_SIZE 2048
41 #define RX_SEGMENT_BUFSIZE (SKB_WITH_OVERHEAD(RX_SEGMENT_ALLOC_SIZE))
42 #define RX_SEGMENT_MRU (((RX_SEGMENT_BUFSIZE - SKB_HEAD_ALIGN) & RX_BUFFER_ALIGN_MASK) - NET_IP_ALIGN)
45 #define NAPI_WEIGHT 64
48 #define MDIO_CMD_COMPLETE 0x00008000
49 #define MDIO_WRITE_COMMAND 0x00002000
50 #define MDIO_READ_COMMAND 0x00004000
51 #define MDIO_REG_OFFSET 8
52 #define MDIO_VALUE_OFFSET 16
54 /* Descritor Defines */
55 #define END_OF_RING 0x40000000
56 #define FIRST_SEGMENT 0x20000000
57 #define LAST_SEGMENT 0x10000000
58 #define FORCE_ROUTE 0x04000000
59 #define IP_CHECKSUM 0x00040000
60 #define UDP_CHECKSUM 0x00020000
61 #define TCP_CHECKSUM 0x00010000
63 /* Port Config Defines */
64 #define PORT_BP_ENABLE 0x00020000
65 #define PORT_DISABLE 0x00040000
66 #define PORT_LEARN_DIS 0x00080000
67 #define PORT_BLOCK_STATE 0x00100000
68 #define PORT_BLOCK_MODE 0x00200000
70 #define PROMISC_OFFSET 29
72 /* Global Config Defines */
73 #define UNKNOWN_VLAN_TO_CPU 0x02000000
74 #define ACCEPT_CRC_PACKET 0x00200000
75 #define CRC_STRIPPING 0x00100000
77 /* VLAN Config Defines */
78 #define NIC_MODE 0x00008000
79 #define VLAN_UNAWARE 0x00000001
81 /* DMA AUTO Poll Defines */
82 #define TS_POLL_EN 0x00000020
83 #define TS_SUSPEND 0x00000010
84 #define FS_POLL_EN 0x00000002
85 #define FS_SUSPEND 0x00000001
87 /* DMA Ring Control Defines */
88 #define QUEUE_THRESHOLD 0x000000f0
89 #define CLR_FS_STATE 0x80000000
91 /* Interrupt Status Defines */
92 #define MAC0_STATUS_CHANGE 0x00004000
93 #define MAC1_STATUS_CHANGE 0x00008000
94 #define MAC2_STATUS_CHANGE 0x00010000
95 #define MAC0_RX_ERROR 0x00100000
96 #define MAC1_RX_ERROR 0x00200000
97 #define MAC2_RX_ERROR 0x00400000
101 u32 sdp
; /* segment data pointer */
105 u32 sdl
:16; /* segment data length */
109 u32 rsv_1
:3; /* reserve */
111 u32 fp
:1; /* force priority */
151 u8 alignment
[16]; /* for 32 byte */
156 u32 sdp
; /* segment data pointer */
160 u32 sdl
:16; /* segment data length */
205 u8 alignment
[16]; /* for 32 byte alignment */
214 u32 mac_pri_ctrl
[5], __res
;
236 u32 fc_input_thrs
, __res1
[2];
238 u32 mac_glob_cfg_ext
, __res2
[2];
240 u32 dma_auto_poll_cfg
;
241 u32 delay_intr_cfg
, __res3
;
244 u32 ts_desc_base_addr0
, __res4
;
247 u32 fs_desc_base_addr0
, __res5
;
250 u32 ts_desc_base_addr1
, __res6
;
253 u32 fs_desc_base_addr1
;
255 u32 mac_counter0
[13];
259 struct tx_desc
*desc
;
260 dma_addr_t phys_addr
;
261 struct tx_desc
*cur_addr
;
262 struct sk_buff
*buff_tab
[TX_DESCS
];
263 unsigned int phys_tab
[TX_DESCS
];
273 struct rx_desc
*desc
;
274 dma_addr_t phys_addr
;
275 struct rx_desc
*cur_addr
;
276 void *buff_tab
[RX_DESCS
];
277 unsigned int phys_tab
[RX_DESCS
];
284 struct switch_regs __iomem
*regs
;
285 struct napi_struct napi
;
286 struct cns3xxx_plat_info
*plat
;
287 struct _tx_ring tx_ring
;
288 struct _rx_ring rx_ring
;
289 struct sk_buff
*frag_first
;
290 struct sk_buff
*frag_last
;
297 struct net_device
*netdev
;
298 struct phy_device
*phydev
;
300 int id
; /* logical port ID */
304 static spinlock_t mdio_lock
;
305 static DEFINE_SPINLOCK(tx_lock
);
306 static struct switch_regs __iomem
*mdio_regs
; /* mdio command and status only */
307 struct mii_bus
*mdio_bus
;
308 static int ports_open
;
309 static struct port
*switch_port_tab
[4];
310 static struct dma_pool
*rx_dma_pool
;
311 static struct dma_pool
*tx_dma_pool
;
312 struct net_device
*napi_dev
;
314 static int cns3xxx_mdio_cmd(struct mii_bus
*bus
, int phy_id
, int location
,
320 temp
= __raw_readl(&mdio_regs
->phy_control
);
321 temp
|= MDIO_CMD_COMPLETE
;
322 __raw_writel(temp
, &mdio_regs
->phy_control
);
326 temp
= (cmd
<< MDIO_VALUE_OFFSET
);
327 temp
|= MDIO_WRITE_COMMAND
;
329 temp
= MDIO_READ_COMMAND
;
331 temp
|= ((location
& 0x1f) << MDIO_REG_OFFSET
);
332 temp
|= (phy_id
& 0x1f);
334 __raw_writel(temp
, &mdio_regs
->phy_control
);
336 while (((__raw_readl(&mdio_regs
->phy_control
) & MDIO_CMD_COMPLETE
) == 0)
342 if (cycles
== 5000) {
343 printk(KERN_ERR
"%s #%i: MII transaction failed\n", bus
->name
,
348 temp
= __raw_readl(&mdio_regs
->phy_control
);
349 temp
|= MDIO_CMD_COMPLETE
;
350 __raw_writel(temp
, &mdio_regs
->phy_control
);
355 return ((temp
>> MDIO_VALUE_OFFSET
) & 0xFFFF);
358 static int cns3xxx_mdio_read(struct mii_bus
*bus
, int phy_id
, int location
)
363 spin_lock_irqsave(&mdio_lock
, flags
);
364 ret
= cns3xxx_mdio_cmd(bus
, phy_id
, location
, 0, 0);
365 spin_unlock_irqrestore(&mdio_lock
, flags
);
369 static int cns3xxx_mdio_write(struct mii_bus
*bus
, int phy_id
, int location
,
375 spin_lock_irqsave(&mdio_lock
, flags
);
376 ret
= cns3xxx_mdio_cmd(bus
, phy_id
, location
, 1, val
);
377 spin_unlock_irqrestore(&mdio_lock
, flags
);
381 static int cns3xxx_mdio_register(void __iomem
*base
)
385 if (!(mdio_bus
= mdiobus_alloc()))
390 spin_lock_init(&mdio_lock
);
391 mdio_bus
->name
= "CNS3xxx MII Bus";
392 mdio_bus
->read
= &cns3xxx_mdio_read
;
393 mdio_bus
->write
= &cns3xxx_mdio_write
;
394 strcpy(mdio_bus
->id
, "0");
396 if ((err
= mdiobus_register(mdio_bus
)))
397 mdiobus_free(mdio_bus
);
401 static void cns3xxx_mdio_remove(void)
403 mdiobus_unregister(mdio_bus
);
404 mdiobus_free(mdio_bus
);
407 static void enable_tx_dma(struct sw
*sw
)
409 __raw_writel(0x1, &sw
->regs
->ts_dma_ctrl0
);
412 static void enable_rx_dma(struct sw
*sw
)
414 __raw_writel(0x1, &sw
->regs
->fs_dma_ctrl0
);
417 static void cns3xxx_adjust_link(struct net_device
*dev
)
419 struct port
*port
= netdev_priv(dev
);
420 struct phy_device
*phydev
= port
->phydev
;
425 printk(KERN_INFO
"%s: link down\n", dev
->name
);
430 if (port
->speed
== phydev
->speed
&& port
->duplex
== phydev
->duplex
)
433 port
->speed
= phydev
->speed
;
434 port
->duplex
= phydev
->duplex
;
436 printk(KERN_INFO
"%s: link up, speed %u Mb/s, %s duplex\n",
437 dev
->name
, port
->speed
, port
->duplex
? "full" : "half");
440 static void eth_schedule_poll(struct sw
*sw
)
442 if (unlikely(!napi_schedule_prep(&sw
->napi
)))
445 disable_irq_nosync(sw
->rx_irq
);
446 __napi_schedule(&sw
->napi
);
449 irqreturn_t
eth_rx_irq(int irq
, void *pdev
)
451 struct net_device
*dev
= pdev
;
452 struct sw
*sw
= netdev_priv(dev
);
453 eth_schedule_poll(sw
);
454 return (IRQ_HANDLED
);
457 irqreturn_t
eth_stat_irq(int irq
, void *pdev
)
459 struct net_device
*dev
= pdev
;
460 struct sw
*sw
= netdev_priv(dev
);
462 u32 stat
= __raw_readl(&sw
->regs
->intr_stat
);
463 __raw_writel(0xffffffff, &sw
->regs
->intr_stat
);
465 if (stat
& MAC2_RX_ERROR
)
466 switch_port_tab
[3]->netdev
->stats
.rx_dropped
++;
467 if (stat
& MAC1_RX_ERROR
)
468 switch_port_tab
[1]->netdev
->stats
.rx_dropped
++;
469 if (stat
& MAC0_RX_ERROR
)
470 switch_port_tab
[0]->netdev
->stats
.rx_dropped
++;
472 if (stat
& MAC0_STATUS_CHANGE
) {
473 cfg
= __raw_readl(&sw
->regs
->mac_cfg
[0]);
474 switch_port_tab
[0]->phydev
->link
= (cfg
& 0x1);
475 switch_port_tab
[0]->phydev
->duplex
= ((cfg
>> 4) & 0x1);
476 if (((cfg
>> 2) & 0x3) == 2)
477 switch_port_tab
[0]->phydev
->speed
= 1000;
478 else if (((cfg
>> 2) & 0x3) == 1)
479 switch_port_tab
[0]->phydev
->speed
= 100;
481 switch_port_tab
[0]->phydev
->speed
= 10;
482 cns3xxx_adjust_link(switch_port_tab
[0]->netdev
);
485 if (stat
& MAC1_STATUS_CHANGE
) {
486 cfg
= __raw_readl(&sw
->regs
->mac_cfg
[1]);
487 switch_port_tab
[1]->phydev
->link
= (cfg
& 0x1);
488 switch_port_tab
[1]->phydev
->duplex
= ((cfg
>> 4) & 0x1);
489 if (((cfg
>> 2) & 0x3) == 2)
490 switch_port_tab
[1]->phydev
->speed
= 1000;
491 else if (((cfg
>> 2) & 0x3) == 1)
492 switch_port_tab
[1]->phydev
->speed
= 100;
494 switch_port_tab
[1]->phydev
->speed
= 10;
495 cns3xxx_adjust_link(switch_port_tab
[1]->netdev
);
498 if (stat
& MAC2_STATUS_CHANGE
) {
499 cfg
= __raw_readl(&sw
->regs
->mac_cfg
[3]);
500 switch_port_tab
[3]->phydev
->link
= (cfg
& 0x1);
501 switch_port_tab
[3]->phydev
->duplex
= ((cfg
>> 4) & 0x1);
502 if (((cfg
>> 2) & 0x3) == 2)
503 switch_port_tab
[3]->phydev
->speed
= 1000;
504 else if (((cfg
>> 2) & 0x3) == 1)
505 switch_port_tab
[3]->phydev
->speed
= 100;
507 switch_port_tab
[3]->phydev
->speed
= 10;
508 cns3xxx_adjust_link(switch_port_tab
[3]->netdev
);
511 return (IRQ_HANDLED
);
515 static void cns3xxx_alloc_rx_buf(struct sw
*sw
, int received
)
517 struct _rx_ring
*rx_ring
= &sw
->rx_ring
;
518 unsigned int i
= rx_ring
->alloc_index
;
519 struct rx_desc
*desc
= &(rx_ring
)->desc
[i
];
523 for (received
+= rx_ring
->alloc_count
; received
> 0; received
--) {
524 buf
= kmalloc(RX_SEGMENT_ALLOC_SIZE
, GFP_ATOMIC
);
528 phys
= dma_map_single(sw
->dev
, buf
+ SKB_HEAD_ALIGN
,
529 RX_SEGMENT_MRU
, DMA_FROM_DEVICE
);
530 if (dma_mapping_error(sw
->dev
, phys
)) {
535 desc
->sdl
= RX_SEGMENT_MRU
;
540 /* put the new buffer on RX-free queue */
541 rx_ring
->buff_tab
[i
] = buf
;
542 rx_ring
->phys_tab
[i
] = phys
;
543 if (i
== RX_DESCS
- 1) {
545 desc
->config0
= END_OF_RING
| FIRST_SEGMENT
|
546 LAST_SEGMENT
| RX_SEGMENT_MRU
;
547 desc
= &(rx_ring
)->desc
[i
];
549 desc
->config0
= FIRST_SEGMENT
| LAST_SEGMENT
|
556 rx_ring
->alloc_count
= received
;
557 rx_ring
->alloc_index
= i
;
560 static void eth_check_num_used(struct _tx_ring
*tx_ring
)
565 if (tx_ring
->num_used
>= TX_DESCS
- TX_DESC_RESERVE
)
568 if (tx_ring
->stopped
== stop
)
571 tx_ring
->stopped
= stop
;
572 for (i
= 0; i
< 4; i
++) {
573 struct port
*port
= switch_port_tab
[i
];
574 struct net_device
*dev
;
581 netif_stop_queue(dev
);
583 netif_wake_queue(dev
);
587 static void eth_complete_tx(struct sw
*sw
)
589 struct _tx_ring
*tx_ring
= &sw
->tx_ring
;
590 struct tx_desc
*desc
;
593 int num_used
= tx_ring
->num_used
;
596 index
= tx_ring
->free_index
;
597 desc
= &(tx_ring
)->desc
[index
];
598 for (i
= 0; i
< num_used
; i
++) {
600 skb
= tx_ring
->buff_tab
[index
];
601 tx_ring
->buff_tab
[index
] = 0;
603 dev_kfree_skb_any(skb
);
604 dma_unmap_single(sw
->dev
, tx_ring
->phys_tab
[index
],
605 desc
->sdl
, DMA_TO_DEVICE
);
606 if (++index
== TX_DESCS
) {
608 desc
= &(tx_ring
)->desc
[index
];
616 tx_ring
->free_index
= index
;
617 tx_ring
->num_used
-= i
;
618 eth_check_num_used(tx_ring
);
621 static int eth_poll(struct napi_struct
*napi
, int budget
)
623 struct sw
*sw
= container_of(napi
, struct sw
, napi
);
624 struct _rx_ring
*rx_ring
= &sw
->rx_ring
;
627 unsigned int i
= rx_ring
->cur_index
;
628 struct rx_desc
*desc
= &(rx_ring
)->desc
[i
];
629 unsigned int alloc_count
= rx_ring
->alloc_count
;
631 while (desc
->cown
&& alloc_count
+ received
< RX_DESCS
- 1) {
633 int reserve
= SKB_HEAD_ALIGN
;
635 if (received
>= budget
)
638 /* process received frame */
639 dma_unmap_single(sw
->dev
, rx_ring
->phys_tab
[i
],
640 RX_SEGMENT_MRU
, DMA_FROM_DEVICE
);
642 skb
= build_skb(rx_ring
->buff_tab
[i
], 0);
646 skb
->dev
= switch_port_tab
[desc
->sp
]->netdev
;
649 if (desc
->fsd
&& !desc
->lsd
)
650 length
= RX_SEGMENT_MRU
;
653 reserve
-= NET_IP_ALIGN
;
655 length
+= NET_IP_ALIGN
;
658 skb_reserve(skb
, reserve
);
659 skb_put(skb
, length
);
662 sw
->frag_first
= skb
;
664 if (sw
->frag_first
== sw
->frag_last
)
665 skb_frag_add_head(sw
->frag_first
, skb
);
667 sw
->frag_last
->next
= skb
;
668 sw
->frag_first
->len
+= skb
->len
;
669 sw
->frag_first
->data_len
+= skb
->len
;
670 sw
->frag_first
->truesize
+= skb
->truesize
;
675 struct net_device
*dev
;
677 skb
= sw
->frag_first
;
679 skb
->protocol
= eth_type_trans(skb
, dev
);
681 dev
->stats
.rx_packets
++;
682 dev
->stats
.rx_bytes
+= skb
->len
;
684 /* RX Hardware checksum offload */
685 skb
->ip_summed
= CHECKSUM_NONE
;
686 switch (desc
->prot
) {
694 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
695 napi_gro_receive(napi
, skb
);
700 netif_receive_skb(skb
);
704 sw
->frag_first
= NULL
;
705 sw
->frag_last
= NULL
;
709 if (++i
== RX_DESCS
) {
711 desc
= &(rx_ring
)->desc
[i
];
717 rx_ring
->cur_index
= i
;
720 enable_irq(sw
->rx_irq
);
722 /* if rx descriptors are full schedule another poll */
723 if (rx_ring
->desc
[(i
-1) & (RX_DESCS
-1)].cown
)
724 eth_schedule_poll(sw
);
727 spin_lock_bh(&tx_lock
);
729 spin_unlock_bh(&tx_lock
);
731 cns3xxx_alloc_rx_buf(sw
, received
);
739 static void eth_set_desc(struct sw
*sw
, struct _tx_ring
*tx_ring
, int index
,
740 int index_last
, void *data
, int len
, u32 config0
,
743 struct tx_desc
*tx_desc
= &(tx_ring
)->desc
[index
];
746 phys
= dma_map_single(sw
->dev
, data
, len
, DMA_TO_DEVICE
);
748 tx_desc
->pmap
= pmap
;
749 tx_ring
->phys_tab
[index
] = phys
;
752 if (index
== TX_DESCS
- 1)
753 config0
|= END_OF_RING
;
754 if (index
== index_last
)
755 config0
|= LAST_SEGMENT
;
758 tx_desc
->config0
= config0
;
761 static int eth_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
763 struct port
*port
= netdev_priv(dev
);
764 struct sw
*sw
= port
->sw
;
765 struct _tx_ring
*tx_ring
= &sw
->tx_ring
;
766 struct sk_buff
*skb1
;
767 char pmap
= (1 << port
->id
);
768 int nr_frags
= skb_shinfo(skb
)->nr_frags
;
769 int nr_desc
= nr_frags
;
770 int index0
, index
, index_last
;
778 skb_walk_frags(skb
, skb1
)
781 eth_schedule_poll(sw
);
782 spin_lock_bh(&tx_lock
);
783 if ((tx_ring
->num_used
+ nr_desc
+ 1) >= TX_DESCS
) {
784 spin_unlock_bh(&tx_lock
);
785 return NETDEV_TX_BUSY
;
788 index
= index0
= tx_ring
->cur_index
;
789 index_last
= (index0
+ nr_desc
) % TX_DESCS
;
790 tx_ring
->cur_index
= (index_last
+ 1) % TX_DESCS
;
792 spin_unlock_bh(&tx_lock
);
794 config0
= FORCE_ROUTE
;
795 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
796 config0
|= UDP_CHECKSUM
| TCP_CHECKSUM
;
801 for (i
= 0; i
< nr_frags
; i
++) {
802 struct skb_frag_struct
*frag
;
805 index
= (index
+ 1) % TX_DESCS
;
807 frag
= &skb_shinfo(skb
)->frags
[i
];
808 addr
= page_address(skb_frag_page(frag
)) + frag
->page_offset
;
810 eth_set_desc(sw
, tx_ring
, index
, index_last
, addr
, frag
->size
,
815 len0
= skb
->len
- skb
->data_len
;
817 skb_walk_frags(skb
, skb1
) {
818 index
= (index
+ 1) % TX_DESCS
;
821 eth_set_desc(sw
, tx_ring
, index
, index_last
, skb1
->data
,
822 skb1
->len
, config0
, pmap
);
825 tx_ring
->buff_tab
[index0
] = skb
;
826 eth_set_desc(sw
, tx_ring
, index0
, index_last
, skb
->data
, len0
,
827 config0
| FIRST_SEGMENT
, pmap
);
832 tx_ring
->num_used
+= nr_desc
+ 1;
833 spin_unlock(&tx_lock
);
835 dev
->stats
.tx_packets
++;
836 dev
->stats
.tx_bytes
+= skb
->len
;
843 static int eth_ioctl(struct net_device
*dev
, struct ifreq
*req
, int cmd
)
845 struct port
*port
= netdev_priv(dev
);
847 if (!netif_running(dev
))
849 return phy_mii_ioctl(port
->phydev
, req
, cmd
);
852 /* ethtool support */
854 static void cns3xxx_get_drvinfo(struct net_device
*dev
,
855 struct ethtool_drvinfo
*info
)
857 strcpy(info
->driver
, DRV_NAME
);
858 strcpy(info
->bus_info
, "internal");
861 static int cns3xxx_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
863 struct port
*port
= netdev_priv(dev
);
864 return phy_ethtool_gset(port
->phydev
, cmd
);
867 static int cns3xxx_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
869 struct port
*port
= netdev_priv(dev
);
870 return phy_ethtool_sset(port
->phydev
, cmd
);
873 static int cns3xxx_nway_reset(struct net_device
*dev
)
875 struct port
*port
= netdev_priv(dev
);
876 return phy_start_aneg(port
->phydev
);
879 static struct ethtool_ops cns3xxx_ethtool_ops
= {
880 .get_drvinfo
= cns3xxx_get_drvinfo
,
881 .get_settings
= cns3xxx_get_settings
,
882 .set_settings
= cns3xxx_set_settings
,
883 .nway_reset
= cns3xxx_nway_reset
,
884 .get_link
= ethtool_op_get_link
,
888 static int init_rings(struct sw
*sw
)
891 struct _rx_ring
*rx_ring
= &sw
->rx_ring
;
892 struct _tx_ring
*tx_ring
= &sw
->tx_ring
;
894 __raw_writel(0, &sw
->regs
->fs_dma_ctrl0
);
895 __raw_writel(TS_SUSPEND
| FS_SUSPEND
, &sw
->regs
->dma_auto_poll_cfg
);
896 __raw_writel(QUEUE_THRESHOLD
, &sw
->regs
->dma_ring_ctrl
);
897 __raw_writel(CLR_FS_STATE
| QUEUE_THRESHOLD
, &sw
->regs
->dma_ring_ctrl
);
899 __raw_writel(QUEUE_THRESHOLD
, &sw
->regs
->dma_ring_ctrl
);
901 if (!(rx_dma_pool
= dma_pool_create(DRV_NAME
, sw
->dev
,
902 RX_POOL_ALLOC_SIZE
, 32, 0)))
905 if (!(rx_ring
->desc
= dma_pool_alloc(rx_dma_pool
, GFP_KERNEL
,
906 &rx_ring
->phys_addr
)))
908 memset(rx_ring
->desc
, 0, RX_POOL_ALLOC_SIZE
);
910 /* Setup RX buffers */
911 for (i
= 0; i
< RX_DESCS
; i
++) {
912 struct rx_desc
*desc
= &(rx_ring
)->desc
[i
];
915 buf
= kzalloc(RX_SEGMENT_ALLOC_SIZE
, GFP_KERNEL
);
919 desc
->sdl
= RX_SEGMENT_MRU
;
920 if (i
== (RX_DESCS
- 1))
925 desc
->sdp
= dma_map_single(sw
->dev
, buf
+ SKB_HEAD_ALIGN
,
926 RX_SEGMENT_MRU
, DMA_FROM_DEVICE
);
927 if (dma_mapping_error(sw
->dev
, desc
->sdp
))
930 rx_ring
->buff_tab
[i
] = buf
;
931 rx_ring
->phys_tab
[i
] = desc
->sdp
;
934 __raw_writel(rx_ring
->phys_addr
, &sw
->regs
->fs_desc_ptr0
);
935 __raw_writel(rx_ring
->phys_addr
, &sw
->regs
->fs_desc_base_addr0
);
937 if (!(tx_dma_pool
= dma_pool_create(DRV_NAME
, sw
->dev
,
938 TX_POOL_ALLOC_SIZE
, 32, 0)))
941 if (!(tx_ring
->desc
= dma_pool_alloc(tx_dma_pool
, GFP_KERNEL
,
942 &tx_ring
->phys_addr
)))
944 memset(tx_ring
->desc
, 0, TX_POOL_ALLOC_SIZE
);
946 /* Setup TX buffers */
947 for (i
= 0; i
< TX_DESCS
; i
++) {
948 struct tx_desc
*desc
= &(tx_ring
)->desc
[i
];
949 tx_ring
->buff_tab
[i
] = 0;
951 if (i
== (TX_DESCS
- 1))
955 __raw_writel(tx_ring
->phys_addr
, &sw
->regs
->ts_desc_ptr0
);
956 __raw_writel(tx_ring
->phys_addr
, &sw
->regs
->ts_desc_base_addr0
);
961 static void destroy_rings(struct sw
*sw
)
964 if (sw
->rx_ring
.desc
) {
965 for (i
= 0; i
< RX_DESCS
; i
++) {
966 struct _rx_ring
*rx_ring
= &sw
->rx_ring
;
967 struct rx_desc
*desc
= &(rx_ring
)->desc
[i
];
968 struct sk_buff
*skb
= sw
->rx_ring
.buff_tab
[i
];
973 dma_unmap_single(sw
->dev
, desc
->sdp
, RX_SEGMENT_MRU
,
977 dma_pool_free(rx_dma_pool
, sw
->rx_ring
.desc
, sw
->rx_ring
.phys_addr
);
978 dma_pool_destroy(rx_dma_pool
);
980 sw
->rx_ring
.desc
= 0;
982 if (sw
->tx_ring
.desc
) {
983 for (i
= 0; i
< TX_DESCS
; i
++) {
984 struct _tx_ring
*tx_ring
= &sw
->tx_ring
;
985 struct tx_desc
*desc
= &(tx_ring
)->desc
[i
];
986 struct sk_buff
*skb
= sw
->tx_ring
.buff_tab
[i
];
988 dma_unmap_single(sw
->dev
, desc
->sdp
,
989 skb
->len
, DMA_TO_DEVICE
);
993 dma_pool_free(tx_dma_pool
, sw
->tx_ring
.desc
, sw
->tx_ring
.phys_addr
);
994 dma_pool_destroy(tx_dma_pool
);
996 sw
->tx_ring
.desc
= 0;
1000 static int eth_open(struct net_device
*dev
)
1002 struct port
*port
= netdev_priv(dev
);
1003 struct sw
*sw
= port
->sw
;
1006 port
->speed
= 0; /* force "link up" message */
1007 phy_start(port
->phydev
);
1009 netif_start_queue(dev
);
1012 request_irq(sw
->rx_irq
, eth_rx_irq
, IRQF_SHARED
, "gig_switch", napi_dev
);
1013 request_irq(sw
->stat_irq
, eth_stat_irq
, IRQF_SHARED
, "gig_stat", napi_dev
);
1014 napi_enable(&sw
->napi
);
1015 netif_start_queue(napi_dev
);
1017 __raw_writel(~(MAC0_STATUS_CHANGE
| MAC1_STATUS_CHANGE
| MAC2_STATUS_CHANGE
|
1018 MAC0_RX_ERROR
| MAC1_RX_ERROR
| MAC2_RX_ERROR
), &sw
->regs
->intr_mask
);
1020 temp
= __raw_readl(&sw
->regs
->mac_cfg
[2]);
1021 temp
&= ~(PORT_DISABLE
);
1022 __raw_writel(temp
, &sw
->regs
->mac_cfg
[2]);
1024 temp
= __raw_readl(&sw
->regs
->dma_auto_poll_cfg
);
1025 temp
&= ~(TS_SUSPEND
| FS_SUSPEND
);
1026 __raw_writel(temp
, &sw
->regs
->dma_auto_poll_cfg
);
1030 temp
= __raw_readl(&sw
->regs
->mac_cfg
[port
->id
]);
1031 temp
&= ~(PORT_DISABLE
);
1032 __raw_writel(temp
, &sw
->regs
->mac_cfg
[port
->id
]);
1035 netif_carrier_on(dev
);
1040 static int eth_close(struct net_device
*dev
)
1042 struct port
*port
= netdev_priv(dev
);
1043 struct sw
*sw
= port
->sw
;
1048 temp
= __raw_readl(&sw
->regs
->mac_cfg
[port
->id
]);
1049 temp
|= (PORT_DISABLE
);
1050 __raw_writel(temp
, &sw
->regs
->mac_cfg
[port
->id
]);
1052 netif_stop_queue(dev
);
1054 phy_stop(port
->phydev
);
1057 disable_irq(sw
->rx_irq
);
1058 free_irq(sw
->rx_irq
, napi_dev
);
1059 disable_irq(sw
->stat_irq
);
1060 free_irq(sw
->stat_irq
, napi_dev
);
1061 napi_disable(&sw
->napi
);
1062 netif_stop_queue(napi_dev
);
1063 temp
= __raw_readl(&sw
->regs
->mac_cfg
[2]);
1064 temp
|= (PORT_DISABLE
);
1065 __raw_writel(temp
, &sw
->regs
->mac_cfg
[2]);
1067 __raw_writel(TS_SUSPEND
| FS_SUSPEND
,
1068 &sw
->regs
->dma_auto_poll_cfg
);
1071 netif_carrier_off(dev
);
1075 static void eth_rx_mode(struct net_device
*dev
)
1077 struct port
*port
= netdev_priv(dev
);
1078 struct sw
*sw
= port
->sw
;
1081 temp
= __raw_readl(&sw
->regs
->mac_glob_cfg
);
1083 if (dev
->flags
& IFF_PROMISC
) {
1085 temp
|= ((1 << 2) << PROMISC_OFFSET
);
1087 temp
|= ((1 << port
->id
) << PROMISC_OFFSET
);
1090 temp
&= ~((1 << 2) << PROMISC_OFFSET
);
1092 temp
&= ~((1 << port
->id
) << PROMISC_OFFSET
);
1094 __raw_writel(temp
, &sw
->regs
->mac_glob_cfg
);
1097 static int eth_set_mac(struct net_device
*netdev
, void *p
)
1099 struct port
*port
= netdev_priv(netdev
);
1100 struct sw
*sw
= port
->sw
;
1101 struct sockaddr
*addr
= p
;
1104 if (!is_valid_ether_addr(addr
->sa_data
))
1105 return -EADDRNOTAVAIL
;
1107 /* Invalidate old ARL Entry */
1109 __raw_writel((port
->id
<< 16) | (0x4 << 9), &sw
->regs
->arl_ctrl
[0]);
1111 __raw_writel(((port
->id
+ 1) << 16) | (0x4 << 9), &sw
->regs
->arl_ctrl
[0]);
1112 __raw_writel( ((netdev
->dev_addr
[0] << 24) | (netdev
->dev_addr
[1] << 16) |
1113 (netdev
->dev_addr
[2] << 8) | (netdev
->dev_addr
[3])),
1114 &sw
->regs
->arl_ctrl
[1]);
1116 __raw_writel( ((netdev
->dev_addr
[4] << 24) | (netdev
->dev_addr
[5] << 16) |
1118 &sw
->regs
->arl_ctrl
[2]);
1119 __raw_writel((1 << 19), &sw
->regs
->arl_vlan_cmd
);
1121 while (((__raw_readl(&sw
->regs
->arl_vlan_cmd
) & (1 << 21)) == 0)
1128 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
1131 __raw_writel((port
->id
<< 16) | (0x4 << 9), &sw
->regs
->arl_ctrl
[0]);
1133 __raw_writel(((port
->id
+ 1) << 16) | (0x4 << 9), &sw
->regs
->arl_ctrl
[0]);
1134 __raw_writel( ((addr
->sa_data
[0] << 24) | (addr
->sa_data
[1] << 16) |
1135 (addr
->sa_data
[2] << 8) | (addr
->sa_data
[3])),
1136 &sw
->regs
->arl_ctrl
[1]);
1138 __raw_writel( ((addr
->sa_data
[4] << 24) | (addr
->sa_data
[5] << 16) |
1139 (7 << 4) | (1 << 1)), &sw
->regs
->arl_ctrl
[2]);
1140 __raw_writel((1 << 19), &sw
->regs
->arl_vlan_cmd
);
1142 while (((__raw_readl(&sw
->regs
->arl_vlan_cmd
) & (1 << 21)) == 0)
1150 static int cns3xxx_change_mtu(struct net_device
*dev
, int new_mtu
)
1152 if (new_mtu
> MAX_MTU
)
1159 static const struct net_device_ops cns3xxx_netdev_ops
= {
1160 .ndo_open
= eth_open
,
1161 .ndo_stop
= eth_close
,
1162 .ndo_start_xmit
= eth_xmit
,
1163 .ndo_set_rx_mode
= eth_rx_mode
,
1164 .ndo_do_ioctl
= eth_ioctl
,
1165 .ndo_change_mtu
= cns3xxx_change_mtu
,
1166 .ndo_set_mac_address
= eth_set_mac
,
1167 .ndo_validate_addr
= eth_validate_addr
,
1170 static int eth_init_one(struct platform_device
*pdev
)
1175 struct net_device
*dev
;
1176 struct cns3xxx_plat_info
*plat
= pdev
->dev
.platform_data
;
1177 char phy_id
[MII_BUS_ID_SIZE
+ 3];
1180 struct resource
*res
;
1183 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1184 regs
= devm_ioremap_resource(&pdev
->dev
, res
);
1186 return PTR_ERR(regs
);
1188 err
= cns3xxx_mdio_register(regs
);
1192 if (!(napi_dev
= alloc_etherdev(sizeof(struct sw
)))) {
1194 goto err_remove_mdio
;
1197 strcpy(napi_dev
->name
, "switch%d");
1198 napi_dev
->features
= NETIF_F_IP_CSUM
| NETIF_F_SG
| NETIF_F_FRAGLIST
;
1200 SET_NETDEV_DEV(napi_dev
, &pdev
->dev
);
1201 sw
= netdev_priv(napi_dev
);
1202 memset(sw
, 0, sizeof(struct sw
));
1204 sw
->dev
= &pdev
->dev
;
1206 sw
->rx_irq
= platform_get_irq_byname(pdev
, "eth_rx");
1207 sw
->stat_irq
= platform_get_irq_byname(pdev
, "eth_stat");
1209 temp
= __raw_readl(&sw
->regs
->phy_auto_addr
);
1210 temp
|= (3 << 30); /* maximum frame length: 9600 bytes */
1211 __raw_writel(temp
, &sw
->regs
->phy_auto_addr
);
1213 for (i
= 0; i
< 4; i
++) {
1214 temp
= __raw_readl(&sw
->regs
->mac_cfg
[i
]);
1215 temp
|= (PORT_DISABLE
);
1216 __raw_writel(temp
, &sw
->regs
->mac_cfg
[i
]);
1219 temp
= PORT_DISABLE
;
1220 __raw_writel(temp
, &sw
->regs
->mac_cfg
[2]);
1222 temp
= __raw_readl(&sw
->regs
->vlan_cfg
);
1223 temp
|= NIC_MODE
| VLAN_UNAWARE
;
1224 __raw_writel(temp
, &sw
->regs
->vlan_cfg
);
1226 __raw_writel(UNKNOWN_VLAN_TO_CPU
|
1227 CRC_STRIPPING
, &sw
->regs
->mac_glob_cfg
);
1229 if ((err
= init_rings(sw
)) != 0) {
1234 platform_set_drvdata(pdev
, napi_dev
);
1236 netif_napi_add(napi_dev
, &sw
->napi
, eth_poll
, NAPI_WEIGHT
);
1238 for (i
= 0; i
< 3; i
++) {
1239 if (!(plat
->ports
& (1 << i
))) {
1243 if (!(dev
= alloc_etherdev(sizeof(struct port
)))) {
1247 port
= netdev_priv(dev
);
1255 temp
= __raw_readl(&sw
->regs
->mac_cfg
[port
->id
]);
1256 temp
|= (PORT_DISABLE
| PORT_BLOCK_STATE
| PORT_LEARN_DIS
);
1257 __raw_writel(temp
, &sw
->regs
->mac_cfg
[port
->id
]);
1259 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1260 dev
->netdev_ops
= &cns3xxx_netdev_ops
;
1261 dev
->ethtool_ops
= &cns3xxx_ethtool_ops
;
1262 dev
->tx_queue_len
= 1000;
1263 dev
->features
= NETIF_F_IP_CSUM
| NETIF_F_SG
| NETIF_F_FRAGLIST
;
1265 switch_port_tab
[port
->id
] = port
;
1266 memcpy(dev
->dev_addr
, &plat
->hwaddr
[i
], ETH_ALEN
);
1268 snprintf(phy_id
, MII_BUS_ID_SIZE
+ 3, PHY_ID_FMT
, "0", plat
->phy
[i
]);
1269 port
->phydev
= phy_connect(dev
, phy_id
, &cns3xxx_adjust_link
,
1270 PHY_INTERFACE_MODE_RGMII
);
1271 if ((err
= IS_ERR(port
->phydev
))) {
1272 switch_port_tab
[port
->id
] = 0;
1277 port
->phydev
->irq
= PHY_IGNORE_INTERRUPT
;
1279 if ((err
= register_netdev(dev
))) {
1280 phy_disconnect(port
->phydev
);
1281 switch_port_tab
[port
->id
] = 0;
1286 printk(KERN_INFO
"%s: RGMII PHY %i on cns3xxx Switch\n", dev
->name
, plat
->phy
[i
]);
1287 netif_carrier_off(dev
);
1295 for (--i
; i
>= 0; i
--) {
1296 if (switch_port_tab
[i
]) {
1297 port
= switch_port_tab
[i
];
1299 unregister_netdev(dev
);
1300 phy_disconnect(port
->phydev
);
1301 switch_port_tab
[i
] = 0;
1306 free_netdev(napi_dev
);
1308 cns3xxx_mdio_remove();
1312 static int eth_remove_one(struct platform_device
*pdev
)
1314 struct net_device
*dev
= platform_get_drvdata(pdev
);
1315 struct sw
*sw
= netdev_priv(dev
);
1319 for (i
= 3; i
>= 0; i
--) {
1320 if (switch_port_tab
[i
]) {
1321 struct port
*port
= switch_port_tab
[i
];
1322 struct net_device
*dev
= port
->netdev
;
1323 unregister_netdev(dev
);
1324 phy_disconnect(port
->phydev
);
1325 switch_port_tab
[i
] = 0;
1330 free_netdev(napi_dev
);
1331 cns3xxx_mdio_remove();
1336 static struct platform_driver cns3xxx_eth_driver
= {
1337 .driver
.name
= DRV_NAME
,
1338 .probe
= eth_init_one
,
1339 .remove
= eth_remove_one
,
1342 static int __init
eth_init_module(void)
1344 return platform_driver_register(&cns3xxx_eth_driver
);
1347 static void __exit
eth_cleanup_module(void)
1349 platform_driver_unregister(&cns3xxx_eth_driver
);
1352 module_init(eth_init_module
);
1353 module_exit(eth_cleanup_module
);
1355 MODULE_AUTHOR("Chris Lang");
1356 MODULE_DESCRIPTION("Cavium CNS3xxx Ethernet driver");
1357 MODULE_LICENSE("GPL v2");
1358 MODULE_ALIAS("platform:cns3xxx_eth");