1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
36 * This file implements the Peripheral Controller Driver.
38 * The Peripheral Controller Driver (PCD) is responsible for
39 * translating requests from the Function Driver into the appropriate
40 * actions on the DWC_otg controller. It isolates the Function Driver
41 * from the specifics of the controller by providing an API to the
44 * The Peripheral Controller Driver for Linux will implement the
45 * Gadget API, so that the existing Gadget drivers can be used.
46 * (Gadget Driver is the Linux terminology for a Function Driver.)
48 * The Linux Gadget API is defined in the header file
49 * <code><linux/usb_gadget.h></code>. The USB EP operations API is
50 * defined in the structure <code>usb_ep_ops</code> and the USB
51 * Controller API is defined in the structure
52 * <code>usb_gadget_ops</code>.
54 * An important function of the PCD is managing interrupts generated
55 * by the DWC_otg controller. The implementation of the DWC_otg device
56 * mode interrupt service routines is in dwc_otg_pcd_intr.c.
58 * @todo Add Device Mode test modes (Test J mode, Test K mode, etc).
59 * @todo Does it work when the request size is greater than DEPTSIZ
65 #include <linux/kernel.h>
66 #include <linux/module.h>
67 #include <linux/moduleparam.h>
68 #include <linux/init.h>
69 #include <linux/device.h>
70 #include <linux/platform_device.h>
71 #include <linux/errno.h>
72 #include <linux/list.h>
73 #include <linux/interrupt.h>
74 #include <linux/string.h>
75 #include <linux/dma-mapping.h>
76 #include <linux/version.h>
78 #include <mach/irqs.h>
79 #include <linux/usb/ch9.h>
81 //#include <linux/usb_gadget.h>
83 #include "otg_driver.h"
89 * Static PCD pointer for use in usb_gadget_register_driver and
90 * usb_gadget_unregister_driver. Initialized in dwc_otg_pcd_init.
92 static dwc_otg_pcd_t
*s_pcd
= 0;
95 /* Display the contents of the buffer */
96 extern void dump_msg(const u8
*buf
, unsigned int length
);
100 * This function completes a request. It call's the request call back.
102 void dwc_otg_request_done(dwc_otg_pcd_ep_t
*ep
, dwc_otg_pcd_request_t
*req
,
105 unsigned stopped
= ep
->stopped
;
107 DWC_DEBUGPL(DBG_PCDV
, "%s(%p)\n", __func__
, ep
);
108 list_del_init(&req
->queue
);
110 if (req
->req
.status
== -EINPROGRESS
) {
111 req
->req
.status
= status
;
113 status
= req
->req
.status
;
116 /* don't modify queue heads during completion callback */
118 SPIN_UNLOCK(&ep
->pcd
->lock
);
119 req
->req
.complete(&ep
->ep
, &req
->req
);
120 SPIN_LOCK(&ep
->pcd
->lock
);
122 if (ep
->pcd
->request_pending
> 0) {
123 --ep
->pcd
->request_pending
;
126 ep
->stopped
= stopped
;
130 * This function terminates all the requsts in the EP request queue.
132 void dwc_otg_request_nuke(dwc_otg_pcd_ep_t
*ep
)
134 dwc_otg_pcd_request_t
*req
;
138 /* called with irqs blocked?? */
139 while (!list_empty(&ep
->queue
)) {
140 req
= list_entry(ep
->queue
.next
, dwc_otg_pcd_request_t
,
142 dwc_otg_request_done(ep
, req
, -ESHUTDOWN
);
146 /* USB Endpoint Operations */
148 * The following sections briefly describe the behavior of the Gadget
149 * API endpoint operations implemented in the DWC_otg driver
150 * software. Detailed descriptions of the generic behavior of each of
151 * these functions can be found in the Linux header file
152 * include/linux/usb_gadget.h.
154 * The Gadget API provides wrapper functions for each of the function
155 * pointers defined in usb_ep_ops. The Gadget Driver calls the wrapper
156 * function, which then calls the underlying PCD function. The
157 * following sections are named according to the wrapper
158 * functions. Within each section, the corresponding DWC_otg PCD
159 * function name is specified.
164 * This function assigns periodic Tx FIFO to an periodic EP
165 * in shared Tx FIFO mode
167 static uint32_t assign_perio_tx_fifo(dwc_otg_core_if_t
*core_if
)
169 uint32_t PerTxMsk
= 1;
171 for(i
= 0; i
< core_if
->hwcfg4
.b
.num_dev_perio_in_ep
; ++i
)
173 if((PerTxMsk
& core_if
->p_tx_msk
) == 0) {
174 core_if
->p_tx_msk
|= PerTxMsk
;
182 * This function releases periodic Tx FIFO
183 * in shared Tx FIFO mode
185 static void release_perio_tx_fifo(dwc_otg_core_if_t
*core_if
, uint32_t fifo_num
)
187 core_if
->p_tx_msk
= (core_if
->p_tx_msk
& (1 << (fifo_num
- 1))) ^ core_if
->p_tx_msk
;
190 * This function assigns periodic Tx FIFO to an periodic EP
191 * in shared Tx FIFO mode
193 static uint32_t assign_tx_fifo(dwc_otg_core_if_t
*core_if
)
198 for(i
= 0; i
< core_if
->hwcfg4
.b
.num_in_eps
; ++i
)
200 if((TxMsk
& core_if
->tx_msk
) == 0) {
201 core_if
->tx_msk
|= TxMsk
;
209 * This function releases periodic Tx FIFO
210 * in shared Tx FIFO mode
212 static void release_tx_fifo(dwc_otg_core_if_t
*core_if
, uint32_t fifo_num
)
214 core_if
->tx_msk
= (core_if
->tx_msk
& (1 << (fifo_num
- 1))) ^ core_if
->tx_msk
;
218 * This function is called by the Gadget Driver for each EP to be
219 * configured for the current configuration (SET_CONFIGURATION).
221 * This function initializes the dwc_otg_ep_t data structure, and then
222 * calls dwc_otg_ep_activate.
224 static int dwc_otg_pcd_ep_enable(struct usb_ep
*usb_ep
,
225 const struct usb_endpoint_descriptor
*ep_desc
)
227 dwc_otg_pcd_ep_t
*ep
= 0;
228 dwc_otg_pcd_t
*pcd
= 0;
231 DWC_DEBUGPL(DBG_PCDV
,"%s(%p,%p)\n", __func__
, usb_ep
, ep_desc
);
233 ep
= container_of(usb_ep
, dwc_otg_pcd_ep_t
, ep
);
234 if (!usb_ep
|| !ep_desc
|| ep
->desc
||
235 ep_desc
->bDescriptorType
!= USB_DT_ENDPOINT
) {
236 DWC_WARN("%s, bad ep or descriptor\n", __func__
);
239 if (ep
== &ep
->pcd
->ep0
) {
240 DWC_WARN("%s, bad ep(0)\n", __func__
);
244 /* Check FIFO size? */
245 if (!ep_desc
->wMaxPacketSize
) {
246 DWC_WARN("%s, bad %s maxpacket\n", __func__
, usb_ep
->name
);
251 if (!pcd
->driver
|| pcd
->gadget
.speed
== USB_SPEED_UNKNOWN
) {
252 DWC_WARN("%s, bogus device state\n", __func__
);
256 SPIN_LOCK_IRQSAVE(&pcd
->lock
, flags
);
259 ep
->ep
.maxpacket
= le16_to_cpu (ep_desc
->wMaxPacketSize
);
266 ep
->dwc_ep
.is_in
= (USB_DIR_IN
& ep_desc
->bEndpointAddress
) != 0;
267 ep
->dwc_ep
.maxpacket
= ep
->ep
.maxpacket
;
269 ep
->dwc_ep
.type
= ep_desc
->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
;
271 if(ep
->dwc_ep
.is_in
) {
272 if(!pcd
->otg_dev
->core_if
->en_multiple_tx_fifo
) {
273 ep
->dwc_ep
.tx_fifo_num
= 0;
275 if (ep
->dwc_ep
.type
== USB_ENDPOINT_XFER_ISOC
) {
277 * if ISOC EP then assign a Periodic Tx FIFO.
279 ep
->dwc_ep
.tx_fifo_num
= assign_perio_tx_fifo(pcd
->otg_dev
->core_if
);
283 * if Dedicated FIFOs mode is on then assign a Tx FIFO.
285 ep
->dwc_ep
.tx_fifo_num
= assign_tx_fifo(pcd
->otg_dev
->core_if
);
289 /* Set initial data PID. */
290 if (ep
->dwc_ep
.type
== USB_ENDPOINT_XFER_BULK
) {
291 ep
->dwc_ep
.data_pid_start
= 0;
294 DWC_DEBUGPL(DBG_PCD
, "Activate %s-%s: type=%d, mps=%d desc=%p\n",
295 ep
->ep
.name
, (ep
->dwc_ep
.is_in
?"IN":"OUT"),
296 ep
->dwc_ep
.type
, ep
->dwc_ep
.maxpacket
, ep
->desc
);
298 if(ep
->dwc_ep
.type
!= USB_ENDPOINT_XFER_ISOC
) {
299 ep
->dwc_ep
.desc_addr
= dwc_otg_ep_alloc_desc_chain(&ep
->dwc_ep
.dma_desc_addr
, MAX_DMA_DESC_CNT
);
302 dwc_otg_ep_activate(GET_CORE_IF(pcd
), &ep
->dwc_ep
);
303 SPIN_UNLOCK_IRQRESTORE(&pcd
->lock
, flags
);
309 * This function is called when an EP is disabled due to disconnect or
310 * change in configuration. Any pending requests will terminate with a
311 * status of -ESHUTDOWN.
313 * This function modifies the dwc_otg_ep_t data structure for this EP,
314 * and then calls dwc_otg_ep_deactivate.
316 static int dwc_otg_pcd_ep_disable(struct usb_ep
*usb_ep
)
318 dwc_otg_pcd_ep_t
*ep
;
319 dwc_otg_pcd_t
*pcd
= 0;
322 DWC_DEBUGPL(DBG_PCDV
,"%s(%p)\n", __func__
, usb_ep
);
323 ep
= container_of(usb_ep
, dwc_otg_pcd_ep_t
, ep
);
324 if (!usb_ep
|| !ep
->desc
) {
325 DWC_DEBUGPL(DBG_PCD
, "%s, %s not enabled\n", __func__
,
326 usb_ep
? ep
->ep
.name
: NULL
);
330 SPIN_LOCK_IRQSAVE(&ep
->pcd
->lock
, flags
);
332 dwc_otg_request_nuke(ep
);
334 dwc_otg_ep_deactivate(GET_CORE_IF(ep
->pcd
), &ep
->dwc_ep
);
338 if(ep
->dwc_ep
.is_in
) {
339 dwc_otg_flush_tx_fifo(GET_CORE_IF(ep
->pcd
), ep
->dwc_ep
.tx_fifo_num
);
340 release_perio_tx_fifo(GET_CORE_IF(ep
->pcd
), ep
->dwc_ep
.tx_fifo_num
);
341 release_tx_fifo(GET_CORE_IF(ep
->pcd
), ep
->dwc_ep
.tx_fifo_num
);
344 /* Free DMA Descriptors */
347 SPIN_UNLOCK_IRQRESTORE(&ep
->pcd
->lock
, flags
);
349 if(ep
->dwc_ep
.type
!= USB_ENDPOINT_XFER_ISOC
&& ep
->dwc_ep
.desc_addr
) {
350 dwc_otg_ep_free_desc_chain(ep
->dwc_ep
.desc_addr
, ep
->dwc_ep
.dma_desc_addr
, MAX_DMA_DESC_CNT
);
353 DWC_DEBUGPL(DBG_PCD
, "%s disabled\n", usb_ep
->name
);
359 * This function allocates a request object to use with the specified
362 * @param ep The endpoint to be used with with the request
363 * @param gfp_flags the GFP_* flags to use.
365 static struct usb_request
*dwc_otg_pcd_alloc_request(struct usb_ep
*ep
,
368 dwc_otg_pcd_request_t
*req
;
370 DWC_DEBUGPL(DBG_PCDV
,"%s(%p,%d)\n", __func__
, ep
, gfp_flags
);
372 DWC_WARN("%s() %s\n", __func__
, "Invalid EP!\n");
375 req
= kmalloc(sizeof(dwc_otg_pcd_request_t
), gfp_flags
);
377 DWC_WARN("%s() %s\n", __func__
,
378 "request allocation failed!\n");
381 memset(req
, 0, sizeof(dwc_otg_pcd_request_t
));
382 req
->req
.dma
= DMA_ADDR_INVALID
;
383 INIT_LIST_HEAD(&req
->queue
);
388 * This function frees a request object.
390 * @param ep The endpoint associated with the request
391 * @param req The request being freed
393 static void dwc_otg_pcd_free_request(struct usb_ep
*ep
,
394 struct usb_request
*req
)
396 dwc_otg_pcd_request_t
*request
;
397 DWC_DEBUGPL(DBG_PCDV
,"%s(%p,%p)\n", __func__
, ep
, req
);
399 if (0 == ep
|| 0 == req
) {
400 DWC_WARN("%s() %s\n", __func__
,
401 "Invalid ep or req argument!\n");
405 request
= container_of(req
, dwc_otg_pcd_request_t
, req
);
411 * This function allocates an I/O buffer to be used for a transfer
412 * to/from the specified endpoint.
414 * @param usb_ep The endpoint to be used with with the request
415 * @param bytes The desired number of bytes for the buffer
416 * @param dma Pointer to the buffer's DMA address; must be valid
417 * @param gfp_flags the GFP_* flags to use.
418 * @return address of a new buffer or null is buffer could not be allocated.
420 static void *dwc_otg_pcd_alloc_buffer(struct usb_ep
*usb_ep
, unsigned bytes
,
425 dwc_otg_pcd_ep_t
*ep
;
426 dwc_otg_pcd_t
*pcd
= 0;
428 ep
= container_of(usb_ep
, dwc_otg_pcd_ep_t
, ep
);
431 DWC_DEBUGPL(DBG_PCDV
,"%s(%p,%d,%p,%0x)\n", __func__
, usb_ep
, bytes
,
434 /* Check dword alignment */
435 if ((bytes
& 0x3UL
) != 0) {
436 DWC_WARN("%s() Buffer size is not a multiple of"
437 "DWORD size (%d)",__func__
, bytes
);
440 if (GET_CORE_IF(pcd
)->dma_enable
) {
441 buf
= dma_alloc_coherent (NULL
, bytes
, dma
, gfp_flags
);
444 buf
= kmalloc(bytes
, gfp_flags
);
447 /* Check dword alignment */
448 if (((int)buf
& 0x3UL
) != 0) {
449 DWC_WARN("%s() Buffer is not DWORD aligned (%p)",
457 * This function frees an I/O buffer that was allocated by alloc_buffer.
459 * @param usb_ep the endpoint associated with the buffer
460 * @param buf address of the buffer
461 * @param dma The buffer's DMA address
462 * @param bytes The number of bytes of the buffer
464 static void dwc_otg_pcd_free_buffer(struct usb_ep
*usb_ep
, void *buf
,
465 dma_addr_t dma
, unsigned bytes
)
467 dwc_otg_pcd_ep_t
*ep
;
468 dwc_otg_pcd_t
*pcd
= 0;
470 ep
= container_of(usb_ep
, dwc_otg_pcd_ep_t
, ep
);
473 DWC_DEBUGPL(DBG_PCDV
,"%s(%p,%p,%0x,%d)\n", __func__
, ep
, buf
, dma
, bytes
);
475 if (GET_CORE_IF(pcd
)->dma_enable
) {
476 dma_free_coherent (NULL
, bytes
, buf
, dma
);
485 * This function is used to submit an I/O Request to an EP.
487 * - When the request completes the request's completion callback
488 * is called to return the request to the driver.
489 * - An EP, except control EPs, may have multiple requests
491 * - Once submitted the request cannot be examined or modified.
492 * - Each request is turned into one or more packets.
493 * - A BULK EP can queue any amount of data; the transfer is
495 * - Zero length Packets are specified with the request 'zero'
498 static int dwc_otg_pcd_ep_queue(struct usb_ep
*usb_ep
,
499 struct usb_request
*usb_req
,
503 dwc_otg_pcd_request_t
*req
;
504 dwc_otg_pcd_ep_t
*ep
;
506 unsigned long flags
= 0;
508 DWC_DEBUGPL(DBG_PCDV
,"%s(%p,%p,%d)\n",
509 __func__
, usb_ep
, usb_req
, gfp_flags
);
511 req
= container_of(usb_req
, dwc_otg_pcd_request_t
, req
);
512 if (!usb_req
|| !usb_req
->complete
|| !usb_req
->buf
||
513 !list_empty(&req
->queue
)) {
514 DWC_WARN("%s, bad params\n", __func__
);
518 ep
= container_of(usb_ep
, dwc_otg_pcd_ep_t
, ep
);
519 if (!usb_ep
|| (!ep
->desc
&& ep
->dwc_ep
.num
!= 0)/* || ep->stopped != 0*/) {
520 DWC_WARN("%s, bad ep\n", __func__
);
525 if (!pcd
->driver
|| pcd
->gadget
.speed
== USB_SPEED_UNKNOWN
) {
526 DWC_DEBUGPL(DBG_PCDV
, "gadget.speed=%d\n", pcd
->gadget
.speed
);
527 DWC_WARN("%s, bogus device state\n", __func__
);
532 DWC_DEBUGPL(DBG_PCD
, "%s queue req %p, len %d buf %p\n",
533 usb_ep
->name
, usb_req
, usb_req
->length
, usb_req
->buf
);
535 if (!GET_CORE_IF(pcd
)->core_params
->opt
) {
536 if (ep
->dwc_ep
.num
!= 0) {
537 DWC_ERROR("%s queue req %p, len %d buf %p\n",
538 usb_ep
->name
, usb_req
, usb_req
->length
, usb_req
->buf
);
542 SPIN_LOCK_IRQSAVE(&ep
->pcd
->lock
, flags
);
544 #if defined(DEBUG) & defined(VERBOSE)
545 dump_msg(usb_req
->buf
, usb_req
->length
);
548 usb_req
->status
= -EINPROGRESS
;
552 * For EP0 IN without premature status, zlp is required?
554 if (ep
->dwc_ep
.num
== 0 && ep
->dwc_ep
.is_in
) {
555 DWC_DEBUGPL(DBG_PCDV
, "%s-OUT ZLP\n", usb_ep
->name
);
559 /* Start the transfer */
560 if (list_empty(&ep
->queue
) && !ep
->stopped
) {
562 if (ep
->dwc_ep
.num
== 0) {
563 switch (pcd
->ep0state
) {
564 case EP0_IN_DATA_PHASE
:
566 "%s ep0: EP0_IN_DATA_PHASE\n",
570 case EP0_OUT_DATA_PHASE
:
572 "%s ep0: EP0_OUT_DATA_PHASE\n",
574 if (pcd
->request_config
) {
575 /* Complete STATUS PHASE */
576 ep
->dwc_ep
.is_in
= 1;
577 pcd
->ep0state
= EP0_IN_STATUS_PHASE
;
581 case EP0_IN_STATUS_PHASE
:
583 "%s ep0: EP0_IN_STATUS_PHASE\n",
588 DWC_DEBUGPL(DBG_ANY
, "ep0: odd state %d\n",
590 SPIN_UNLOCK_IRQRESTORE(&pcd
->lock
, flags
);
593 ep
->dwc_ep
.dma_addr
= usb_req
->dma
;
594 ep
->dwc_ep
.start_xfer_buff
= usb_req
->buf
;
595 ep
->dwc_ep
.xfer_buff
= usb_req
->buf
;
596 ep
->dwc_ep
.xfer_len
= usb_req
->length
;
597 ep
->dwc_ep
.xfer_count
= 0;
598 ep
->dwc_ep
.sent_zlp
= 0;
599 ep
->dwc_ep
.total_len
= ep
->dwc_ep
.xfer_len
;
602 if((ep
->dwc_ep
.xfer_len
% ep
->dwc_ep
.maxpacket
== 0)
603 && (ep
->dwc_ep
.xfer_len
!= 0)) {
604 ep
->dwc_ep
.sent_zlp
= 1;
609 ep_check_and_patch_dma_addr(ep
);
610 dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd
), &ep
->dwc_ep
);
614 uint32_t max_transfer
= GET_CORE_IF(ep
->pcd
)->core_params
->max_transfer_size
;
616 /* Setup and start the Transfer */
617 ep
->dwc_ep
.dma_addr
= usb_req
->dma
;
618 ep
->dwc_ep
.start_xfer_buff
= usb_req
->buf
;
619 ep
->dwc_ep
.xfer_buff
= usb_req
->buf
;
620 ep
->dwc_ep
.sent_zlp
= 0;
621 ep
->dwc_ep
.total_len
= usb_req
->length
;
622 ep
->dwc_ep
.xfer_len
= 0;
623 ep
->dwc_ep
.xfer_count
= 0;
625 if(max_transfer
> MAX_TRANSFER_SIZE
) {
626 ep
->dwc_ep
.maxxfer
= max_transfer
- (max_transfer
% ep
->dwc_ep
.maxpacket
);
628 ep
->dwc_ep
.maxxfer
= max_transfer
;
632 if((ep
->dwc_ep
.total_len
% ep
->dwc_ep
.maxpacket
== 0)
633 && (ep
->dwc_ep
.total_len
!= 0)) {
634 ep
->dwc_ep
.sent_zlp
= 1;
639 ep_check_and_patch_dma_addr(ep
);
640 dwc_otg_ep_start_transfer(GET_CORE_IF(pcd
), &ep
->dwc_ep
);
644 if ((req
!= 0) || prevented
) {
645 ++pcd
->request_pending
;
646 list_add_tail(&req
->queue
, &ep
->queue
);
647 if (ep
->dwc_ep
.is_in
&& ep
->stopped
&& !(GET_CORE_IF(pcd
)->dma_enable
)) {
648 /** @todo NGS Create a function for this. */
649 diepmsk_data_t diepmsk
= { .d32
= 0};
650 diepmsk
.b
.intktxfemp
= 1;
651 if(&GET_CORE_IF(pcd
)->multiproc_int_enable
) {
652 dwc_modify_reg32(&GET_CORE_IF(pcd
)->dev_if
->dev_global_regs
->diepeachintmsk
[ep
->dwc_ep
.num
],
655 dwc_modify_reg32(&GET_CORE_IF(pcd
)->dev_if
->dev_global_regs
->diepmsk
, 0, diepmsk
.d32
);
660 SPIN_UNLOCK_IRQRESTORE(&pcd
->lock
, flags
);
665 * This function cancels an I/O request from an EP.
667 static int dwc_otg_pcd_ep_dequeue(struct usb_ep
*usb_ep
,
668 struct usb_request
*usb_req
)
670 dwc_otg_pcd_request_t
*req
;
671 dwc_otg_pcd_ep_t
*ep
;
675 DWC_DEBUGPL(DBG_PCDV
,"%s(%p,%p)\n", __func__
, usb_ep
, usb_req
);
677 ep
= container_of(usb_ep
, dwc_otg_pcd_ep_t
, ep
);
678 if (!usb_ep
|| !usb_req
|| (!ep
->desc
&& ep
->dwc_ep
.num
!= 0)) {
679 DWC_WARN("%s, bad argument\n", __func__
);
683 if (!pcd
->driver
|| pcd
->gadget
.speed
== USB_SPEED_UNKNOWN
) {
684 DWC_WARN("%s, bogus device state\n", __func__
);
688 SPIN_LOCK_IRQSAVE(&pcd
->lock
, flags
);
689 DWC_DEBUGPL(DBG_PCDV
, "%s %s %s %p\n", __func__
, usb_ep
->name
,
690 ep
->dwc_ep
.is_in
? "IN" : "OUT",
693 /* make sure it's actually queued on this endpoint */
694 list_for_each_entry(req
, &ep
->queue
, queue
)
696 if (&req
->req
== usb_req
) {
701 if (&req
->req
!= usb_req
) {
702 SPIN_UNLOCK_IRQRESTORE(&pcd
->lock
, flags
);
706 if (!list_empty(&req
->queue
)) {
707 dwc_otg_request_done(ep
, req
, -ECONNRESET
);
713 SPIN_UNLOCK_IRQRESTORE(&pcd
->lock
, flags
);
715 return req
? 0 : -EOPNOTSUPP
;
719 * usb_ep_set_halt stalls an endpoint.
721 * usb_ep_clear_halt clears an endpoint halt and resets its data
724 * Both of these functions are implemented with the same underlying
725 * function. The behavior depends on the value argument.
727 * @param[in] usb_ep the Endpoint to halt or clear halt.
729 * - 0 means clear_halt.
730 * - 1 means set_halt,
731 * - 2 means clear stall lock flag.
732 * - 3 means set stall lock flag.
734 static int dwc_otg_pcd_ep_set_halt(struct usb_ep
*usb_ep
, int value
)
738 dwc_otg_pcd_ep_t
*ep
= 0;
741 DWC_DEBUGPL(DBG_PCD
,"HALT %s %d\n", usb_ep
->name
, value
);
743 ep
= container_of(usb_ep
, dwc_otg_pcd_ep_t
, ep
);
745 if (!usb_ep
|| (!ep
->desc
&& ep
!= &ep
->pcd
->ep0
) ||
746 ep
->desc
->bmAttributes
== USB_ENDPOINT_XFER_ISOC
) {
747 DWC_WARN("%s, bad ep\n", __func__
);
751 SPIN_LOCK_IRQSAVE(&ep
->pcd
->lock
, flags
);
752 if (!list_empty(&ep
->queue
)) {
753 DWC_WARN("%s() %s XFer In process\n", __func__
, usb_ep
->name
);
756 else if (value
== 0) {
757 dwc_otg_ep_clear_stall(ep
->pcd
->otg_dev
->core_if
,
760 else if(value
== 1) {
761 if (ep
->dwc_ep
.is_in
== 1 && ep
->pcd
->otg_dev
->core_if
->dma_desc_enable
) {
762 dtxfsts_data_t txstatus
;
763 fifosize_data_t txfifosize
;
765 txfifosize
.d32
= dwc_read_reg32(&ep
->pcd
->otg_dev
->core_if
->core_global_regs
->dptxfsiz_dieptxf
[ep
->dwc_ep
.tx_fifo_num
]);
766 txstatus
.d32
= dwc_read_reg32(&ep
->pcd
->otg_dev
->core_if
->dev_if
->in_ep_regs
[ep
->dwc_ep
.num
]->dtxfsts
);
768 if(txstatus
.b
.txfspcavail
< txfifosize
.b
.depth
) {
769 DWC_WARN("%s() %s Data In Tx Fifo\n", __func__
, usb_ep
->name
);
773 if (ep
->dwc_ep
.num
== 0) {
774 ep
->pcd
->ep0state
= EP0_STALL
;
778 dwc_otg_ep_set_stall(ep
->pcd
->otg_dev
->core_if
,
783 if (ep
->dwc_ep
.num
== 0) {
784 ep
->pcd
->ep0state
= EP0_STALL
;
788 dwc_otg_ep_set_stall(ep
->pcd
->otg_dev
->core_if
,
792 else if (value
== 2) {
793 ep
->dwc_ep
.stall_clear_flag
= 0;
795 else if (value
== 3) {
796 ep
->dwc_ep
.stall_clear_flag
= 1;
799 SPIN_UNLOCK_IRQRESTORE(&ep
->pcd
->lock
, flags
);
804 * This function allocates a DMA Descriptor chain for the Endpoint
805 * buffer to be used for a transfer to/from the specified endpoint.
807 dwc_otg_dma_desc_t
* dwc_otg_ep_alloc_desc_chain(uint32_t * dma_desc_addr
, uint32_t count
)
810 return dma_alloc_coherent(NULL
, count
* sizeof(dwc_otg_dma_desc_t
), dma_desc_addr
, GFP_KERNEL
);
813 LIST_HEAD(tofree_list
);
814 DEFINE_SPINLOCK(tofree_list_lock
);
817 struct list_head list
;
823 static void free_list_agent_fn(struct work_struct
*work
) {
824 struct list_head free_list
;
825 struct free_param
*cur
,*next
;
827 spin_lock(&tofree_list_lock
);
828 list_add(&free_list
,&tofree_list
);
829 list_del_init(&tofree_list
);
830 spin_unlock(&tofree_list_lock
);
832 list_for_each_entry_safe(cur
,next
,&free_list
,list
){
833 if(&cur
->list
==&free_list
) break;
834 dma_free_coherent(NULL
,cur
->size
,cur
->addr
,cur
->dma_addr
);
835 list_del(&cur
->list
);
839 DECLARE_WORK(free_list_agent
,free_list_agent_fn
);
841 * This function frees a DMA Descriptor chain that was allocated by ep_alloc_desc.
843 void dwc_otg_ep_free_desc_chain(dwc_otg_dma_desc_t
* desc_addr
, uint32_t dma_desc_addr
, uint32_t count
)
846 struct free_param
* fp
=kmalloc(sizeof(struct free_param
),GFP_KERNEL
);
848 fp
->dma_addr
=dma_desc_addr
;
849 fp
->size
=count
*sizeof(dwc_otg_dma_desc_t
);
851 spin_lock(&tofree_list_lock
);
852 list_add(&fp
->list
,&tofree_list
);
853 spin_unlock(&tofree_list_lock
);
855 schedule_work(&free_list_agent
);
858 dma_free_coherent(NULL
, count
* sizeof(dwc_otg_dma_desc_t
), desc_addr
, dma_desc_addr
);
864 * This function initializes a descriptor chain for Isochronous transfer
866 * @param core_if Programming view of DWC_otg controller.
867 * @param dwc_ep The EP to start the transfer on.
870 void dwc_otg_iso_ep_start_ddma_transfer(dwc_otg_core_if_t
*core_if
, dwc_ep_t
*dwc_ep
)
873 dsts_data_t dsts
= { .d32
= 0};
874 depctl_data_t depctl
= { .d32
= 0 };
875 volatile uint32_t *addr
;
879 dwc_ep
->desc_cnt
= dwc_ep
->buf_proc_intrvl
/ dwc_ep
->bInterval
;
881 dwc_ep
->desc_cnt
= dwc_ep
->buf_proc_intrvl
* dwc_ep
->pkt_per_frm
/ dwc_ep
->bInterval
;
884 /** Allocate descriptors for double buffering */
885 dwc_ep
->iso_desc_addr
= dwc_otg_ep_alloc_desc_chain(&dwc_ep
->iso_dma_desc_addr
,dwc_ep
->desc_cnt
*2);
886 if(dwc_ep
->desc_addr
) {
887 DWC_WARN("%s, can't allocate DMA descriptor chain\n", __func__
);
891 dsts
.d32
= dwc_read_reg32(&core_if
->dev_if
->dev_global_regs
->dsts
);
894 if(dwc_ep
->is_in
== 0) {
895 desc_sts_data_t sts
= { .d32
=0 };
896 dwc_otg_dma_desc_t
* dma_desc
= dwc_ep
->iso_desc_addr
;
898 uint32_t data_per_desc
;
899 dwc_otg_dev_out_ep_regs_t
*out_regs
=
900 core_if
->dev_if
->out_ep_regs
[dwc_ep
->num
];
903 addr
= &core_if
->dev_if
->out_ep_regs
[dwc_ep
->num
]->doepctl
;
904 dma_ad
= (dma_addr_t
)dwc_read_reg32(&(out_regs
->doepdma
));
906 /** Buffer 0 descriptors setup */
907 dma_ad
= dwc_ep
->dma_addr0
;
909 sts
.b_iso_out
.bs
= BS_HOST_READY
;
910 sts
.b_iso_out
.rxsts
= 0;
912 sts
.b_iso_out
.sp
= 0;
913 sts
.b_iso_out
.ioc
= 0;
914 sts
.b_iso_out
.pid
= 0;
915 sts
.b_iso_out
.framenum
= 0;
918 for(i
= 0; i
< dwc_ep
->desc_cnt
- dwc_ep
->pkt_per_frm
; i
+= dwc_ep
->pkt_per_frm
)
921 for(j
= 0; j
< dwc_ep
->pkt_per_frm
; ++j
)
923 data_per_desc
= ((j
+ 1) * dwc_ep
->maxpacket
> dwc_ep
->data_per_frame
) ?
924 dwc_ep
->data_per_frame
- j
* dwc_ep
->maxpacket
: dwc_ep
->maxpacket
;
926 data_per_desc
+= (data_per_desc
% 4) ? (4 - data_per_desc
% 4):0;
927 sts
.b_iso_out
.rxbytes
= data_per_desc
;
928 writel((uint32_t)dma_ad
, &dma_desc
->buf
);
929 writel(sts
.d32
, &dma_desc
->status
);
931 offset
+= data_per_desc
;
933 //(uint32_t)dma_ad += data_per_desc;
934 dma_ad
= (uint32_t)dma_ad
+ data_per_desc
;
938 for(j
= 0; j
< dwc_ep
->pkt_per_frm
- 1; ++j
)
940 data_per_desc
= ((j
+ 1) * dwc_ep
->maxpacket
> dwc_ep
->data_per_frame
) ?
941 dwc_ep
->data_per_frame
- j
* dwc_ep
->maxpacket
: dwc_ep
->maxpacket
;
942 data_per_desc
+= (data_per_desc
% 4) ? (4 - data_per_desc
% 4):0;
943 sts
.b_iso_out
.rxbytes
= data_per_desc
;
944 writel((uint32_t)dma_ad
, &dma_desc
->buf
);
945 writel(sts
.d32
, &dma_desc
->status
);
947 offset
+= data_per_desc
;
949 //(uint32_t)dma_ad += data_per_desc;
950 dma_ad
= (uint32_t)dma_ad
+ data_per_desc
;
953 sts
.b_iso_out
.ioc
= 1;
954 data_per_desc
= ((j
+ 1) * dwc_ep
->maxpacket
> dwc_ep
->data_per_frame
) ?
955 dwc_ep
->data_per_frame
- j
* dwc_ep
->maxpacket
: dwc_ep
->maxpacket
;
956 data_per_desc
+= (data_per_desc
% 4) ? (4 - data_per_desc
% 4):0;
957 sts
.b_iso_out
.rxbytes
= data_per_desc
;
959 writel((uint32_t)dma_ad
, &dma_desc
->buf
);
960 writel(sts
.d32
, &dma_desc
->status
);
963 /** Buffer 1 descriptors setup */
964 sts
.b_iso_out
.ioc
= 0;
965 dma_ad
= dwc_ep
->dma_addr1
;
968 for(i
= 0; i
< dwc_ep
->desc_cnt
- dwc_ep
->pkt_per_frm
; i
+= dwc_ep
->pkt_per_frm
)
970 for(j
= 0; j
< dwc_ep
->pkt_per_frm
; ++j
)
972 data_per_desc
= ((j
+ 1) * dwc_ep
->maxpacket
> dwc_ep
->data_per_frame
) ?
973 dwc_ep
->data_per_frame
- j
* dwc_ep
->maxpacket
: dwc_ep
->maxpacket
;
974 data_per_desc
+= (data_per_desc
% 4) ? (4 - data_per_desc
% 4):0;
975 sts
.b_iso_out
.rxbytes
= data_per_desc
;
976 writel((uint32_t)dma_ad
, &dma_desc
->buf
);
977 writel(sts
.d32
, &dma_desc
->status
);
979 offset
+= data_per_desc
;
981 //(uint32_t)dma_ad += data_per_desc;
982 dma_ad
= (uint32_t)dma_ad
+ data_per_desc
;
985 for(j
= 0; j
< dwc_ep
->pkt_per_frm
- 1; ++j
)
987 data_per_desc
= ((j
+ 1) * dwc_ep
->maxpacket
> dwc_ep
->data_per_frame
) ?
988 dwc_ep
->data_per_frame
- j
* dwc_ep
->maxpacket
: dwc_ep
->maxpacket
;
989 data_per_desc
+= (data_per_desc
% 4) ? (4 - data_per_desc
% 4):0;
990 sts
.b_iso_out
.rxbytes
= data_per_desc
;
991 writel((uint32_t)dma_ad
, &dma_desc
->buf
);
992 writel(sts
.d32
, &dma_desc
->status
);
994 offset
+= data_per_desc
;
996 //(uint32_t)dma_ad += data_per_desc;
997 dma_ad
= (uint32_t)dma_ad
+ data_per_desc
;
1000 sts
.b_iso_out
.ioc
= 1;
1001 sts
.b_iso_out
.l
= 1;
1002 data_per_desc
= ((j
+ 1) * dwc_ep
->maxpacket
> dwc_ep
->data_per_frame
) ?
1003 dwc_ep
->data_per_frame
- j
* dwc_ep
->maxpacket
: dwc_ep
->maxpacket
;
1004 data_per_desc
+= (data_per_desc
% 4) ? (4 - data_per_desc
% 4):0;
1005 sts
.b_iso_out
.rxbytes
= data_per_desc
;
1007 writel((uint32_t)dma_ad
, &dma_desc
->buf
);
1008 writel(sts
.d32
, &dma_desc
->status
);
1010 dwc_ep
->next_frame
= 0;
1012 /** Write dma_ad into DOEPDMA register */
1013 dwc_write_reg32(&(out_regs
->doepdma
),(uint32_t)dwc_ep
->iso_dma_desc_addr
);
1018 desc_sts_data_t sts
= { .d32
=0 };
1019 dwc_otg_dma_desc_t
* dma_desc
= dwc_ep
->iso_desc_addr
;
1021 dwc_otg_dev_in_ep_regs_t
*in_regs
=
1022 core_if
->dev_if
->in_ep_regs
[dwc_ep
->num
];
1023 unsigned int frmnumber
;
1024 fifosize_data_t txfifosize
,rxfifosize
;
1026 txfifosize
.d32
= dwc_read_reg32(&core_if
->dev_if
->in_ep_regs
[dwc_ep
->num
]->dtxfsts
);
1027 rxfifosize
.d32
= dwc_read_reg32(&core_if
->core_global_regs
->grxfsiz
);
1030 addr
= &core_if
->dev_if
->in_ep_regs
[dwc_ep
->num
]->diepctl
;
1032 dma_ad
= dwc_ep
->dma_addr0
;
1034 dsts
.d32
= dwc_read_reg32(&core_if
->dev_if
->dev_global_regs
->dsts
);
1036 sts
.b_iso_in
.bs
= BS_HOST_READY
;
1037 sts
.b_iso_in
.txsts
= 0;
1038 sts
.b_iso_in
.sp
= (dwc_ep
->data_per_frame
% dwc_ep
->maxpacket
)? 1 : 0;
1039 sts
.b_iso_in
.ioc
= 0;
1040 sts
.b_iso_in
.pid
= dwc_ep
->pkt_per_frm
;
1043 frmnumber
= dwc_ep
->next_frame
;
1045 sts
.b_iso_in
.framenum
= frmnumber
;
1046 sts
.b_iso_in
.txbytes
= dwc_ep
->data_per_frame
;
1049 /** Buffer 0 descriptors setup */
1050 for(i
= 0; i
< dwc_ep
->desc_cnt
- 1; i
++)
1052 writel((uint32_t)dma_ad
, &dma_desc
->buf
);
1053 writel(sts
.d32
, &dma_desc
->status
);
1056 //(uint32_t)dma_ad += dwc_ep->data_per_frame;
1057 dma_ad
= (uint32_t)dma_ad
+ dwc_ep
->data_per_frame
;
1058 sts
.b_iso_in
.framenum
+= dwc_ep
->bInterval
;
1061 sts
.b_iso_in
.ioc
= 1;
1062 writel((uint32_t)dma_ad
, &dma_desc
->buf
);
1063 writel(sts
.d32
, &dma_desc
->status
);
1066 /** Buffer 1 descriptors setup */
1067 sts
.b_iso_in
.ioc
= 0;
1068 dma_ad
= dwc_ep
->dma_addr1
;
1070 for(i
= 0; i
< dwc_ep
->desc_cnt
- dwc_ep
->pkt_per_frm
; i
+= dwc_ep
->pkt_per_frm
)
1072 writel((uint32_t)dma_ad
, &dma_desc
->buf
);
1073 writel(sts
.d32
, &dma_desc
->status
);
1076 //(uint32_t)dma_ad += dwc_ep->data_per_frame;
1077 dma_ad
= (uint32_t)dma_ad
+ dwc_ep
->data_per_frame
;
1078 sts
.b_iso_in
.framenum
+= dwc_ep
->bInterval
;
1080 sts
.b_iso_in
.ioc
= 0;
1082 sts
.b_iso_in
.ioc
= 1;
1085 writel((uint32_t)dma_ad
, &dma_desc
->buf
);
1086 writel(sts
.d32
, &dma_desc
->status
);
1088 dwc_ep
->next_frame
= sts
.b_iso_in
.framenum
+ dwc_ep
->bInterval
;
1090 /** Write dma_ad into diepdma register */
1091 dwc_write_reg32(&(in_regs
->diepdma
),(uint32_t)dwc_ep
->iso_dma_desc_addr
);
1093 /** Enable endpoint, clear nak */
1096 depctl
.b
.usbactep
= 1;
1099 dwc_modify_reg32(addr
, depctl
.d32
,depctl
.d32
);
1100 depctl
.d32
= dwc_read_reg32(addr
);
1104 * This function initializes a descriptor chain for Isochronous transfer
1106 * @param core_if Programming view of DWC_otg controller.
1107 * @param ep The EP to start the transfer on.
1111 void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t
*core_if
, dwc_ep_t
*ep
)
1113 depctl_data_t depctl
= { .d32
= 0 };
1114 volatile uint32_t *addr
;
1118 addr
= &core_if
->dev_if
->in_ep_regs
[ep
->num
]->diepctl
;
1120 addr
= &core_if
->dev_if
->out_ep_regs
[ep
->num
]->doepctl
;
1124 if(core_if
->dma_enable
== 0 || core_if
->dma_desc_enable
!= 0) {
1127 deptsiz_data_t deptsiz
= { .d32
= 0 };
1129 ep
->xfer_len
= ep
->data_per_frame
* ep
->buf_proc_intrvl
/ ep
->bInterval
;
1130 ep
->pkt_cnt
= (ep
->xfer_len
- 1 + ep
->maxpacket
) /
1133 ep
->xfer_buff
= (ep
->proc_buf_num
) ? ep
->xfer_buff1
: ep
->xfer_buff0
;
1134 ep
->dma_addr
= (ep
->proc_buf_num
) ? ep
->dma_addr1
: ep
->dma_addr0
;
1137 /* Program the transfer size and packet count
1138 * as follows: xfersize = N * maxpacket +
1139 * short_packet pktcnt = N + (short_packet
1142 deptsiz
.b
.mc
= ep
->pkt_per_frm
;
1143 deptsiz
.b
.xfersize
= ep
->xfer_len
;
1145 (ep
->xfer_len
- 1 + ep
->maxpacket
) /
1147 dwc_write_reg32(&core_if
->dev_if
->in_ep_regs
[ep
->num
]->dieptsiz
, deptsiz
.d32
);
1149 /* Write the DMA register */
1150 dwc_write_reg32 (&(core_if
->dev_if
->in_ep_regs
[ep
->num
]->diepdma
), (uint32_t)ep
->dma_addr
);
1154 (ep
->xfer_len
+ (ep
->maxpacket
- 1)) /
1156 deptsiz
.b
.xfersize
= deptsiz
.b
.pktcnt
* ep
->maxpacket
;
1158 dwc_write_reg32(&core_if
->dev_if
->out_ep_regs
[ep
->num
]->doeptsiz
, deptsiz
.d32
);
1160 /* Write the DMA register */
1161 dwc_write_reg32 (&(core_if
->dev_if
->out_ep_regs
[ep
->num
]->doepdma
), (uint32_t)ep
->dma_addr
);
1164 /** Enable endpoint, clear nak */
1166 dwc_modify_reg32(addr
, depctl
.d32
,depctl
.d32
);
1171 dwc_modify_reg32(addr
, depctl
.d32
,depctl
.d32
);
1177 * This function does the setup for a data transfer for an EP and
1178 * starts the transfer. For an IN transfer, the packets will be
1179 * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
1180 * the packets are unloaded from the Rx FIFO in the ISR. the ISR.
1182 * @param core_if Programming view of DWC_otg controller.
1183 * @param ep The EP to start the transfer on.
1186 void dwc_otg_iso_ep_start_transfer(dwc_otg_core_if_t
*core_if
, dwc_ep_t
*ep
)
1188 if(core_if
->dma_enable
) {
1189 if(core_if
->dma_desc_enable
) {
1191 ep
->desc_cnt
= ep
->pkt_cnt
/ ep
->pkt_per_frm
;
1193 ep
->desc_cnt
= ep
->pkt_cnt
;
1195 dwc_otg_iso_ep_start_ddma_transfer(core_if
, ep
);
1197 if(core_if
->pti_enh_enable
) {
1198 dwc_otg_iso_ep_start_buf_transfer(core_if
, ep
);
1200 ep
->cur_pkt_addr
= (ep
->proc_buf_num
) ? ep
->xfer_buff1
: ep
->xfer_buff0
;
1201 ep
->cur_pkt_dma_addr
= (ep
->proc_buf_num
) ? ep
->dma_addr1
: ep
->dma_addr0
;
1202 dwc_otg_iso_ep_start_frm_transfer(core_if
, ep
);
1206 ep
->cur_pkt_addr
= (ep
->proc_buf_num
) ? ep
->xfer_buff1
: ep
->xfer_buff0
;
1207 ep
->cur_pkt_dma_addr
= (ep
->proc_buf_num
) ? ep
->dma_addr1
: ep
->dma_addr0
;
1208 dwc_otg_iso_ep_start_frm_transfer(core_if
, ep
);
1213 * This function does the setup for a data transfer for an EP and
1214 * starts the transfer. For an IN transfer, the packets will be
1215 * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
1216 * the packets are unloaded from the Rx FIFO in the ISR. the ISR.
1218 * @param core_if Programming view of DWC_otg controller.
1219 * @param ep The EP to start the transfer on.
1222 void dwc_otg_iso_ep_stop_transfer(dwc_otg_core_if_t
*core_if
, dwc_ep_t
*ep
)
1224 depctl_data_t depctl
= { .d32
= 0 };
1225 volatile uint32_t *addr
;
1227 if(ep
->is_in
== 1) {
1228 addr
= &core_if
->dev_if
->in_ep_regs
[ep
->num
]->diepctl
;
1231 addr
= &core_if
->dev_if
->out_ep_regs
[ep
->num
]->doepctl
;
1234 /* disable the ep */
1235 depctl
.d32
= dwc_read_reg32(addr
);
1240 dwc_write_reg32(addr
, depctl
.d32
);
1242 if(core_if
->dma_desc_enable
&&
1243 ep
->iso_desc_addr
&& ep
->iso_dma_desc_addr
) {
1244 dwc_otg_ep_free_desc_chain(ep
->iso_desc_addr
,ep
->iso_dma_desc_addr
,ep
->desc_cnt
* 2);
1247 /* reset varibales */
1252 ep
->data_per_frame
= 0;
1253 ep
->data_pattern_frame
= 0;
1255 ep
->buf_proc_intrvl
= 0;
1257 ep
->proc_buf_num
= 0;
1258 ep
->pkt_per_frm
= 0;
1259 ep
->pkt_per_frm
= 0;
1261 ep
->iso_desc_addr
= 0;
1262 ep
->iso_dma_desc_addr
= 0;
1267 * This function is used to submit an ISOC Transfer Request to an EP.
1269 * - Every time a sync period completes the request's completion callback
1270 * is called to provide data to the gadget driver.
1271 * - Once submitted the request cannot be modified.
1272 * - Each request is turned into periodic data packets untill ISO
1273 * Transfer is stopped..
1275 static int dwc_otg_pcd_iso_ep_start(struct usb_ep
*usb_ep
, struct usb_iso_request
*req
,
1278 dwc_otg_pcd_ep_t
*ep
;
1281 unsigned long flags
= 0;
1283 dwc_otg_core_if_t
*core_if
;
1288 if (!req
|| !req
->process_buffer
|| !req
->buf0
|| !req
->buf1
) {
1289 DWC_WARN("%s, bad params\n", __func__
);
1293 ep
= container_of(usb_ep
, dwc_otg_pcd_ep_t
, ep
);
1295 if (!usb_ep
|| !ep
->desc
|| ep
->dwc_ep
.num
== 0) {
1296 DWC_WARN("%s, bad ep\n", __func__
);
1301 core_if
= GET_CORE_IF(pcd
);
1303 dcfg
.d32
= dwc_read_reg32(&core_if
->dev_if
->dev_global_regs
->dcfg
);
1305 if (!pcd
->driver
|| pcd
->gadget
.speed
== USB_SPEED_UNKNOWN
) {
1306 DWC_DEBUGPL(DBG_PCDV
, "gadget.speed=%d\n", pcd
->gadget
.speed
);
1307 DWC_WARN("%s, bogus device state\n", __func__
);
1311 SPIN_LOCK_IRQSAVE(&ep
->pcd
->lock
, flags
);
1313 dwc_ep
= &ep
->dwc_ep
;
1316 DWC_WARN("%s, iso request in progress\n", __func__
);
1318 req
->status
= -EINPROGRESS
;
1320 dwc_ep
->dma_addr0
= req
->dma0
;
1321 dwc_ep
->dma_addr1
= req
->dma1
;
1323 dwc_ep
->xfer_buff0
= req
->buf0
;
1324 dwc_ep
->xfer_buff1
= req
->buf1
;
1328 dwc_ep
->data_per_frame
= req
->data_per_frame
;
1330 /** @todo - pattern data support is to be implemented in the future */
1331 dwc_ep
->data_pattern_frame
= req
->data_pattern_frame
;
1332 dwc_ep
->sync_frame
= req
->sync_frame
;
1334 dwc_ep
->buf_proc_intrvl
= req
->buf_proc_intrvl
;
1336 dwc_ep
->bInterval
= 1 << (ep
->desc
->bInterval
- 1);
1338 dwc_ep
->proc_buf_num
= 0;
1340 dwc_ep
->pkt_per_frm
= 0;
1341 frm_data
= ep
->dwc_ep
.data_per_frame
;
1342 while(frm_data
> 0) {
1343 dwc_ep
->pkt_per_frm
++;
1344 frm_data
-= ep
->dwc_ep
.maxpacket
;
1347 dsts
.d32
= dwc_read_reg32(&core_if
->dev_if
->dev_global_regs
->dsts
);
1349 if(req
->flags
& USB_REQ_ISO_ASAP
) {
1350 dwc_ep
->next_frame
= dsts
.b
.soffn
+ 1;
1351 if(dwc_ep
->bInterval
!= 1){
1352 dwc_ep
->next_frame
= dwc_ep
->next_frame
+ (dwc_ep
->bInterval
- 1 - dwc_ep
->next_frame
% dwc_ep
->bInterval
);
1355 dwc_ep
->next_frame
= req
->start_frame
;
1359 if(!core_if
->pti_enh_enable
) {
1360 dwc_ep
->pkt_cnt
= dwc_ep
->buf_proc_intrvl
* dwc_ep
->pkt_per_frm
/ dwc_ep
->bInterval
;
1363 (dwc_ep
->data_per_frame
* (dwc_ep
->buf_proc_intrvl
/ dwc_ep
->bInterval
)
1364 - 1 + dwc_ep
->maxpacket
) / dwc_ep
->maxpacket
;
1367 if(core_if
->dma_desc_enable
) {
1369 dwc_ep
->buf_proc_intrvl
* dwc_ep
->pkt_per_frm
/ dwc_ep
->bInterval
;
1372 dwc_ep
->pkt_info
= kmalloc(sizeof(iso_pkt_info_t
) * dwc_ep
->pkt_cnt
, GFP_KERNEL
);
1373 if(!dwc_ep
->pkt_info
) {
1376 if(core_if
->pti_enh_enable
) {
1377 memset(dwc_ep
->pkt_info
, 0, sizeof(iso_pkt_info_t
) * dwc_ep
->pkt_cnt
);
1380 dwc_ep
->cur_pkt
= 0;
1382 SPIN_UNLOCK_IRQRESTORE(&pcd
->lock
, flags
);
1384 dwc_otg_iso_ep_start_transfer(core_if
, dwc_ep
);
1390 * This function stops ISO EP Periodic Data Transfer.
1392 static int dwc_otg_pcd_iso_ep_stop(struct usb_ep
*usb_ep
, struct usb_iso_request
*req
)
1394 dwc_otg_pcd_ep_t
*ep
;
1397 unsigned long flags
;
1399 ep
= container_of(usb_ep
, dwc_otg_pcd_ep_t
, ep
);
1401 if (!usb_ep
|| !ep
->desc
|| ep
->dwc_ep
.num
== 0) {
1402 DWC_WARN("%s, bad ep\n", __func__
);
1408 if (!pcd
->driver
|| pcd
->gadget
.speed
== USB_SPEED_UNKNOWN
) {
1409 DWC_DEBUGPL(DBG_PCDV
, "gadget.speed=%d\n", pcd
->gadget
.speed
);
1410 DWC_WARN("%s, bogus device state\n", __func__
);
1414 dwc_ep
= &ep
->dwc_ep
;
1416 dwc_otg_iso_ep_stop_transfer(GET_CORE_IF(pcd
), dwc_ep
);
1418 kfree(dwc_ep
->pkt_info
);
1420 SPIN_LOCK_IRQSAVE(&pcd
->lock
, flags
);
1422 if(ep
->iso_req
!= req
) {
1426 req
->status
= -ECONNRESET
;
1428 SPIN_UNLOCK_IRQRESTORE(&pcd
->lock
, flags
);
1437 * This function is used for perodical data exchnage between PCD and gadget drivers.
1438 * for Isochronous EPs
1440 * - Every time a sync period completes this function is called to
1441 * perform data exchange between PCD and gadget
1443 void dwc_otg_iso_buffer_done(dwc_otg_pcd_ep_t
*ep
, dwc_otg_pcd_iso_request_t
*req
)
1446 struct usb_gadget_iso_packet_descriptor
*iso_packet
;
1449 dwc_ep
= &ep
->dwc_ep
;
1451 if(ep
->iso_req
->status
== -ECONNRESET
) {
1452 DWC_PRINT("Device has already disconnected\n");
1453 /*Device has been disconnected*/
1457 if(dwc_ep
->proc_buf_num
!= 0) {
1458 iso_packet
= ep
->iso_req
->iso_packet_desc0
;
1462 iso_packet
= ep
->iso_req
->iso_packet_desc1
;
1465 /* Fill in ISOC packets descriptors & pass to gadget driver*/
1467 for(i
= 0; i
< dwc_ep
->pkt_cnt
; ++i
) {
1468 iso_packet
[i
].status
= dwc_ep
->pkt_info
[i
].status
;
1469 iso_packet
[i
].offset
= dwc_ep
->pkt_info
[i
].offset
;
1470 iso_packet
[i
].actual_length
= dwc_ep
->pkt_info
[i
].length
;
1471 dwc_ep
->pkt_info
[i
].status
= 0;
1472 dwc_ep
->pkt_info
[i
].offset
= 0;
1473 dwc_ep
->pkt_info
[i
].length
= 0;
1476 /* Call callback function to process data buffer */
1477 ep
->iso_req
->status
= 0;/* success */
1479 SPIN_UNLOCK(&ep
->pcd
->lock
);
1480 ep
->iso_req
->process_buffer(&ep
->ep
, ep
->iso_req
);
1481 SPIN_LOCK(&ep
->pcd
->lock
);
1485 static struct usb_iso_request
*dwc_otg_pcd_alloc_iso_request(struct usb_ep
*ep
,int packets
,
1488 struct usb_iso_request
*pReq
= NULL
;
1492 req_size
= sizeof(struct usb_iso_request
);
1493 req_size
+= (2 * packets
* (sizeof(struct usb_gadget_iso_packet_descriptor
)));
1496 pReq
= kmalloc(req_size
, gfp_flags
);
1498 DWC_WARN("%s, can't allocate Iso Request\n", __func__
);
1501 pReq
->iso_packet_desc0
= (void*) (pReq
+ 1);
1503 pReq
->iso_packet_desc1
= pReq
->iso_packet_desc0
+ packets
;
1508 static void dwc_otg_pcd_free_iso_request(struct usb_ep
*ep
, struct usb_iso_request
*req
)
1513 static struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops
=
1517 .enable
= dwc_otg_pcd_ep_enable
,
1518 .disable
= dwc_otg_pcd_ep_disable
,
1520 .alloc_request
= dwc_otg_pcd_alloc_request
,
1521 .free_request
= dwc_otg_pcd_free_request
,
1523 //.alloc_buffer = dwc_otg_pcd_alloc_buffer,
1524 //.free_buffer = dwc_otg_pcd_free_buffer,
1526 .queue
= dwc_otg_pcd_ep_queue
,
1527 .dequeue
= dwc_otg_pcd_ep_dequeue
,
1529 .set_halt
= dwc_otg_pcd_ep_set_halt
,
1533 .iso_ep_start
= dwc_otg_pcd_iso_ep_start
,
1534 .iso_ep_stop
= dwc_otg_pcd_iso_ep_stop
,
1535 .alloc_iso_request
= dwc_otg_pcd_alloc_iso_request
,
1536 .free_iso_request
= dwc_otg_pcd_free_iso_request
,
1542 static struct usb_ep_ops dwc_otg_pcd_ep_ops
=
1544 .enable
= dwc_otg_pcd_ep_enable
,
1545 .disable
= dwc_otg_pcd_ep_disable
,
1547 .alloc_request
= dwc_otg_pcd_alloc_request
,
1548 .free_request
= dwc_otg_pcd_free_request
,
1550 // .alloc_buffer = dwc_otg_pcd_alloc_buffer,
1551 // .free_buffer = dwc_otg_pcd_free_buffer,
1553 .queue
= dwc_otg_pcd_ep_queue
,
1554 .dequeue
= dwc_otg_pcd_ep_dequeue
,
1556 .set_halt
= dwc_otg_pcd_ep_set_halt
,
1563 #endif /* DWC_EN_ISOC */
1564 /* Gadget Operations */
1566 * The following gadget operations will be implemented in the DWC_otg
1567 * PCD. Functions in the API that are not described below are not
1570 * The Gadget API provides wrapper functions for each of the function
1571 * pointers defined in usb_gadget_ops. The Gadget Driver calls the
1572 * wrapper function, which then calls the underlying PCD function. The
1573 * following sections are named according to the wrapper functions
1574 * (except for ioctl, which doesn't have a wrapper function). Within
1575 * each section, the corresponding DWC_otg PCD function name is
1581 *Gets the USB Frame number of the last SOF.
1583 static int dwc_otg_pcd_get_frame(struct usb_gadget
*gadget
)
1587 DWC_DEBUGPL(DBG_PCDV
,"%s(%p)\n", __func__
, gadget
);
1593 pcd
= container_of(gadget
, dwc_otg_pcd_t
, gadget
);
1594 dwc_otg_get_frame_number(GET_CORE_IF(pcd
));
1600 void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t
*pcd
)
1602 uint32_t *addr
= (uint32_t *)&(GET_CORE_IF(pcd
)->core_global_regs
->gotgctl
);
1606 val
.d32
= dwc_read_reg32(addr
);
1608 DWC_ERROR("Session Request Already active!\n");
1612 DWC_NOTICE("Session Request Initated\n");
1613 mem
.d32
= dwc_read_reg32(addr
);
1615 dwc_write_reg32(addr
, mem
.d32
);
1617 /* Start the SRP timer */
1618 dwc_otg_pcd_start_srp_timer(pcd
);
1622 void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t
*pcd
, int set
)
1624 dctl_data_t dctl
= {.d32
=0};
1625 volatile uint32_t *addr
= &(GET_CORE_IF(pcd
)->dev_if
->dev_global_regs
->dctl
);
1627 if (dwc_otg_is_device_mode(GET_CORE_IF(pcd
))) {
1628 if (pcd
->remote_wakeup_enable
) {
1630 dctl
.b
.rmtwkupsig
= 1;
1631 dwc_modify_reg32(addr
, 0, dctl
.d32
);
1632 DWC_DEBUGPL(DBG_PCD
, "Set Remote Wakeup\n");
1634 dwc_modify_reg32(addr
, dctl
.d32
, 0);
1635 DWC_DEBUGPL(DBG_PCD
, "Clear Remote Wakeup\n");
1641 DWC_DEBUGPL(DBG_PCD
, "Remote Wakeup is disabled\n");
1648 * Initiates Session Request Protocol (SRP) to wakeup the host if no
1649 * session is in progress. If a session is already in progress, but
1650 * the device is suspended, remote wakeup signaling is started.
1653 static int dwc_otg_pcd_wakeup(struct usb_gadget
*gadget
)
1655 unsigned long flags
;
1658 gotgctl_data_t gotgctl
;
1660 DWC_DEBUGPL(DBG_PCDV
,"%s(%p)\n", __func__
, gadget
);
1666 pcd
= container_of(gadget
, dwc_otg_pcd_t
, gadget
);
1668 SPIN_LOCK_IRQSAVE(&pcd
->lock
, flags
);
1671 * This function starts the Protocol if no session is in progress. If
1672 * a session is already in progress, but the device is suspended,
1673 * remote wakeup signaling is started.
1676 /* Check if valid session */
1677 gotgctl
.d32
= dwc_read_reg32(&(GET_CORE_IF(pcd
)->core_global_regs
->gotgctl
));
1678 if (gotgctl
.b
.bsesvld
) {
1679 /* Check if suspend state */
1680 dsts
.d32
= dwc_read_reg32(&(GET_CORE_IF(pcd
)->dev_if
->dev_global_regs
->dsts
));
1681 if (dsts
.b
.suspsts
) {
1682 dwc_otg_pcd_remote_wakeup(pcd
, 1);
1686 dwc_otg_pcd_initiate_srp(pcd
);
1689 SPIN_UNLOCK_IRQRESTORE(&pcd
->lock
, flags
);
1693 static const struct usb_gadget_ops dwc_otg_pcd_ops
=
1695 .get_frame
= dwc_otg_pcd_get_frame
,
1696 .wakeup
= dwc_otg_pcd_wakeup
,
1697 // current versions must always be self-powered
1701 * This function updates the otg values in the gadget structure.
1703 void dwc_otg_pcd_update_otg(dwc_otg_pcd_t
*pcd
, const unsigned reset
)
1706 if (!pcd
->gadget
.is_otg
)
1710 pcd
->b_hnp_enable
= 0;
1711 pcd
->a_hnp_support
= 0;
1712 pcd
->a_alt_hnp_support
= 0;
1715 pcd
->gadget
.b_hnp_enable
= pcd
->b_hnp_enable
;
1716 pcd
->gadget
.a_hnp_support
= pcd
->a_hnp_support
;
1717 pcd
->gadget
.a_alt_hnp_support
= pcd
->a_alt_hnp_support
;
1721 * This function is the top level PCD interrupt handler.
1723 static irqreturn_t
dwc_otg_pcd_irq(int irq
, void *dev
)
1725 dwc_otg_pcd_t
*pcd
= dev
;
1726 int32_t retval
= IRQ_NONE
;
1728 retval
= dwc_otg_pcd_handle_intr(pcd
);
1729 return IRQ_RETVAL(retval
);
1733 * PCD Callback function for initializing the PCD when switching to
1736 * @param p void pointer to the <code>dwc_otg_pcd_t</code>
1738 static int32_t dwc_otg_pcd_start_cb(void *p
)
1740 dwc_otg_pcd_t
*pcd
= (dwc_otg_pcd_t
*)p
;
1743 * Initialized the Core for Device mode.
1745 if (dwc_otg_is_device_mode(GET_CORE_IF(pcd
))) {
1746 dwc_otg_core_dev_init(GET_CORE_IF(pcd
));
1752 * PCD Callback function for stopping the PCD when switching to Host
1755 * @param p void pointer to the <code>dwc_otg_pcd_t</code>
1757 static int32_t dwc_otg_pcd_stop_cb(void *p
)
1759 dwc_otg_pcd_t
*pcd
= (dwc_otg_pcd_t
*)p
;
1760 extern void dwc_otg_pcd_stop(dwc_otg_pcd_t
*_pcd
);
1762 dwc_otg_pcd_stop(pcd
);
1768 * PCD Callback function for notifying the PCD when resuming from
1771 * @param p void pointer to the <code>dwc_otg_pcd_t</code>
1773 static int32_t dwc_otg_pcd_suspend_cb(void *p
)
1775 dwc_otg_pcd_t
*pcd
= (dwc_otg_pcd_t
*)p
;
1777 if (pcd
->driver
&& pcd
->driver
->resume
) {
1778 SPIN_UNLOCK(&pcd
->lock
);
1779 pcd
->driver
->suspend(&pcd
->gadget
);
1780 SPIN_LOCK(&pcd
->lock
);
1788 * PCD Callback function for notifying the PCD when resuming from
1791 * @param p void pointer to the <code>dwc_otg_pcd_t</code>
1793 static int32_t dwc_otg_pcd_resume_cb(void *p
)
1795 dwc_otg_pcd_t
*pcd
= (dwc_otg_pcd_t
*)p
;
1797 if (pcd
->driver
&& pcd
->driver
->resume
) {
1798 SPIN_UNLOCK(&pcd
->lock
);
1799 pcd
->driver
->resume(&pcd
->gadget
);
1800 SPIN_LOCK(&pcd
->lock
);
1803 /* Stop the SRP timeout timer. */
1804 if ((GET_CORE_IF(pcd
)->core_params
->phy_type
!= DWC_PHY_TYPE_PARAM_FS
) ||
1805 (!GET_CORE_IF(pcd
)->core_params
->i2c_enable
)) {
1806 if (GET_CORE_IF(pcd
)->srp_timer_started
) {
1807 GET_CORE_IF(pcd
)->srp_timer_started
= 0;
1808 del_timer(&pcd
->srp_timer
);
1816 * PCD Callback structure for handling mode switching.
1818 static dwc_otg_cil_callbacks_t pcd_callbacks
=
1820 .start
= dwc_otg_pcd_start_cb
,
1821 .stop
= dwc_otg_pcd_stop_cb
,
1822 .suspend
= dwc_otg_pcd_suspend_cb
,
1823 .resume_wakeup
= dwc_otg_pcd_resume_cb
,
1824 .p
= 0, /* Set at registration */
1828 * This function is called when the SRP timer expires. The SRP should
1829 * complete within 6 seconds.
1831 static void srp_timeout(unsigned long ptr
)
1833 gotgctl_data_t gotgctl
;
1834 dwc_otg_core_if_t
*core_if
= (dwc_otg_core_if_t
*)ptr
;
1835 volatile uint32_t *addr
= &core_if
->core_global_regs
->gotgctl
;
1837 gotgctl
.d32
= dwc_read_reg32(addr
);
1839 core_if
->srp_timer_started
= 0;
1841 if ((core_if
->core_params
->phy_type
== DWC_PHY_TYPE_PARAM_FS
) &&
1842 (core_if
->core_params
->i2c_enable
)) {
1843 DWC_PRINT("SRP Timeout\n");
1845 if ((core_if
->srp_success
) &&
1846 (gotgctl
.b
.bsesvld
)) {
1847 if (core_if
->pcd_cb
&& core_if
->pcd_cb
->resume_wakeup
) {
1848 core_if
->pcd_cb
->resume_wakeup(core_if
->pcd_cb
->p
);
1851 /* Clear Session Request */
1853 gotgctl
.b
.sesreq
= 1;
1854 dwc_modify_reg32(&core_if
->core_global_regs
->gotgctl
,
1857 core_if
->srp_success
= 0;
1860 DWC_ERROR("Device not connected/responding\n");
1861 gotgctl
.b
.sesreq
= 0;
1862 dwc_write_reg32(addr
, gotgctl
.d32
);
1865 else if (gotgctl
.b
.sesreq
) {
1866 DWC_PRINT("SRP Timeout\n");
1868 DWC_ERROR("Device not connected/responding\n");
1869 gotgctl
.b
.sesreq
= 0;
1870 dwc_write_reg32(addr
, gotgctl
.d32
);
1873 DWC_PRINT(" SRP GOTGCTL=%0x\n", gotgctl
.d32
);
1878 * Start the SRP timer to detect when the SRP does not complete within
1881 * @param pcd the pcd structure.
1883 void dwc_otg_pcd_start_srp_timer(dwc_otg_pcd_t
*pcd
)
1885 struct timer_list
*srp_timer
= &pcd
->srp_timer
;
1886 GET_CORE_IF(pcd
)->srp_timer_started
= 1;
1887 init_timer(srp_timer
);
1888 srp_timer
->function
= srp_timeout
;
1889 srp_timer
->data
= (unsigned long)GET_CORE_IF(pcd
);
1890 srp_timer
->expires
= jiffies
+ (HZ
*6);
1891 add_timer(srp_timer
);
1898 extern void start_next_request(dwc_otg_pcd_ep_t
*ep
);
1900 static void start_xfer_tasklet_func (unsigned long data
)
1902 dwc_otg_pcd_t
*pcd
= (dwc_otg_pcd_t
*)data
;
1903 dwc_otg_core_if_t
*core_if
= pcd
->otg_dev
->core_if
;
1906 depctl_data_t diepctl
;
1908 DWC_DEBUGPL(DBG_PCDV
, "Start xfer tasklet\n");
1910 diepctl
.d32
= dwc_read_reg32(&core_if
->dev_if
->in_ep_regs
[0]->diepctl
);
1912 if (pcd
->ep0
.queue_sof
) {
1913 pcd
->ep0
.queue_sof
= 0;
1914 start_next_request (&pcd
->ep0
);
1918 for (i
=0; i
<core_if
->dev_if
->num_in_eps
; i
++)
1920 depctl_data_t diepctl
;
1921 diepctl
.d32
= dwc_read_reg32(&core_if
->dev_if
->in_ep_regs
[i
]->diepctl
);
1923 if (pcd
->in_ep
[i
].queue_sof
) {
1924 pcd
->in_ep
[i
].queue_sof
= 0;
1925 start_next_request (&pcd
->in_ep
[i
]);
1939 static struct tasklet_struct start_xfer_tasklet
= {
1942 .count
= ATOMIC_INIT(0),
1943 .func
= start_xfer_tasklet_func
,
1947 * This function initialized the pcd Dp structures to there default
1950 * @param pcd the pcd structure.
1952 void dwc_otg_pcd_reinit(dwc_otg_pcd_t
*pcd
)
1954 static const char * names
[] =
1992 int in_ep_cntr
, out_ep_cntr
;
1994 uint32_t num_in_eps
= (GET_CORE_IF(pcd
))->dev_if
->num_in_eps
;
1995 uint32_t num_out_eps
= (GET_CORE_IF(pcd
))->dev_if
->num_out_eps
;
1996 dwc_otg_pcd_ep_t
*ep
;
1998 DWC_DEBUGPL(DBG_PCDV
, "%s(%p)\n", __func__
, pcd
);
2000 INIT_LIST_HEAD (&pcd
->gadget
.ep_list
);
2001 pcd
->gadget
.ep0
= &pcd
->ep0
.ep
;
2002 pcd
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2004 INIT_LIST_HEAD (&pcd
->gadget
.ep0
->ep_list
);
2007 * Initialize the EP0 structure.
2011 /* Init EP structure */
2016 /* Init DWC ep structure */
2018 ep
->dwc_ep
.active
= 0;
2019 ep
->dwc_ep
.tx_fifo_num
= 0;
2020 /* Control until ep is actvated */
2021 ep
->dwc_ep
.type
= DWC_OTG_EP_TYPE_CONTROL
;
2022 ep
->dwc_ep
.maxpacket
= MAX_PACKET_SIZE
;
2023 ep
->dwc_ep
.dma_addr
= 0;
2024 ep
->dwc_ep
.start_xfer_buff
= 0;
2025 ep
->dwc_ep
.xfer_buff
= 0;
2026 ep
->dwc_ep
.xfer_len
= 0;
2027 ep
->dwc_ep
.xfer_count
= 0;
2028 ep
->dwc_ep
.sent_zlp
= 0;
2029 ep
->dwc_ep
.total_len
= 0;
2031 ep
->dwc_ep
.desc_addr
= 0;
2032 ep
->dwc_ep
.dma_desc_addr
= 0;
2034 ep
->dwc_ep
.aligned_buf
=NULL
;
2035 ep
->dwc_ep
.aligned_buf_size
=0;
2036 ep
->dwc_ep
.aligned_dma_addr
=0;
2039 /* Init the usb_ep structure. */
2040 ep
->ep
.name
= names
[0];
2041 ep
->ep
.ops
= (struct usb_ep_ops
*)&dwc_otg_pcd_ep_ops
;
2044 * @todo NGS: What should the max packet size be set to
2045 * here? Before EP type is set?
2047 ep
->ep
.maxpacket
= MAX_PACKET_SIZE
;
2049 list_add_tail (&ep
->ep
.ep_list
, &pcd
->gadget
.ep_list
);
2051 INIT_LIST_HEAD (&ep
->queue
);
2053 * Initialize the EP structures.
2056 hwcfg1
= (GET_CORE_IF(pcd
))->hwcfg1
.d32
>> 3;
2058 for (i
= 1; in_ep_cntr
< num_in_eps
; i
++)
2060 if((hwcfg1
& 0x1) == 0) {
2061 dwc_otg_pcd_ep_t
*ep
= &pcd
->in_ep
[in_ep_cntr
];
2064 /* Init EP structure */
2069 /* Init DWC ep structure */
2070 ep
->dwc_ep
.is_in
= 1;
2072 ep
->dwc_ep
.active
= 0;
2073 ep
->dwc_ep
.tx_fifo_num
= 0;
2075 /* Control until ep is actvated */
2076 ep
->dwc_ep
.type
= DWC_OTG_EP_TYPE_CONTROL
;
2077 ep
->dwc_ep
.maxpacket
= MAX_PACKET_SIZE
;
2078 ep
->dwc_ep
.dma_addr
= 0;
2079 ep
->dwc_ep
.start_xfer_buff
= 0;
2080 ep
->dwc_ep
.xfer_buff
= 0;
2081 ep
->dwc_ep
.xfer_len
= 0;
2082 ep
->dwc_ep
.xfer_count
= 0;
2083 ep
->dwc_ep
.sent_zlp
= 0;
2084 ep
->dwc_ep
.total_len
= 0;
2086 ep
->dwc_ep
.desc_addr
= 0;
2087 ep
->dwc_ep
.dma_desc_addr
= 0;
2089 /* Init the usb_ep structure. */
2090 ep
->ep
.name
= names
[i
];
2091 ep
->ep
.ops
= (struct usb_ep_ops
*)&dwc_otg_pcd_ep_ops
;
2094 * @todo NGS: What should the max packet size be set to
2095 * here? Before EP type is set?
2097 ep
->ep
.maxpacket
= MAX_PACKET_SIZE
;
2099 //add only even number ep as in
2101 list_add_tail (&ep
->ep
.ep_list
, &pcd
->gadget
.ep_list
);
2103 INIT_LIST_HEAD (&ep
->queue
);
2109 hwcfg1
= (GET_CORE_IF(pcd
))->hwcfg1
.d32
>> 2;
2111 for (i
= 1; out_ep_cntr
< num_out_eps
; i
++)
2113 if((hwcfg1
& 0x1) == 0) {
2114 dwc_otg_pcd_ep_t
*ep
= &pcd
->out_ep
[out_ep_cntr
];
2117 /* Init EP structure */
2122 /* Init DWC ep structure */
2123 ep
->dwc_ep
.is_in
= 0;
2125 ep
->dwc_ep
.active
= 0;
2126 ep
->dwc_ep
.tx_fifo_num
= 0;
2127 /* Control until ep is actvated */
2128 ep
->dwc_ep
.type
= DWC_OTG_EP_TYPE_CONTROL
;
2129 ep
->dwc_ep
.maxpacket
= MAX_PACKET_SIZE
;
2130 ep
->dwc_ep
.dma_addr
= 0;
2131 ep
->dwc_ep
.start_xfer_buff
= 0;
2132 ep
->dwc_ep
.xfer_buff
= 0;
2133 ep
->dwc_ep
.xfer_len
= 0;
2134 ep
->dwc_ep
.xfer_count
= 0;
2135 ep
->dwc_ep
.sent_zlp
= 0;
2136 ep
->dwc_ep
.total_len
= 0;
2139 /* Init the usb_ep structure. */
2140 ep
->ep
.name
= names
[15 + i
];
2141 ep
->ep
.ops
= (struct usb_ep_ops
*)&dwc_otg_pcd_ep_ops
;
2143 * @todo NGS: What should the max packet size be set to
2144 * here? Before EP type is set?
2146 ep
->ep
.maxpacket
= MAX_PACKET_SIZE
;
2148 //add only odd number ep as out
2150 list_add_tail (&ep
->ep
.ep_list
, &pcd
->gadget
.ep_list
);
2152 INIT_LIST_HEAD (&ep
->queue
);
2157 /* remove ep0 from the list. There is a ep0 pointer.*/
2158 list_del_init (&pcd
->ep0
.ep
.ep_list
);
2160 pcd
->ep0state
= EP0_DISCONNECT
;
2161 pcd
->ep0
.ep
.maxpacket
= MAX_EP0_SIZE
;
2162 pcd
->ep0
.dwc_ep
.maxpacket
= MAX_EP0_SIZE
;
2163 pcd
->ep0
.dwc_ep
.type
= DWC_OTG_EP_TYPE_CONTROL
;
2167 * This function releases the Gadget device.
2168 * required by device_unregister().
2170 * @todo Should this do something? Should it free the PCD?
2172 static void dwc_otg_pcd_gadget_release(struct device
*dev
)
2174 DWC_DEBUGPL(DBG_PCDV
,"%s(%p)\n", __func__
, dev
);
2180 * This function initialized the PCD portion of the driver.
2183 u8 dev_id
[]="gadget";
2184 int dwc_otg_pcd_init(struct platform_device
*pdev
)
2186 static char pcd_name
[] = "dwc_otg_pcd";
2188 dwc_otg_core_if_t
* core_if
;
2189 dwc_otg_dev_if_t
* dev_if
;
2190 dwc_otg_device_t
*otg_dev
= platform_get_drvdata(pdev
);
2194 DWC_DEBUGPL(DBG_PCDV
,"%s(%p)\n",__func__
, pdev
);
2196 * Allocate PCD structure
2198 pcd
= kmalloc(sizeof(dwc_otg_pcd_t
), GFP_KERNEL
);
2204 memset(pcd
, 0, sizeof(dwc_otg_pcd_t
));
2205 spin_lock_init(&pcd
->lock
);
2209 pcd
->gadget
.name
= pcd_name
;
2211 pcd
->gadget
.dev
.init_name
= dev_id
;
2212 pcd
->otg_dev
= platform_get_drvdata(pdev
);
2214 pcd
->gadget
.dev
.parent
= &pdev
->dev
;
2215 pcd
->gadget
.dev
.release
= dwc_otg_pcd_gadget_release
;
2216 pcd
->gadget
.ops
= &dwc_otg_pcd_ops
;
2218 core_if
= GET_CORE_IF(pcd
);
2219 dev_if
= core_if
->dev_if
;
2221 if(core_if
->hwcfg4
.b
.ded_fifo_en
) {
2222 DWC_PRINT("Dedicated Tx FIFOs mode\n");
2225 DWC_PRINT("Shared Tx FIFO mode\n");
2228 /* If the module is set to FS or if the PHY_TYPE is FS then the gadget
2229 * should not report as dual-speed capable. replace the following line
2230 * with the block of code below it once the software is debugged for
2231 * this. If is_dualspeed = 0 then the gadget driver should not report
2232 * a device qualifier descriptor when queried. */
2233 if ((GET_CORE_IF(pcd
)->core_params
->speed
== DWC_SPEED_PARAM_FULL
) ||
2234 ((GET_CORE_IF(pcd
)->hwcfg2
.b
.hs_phy_type
== 2) &&
2235 (GET_CORE_IF(pcd
)->hwcfg2
.b
.fs_phy_type
== 1) &&
2236 (GET_CORE_IF(pcd
)->core_params
->ulpi_fs_ls
))) {
2237 pcd
->gadget
.max_speed
= USB_SPEED_FULL
;
2240 pcd
->gadget
.max_speed
= USB_SPEED_HIGH
;
2243 if ((otg_dev
->core_if
->hwcfg2
.b
.op_mode
== DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE
) ||
2244 (otg_dev
->core_if
->hwcfg2
.b
.op_mode
== DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST
) ||
2245 (otg_dev
->core_if
->hwcfg2
.b
.op_mode
== DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE
) ||
2246 (otg_dev
->core_if
->hwcfg2
.b
.op_mode
== DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST
)) {
2247 pcd
->gadget
.is_otg
= 0;
2250 pcd
->gadget
.is_otg
= 1;
2255 /* Register the gadget device */
2256 printk("%s: 1\n",__func__
);
2257 retval
= device_register(&pcd
->gadget
.dev
);
2260 printk("%s: 2\n",__func__
);
2266 * Initialized the Core for Device mode.
2268 if (dwc_otg_is_device_mode(core_if
)) {
2269 dwc_otg_core_dev_init(core_if
);
2273 * Initialize EP structures
2275 dwc_otg_pcd_reinit(pcd
);
2278 * Register the PCD Callbacks.
2280 dwc_otg_cil_register_pcd_callbacks(otg_dev
->core_if
, &pcd_callbacks
,
2283 * Setup interupt handler
2285 DWC_DEBUGPL(DBG_ANY
, "registering handler for irq%d\n", otg_dev
->irq
);
2286 retval
= request_irq(otg_dev
->irq
, dwc_otg_pcd_irq
,
2287 IRQF_SHARED
, pcd
->gadget
.name
, pcd
);
2289 DWC_ERROR("request of irq%d failed\n", otg_dev
->irq
);
2290 device_unregister(&pcd
->gadget
.dev
);
2296 * Initialize the DMA buffer for SETUP packets
2298 if (GET_CORE_IF(pcd
)->dma_enable
) {
2299 pcd
->setup_pkt
= dma_alloc_coherent (NULL
, sizeof (*pcd
->setup_pkt
) * 5, &pcd
->setup_pkt_dma_handle
, 0);
2300 if (pcd
->setup_pkt
== 0) {
2301 free_irq(otg_dev
->irq
, pcd
);
2302 device_unregister(&pcd
->gadget
.dev
);
2307 pcd
->status_buf
= dma_alloc_coherent (NULL
, sizeof (uint16_t), &pcd
->status_buf_dma_handle
, 0);
2308 if (pcd
->status_buf
== 0) {
2309 dma_free_coherent(NULL
, sizeof(*pcd
->setup_pkt
), pcd
->setup_pkt
, pcd
->setup_pkt_dma_handle
);
2310 free_irq(otg_dev
->irq
, pcd
);
2311 device_unregister(&pcd
->gadget
.dev
);
2316 if (GET_CORE_IF(pcd
)->dma_desc_enable
) {
2317 dev_if
->setup_desc_addr
[0] = dwc_otg_ep_alloc_desc_chain(&dev_if
->dma_setup_desc_addr
[0], 1);
2318 dev_if
->setup_desc_addr
[1] = dwc_otg_ep_alloc_desc_chain(&dev_if
->dma_setup_desc_addr
[1], 1);
2319 dev_if
->in_desc_addr
= dwc_otg_ep_alloc_desc_chain(&dev_if
->dma_in_desc_addr
, 1);
2320 dev_if
->out_desc_addr
= dwc_otg_ep_alloc_desc_chain(&dev_if
->dma_out_desc_addr
, 1);
2322 if(dev_if
->setup_desc_addr
[0] == 0
2323 || dev_if
->setup_desc_addr
[1] == 0
2324 || dev_if
->in_desc_addr
== 0
2325 || dev_if
->out_desc_addr
== 0 ) {
2327 if(dev_if
->out_desc_addr
)
2328 dwc_otg_ep_free_desc_chain(dev_if
->out_desc_addr
, dev_if
->dma_out_desc_addr
, 1);
2329 if(dev_if
->in_desc_addr
)
2330 dwc_otg_ep_free_desc_chain(dev_if
->in_desc_addr
, dev_if
->dma_in_desc_addr
, 1);
2331 if(dev_if
->setup_desc_addr
[1])
2332 dwc_otg_ep_free_desc_chain(dev_if
->setup_desc_addr
[1], dev_if
->dma_setup_desc_addr
[1], 1);
2333 if(dev_if
->setup_desc_addr
[0])
2334 dwc_otg_ep_free_desc_chain(dev_if
->setup_desc_addr
[0], dev_if
->dma_setup_desc_addr
[0], 1);
2337 dma_free_coherent(NULL
, sizeof(*pcd
->status_buf
), pcd
->status_buf
, pcd
->setup_pkt_dma_handle
);
2338 dma_free_coherent(NULL
, sizeof(*pcd
->setup_pkt
), pcd
->setup_pkt
, pcd
->setup_pkt_dma_handle
);
2340 free_irq(otg_dev
->irq
, pcd
);
2341 device_unregister(&pcd
->gadget
.dev
);
2349 pcd
->setup_pkt
= kmalloc (sizeof (*pcd
->setup_pkt
) * 5, GFP_KERNEL
);
2350 if (pcd
->setup_pkt
== 0) {
2351 free_irq(otg_dev
->irq
, pcd
);
2352 device_unregister(&pcd
->gadget
.dev
);
2357 pcd
->status_buf
= kmalloc (sizeof (uint16_t), GFP_KERNEL
);
2358 if (pcd
->status_buf
== 0) {
2359 kfree(pcd
->setup_pkt
);
2360 free_irq(otg_dev
->irq
, pcd
);
2361 device_unregister(&pcd
->gadget
.dev
);
2368 /* Initialize tasklet */
2369 start_xfer_tasklet
.data
= (unsigned long)pcd
;
2370 pcd
->start_xfer_tasklet
= &start_xfer_tasklet
;
2378 void dwc_otg_pcd_remove(struct platform_device
*pdev
)
2380 dwc_otg_device_t
*otg_dev
= platform_get_drvdata(pdev
);
2381 dwc_otg_pcd_t
*pcd
= otg_dev
->pcd
;
2382 dwc_otg_dev_if_t
* dev_if
= GET_CORE_IF(pcd
)->dev_if
;
2384 DWC_DEBUGPL(DBG_PCDV
, "%s(%p)\n", __func__
, pdev
);
2389 free_irq(otg_dev
->irq
, pcd
);
2391 /* start with the driver above us */
2393 /* should have been done already by driver model core */
2394 DWC_WARN("driver '%s' is still registered\n",
2395 pcd
->driver
->driver
.name
);
2396 usb_gadget_unregister_driver(pcd
->driver
);
2398 device_unregister(&pcd
->gadget
.dev
);
2400 if (GET_CORE_IF(pcd
)->dma_enable
) {
2401 dma_free_coherent (NULL
, sizeof (*pcd
->setup_pkt
) * 5, pcd
->setup_pkt
, pcd
->setup_pkt_dma_handle
);
2402 dma_free_coherent (NULL
, sizeof (uint16_t), pcd
->status_buf
, pcd
->status_buf_dma_handle
);
2403 if (GET_CORE_IF(pcd
)->dma_desc_enable
) {
2404 dwc_otg_ep_free_desc_chain(dev_if
->setup_desc_addr
[0], dev_if
->dma_setup_desc_addr
[0], 1);
2405 dwc_otg_ep_free_desc_chain(dev_if
->setup_desc_addr
[1], dev_if
->dma_setup_desc_addr
[1], 1);
2406 dwc_otg_ep_free_desc_chain(dev_if
->in_desc_addr
, dev_if
->dma_in_desc_addr
, 1);
2407 dwc_otg_ep_free_desc_chain(dev_if
->out_desc_addr
, dev_if
->dma_out_desc_addr
, 1);
2411 kfree (pcd
->setup_pkt
);
2412 kfree (pcd
->status_buf
);
2419 #endif /* DWC_HOST_ONLY */