1 --- a/arch/arm/mach-cns3xxx/cns3420vb.c
2 +++ b/arch/arm/mach-cns3xxx/cns3420vb.c
3 @@ -274,7 +274,7 @@ static int __init cns3420vb_pcie_init(vo
4 if (!machine_is_cns3420vb())
7 - return cns3xxx_pcie_init();
8 + return cns3xxx_pcie_init(NULL, NULL);
10 subsys_initcall(cns3420vb_pcie_init);
12 --- a/arch/arm/mach-cns3xxx/core.h
13 +++ b/arch/arm/mach-cns3xxx/core.h
14 @@ -17,7 +17,7 @@ extern void cns3xxx_pcie_iotable_init(vo
16 void __init cns3xxx_map_io(void);
17 void __init cns3xxx_init_irq(void);
18 -int __init cns3xxx_pcie_init(void);
19 +int __init cns3xxx_pcie_init(int *pcie0_irqs, int *pcie1_irqs);
20 void cns3xxx_power_off(void);
21 void cns3xxx_restart(char, const char *);
23 --- a/arch/arm/mach-cns3xxx/laguna.c
24 +++ b/arch/arm/mach-cns3xxx/laguna.c
26 #include <linux/kernel.h>
27 #include <linux/compiler.h>
29 +#include <linux/irq.h>
30 #include <linux/gpio.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/serial_core.h>
33 @@ -869,12 +870,42 @@ static int laguna_register_gpio(struct g
37 +/* allow disabling of external isolated PCIe IRQs */
38 +static int cns3xxx_pciextirq = 1;
39 +static int __init cns3xxx_pciextirq_disable(char *s)
41 + cns3xxx_pciextirq = 0;
44 +__setup("noextirq", cns3xxx_pciextirq_disable);
46 static int __init laguna_pcie_init(void)
48 + u32 __iomem *mem = (void __iomem *)(CNS3XXX_GPIOB_BASE_VIRT + 0x0004);
49 + u32 reg = (__raw_readl(mem) >> 26) & 0xf;
51 + IRQ_CNS3XXX_EXTERNAL_PIN0,
52 + IRQ_CNS3XXX_EXTERNAL_PIN1,
53 + IRQ_CNS3XXX_EXTERNAL_PIN2,
57 if (!machine_is_gw2388())
60 - return cns3xxx_pcie_init();
61 + /* Verify GPIOB[26:29] == 0001b indicating support for ext irqs */
62 + if (cns3xxx_pciextirq && reg != 1)
63 + cns3xxx_pciextirq = 0;
65 + if (cns3xxx_pciextirq) {
66 + printk("laguna: using isolated PCI interrupts:"
67 + " irq%d/irq%d/irq%d/irq%d\n",
68 + irqs[0], irqs[1], irqs[2], irqs[3]);
69 + return cns3xxx_pcie_init(irqs, NULL);
71 + printk("laguna: using shared PCI interrupts: irq%d\n",
72 + IRQ_CNS3XXX_PCIE0_DEVICE);
73 + return cns3xxx_pcie_init(NULL, NULL);
75 subsys_initcall(laguna_pcie_init);
77 @@ -889,8 +923,33 @@ static int __init laguna_model_setup(voi
78 printk("Running on Gateworks Laguna %s\n", laguna_info.model);
79 cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
81 - cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
82 - NR_IRQS_CNS3XXX + 32);
85 + * If pcie external interrupts are supported and desired
86 + * configure IRQ types and configure pin function.
87 + * Note that cns3xxx_pciextirq is enabled by default, but can be
88 + * unset via the 'noextirq' kernel param or by laguna_pcie_init() if
89 + * the baseboard model does not support this hardware feature.
91 + if (cns3xxx_pciextirq) {
92 + mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0018);
93 + reg = __raw_readl(mem);
94 + /* GPIO26 is gpio, EXT_INT[0:2] not gpio func */
97 + __raw_writel(reg, mem);
99 + cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
100 + IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
102 + irq_set_irq_type(154, IRQ_TYPE_LEVEL_LOW);
103 + irq_set_irq_type(93, IRQ_TYPE_LEVEL_HIGH);
104 + irq_set_irq_type(94, IRQ_TYPE_LEVEL_HIGH);
105 + irq_set_irq_type(95, IRQ_TYPE_LEVEL_HIGH);
107 + cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
108 + IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
111 if (strncmp(laguna_info.model, "GW", 2) == 0) {
112 if (laguna_info.config_bitmap & ETH0_LOAD)
113 --- a/arch/arm/mach-cns3xxx/pcie.c
114 +++ b/arch/arm/mach-cns3xxx/pcie.c
116 #include <linux/io.h>
117 #include <linux/ioport.h>
118 #include <linux/interrupt.h>
119 +#include <linux/irq.h>
120 #include <linux/ptrace.h>
121 #include <asm/mach/map.h>
123 @@ -32,7 +33,7 @@ enum cns3xxx_access_type {
125 struct cns3xxx_pcie {
126 struct map_desc cfg_bases[CNS3XXX_NUM_ACCESS_TYPES];
127 - unsigned int irqs[2];
128 + unsigned int irqs[6];
129 struct resource res_io;
130 struct resource res_mem;
131 struct hw_pci hw_pci;
132 @@ -255,7 +256,7 @@ static struct pci_ops cns3xxx_pcie_ops =
133 static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
135 struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
136 - int irq = cnspci->irqs[slot];
137 + int irq = cnspci->irqs[slot+pin-1];
139 pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
140 pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
141 @@ -298,7 +299,12 @@ static struct cns3xxx_pcie cns3xxx_pcie[
142 .end = CNS3XXX_PCIE0_MEM_BASE + SZ_16M - 1,
143 .flags = IORESOURCE_MEM,
145 - .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
146 + .irqs = { IRQ_CNS3XXX_PCIE0_RC,
147 + IRQ_CNS3XXX_PCIE0_DEVICE,
148 + IRQ_CNS3XXX_PCIE0_DEVICE,
149 + IRQ_CNS3XXX_PCIE0_DEVICE,
150 + IRQ_CNS3XXX_PCIE0_DEVICE,
155 @@ -340,7 +346,13 @@ static struct cns3xxx_pcie cns3xxx_pcie[
156 .end = CNS3XXX_PCIE1_MEM_BASE + SZ_16M - 1,
157 .flags = IORESOURCE_MEM,
159 - .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
161 + IRQ_CNS3XXX_PCIE1_RC,
162 + IRQ_CNS3XXX_PCIE1_DEVICE,
163 + IRQ_CNS3XXX_PCIE1_DEVICE,
164 + IRQ_CNS3XXX_PCIE1_DEVICE,
165 + IRQ_CNS3XXX_PCIE1_DEVICE,
170 @@ -460,13 +472,22 @@ void __init cns3xxx_pcie_iotable_init()
174 -int __init cns3xxx_pcie_init(void)
175 +int __init cns3xxx_pcie_init(int *pcie0_irqs, int *pcie1_irqs)
183 + for (i = 0; i < 4; i++)
184 + cns3xxx_pcie[0].irqs[i+1] = pcie0_irqs[i];
187 + for (i = 0; i < 4; i++)
188 + cns3xxx_pcie[1].irqs[i+1] = pcie1_irqs[i];
191 hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0,
192 "imprecise external abort");