target/linux/cns3xxx/patches-3.3/066-pcie_bus_topology.patch

   1 --- a/arch/arm/mach-cns3xxx/pcie.c
   2 +++ b/arch/arm/mach-cns3xxx/pcie.c
   3 @@ -79,9 +79,11 @@ static void __iomem *cns3xxx_pci_cfg_bas
   4          * the first device on the same bus as the CNS PCI bridge.
   5          */
   6         if (busno == 0) {
   7 -               if (slot > 1)
   8 +               if (slot > 0)
   9                         return NULL;
  10                 type = slot;
  11 +       } else if (busno == 1) {
  12 +               type = CNS3XXX_CFG0_TYPE;
  13         } else {
  14                 type = CNS3XXX_CFG1_TYPE;
  15         }
  16 @@ -428,8 +430,9 @@ static void __init cns3xxx_pcie_hw_init(
  17         if (!cnspci->linked)
  18                 return;
  19
  20 -       /* Set Device Max_Read_Request_Size to 128 byte */
  21 -       devfn = PCI_DEVFN(1, 0);
  22 +       /* Configure Root Complex: Set Device Max_Read_Request_Size to 128 byte */
  23 +       bus.number = 1;
  24 +       devfn = PCI_DEVFN(0, 0);
  25         pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP);
  26         pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
  27         dc &= ~(0x3 << 12);     /* Clear Device Control Register [14:12] */