target/linux/cns3xxx/patches-3.8/010-move_virtual_io_space.patch

   1 --- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
   2 +++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
   3 @@ -20,22 +20,22 @@
   4  #define CNS3XXX_SPI_FLASH_BASE                 0x60000000      /* SPI Serial Flash Memory */
   5
   6  #define CNS3XXX_SWITCH_BASE                    0x70000000      /* Switch and HNAT Control */
   7 -#define CNS3XXX_SWITCH_BASE_VIRT               0xFFF00000
   8 +#define CNS3XXX_SWITCH_BASE_VIRT               0xFEF00000
   9
  10  #define CNS3XXX_PPE_BASE                       0x70001000      /* HANT */
  11 -#define CNS3XXX_PPE_BASE_VIRT                  0xFFF50000
  12 +#define CNS3XXX_PPE_BASE_VIRT                  0xFEF50000
  13
  14  #define CNS3XXX_EMBEDDED_SRAM_BASE             0x70002000      /* HANT Embedded SRAM */
  15 -#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT                0xFFF60000
  16 +#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT                0xFEF60000
  17
  18  #define CNS3XXX_SSP_BASE                       0x71000000      /* Synchronous Serial Port - SPI/PCM/I2C */
  19 -#define CNS3XXX_SSP_BASE_VIRT                  0xFFF01000
  20 +#define CNS3XXX_SSP_BASE_VIRT                  0xFEF01000
  21
  22  #define CNS3XXX_DMC_BASE                       0x72000000      /* DMC Control (DDR2 SDRAM) */
  23 -#define CNS3XXX_DMC_BASE_VIRT                  0xFFF02000
  24 +#define CNS3XXX_DMC_BASE_VIRT                  0xFEF02000
  25
  26  #define CNS3XXX_SMC_BASE                       0x73000000      /* SMC Control */
  27 -#define CNS3XXX_SMC_BASE_VIRT                  0xFFF03000
  28 +#define CNS3XXX_SMC_BASE_VIRT                  0xFEF03000
  29
  30  #define SMC_MEMC_STATUS_OFFSET                 0x000
  31  #define SMC_MEMIF_CFG_OFFSET                   0x004
  32 @@ -74,13 +74,13 @@
  33  #define SMC_PCELL_ID_3_OFFSET                  0xFFC
  34
  35  #define CNS3XXX_GPIOA_BASE                     0x74000000      /* GPIO port A */
  36 -#define CNS3XXX_GPIOA_BASE_VIRT                        0xFFF04000
  37 +#define CNS3XXX_GPIOA_BASE_VIRT                        0xFEF04000
  38
  39  #define CNS3XXX_GPIOB_BASE                     0x74800000      /* GPIO port B */
  40 -#define CNS3XXX_GPIOB_BASE_VIRT                        0xFFF05000
  41 +#define CNS3XXX_GPIOB_BASE_VIRT                        0xFEF05000
  42
  43  #define CNS3XXX_RTC_BASE                       0x75000000      /* Real Time Clock */
  44 -#define CNS3XXX_RTC_BASE_VIRT                  0xFFF06000
  45 +#define CNS3XXX_RTC_BASE_VIRT                  0xFEF06000
  46
  47  #define RTC_SEC_OFFSET                         0x00
  48  #define RTC_MIN_OFFSET                         0x04
  49 @@ -94,10 +94,10 @@
  50  #define RTC_INTR_STS_OFFSET                    0x34
  51
  52  #define CNS3XXX_MISC_BASE                      0x76000000      /* Misc Control */
  53 -#define CNS3XXX_MISC_BASE_VIRT                 0xFB000000      /* Misc Control */
  54 +#define CNS3XXX_MISC_BASE_VIRT                 0xFEF07000      /* Misc Control */
  55
  56  #define CNS3XXX_PM_BASE                                0x77000000      /* Power Management Control */
  57 -#define CNS3XXX_PM_BASE_VIRT                   0xFB001000
  58 +#define CNS3XXX_PM_BASE_VIRT                   0xFEF08000
  59
  60  #define PM_CLK_GATE_OFFSET                     0x00
  61  #define PM_SOFT_RST_OFFSET                     0x04
  62 @@ -109,28 +109,28 @@
  63  #define PM_PLL_HM_PD_OFFSET                    0x1C
  64
  65  #define CNS3XXX_UART0_BASE                     0x78000000      /* UART 0 */
  66 -#define CNS3XXX_UART0_BASE_VIRT                        0xFB002000
  67 +#define CNS3XXX_UART0_BASE_VIRT                        0xFEF09000
  68
  69  #define CNS3XXX_UART1_BASE                     0x78400000      /* UART 1 */
  70 -#define CNS3XXX_UART1_BASE_VIRT                        0xFFF0A000
  71 +#define CNS3XXX_UART1_BASE_VIRT                        0xFEF0A000
  72
  73  #define CNS3XXX_UART2_BASE                     0x78800000      /* UART 2 */
  74 -#define CNS3XXX_UART2_BASE_VIRT                        0xFFF0B000
  75 +#define CNS3XXX_UART2_BASE_VIRT                        0xFEF0B000
  76
  77  #define CNS3XXX_DMAC_BASE                      0x79000000      /* Generic DMA Control */
  78 -#define CNS3XXX_DMAC_BASE_VIRT                 0xFFF0D000
  79 +#define CNS3XXX_DMAC_BASE_VIRT                 0xFEF0D000
  80
  81  #define CNS3XXX_CORESIGHT_BASE                 0x7A000000      /* CoreSight */
  82 -#define CNS3XXX_CORESIGHT_BASE_VIRT            0xFFF0E000
  83 +#define CNS3XXX_CORESIGHT_BASE_VIRT            0xFEF0E000
  84
  85  #define CNS3XXX_CRYPTO_BASE                    0x7B000000      /* Crypto */
  86 -#define CNS3XXX_CRYPTO_BASE_VIRT               0xFFF0F000
  87 +#define CNS3XXX_CRYPTO_BASE_VIRT               0xFEF0F000
  88
  89  #define CNS3XXX_I2S_BASE                       0x7C000000      /* I2S */
  90 -#define CNS3XXX_I2S_BASE_VIRT                  0xFFF10000
  91 +#define CNS3XXX_I2S_BASE_VIRT                  0xFEF10000
  92
  93  #define CNS3XXX_TIMER1_2_3_BASE                        0x7C800000      /* Timer */
  94 -#define CNS3XXX_TIMER1_2_3_BASE_VIRT           0xFB003000
  95 +#define CNS3XXX_TIMER1_2_3_BASE_VIRT           0xFEF10800
  96
  97  #define TIMER1_COUNTER_OFFSET                  0x00
  98  #define TIMER1_AUTO_RELOAD_OFFSET              0x04
  99 @@ -150,42 +150,42 @@
 100  #define TIMER_FREERUN_CONTROL_OFFSET           0x44
 101
 102  #define CNS3XXX_HCIE_BASE                      0x7D000000      /* HCIE Control */
 103 -#define CNS3XXX_HCIE_BASE_VIRT                 0xFFF30000
 104 +#define CNS3XXX_HCIE_BASE_VIRT                 0xFEF30000
 105
 106  #define CNS3XXX_RAID_BASE                      0x7E000000      /* RAID Control */
 107 -#define CNS3XXX_RAID_BASE_VIRT                 0xFFF12000
 108 +#define CNS3XXX_RAID_BASE_VIRT                 0xFEF12000
 109
 110  #define CNS3XXX_AXI_IXC_BASE                   0x7F000000      /* AXI IXC */
 111 -#define CNS3XXX_AXI_IXC_BASE_VIRT              0xFFF13000
 112 +#define CNS3XXX_AXI_IXC_BASE_VIRT              0xFEF13000
 113
 114  #define CNS3XXX_CLCD_BASE                      0x80000000      /* LCD Control */
 115 -#define CNS3XXX_CLCD_BASE_VIRT                 0xFFF14000
 116 +#define CNS3XXX_CLCD_BASE_VIRT                 0xFEF14000
 117
 118  #define CNS3XXX_USBOTG_BASE                    0x81000000      /* USB OTG Control */
 119 -#define CNS3XXX_USBOTG_BASE_VIRT               0xFFF15000
 120 +#define CNS3XXX_USBOTG_BASE_VIRT               0xFEF15000
 121
 122  #define CNS3XXX_USB_BASE                       0x82000000      /* USB Host Control */
 123
 124  #define CNS3XXX_SATA2_BASE                     0x83000000      /* SATA */
 125  #define CNS3XXX_SATA2_SIZE                     SZ_16M
 126 -#define CNS3XXX_SATA2_BASE_VIRT                        0xFFF17000
 127 +#define CNS3XXX_SATA2_BASE_VIRT                        0xFEF17000
 128
 129  #define CNS3XXX_CAMERA_BASE                    0x84000000      /* Camera Interface */
 130 -#define CNS3XXX_CAMERA_BASE_VIRT               0xFFF18000
 131 +#define CNS3XXX_CAMERA_BASE_VIRT               0xFEF18000
 132
 133  #define CNS3XXX_SDIO_BASE                      0x85000000      /* SDIO */
 134 -#define CNS3XXX_SDIO_BASE_VIRT                 0xFFF19000
 135 +#define CNS3XXX_SDIO_BASE_VIRT                 0xFEF19000
 136
 137  #define CNS3XXX_I2S_TDM_BASE                   0x86000000      /* I2S TDM */
 138 -#define CNS3XXX_I2S_TDM_BASE_VIRT              0xFFF1A000
 139 +#define CNS3XXX_I2S_TDM_BASE_VIRT              0xFEF1A000
 140
 141  #define CNS3XXX_2DG_BASE                       0x87000000      /* 2D Graphic Control */
 142 -#define CNS3XXX_2DG_BASE_VIRT                  0xFFF1B000
 143 +#define CNS3XXX_2DG_BASE_VIRT                  0xFEF1B000
 144
 145  #define CNS3XXX_USB_OHCI_BASE                  0x88000000      /* USB OHCI */
 146
 147  #define CNS3XXX_L2C_BASE                       0x92000000      /* L2 Cache Control */
 148 -#define CNS3XXX_L2C_BASE_VIRT                  0xFFF27000
 149 +#define CNS3XXX_L2C_BASE_VIRT                  0xFEF27000
 150
 151  #define CNS3XXX_PCIE0_MEM_BASE                 0xA0000000      /* PCIe Port 0 IO/Memory Space */
 152  #define CNS3XXX_PCIE0_MEM_BASE_VIRT            0xE0000000
 153 @@ -227,7 +227,7 @@
 154   * Testchip peripheral and fpga gic regions
 155   */
 156  #define CNS3XXX_TC11MP_SCU_BASE                        0x90000000      /* IRQ, Test chip */
 157 -#define CNS3XXX_TC11MP_SCU_BASE_VIRT           0xFB004000
 158 +#define CNS3XXX_TC11MP_SCU_BASE_VIRT           0xFEE00000
 159
 160  #define CNS3XXX_TC11MP_GIC_CPU_BASE            0x90000100      /* Test chip interrupt controller CPU interface */
 161  #define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT       (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x100)
 162 @@ -239,7 +239,7 @@
 163  #define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT      (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000)
 164
 165  #define CNS3XXX_TC11MP_L220_BASE               0x92002000      /* L220 registers */
 166 -#define CNS3XXX_TC11MP_L220_BASE_VIRT          0xFF002000
 167 +#define CNS3XXX_TC11MP_L220_BASE_VIRT          0xFEE02000
 168
 169  /*
 170   * Misc block