target/linux/gemini/patches-4.14/0021-net-ethernet-Add-DT-bindings-for-the-Gemini-ethernet.patch

   1 From 49bc597009f52ec8970269f6201d3ed415a844ee Mon Sep 17 00:00:00 2001
   2 From: Linus Walleij <linus.walleij@linaro.org>
   3 Date: Fri, 12 Jan 2018 22:34:23 +0100
   4 Subject: [PATCH 21/31] net: ethernet: Add DT bindings for the Gemini ethernet
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
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   8
   9 This adds the device tree bindings for the Gemini ethernet
  10 controller. It is pretty straight-forward, using standard
  11 bindings and modelling the two child ports as child devices
  12 under the parent ethernet controller device.
  13
  14 Cc: devicetree@vger.kernel.org
  15 Cc: Tobias Waldvogel <tobias.waldvogel@gmail.com>
  16 Cc: Michał Mirosław <mirq-linux@rere.qmqm.pl>
  17 Reviewed-by: Rob Herring <robh@kernel.org>
  18 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
  19 Signed-off-by: David S. Miller <davem@davemloft.net>
  20 ---
  21  .../bindings/net/cortina,gemini-ethernet.txt       | 92 ++++++++++++++++++++++
  22  1 file changed, 92 insertions(+)
  23  create mode 100644 Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt
  24
  25 --- /dev/null
  26 +++ b/Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt
  27 @@ -0,0 +1,92 @@
  28 +Cortina Systems Gemini Ethernet Controller
  29 +==========================================
  30 +
  31 +This ethernet controller is found in the Gemini SoC family:
  32 +StorLink SL3512 and SL3516, also known as Cortina Systems
  33 +CS3512 and CS3516.
  34 +
  35 +Required properties:
  36 +- compatible: must be "cortina,gemini-ethernet"
  37 +- reg: must contain the global registers and the V-bit and A-bit
  38 +  memory areas, in total three register sets.
  39 +- syscon: a phandle to the system controller
  40 +- #address-cells: must be specified, must be <1>
  41 +- #size-cells: must be specified, must be <1>
  42 +- ranges: should be state like this giving a 1:1 address translation
  43 +  for the subnodes
  44 +
  45 +The subnodes represents the two ethernet ports in this device.
  46 +They are not independent of each other since they share resources
  47 +in the parent node, and are thus children.
  48 +
  49 +Required subnodes:
  50 +- port0: contains the resources for ethernet port 0
  51 +- port1: contains the resources for ethernet port 1
  52 +
  53 +Required subnode properties:
  54 +- compatible: must be "cortina,gemini-ethernet-port"
  55 +- reg: must contain two register areas: the DMA/TOE memory and
  56 +  the GMAC memory area of the port
  57 +- interrupts: should contain the interrupt line of the port.
  58 +  this is nominally a level interrupt active high.
  59 +- resets: this must provide an SoC-integrated reset line for
  60 +  the port.
  61 +- clocks: this should contain a handle to the PCLK clock for
  62 +  clocking the silicon in this port
  63 +- clock-names: must be "PCLK"
  64 +
  65 +Optional subnode properties:
  66 +- phy-mode: see ethernet.txt
  67 +- phy-handle: see ethernet.txt
  68 +
  69 +Example:
  70 +
  71 +mdio-bus {
  72 +       (...)
  73 +       phy0: ethernet-phy@1 {
  74 +               reg = <1>;
  75 +               device_type = "ethernet-phy";
  76 +       };
  77 +       phy1: ethernet-phy@3 {
  78 +               reg = <3>;
  79 +               device_type = "ethernet-phy";
  80 +       };
  81 +};
  82 +
  83 +
  84 +ethernet@60000000 {
  85 +       compatible = "cortina,gemini-ethernet";
  86 +       reg = <0x60000000 0x4000>, /* Global registers, queue */
  87 +             <0x60004000 0x2000>, /* V-bit */
  88 +             <0x60006000 0x2000>; /* A-bit */
  89 +       syscon = <&syscon>;
  90 +       #address-cells = <1>;
  91 +       #size-cells = <1>;
  92 +       ranges;
  93 +
  94 +       gmac0: ethernet-port@0 {
  95 +               compatible = "cortina,gemini-ethernet-port";
  96 +               reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
  97 +                     <0x6000a000 0x2000>; /* Port 0 GMAC */
  98 +               interrupt-parent = <&intcon>;
  99 +               interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
 100 +               resets = <&syscon GEMINI_RESET_GMAC0>;
 101 +               clocks = <&syscon GEMINI_CLK_GATE_GMAC0>;
 102 +               clock-names = "PCLK";
 103 +               phy-mode = "rgmii";
 104 +               phy-handle = <&phy0>;
 105 +       };
 106 +
 107 +       gmac1: ethernet-port@1 {
 108 +               compatible = "cortina,gemini-ethernet-port";
 109 +               reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
 110 +                     <0x6000e000 0x2000>; /* Port 1 GMAC */
 111 +               interrupt-parent = <&intcon>;
 112 +               interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 113 +               resets = <&syscon GEMINI_RESET_GMAC1>;
 114 +               clocks = <&syscon GEMINI_CLK_GATE_GMAC1>;
 115 +               clock-names = "PCLK";
 116 +               phy-mode = "rgmii";
 117 +               phy-handle = <&phy1>;
 118 +       };
 119 +};