1 From b1ae3587d16a8c8fc9453e147c8708d6f006ffbb Mon Sep 17 00:00:00 2001
2 From: Bjarni Jonasson <bjarni.jonasson@microchip.com>
3 Date: Wed, 13 Jan 2021 12:56:25 +0100
4 Subject: [PATCH] net: phy: Add 100 base-x mode
6 Sparx-5 supports this mode and it is missing in the PHY core.
8 Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com>
9 Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk>
10 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
12 Documentation/networking/phy.rst | 5 +++++
13 include/linux/phy.h | 4 ++++
14 2 files changed, 9 insertions(+)
16 --- a/Documentation/networking/phy.rst
17 +++ b/Documentation/networking/phy.rst
18 @@ -286,6 +286,11 @@ Some of the interface modes are describe
19 Note: due to legacy usage, some 10GBASE-R usage incorrectly makes
20 use of this definition.
22 +``PHY_INTERFACE_MODE_100BASEX``
23 + This defines IEEE 802.3 Clause 24. The link operates at a fixed data
24 + rate of 125Mpbs using a 4B/5B encoding scheme, resulting in an underlying
25 + data rate of 100Mpbs.
27 Pause frames / flow control
28 ===========================
30 --- a/include/linux/phy.h
31 +++ b/include/linux/phy.h
32 @@ -104,6 +104,7 @@ extern const int phy_10gbit_features_arr
33 * @PHY_INTERFACE_MODE_MOCA: Multimedia over Coax
34 * @PHY_INTERFACE_MODE_QSGMII: Quad SGMII
35 * @PHY_INTERFACE_MODE_TRGMII: Turbo RGMII
36 + * @PHY_INTERFACE_MODE_100BASEX: 100 BaseX
37 * @PHY_INTERFACE_MODE_1000BASEX: 1000 BaseX
38 * @PHY_INTERFACE_MODE_2500BASEX: 2500 BaseX
39 * @PHY_INTERFACE_MODE_RXAUI: Reduced XAUI
40 @@ -135,6 +136,7 @@ typedef enum {
41 PHY_INTERFACE_MODE_MOCA,
42 PHY_INTERFACE_MODE_QSGMII,
43 PHY_INTERFACE_MODE_TRGMII,
44 + PHY_INTERFACE_MODE_100BASEX,
45 PHY_INTERFACE_MODE_1000BASEX,
46 PHY_INTERFACE_MODE_2500BASEX,
47 PHY_INTERFACE_MODE_RXAUI,
48 @@ -217,6 +219,8 @@ static inline const char *phy_modes(phy_
50 case PHY_INTERFACE_MODE_10GKR:
52 + case PHY_INTERFACE_MODE_100BASEX: