1 From e4b9977cee1583da38a6e9118078bb728aaccf7b Mon Sep 17 00:00:00 2001
2 From: Ansuel Smith <ansuelsmth@gmail.com>
3 Date: Fri, 14 May 2021 23:00:06 +0200
4 Subject: [PATCH] net: dsa: qca8k: make rgmii delay configurable
6 The legacy qsdk code used a different delay instead of the max value.
7 Qsdk use 1 ns for rx and 2 ns for tx. Make these values configurable
8 using the standard rx/tx-internal-delay-ps ethernet binding and apply
9 qsdk values by default. The connected gmac doesn't add any delay so no
10 additional delay is added to tx/rx.
11 On this switch the delay is actually in ns so value should be in the
12 1000 order. Any value converted from ps to ns by dividing it by 1000
13 as the switch max value for delay is 3ns.
15 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
16 Signed-off-by: David S. Miller <davem@davemloft.net>
18 drivers/net/dsa/qca8k.c | 82 ++++++++++++++++++++++++++++++++++++++++-
19 drivers/net/dsa/qca8k.h | 11 +++---
20 2 files changed, 86 insertions(+), 7 deletions(-)
22 --- a/drivers/net/dsa/qca8k.c
23 +++ b/drivers/net/dsa/qca8k.c
24 @@ -778,6 +778,68 @@ qca8k_setup_mdio_bus(struct qca8k_priv *
28 +qca8k_setup_of_rgmii_delay(struct qca8k_priv *priv)
30 + struct device_node *port_dn;
31 + phy_interface_t mode;
32 + struct dsa_port *dp;
35 + /* CPU port is already checked */
36 + dp = dsa_to_port(priv->ds, 0);
40 + /* Check if port 0 is set to the correct type */
41 + of_get_phy_mode(port_dn, &mode);
42 + if (mode != PHY_INTERFACE_MODE_RGMII_ID &&
43 + mode != PHY_INTERFACE_MODE_RGMII_RXID &&
44 + mode != PHY_INTERFACE_MODE_RGMII_TXID) {
49 + case PHY_INTERFACE_MODE_RGMII_ID:
50 + case PHY_INTERFACE_MODE_RGMII_RXID:
51 + if (of_property_read_u32(port_dn, "rx-internal-delay-ps", &val))
54 + /* Switch regs accept value in ns, convert ps to ns */
57 + if (val > QCA8K_MAX_DELAY) {
58 + dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value");
62 + priv->rgmii_rx_delay = val;
63 + /* Stop here if we need to check only for rx delay */
64 + if (mode != PHY_INTERFACE_MODE_RGMII_ID)
68 + case PHY_INTERFACE_MODE_RGMII_TXID:
69 + if (of_property_read_u32(port_dn, "tx-internal-delay-ps", &val))
72 + /* Switch regs accept value in ns, convert ps to ns */
75 + if (val > QCA8K_MAX_DELAY) {
76 + dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value");
80 + priv->rgmii_tx_delay = val;
90 qca8k_setup(struct dsa_switch *ds)
92 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
93 @@ -802,6 +864,10 @@ qca8k_setup(struct dsa_switch *ds)
97 + ret = qca8k_setup_of_rgmii_delay(priv);
101 /* Enable CPU Port */
102 ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
103 QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
104 @@ -970,6 +1036,8 @@ qca8k_phylink_mac_config(struct dsa_swit
105 case 0: /* 1st CPU port */
106 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
107 state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
108 + state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
109 + state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
110 state->interface != PHY_INTERFACE_MODE_SGMII)
113 @@ -985,6 +1053,8 @@ qca8k_phylink_mac_config(struct dsa_swit
114 case 6: /* 2nd CPU port / external PHY */
115 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
116 state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
117 + state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
118 + state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
119 state->interface != PHY_INTERFACE_MODE_SGMII &&
120 state->interface != PHY_INTERFACE_MODE_1000BASEX)
122 @@ -1008,14 +1078,18 @@ qca8k_phylink_mac_config(struct dsa_swit
123 qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN);
125 case PHY_INTERFACE_MODE_RGMII_ID:
126 + case PHY_INTERFACE_MODE_RGMII_TXID:
127 + case PHY_INTERFACE_MODE_RGMII_RXID:
128 /* RGMII_ID needs internal delay. This is enabled through
129 * PORT5_PAD_CTRL for all ports, rather than individual port
132 qca8k_write(priv, reg,
133 QCA8K_PORT_PAD_RGMII_EN |
134 - QCA8K_PORT_PAD_RGMII_TX_DELAY(QCA8K_MAX_DELAY) |
135 - QCA8K_PORT_PAD_RGMII_RX_DELAY(QCA8K_MAX_DELAY));
136 + QCA8K_PORT_PAD_RGMII_TX_DELAY(priv->rgmii_tx_delay) |
137 + QCA8K_PORT_PAD_RGMII_RX_DELAY(priv->rgmii_rx_delay) |
138 + QCA8K_PORT_PAD_RGMII_TX_DELAY_EN |
139 + QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
140 /* QCA8337 requires to set rgmii rx delay */
141 if (priv->switch_id == QCA8K_ID_QCA8337)
142 qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
143 @@ -1073,6 +1147,8 @@ qca8k_phylink_validate(struct dsa_switch
144 if (state->interface != PHY_INTERFACE_MODE_NA &&
145 state->interface != PHY_INTERFACE_MODE_RGMII &&
146 state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
147 + state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
148 + state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
149 state->interface != PHY_INTERFACE_MODE_SGMII)
152 @@ -1090,6 +1166,8 @@ qca8k_phylink_validate(struct dsa_switch
153 if (state->interface != PHY_INTERFACE_MODE_NA &&
154 state->interface != PHY_INTERFACE_MODE_RGMII &&
155 state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
156 + state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
157 + state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
158 state->interface != PHY_INTERFACE_MODE_SGMII &&
159 state->interface != PHY_INTERFACE_MODE_1000BASEX)
161 --- a/drivers/net/dsa/qca8k.h
162 +++ b/drivers/net/dsa/qca8k.h
164 #define QCA8K_REG_PORT5_PAD_CTRL 0x008
165 #define QCA8K_REG_PORT6_PAD_CTRL 0x00c
166 #define QCA8K_PORT_PAD_RGMII_EN BIT(26)
167 -#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) \
168 - ((0x8 + (x & 0x3)) << 22)
169 -#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) \
170 - ((0x10 + (x & 0x3)) << 20)
171 -#define QCA8K_MAX_DELAY 3
172 +#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) ((x) << 22)
173 +#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) ((x) << 20)
174 +#define QCA8K_PORT_PAD_RGMII_TX_DELAY_EN BIT(25)
175 #define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24)
176 +#define QCA8K_MAX_DELAY 3
177 #define QCA8K_PORT_PAD_SGMII_EN BIT(7)
178 #define QCA8K_REG_PWS 0x010
179 #define QCA8K_PWS_SERDES_AEN_DIS BIT(7)
180 @@ -254,6 +253,8 @@ struct qca8k_match_data {
186 struct regmap *regmap;
188 struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS];