1 From c93c613214ac70c87beab5422a60077bf126b855 Mon Sep 17 00:00:00 2001
2 From: Chuanhong Guo <gch981213@gmail.com>
3 Date: Wed, 28 Nov 2018 21:07:25 +0800
4 Subject: [PATCH 3/8] mtd: spinand: add support for GigaDevice GD5FxGQ4xA
6 Add support for GigaDevice GD5F1G/2G/4GQ4xA SPI NAND.
8 Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
9 Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
10 Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
12 drivers/mtd/nand/spi/Makefile | 2 +-
13 drivers/mtd/nand/spi/core.c | 1 +
14 drivers/mtd/nand/spi/gigadevice.c | 148 ++++++++++++++++++++++++++++++
15 include/linux/mtd/spinand.h | 1 +
16 4 files changed, 151 insertions(+), 1 deletion(-)
17 create mode 100644 drivers/mtd/nand/spi/gigadevice.c
19 --- a/drivers/mtd/nand/spi/Makefile
20 +++ b/drivers/mtd/nand/spi/Makefile
22 # SPDX-License-Identifier: GPL-2.0
23 -spinand-objs := core.o macronix.o micron.o toshiba.o winbond.o
24 +spinand-objs := core.o gigadevice.o macronix.o micron.o toshiba.o winbond.o
25 obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
26 --- a/drivers/mtd/nand/spi/core.c
27 +++ b/drivers/mtd/nand/spi/core.c
28 @@ -762,6 +762,7 @@ static const struct nand_ops spinand_ops
31 static const struct spinand_manufacturer *spinand_manufacturers[] = {
32 + &gigadevice_spinand_manufacturer,
33 ¯onix_spinand_manufacturer,
34 µn_spinand_manufacturer,
35 &toshiba_spinand_manufacturer,
37 +++ b/drivers/mtd/nand/spi/gigadevice.c
39 +// SPDX-License-Identifier: GPL-2.0
42 + * Chuanhong Guo <gch981213@gmail.com>
45 +#include <linux/device.h>
46 +#include <linux/kernel.h>
47 +#include <linux/mtd/spinand.h>
49 +#define SPINAND_MFR_GIGADEVICE 0xC8
50 +#define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS (1 << 4)
51 +#define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS (3 << 4)
53 +static SPINAND_OP_VARIANTS(read_cache_variants,
54 + SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
55 + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
56 + SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
57 + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
58 + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
59 + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
61 +static SPINAND_OP_VARIANTS(write_cache_variants,
62 + SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
63 + SPINAND_PROG_LOAD(true, 0, NULL, 0));
65 +static SPINAND_OP_VARIANTS(update_cache_variants,
66 + SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
67 + SPINAND_PROG_LOAD(false, 0, NULL, 0));
69 +static int gd5fxgq4xa_ooblayout_ecc(struct mtd_info *mtd, int section,
70 + struct mtd_oob_region *region)
75 + region->offset = (16 * section) + 8;
81 +static int gd5fxgq4xa_ooblayout_free(struct mtd_info *mtd, int section,
82 + struct mtd_oob_region *region)
88 + region->offset = 16 * section;
91 + /* section 0 has one byte reserved for bad block mark */
98 +static int gd5fxgq4xa_ecc_get_status(struct spinand_device *spinand,
101 + switch (status & STATUS_ECC_MASK) {
102 + case STATUS_ECC_NO_BITFLIPS:
105 + case GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS:
106 + /* 1-7 bits are flipped. return the maximum. */
109 + case GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS:
112 + case STATUS_ECC_UNCOR_ERROR:
122 +static const struct mtd_ooblayout_ops gd5fxgq4xa_ooblayout = {
123 + .ecc = gd5fxgq4xa_ooblayout_ecc,
124 + .free = gd5fxgq4xa_ooblayout_free,
127 +static const struct spinand_info gigadevice_spinand_table[] = {
128 + SPINAND_INFO("GD5F1GQ4xA", 0xF1,
129 + NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
130 + NAND_ECCREQ(8, 512),
131 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
132 + &write_cache_variants,
133 + &update_cache_variants),
135 + SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
136 + gd5fxgq4xa_ecc_get_status)),
137 + SPINAND_INFO("GD5F2GQ4xA", 0xF2,
138 + NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
139 + NAND_ECCREQ(8, 512),
140 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
141 + &write_cache_variants,
142 + &update_cache_variants),
144 + SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
145 + gd5fxgq4xa_ecc_get_status)),
146 + SPINAND_INFO("GD5F4GQ4xA", 0xF4,
147 + NAND_MEMORG(1, 2048, 64, 64, 4096, 1, 1, 1),
148 + NAND_ECCREQ(8, 512),
149 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
150 + &write_cache_variants,
151 + &update_cache_variants),
153 + SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
154 + gd5fxgq4xa_ecc_get_status)),
157 +static int gigadevice_spinand_detect(struct spinand_device *spinand)
159 + u8 *id = spinand->id.data;
163 + * For GD NANDs, There is an address byte needed to shift in before IDs
164 + * are read out, so the first byte in raw_id is dummy.
166 + if (id[1] != SPINAND_MFR_GIGADEVICE)
169 + ret = spinand_match_and_init(spinand, gigadevice_spinand_table,
170 + ARRAY_SIZE(gigadevice_spinand_table),
178 +static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
179 + .detect = gigadevice_spinand_detect,
182 +const struct spinand_manufacturer gigadevice_spinand_manufacturer = {
183 + .id = SPINAND_MFR_GIGADEVICE,
184 + .name = "GigaDevice",
185 + .ops = &gigadevice_spinand_manuf_ops,
187 --- a/include/linux/mtd/spinand.h
188 +++ b/include/linux/mtd/spinand.h
189 @@ -194,6 +194,7 @@ struct spinand_manufacturer {
192 /* SPI NAND manufacturers */
193 +extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
194 extern const struct spinand_manufacturer macronix_spinand_manufacturer;
195 extern const struct spinand_manufacturer micron_spinand_manufacturer;
196 extern const struct spinand_manufacturer toshiba_spinand_manufacturer;