1 From e0256648c831af13cbfe4a1787327fcec01c2807 Mon Sep 17 00:00:00 2001
2 From: Christian Marangi <ansuelsmth@gmail.com>
3 Date: Mon, 29 May 2023 18:32:42 +0200
4 Subject: [PATCH 12/13] net: dsa: qca8k: implement hw_control ops
6 Implement hw_control ops to drive Switch LEDs based on hardware events.
8 Netdev trigger is the declared supported trigger for hw control
9 operation and supports the following mode:
13 When hw_control_set is called, LEDs are set to follow the requested
15 Each LEDs will blink at 4Hz by default.
17 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
18 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
19 Signed-off-by: David S. Miller <davem@davemloft.net>
21 drivers/net/dsa/qca/qca8k-leds.c | 154 +++++++++++++++++++++++++++++++
22 1 file changed, 154 insertions(+)
24 --- a/drivers/net/dsa/qca/qca8k-leds.c
25 +++ b/drivers/net/dsa/qca/qca8k-leds.c
26 @@ -32,6 +32,43 @@ qca8k_get_enable_led_reg(int port_num, i
30 +qca8k_get_control_led_reg(int port_num, int led_num, struct qca8k_led_pattern_en *reg_info)
32 + reg_info->reg = QCA8K_LED_CTRL_REG(led_num);
34 + /* 6 total control rule:
35 + * 3 control rules for phy0-3 that applies to all their leds
36 + * 3 control rules for phy4
39 + reg_info->shift = QCA8K_LED_PHY4_CONTROL_RULE_SHIFT;
41 + reg_info->shift = QCA8K_LED_PHY0123_CONTROL_RULE_SHIFT;
47 +qca8k_parse_netdev(unsigned long rules, u32 *offload_trigger)
49 + /* Parsing specific to netdev trigger */
50 + if (test_bit(TRIGGER_NETDEV_TX, &rules))
51 + *offload_trigger |= QCA8K_LED_TX_BLINK_MASK;
52 + if (test_bit(TRIGGER_NETDEV_RX, &rules))
53 + *offload_trigger |= QCA8K_LED_RX_BLINK_MASK;
55 + if (rules && !*offload_trigger)
58 + /* Enable some default rule by default to the requested mode:
59 + * - Blink at 4Hz by default
61 + *offload_trigger |= QCA8K_LED_BLINK_4HZ;
67 qca8k_led_brightness_set(struct qca8k_led *led,
68 enum led_brightness brightness)
70 @@ -165,6 +202,119 @@ qca8k_cled_blink_set(struct led_classdev
74 +qca8k_cled_trigger_offload(struct led_classdev *ldev, bool enable)
76 + struct qca8k_led *led = container_of(ldev, struct qca8k_led, cdev);
78 + struct qca8k_led_pattern_en reg_info;
79 + struct qca8k_priv *priv = led->priv;
80 + u32 mask, val = QCA8K_LED_ALWAYS_OFF;
82 + qca8k_get_enable_led_reg(led->port_num, led->led_num, ®_info);
85 + val = QCA8K_LED_RULE_CONTROLLED;
87 + if (led->port_num == 0 || led->port_num == 4) {
88 + mask = QCA8K_LED_PATTERN_EN_MASK;
89 + val <<= QCA8K_LED_PATTERN_EN_SHIFT;
91 + mask = QCA8K_LED_PHY123_PATTERN_EN_MASK;
94 + return regmap_update_bits(priv->regmap, reg_info.reg, mask << reg_info.shift,
95 + val << reg_info.shift);
99 +qca8k_cled_hw_control_status(struct led_classdev *ldev)
101 + struct qca8k_led *led = container_of(ldev, struct qca8k_led, cdev);
103 + struct qca8k_led_pattern_en reg_info;
104 + struct qca8k_priv *priv = led->priv;
107 + qca8k_get_enable_led_reg(led->port_num, led->led_num, ®_info);
109 + regmap_read(priv->regmap, reg_info.reg, &val);
111 + val >>= reg_info.shift;
113 + if (led->port_num == 0 || led->port_num == 4) {
114 + val &= QCA8K_LED_PATTERN_EN_MASK;
115 + val >>= QCA8K_LED_PATTERN_EN_SHIFT;
117 + val &= QCA8K_LED_PHY123_PATTERN_EN_MASK;
120 + return val == QCA8K_LED_RULE_CONTROLLED;
124 +qca8k_cled_hw_control_is_supported(struct led_classdev *ldev, unsigned long rules)
126 + u32 offload_trigger = 0;
128 + return qca8k_parse_netdev(rules, &offload_trigger);
132 +qca8k_cled_hw_control_set(struct led_classdev *ldev, unsigned long rules)
134 + struct qca8k_led *led = container_of(ldev, struct qca8k_led, cdev);
135 + struct qca8k_led_pattern_en reg_info;
136 + struct qca8k_priv *priv = led->priv;
137 + u32 offload_trigger = 0;
140 + ret = qca8k_parse_netdev(rules, &offload_trigger);
144 + ret = qca8k_cled_trigger_offload(ldev, true);
148 + qca8k_get_control_led_reg(led->port_num, led->led_num, ®_info);
150 + return regmap_update_bits(priv->regmap, reg_info.reg,
151 + QCA8K_LED_RULE_MASK << reg_info.shift,
152 + offload_trigger << reg_info.shift);
156 +qca8k_cled_hw_control_get(struct led_classdev *ldev, unsigned long *rules)
158 + struct qca8k_led *led = container_of(ldev, struct qca8k_led, cdev);
159 + struct qca8k_led_pattern_en reg_info;
160 + struct qca8k_priv *priv = led->priv;
164 + /* With hw control not active return err */
165 + if (!qca8k_cled_hw_control_status(ldev))
168 + qca8k_get_control_led_reg(led->port_num, led->led_num, ®_info);
170 + ret = regmap_read(priv->regmap, reg_info.reg, &val);
174 + val >>= reg_info.shift;
175 + val &= QCA8K_LED_RULE_MASK;
177 + /* Parsing specific to netdev trigger */
178 + if (val & QCA8K_LED_TX_BLINK_MASK)
179 + set_bit(TRIGGER_NETDEV_TX, rules);
180 + if (val & QCA8K_LED_RX_BLINK_MASK)
181 + set_bit(TRIGGER_NETDEV_RX, rules);
187 qca8k_parse_port_leds(struct qca8k_priv *priv, struct fwnode_handle *port, int port_num)
189 struct fwnode_handle *led = NULL, *leds = NULL;
190 @@ -224,6 +374,10 @@ qca8k_parse_port_leds(struct qca8k_priv
191 port_led->cdev.max_brightness = 1;
192 port_led->cdev.brightness_set_blocking = qca8k_cled_brightness_set_blocking;
193 port_led->cdev.blink_set = qca8k_cled_blink_set;
194 + port_led->cdev.hw_control_is_supported = qca8k_cled_hw_control_is_supported;
195 + port_led->cdev.hw_control_set = qca8k_cled_hw_control_set;
196 + port_led->cdev.hw_control_get = qca8k_cled_hw_control_get;
197 + port_led->cdev.hw_control_trigger = "netdev";
198 init_data.default_label = ":port";
199 init_data.fwnode = led;
200 init_data.devname_mandatory = true;