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12 ********************************************************************************
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45 notice, this list of conditions and the following disclaimer in the
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52 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
53 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
54 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
55 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
56 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
57 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
58 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
59 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
60 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
61 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *******************************************************************************/
65 /*******************************************************************************
69 * Memory full detection and best timing configuration is done in
70 * C code. C runtime environment requires a stack. This module API
71 * initialize DRAM interface chip select 0 for basic functionality for
73 * The module API assumes DRAM information is stored in I2C EEPROM reside
74 * in a given I2C address MV_BOARD_DIMM0_I2C_ADDR. The I2C EEPROM
75 * internal data structure is assumed to be orgenzied in common DRAM
76 * vendor SPD structure.
77 * NOTE: DFCDL values are assumed to be already initialized prior to
78 * this module API activity.
84 *******************************************************************************/
88 #define MV_ASMLANGUAGE
90 #include "mvSysHwConfig.h"
91 #include "mvDramIfRegs.h"
92 #include "mvDramIfConfig.h"
93 #include "ctrlEnv/sys/mvCpuIfRegs.h"
94 #include "pex/mvPexRegs.h"
95 #include "ctrlEnv/mvCtrlEnvSpec.h"
102 .globl _mvDramIfConfig
104 .globl _mvDramIfMemInit
106 /*******************************************************************************
107 * _mvDramIfConfig - Basic DRAM interface initialization.
110 * The function will initialize the following DRAM parameters using the
111 * values prepared by mvDramIfDetect routine. Values are located
112 * in predefined registers.
123 *******************************************************************************/
127 /* Save register on stack */
131 stmdb sp!, {r1, r2, r3, r4}
134 /* Dunit FTDLL Configuration Register */
135 /* 0) Write to SDRAM FTDLL coniguration register */
136 ldr r4, = SDRAM_FTDLL_REG_DEFAULT_LEFT;
137 ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_LEFT_REG)
139 ldr r4, = SDRAM_FTDLL_REG_DEFAULT_RIGHT;
140 ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_RIGHT_REG)
142 ldr r4, = SDRAM_FTDLL_REG_DEFAULT_UP;
143 ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_UP_REG)
146 /* 1) Write to SDRAM coniguration register */
147 ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG1)
149 ldr r1, =(INTER_REGS_BASE + SDRAM_CONFIG_REG)
152 /* 2) Write Dunit control low register */
153 ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG3)
155 ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_REG)
158 /* 2) Write Dunit control high register */
159 ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG13)
161 ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_HI_REG)
164 /* 3) Write SDRAM address control register */
165 ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG4)
167 ldr r1, =(INTER_REGS_BASE + SDRAM_ADDR_CTRL_REG)
169 #if defined(MV_STATIC_DRAM_ON_BOARD)
170 /* 4) Write SDRAM bank 0 size register */
171 ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG0)
173 ldr r1, =(INTER_REGS_BASE + SDRAM_SIZE_REG(0,0))
177 /* 5) Write SDRAM open pages control register */
178 ldr r1, =(INTER_REGS_BASE + SDRAM_OPEN_PAGE_CTRL_REG)
179 ldr r4, =SDRAM_OPEN_PAGES_CTRL_REG_DV
182 /* 6) Write SDRAM timing Low register */
183 ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG5)
185 ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_LOW_REG)
188 /* 7) Write SDRAM timing High register */
189 ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG6)
191 ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_HIGH_REG)
194 /* Config DDR2 On Die Termination (ODT) registers */
195 /* Write SDRAM DDR2 ODT control low register */
196 ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG7)
198 ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_LOW_REG)
201 /* Write SDRAM DDR2 ODT control high register */
202 ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG8)
204 ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_HIGH_REG)
207 /* Write SDRAM DDR2 Dunit ODT control register */
208 ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG9)
210 ldr r1, =(INTER_REGS_BASE + DDR2_DUNIT_ODT_CONTROL_REG)
213 /* Write DDR2 SDRAM timing Low register */
214 ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG11)
216 ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_LO_REG)
219 /* Write DDR2 SDRAM timing High register */
220 ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG12)
222 ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_HI_REG)
225 /* 8) Write SDRAM mode register */
226 /* The CPU must not attempt to change the SDRAM Mode register setting */
227 /* prior to DRAM controller completion of the DRAM initialization */
228 /* sequence. To guarantee this restriction, it is recommended that */
229 /* the CPU sets the SDRAM Operation register to NOP command, performs */
230 /* read polling until the register is back in Normal operation value, */
231 /* and then sets SDRAM Mode register to its new value. */
233 /* 8.1 write 'nop' to SDRAM operation */
234 mov r4, #0x5 /* 'NOP' command */
235 MV_REG_WRITE_ASM(r4, r1, SDRAM_OPERATION_REG)
237 /* 8.2 poll SDRAM operation. Make sure its back to normal operation */
240 cmp r4, #0 /* '0' = Normal SDRAM Mode */
243 /* 8.3 Now its safe to write new value to SDRAM Mode register */
244 ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG2)
246 ldr r1, =(INTER_REGS_BASE + SDRAM_MODE_REG)
249 /* 8.4 Make the Dunit write the DRAM its new mode */
250 mov r4, #0x3 /* Mode Register Set command */
251 MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
253 /* 8.5 poll SDRAM operation. Make sure its back to normal operation */
256 cmp r4, #0 /* '0' = Normal SDRAM Mode */
259 /* Now its safe to write new value to SDRAM Extended Mode regist */
260 ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG10)
262 ldr r1, =(INTER_REGS_BASE + SDRAM_EXTENDED_MODE_REG)
265 /* 9) Write SDRAM Extended mode register This operation should be */
266 /* done for each memory bank */
267 /* write 'nop' to SDRAM operation */
268 mov r4, #0x5 /* 'NOP' command */
269 MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
271 /* poll SDRAM operation. Make sure its back to normal operation */
274 cmp r4, #0 /* '0' = Normal SDRAM Mode */
276 /* Go over each of the Banks */
277 ldr r3, =0 /* r3 = DRAM bank Num */
280 /* Set the SDRAM Operation Control to each of the DRAM banks */
281 mov r4, r3 /* Do not swap the bank counter value */
282 MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_CTRL_REG)
284 /* Make the Dunit write the DRAM its new mode */
285 mov r4, #0x4 /* Extended Mode Register Set command */
286 MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
288 /* poll SDRAM operation. Make sure its back to normal operation */
291 cmp r4, #0 /* '0' = Normal SDRAM Mode */
295 cmp r3, #4 /* 4 = Number of banks */
301 mov r1, LR /* Save link register */
305 mov LR,r1 /* restore link register */
307 /* Restore registers */
308 ldmia sp!, {r1, r2, r3, r4}
314 /*******************************************************************************
315 * _mvDramIfEccMemInit - Basic DRAM ECC initialization.
328 *******************************************************************************/
329 #define XOR_CHAN0 0 /* XOR channel 0 used for memory initialization */
330 #define XOR_UNIT0 0 /* XOR unit 0 used for memory initialization */
331 #define XOR_ADDR_DEC_WIN0 0 /* Enable DRAM access using XOR decode window 0 */
332 /* XOR engine register offsets macros */
333 #define XOR_CONFIG_REG(chan) (XOR_UNIT_BASE(0) + 0x10 + ((chan) * 4))
334 #define XOR_ACTIVATION_REG(chan) (XOR_UNIT_BASE(0) + 0x20 + ((chan) * 4))
335 #define XOR_CAUSE_REG (XOR_UNIT_BASE(0) + 0x30)
336 #define XOR_ERROR_CAUSE_REG (XOR_UNIT_BASE(0) + 0x50)
337 #define XOR_ERROR_ADDR_REG (XOR_UNIT_BASE(0) + 0x60)
338 #define XOR_INIT_VAL_LOW_REG (XOR_UNIT_BASE(0) + 0x2E0)
339 #define XOR_INIT_VAL_HIGH_REG (XOR_UNIT_BASE(0) + 0x2E4)
340 #define XOR_DST_PTR_REG(chan) (XOR_UNIT_BASE(0) + 0x2B0 + ((chan) * 4))
341 #define XOR_BLOCK_SIZE_REG(chan) (XOR_UNIT_BASE(0) + 0x2C0 + ((chan) * 4))
343 /* XOR Engine Address Decoding Register Map */
344 #define XOR_WINDOW_CTRL_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x240 + ((chan) * 4)))
345 #define XOR_BASE_ADDR_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x250 + ((winNum) * 4)))
346 #define XOR_SIZE_MASK_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x270 + ((winNum) * 4)))
348 .globl _mvDramIfEccMemInit
349 /*******************************************************************************
350 * _mvDramIfEccMemInit - mem init for dram cs
353 * This function will clean the cs by ussing the XOR mem init.
356 * r0 - dram bank number.
363 /* Save register on stack */
367 stmdb sp!, {r0,r1, r2, r3, r4, r5, r6}
372 /* Disable all XOR address decode windows to avoid possible overlap */
373 MV_REG_WRITE_ASM (r1, r5, (XOR_WINDOW_CTRL_REG(XOR_UNIT0,XOR_CHAN0)))
375 /* Init r5 to first XOR_SIZE_MASK_REG */
379 add r5, r5,#(INTER_REGS_BASE)
382 MV_REG_WRITE_ASM (r6, r5, XOR_SIZE_MASK_REG(XOR_UNIT0,XOR_ADDR_DEC_WIN0))
386 add r5, r5,#(INTER_REGS_BASE)
388 /* Update destination & size */
389 MV_REG_WRITE_ASM(r6, r5, XOR_DST_PTR_REG(XOR_CHAN0))
391 /* Init r6 to first XOR_BASE_ADDR_REG */
399 MV_REG_WRITE_ASM (r6, r5, XOR_BASE_ADDR_REG(XOR_UNIT0,XOR_ADDR_DEC_WIN0))
402 MV_REG_WRITE_ASM (r6, r5, XOR_WINDOW_CTRL_REG(XOR_UNIT0,XOR_CHAN0))
404 /* Configure XOR engine for memory init function. */
405 MV_REG_READ_ASM (r6, r5, XOR_CONFIG_REG(XOR_CHAN0))
406 and r6, r6, #~0x7 /* Clear operation mode field */
407 orr r6, r6, #0x4 /* Set operation to memory init */
408 MV_REG_WRITE_ASM(r6, r5, XOR_CONFIG_REG(XOR_CHAN0))
410 /* Set initVal in the XOR Engine Initial Value Registers */
412 MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_LOW_REG)
414 MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_HIGH_REG)
416 /* Set block size using DRAM bank size */
421 add r5, r5,#(INTER_REGS_BASE)
425 and r6, r6, #SCSR_SIZE_MASK
426 mov r5, r6, LSR #SCSR_SIZE_OFFS
428 mov r6, r5, LSL #SCSR_SIZE_OFFS
429 MV_REG_WRITE_ASM(r6, r5, XOR_BLOCK_SIZE_REG(XOR_CHAN0))
431 /* Clean interrupt cause*/
432 MV_REG_WRITE_ASM(r1, r5, XOR_CAUSE_REG)
434 /* Clean error interrupt cause*/
435 MV_REG_READ_ASM(r6, r5, XOR_ERROR_CAUSE_REG)
436 MV_REG_READ_ASM(r6, r5, XOR_ERROR_ADDR_REG)
439 MV_REG_READ_ASM (r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0))
440 orr r6, r6, #0x1 /* Preform start command */
441 MV_REG_WRITE_ASM(r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0))
443 /* Wait for engine to finish */
445 MV_REG_READ_ASM(r6, r5, XOR_CAUSE_REG)
450 /* Clear all error report registers */
451 MV_REG_WRITE_ASM(r1, r5, SDRAM_SINGLE_BIT_ERR_CNTR_REG)
452 MV_REG_WRITE_ASM(r1, r5, SDRAM_DOUBLE_BIT_ERR_CNTR_REG)
454 MV_REG_WRITE_ASM(r1, r5, SDRAM_ERROR_CAUSE_REG)
459 ldmia sp!, {r0, r1, r2, r3, r4, r5, r6}
464 /*******************************************************************************
465 * mvDramIfMemInit - Use XOR to clear all memory.
468 * Use assembler function _mvDramIfEccMemInit to fill all memory with FEADFEAD pattern.
478 *******************************************************************************/
482 stmdb sp!, {r0,r1, r2, r3, r4, r5, r6}
483 mov r6, LR /* Save link register */
484 /* Check if dram bank 0 has to be init for ECC */
485 MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,0))
486 and r3, r0, #SCSR_WIN_EN
489 MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,0))
493 bl _mvDramIfEccMemInit
496 /* Check if dram bank 1 has to be init for ECC */
497 MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,1))
498 and r0, r0, #SCSR_WIN_EN
502 bl _mvDramIfEccMemInit
504 /* Check if dram bank 2 has to be init for ECC */
505 MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,2))
506 and r0, r0, #SCSR_WIN_EN
509 MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,2))
513 bl _mvDramIfEccMemInit
516 /* Check if dram bank 3 has to be init for ECC */
517 MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,3))
518 and r0, r0, #SCSR_WIN_EN
522 bl _mvDramIfEccMemInit
524 mov LR ,r6 /* restore link register */
525 ldmia sp!, {r0, r1, r2, r3, r4, r5, r6}