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12 ********************************************************************************
13 Marvell Commercial License Option
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23 modify this File in accordance with the terms and conditions of the General
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37 modify this File under the following licensing terms.
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39 are permitted provided that the following conditions are met:
41 * Redistributions of source code must retain the above copyright notice,
42 this list of conditions and the following disclaimer.
44 * Redistributions in binary form must reproduce the above copyright
45 notice, this list of conditions and the following disclaimer in the
46 documentation and/or other materials provided with the distribution.
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52 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
53 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
54 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
55 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
56 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
57 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
58 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
59 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
60 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
61 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *******************************************************************************/
65 /*******************************************************************************
66 * mvEthDebug.c - Source file for user friendly debug functions
73 *******************************************************************************/
80 #include "ctrlEnv/mvCtrlEnvLib.h"
81 #include "eth-phy/mvEthPhy.h"
82 #include "eth/mvEth.h"
83 #include "eth/gbe/mvEthDebug.h"
85 /* #define mvOsPrintf printf */
87 void mvEthPortShow(void* pHndl
);
88 void mvEthQueuesShow(void* pHndl
, int rxQueue
, int txQueue
, int mode
);
90 /******************************************************************************/
92 /******************************************************************************/
93 void ethRxCoal(int port
, int usec
)
97 pHndl
= mvEthPortHndlGet(port
);
100 mvEthRxCoalSet(pHndl
, usec
);
104 void ethTxCoal(int port
, int usec
)
108 pHndl
= mvEthPortHndlGet(port
);
111 mvEthTxCoalSet(pHndl
, usec
);
115 #if (MV_ETH_VERSION >= 4)
116 void ethEjpModeSet(int port
, int mode
)
120 pHndl
= mvEthPortHndlGet(port
);
123 mvEthEjpModeSet(pHndl
, mode
);
126 #endif /* (MV_ETH_VERSION >= 4) */
128 void ethBpduRxQ(int port
, int bpduQueue
)
132 pHndl
= mvEthPortHndlGet(port
);
135 mvEthBpduRxQueue(pHndl
, bpduQueue
);
139 void ethArpRxQ(int port
, int arpQueue
)
143 pHndl
= mvEthPortHndlGet(port
);
146 mvEthArpRxQueue(pHndl
, arpQueue
);
150 void ethTcpRxQ(int port
, int tcpQueue
)
154 pHndl
= mvEthPortHndlGet(port
);
157 mvEthTcpRxQueue(pHndl
, tcpQueue
);
161 void ethUdpRxQ(int port
, int udpQueue
)
165 pHndl
= mvEthPortHndlGet(port
);
168 mvEthUdpRxQueue(pHndl
, udpQueue
);
172 void ethTxPolicyRegs(int port
)
175 ETH_PORT_CTRL
* pPortCtrl
= (ETH_PORT_CTRL
*)mvEthPortHndlGet(port
);
177 if(pPortCtrl
== NULL
)
181 mvOsPrintf("Port #%d TX Policy: EJP=%d, TXQs: ",
182 port
, pPortCtrl
->portConfig
.ejpMode
);
183 for(queue
=0; queue
<MV_ETH_TX_Q_NUM
; queue
++)
185 if(pPortCtrl
->txQueueConfig
[queue
].descrNum
> 0)
186 mvOsPrintf("%d, ", queue
);
190 mvOsPrintf("\n\t TX policy Port #%d configuration registers\n", port
);
192 mvOsPrintf("ETH_TX_QUEUE_COMMAND_REG : 0x%X = 0x%08x\n",
193 ETH_TX_QUEUE_COMMAND_REG(port
),
194 MV_REG_READ( ETH_TX_QUEUE_COMMAND_REG(port
) ) );
196 mvOsPrintf("ETH_TX_FIXED_PRIO_CFG_REG : 0x%X = 0x%08x\n",
197 ETH_TX_FIXED_PRIO_CFG_REG(port
),
198 MV_REG_READ( ETH_TX_FIXED_PRIO_CFG_REG(port
) ) );
200 mvOsPrintf("ETH_TX_TOKEN_RATE_CFG_REG : 0x%X = 0x%08x\n",
201 ETH_TX_TOKEN_RATE_CFG_REG(port
),
202 MV_REG_READ( ETH_TX_TOKEN_RATE_CFG_REG(port
) ) );
204 mvOsPrintf("ETH_MAX_TRANSMIT_UNIT_REG : 0x%X = 0x%08x\n",
205 ETH_MAX_TRANSMIT_UNIT_REG(port
),
206 MV_REG_READ( ETH_MAX_TRANSMIT_UNIT_REG(port
) ) );
208 mvOsPrintf("ETH_TX_TOKEN_BUCKET_SIZE_REG : 0x%X = 0x%08x\n",
209 ETH_TX_TOKEN_BUCKET_SIZE_REG(port
),
210 MV_REG_READ( ETH_TX_TOKEN_BUCKET_SIZE_REG(port
) ) );
212 mvOsPrintf("ETH_TX_TOKEN_BUCKET_COUNT_REG : 0x%X = 0x%08x\n",
213 ETH_TX_TOKEN_BUCKET_COUNT_REG(port
),
214 MV_REG_READ( ETH_TX_TOKEN_BUCKET_COUNT_REG(port
) ) );
216 for(queue
=0; queue
<MV_ETH_MAX_TXQ
; queue
++)
218 mvOsPrintf("\n\t TX policy Port #%d, Queue #%d configuration registers\n", port
, queue
);
220 mvOsPrintf("ETH_TXQ_TOKEN_COUNT_REG : 0x%X = 0x%08x\n",
221 ETH_TXQ_TOKEN_COUNT_REG(port
, queue
),
222 MV_REG_READ( ETH_TXQ_TOKEN_COUNT_REG(port
, queue
) ) );
224 mvOsPrintf("ETH_TXQ_TOKEN_CFG_REG : 0x%X = 0x%08x\n",
225 ETH_TXQ_TOKEN_CFG_REG(port
, queue
),
226 MV_REG_READ( ETH_TXQ_TOKEN_CFG_REG(port
, queue
) ) );
228 mvOsPrintf("ETH_TXQ_ARBITER_CFG_REG : 0x%X = 0x%08x\n",
229 ETH_TXQ_ARBITER_CFG_REG(port
, queue
),
230 MV_REG_READ( ETH_TXQ_ARBITER_CFG_REG(port
, queue
) ) );
235 /* Print important registers of Ethernet port */
236 void ethPortRegs(int port
)
238 mvOsPrintf("\n\t ethGiga #%d port Registers:\n", port
);
240 mvOsPrintf("ETH_PORT_STATUS_REG : 0x%X = 0x%08x\n",
241 ETH_PORT_STATUS_REG(port
),
242 MV_REG_READ( ETH_PORT_STATUS_REG(port
) ) );
244 mvOsPrintf("ETH_PORT_SERIAL_CTRL_REG : 0x%X = 0x%08x\n",
245 ETH_PORT_SERIAL_CTRL_REG(port
),
246 MV_REG_READ( ETH_PORT_SERIAL_CTRL_REG(port
) ) );
248 mvOsPrintf("ETH_PORT_CONFIG_REG : 0x%X = 0x%08x\n",
249 ETH_PORT_CONFIG_REG(port
),
250 MV_REG_READ( ETH_PORT_CONFIG_REG(port
) ) );
252 mvOsPrintf("ETH_PORT_CONFIG_EXTEND_REG : 0x%X = 0x%08x\n",
253 ETH_PORT_CONFIG_EXTEND_REG(port
),
254 MV_REG_READ( ETH_PORT_CONFIG_EXTEND_REG(port
) ) );
256 mvOsPrintf("ETH_SDMA_CONFIG_REG : 0x%X = 0x%08x\n",
257 ETH_SDMA_CONFIG_REG(port
),
258 MV_REG_READ( ETH_SDMA_CONFIG_REG(port
) ) );
260 mvOsPrintf("ETH_TX_FIFO_URGENT_THRESH_REG : 0x%X = 0x%08x\n",
261 ETH_TX_FIFO_URGENT_THRESH_REG(port
),
262 MV_REG_READ( ETH_TX_FIFO_URGENT_THRESH_REG(port
) ) );
264 mvOsPrintf("ETH_RX_QUEUE_COMMAND_REG : 0x%X = 0x%08x\n",
265 ETH_RX_QUEUE_COMMAND_REG(port
),
266 MV_REG_READ( ETH_RX_QUEUE_COMMAND_REG(port
) ) );
268 mvOsPrintf("ETH_TX_QUEUE_COMMAND_REG : 0x%X = 0x%08x\n",
269 ETH_TX_QUEUE_COMMAND_REG(port
),
270 MV_REG_READ( ETH_TX_QUEUE_COMMAND_REG(port
) ) );
272 mvOsPrintf("ETH_INTR_CAUSE_REG : 0x%X = 0x%08x\n",
273 ETH_INTR_CAUSE_REG(port
),
274 MV_REG_READ( ETH_INTR_CAUSE_REG(port
) ) );
276 mvOsPrintf("ETH_INTR_EXTEND_CAUSE_REG : 0x%X = 0x%08x\n",
277 ETH_INTR_CAUSE_EXT_REG(port
),
278 MV_REG_READ( ETH_INTR_CAUSE_EXT_REG(port
) ) );
280 mvOsPrintf("ETH_INTR_MASK_REG : 0x%X = 0x%08x\n",
281 ETH_INTR_MASK_REG(port
),
282 MV_REG_READ( ETH_INTR_MASK_REG(port
) ) );
284 mvOsPrintf("ETH_INTR_EXTEND_MASK_REG : 0x%X = 0x%08x\n",
285 ETH_INTR_MASK_EXT_REG(port
),
286 MV_REG_READ( ETH_INTR_MASK_EXT_REG(port
) ) );
288 mvOsPrintf("ETH_RX_DESCR_STAT_CMD_REG : 0x%X = 0x%08x\n",
289 ETH_RX_DESCR_STAT_CMD_REG(port
, 0),
290 MV_REG_READ( ETH_RX_DESCR_STAT_CMD_REG(port
, 0) ) );
292 mvOsPrintf("ETH_RX_BYTE_COUNT_REG : 0x%X = 0x%08x\n",
293 ETH_RX_BYTE_COUNT_REG(port
, 0),
294 MV_REG_READ( ETH_RX_BYTE_COUNT_REG(port
, 0) ) );
296 mvOsPrintf("ETH_RX_BUF_PTR_REG : 0x%X = 0x%08x\n",
297 ETH_RX_BUF_PTR_REG(port
, 0),
298 MV_REG_READ( ETH_RX_BUF_PTR_REG(port
, 0) ) );
300 mvOsPrintf("ETH_RX_CUR_DESC_PTR_REG : 0x%X = 0x%08x\n",
301 ETH_RX_CUR_DESC_PTR_REG(port
, 0),
302 MV_REG_READ( ETH_RX_CUR_DESC_PTR_REG(port
, 0) ) );
306 /* Print Giga Ethernet UNIT registers */
307 void ethRegs(int port
)
309 mvOsPrintf("ETH_PHY_ADDR_REG : 0x%X = 0x%08x\n",
310 ETH_PHY_ADDR_REG(port
),
311 MV_REG_READ(ETH_PHY_ADDR_REG(port
)) );
313 mvOsPrintf("ETH_UNIT_INTR_CAUSE_REG : 0x%X = 0x%08x\n",
314 ETH_UNIT_INTR_CAUSE_REG(port
),
315 MV_REG_READ( ETH_UNIT_INTR_CAUSE_REG(port
)) );
317 mvOsPrintf("ETH_UNIT_INTR_MASK_REG : 0x%X = 0x%08x\n",
318 ETH_UNIT_INTR_MASK_REG(port
),
319 MV_REG_READ( ETH_UNIT_INTR_MASK_REG(port
)) );
321 mvOsPrintf("ETH_UNIT_ERROR_ADDR_REG : 0x%X = 0x%08x\n",
322 ETH_UNIT_ERROR_ADDR_REG(port
),
323 MV_REG_READ(ETH_UNIT_ERROR_ADDR_REG(port
)) );
325 mvOsPrintf("ETH_UNIT_INT_ADDR_ERROR_REG : 0x%X = 0x%08x\n",
326 ETH_UNIT_INT_ADDR_ERROR_REG(port
),
327 MV_REG_READ(ETH_UNIT_INT_ADDR_ERROR_REG(port
)) );
331 /******************************************************************************/
332 /* MIB Counters functions */
333 /******************************************************************************/
335 /*******************************************************************************
336 * ethClearMibCounters - Clear all MIB counters
339 * This function clears all MIB counters of a specific ethernet port.
340 * A read from the MIB counter will reset the counter.
343 * int port - Ethernet Port number.
347 *******************************************************************************/
348 void ethClearCounters(int port
)
352 pHndl
= mvEthPortHndlGet(port
);
354 mvEthMibCountersClear(pHndl
);
360 /* Print counters of the Ethernet port */
361 void ethPortCounters(int port
)
363 MV_U32 regValue
, regValHigh
;
366 pHndl
= mvEthPortHndlGet(port
);
370 mvOsPrintf("\n\t Port #%d MIB Counters\n\n", port
);
372 mvOsPrintf("GoodFramesReceived = %u\n",
373 mvEthMibCounterRead(pHndl
, ETH_MIB_GOOD_FRAMES_RECEIVED
, NULL
));
374 mvOsPrintf("BadFramesReceived = %u\n",
375 mvEthMibCounterRead(pHndl
, ETH_MIB_BAD_FRAMES_RECEIVED
, NULL
));
376 mvOsPrintf("BroadcastFramesReceived = %u\n",
377 mvEthMibCounterRead(pHndl
, ETH_MIB_BROADCAST_FRAMES_RECEIVED
, NULL
));
378 mvOsPrintf("MulticastFramesReceived = %u\n",
379 mvEthMibCounterRead(pHndl
, ETH_MIB_MULTICAST_FRAMES_RECEIVED
, NULL
));
381 regValue
= mvEthMibCounterRead(pHndl
, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW
,
383 mvOsPrintf("GoodOctetsReceived = 0x%08x%08x\n",
384 regValHigh
, regValue
);
387 mvOsPrintf("GoodFramesSent = %u\n",
388 mvEthMibCounterRead(pHndl
, ETH_MIB_GOOD_FRAMES_SENT
, NULL
));
389 mvOsPrintf("BroadcastFramesSent = %u\n",
390 mvEthMibCounterRead(pHndl
, ETH_MIB_BROADCAST_FRAMES_SENT
, NULL
));
391 mvOsPrintf("MulticastFramesSent = %u\n",
392 mvEthMibCounterRead(pHndl
, ETH_MIB_MULTICAST_FRAMES_SENT
, NULL
));
394 regValue
= mvEthMibCounterRead(pHndl
, ETH_MIB_GOOD_OCTETS_SENT_LOW
,
396 mvOsPrintf("GoodOctetsSent = 0x%08x%08x\n", regValHigh
, regValue
);
399 mvOsPrintf("\n\t FC Control Counters\n");
401 regValue
= mvEthMibCounterRead(pHndl
, ETH_MIB_UNREC_MAC_CONTROL_RECEIVED
, NULL
);
402 mvOsPrintf("UnrecogMacControlReceived = %u\n", regValue
);
404 regValue
= mvEthMibCounterRead(pHndl
, ETH_MIB_GOOD_FC_RECEIVED
, NULL
);
405 mvOsPrintf("GoodFCFramesReceived = %u\n", regValue
);
407 regValue
= mvEthMibCounterRead(pHndl
, ETH_MIB_BAD_FC_RECEIVED
, NULL
);
408 mvOsPrintf("BadFCFramesReceived = %u\n", regValue
);
410 regValue
= mvEthMibCounterRead(pHndl
, ETH_MIB_FC_SENT
, NULL
);
411 mvOsPrintf("FCFramesSent = %u\n", regValue
);
414 mvOsPrintf("\n\t RX Errors\n");
416 regValue
= mvEthMibCounterRead(pHndl
, ETH_MIB_BAD_OCTETS_RECEIVED
, NULL
);
417 mvOsPrintf("BadOctetsReceived = %u\n", regValue
);
419 regValue
= mvEthMibCounterRead(pHndl
, ETH_MIB_UNDERSIZE_RECEIVED
, NULL
);
420 mvOsPrintf("UndersizeFramesReceived = %u\n", regValue
);
422 regValue
= mvEthMibCounterRead(pHndl
, ETH_MIB_FRAGMENTS_RECEIVED
, NULL
);
423 mvOsPrintf("FragmentsReceived = %u\n", regValue
);
425 regValue
= mvEthMibCounterRead(pHndl
, ETH_MIB_OVERSIZE_RECEIVED
, NULL
);
426 mvOsPrintf("OversizeFramesReceived = %u\n", regValue
);
428 regValue
= mvEthMibCounterRead(pHndl
, ETH_MIB_JABBER_RECEIVED
, NULL
);
429 mvOsPrintf("JabbersReceived = %u\n", regValue
);
431 regValue
= mvEthMibCounterRead(pHndl
, ETH_MIB_MAC_RECEIVE_ERROR
, NULL
);
432 mvOsPrintf("MacReceiveErrors = %u\n", regValue
);
434 regValue
= mvEthMibCounterRead(pHndl
, ETH_MIB_BAD_CRC_EVENT
, NULL
);
435 mvOsPrintf("BadCrcReceived = %u\n", regValue
);
437 mvOsPrintf("\n\t TX Errors\n");
439 regValue
= mvEthMibCounterRead(pHndl
, ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR
, NULL
);
440 mvOsPrintf("TxMacErrors = %u\n", regValue
);
442 regValue
= mvEthMibCounterRead(pHndl
, ETH_MIB_EXCESSIVE_COLLISION
, NULL
);
443 mvOsPrintf("TxExcessiveCollisions = %u\n", regValue
);
445 regValue
= mvEthMibCounterRead(pHndl
, ETH_MIB_COLLISION
, NULL
);
446 mvOsPrintf("TxCollisions = %u\n", regValue
);
448 regValue
= mvEthMibCounterRead(pHndl
, ETH_MIB_LATE_COLLISION
, NULL
);
449 mvOsPrintf("TxLateCollisions = %u\n", regValue
);
453 regValue
= MV_REG_READ( ETH_RX_DISCARD_PKTS_CNTR_REG(port
));
454 mvOsPrintf("Rx Discard packets counter = %u\n", regValue
);
456 regValue
= MV_REG_READ(ETH_RX_OVERRUN_PKTS_CNTR_REG(port
));
457 mvOsPrintf("Rx Overrun packets counter = %u\n", regValue
);
460 /* Print RMON counters of the Ethernet port */
461 void ethPortRmonCounters(int port
)
465 pHndl
= mvEthPortHndlGet(port
);
469 mvOsPrintf("\n\t Port #%d RMON MIB Counters\n\n", port
);
471 mvOsPrintf("64 ByteFramesReceived = %u\n",
472 mvEthMibCounterRead(pHndl
, ETH_MIB_FRAMES_64_OCTETS
, NULL
));
473 mvOsPrintf("65...127 ByteFramesReceived = %u\n",
474 mvEthMibCounterRead(pHndl
, ETH_MIB_FRAMES_65_TO_127_OCTETS
, NULL
));
475 mvOsPrintf("128...255 ByteFramesReceived = %u\n",
476 mvEthMibCounterRead(pHndl
, ETH_MIB_FRAMES_128_TO_255_OCTETS
, NULL
));
477 mvOsPrintf("256...511 ByteFramesReceived = %u\n",
478 mvEthMibCounterRead(pHndl
, ETH_MIB_FRAMES_256_TO_511_OCTETS
, NULL
));
479 mvOsPrintf("512...1023 ByteFramesReceived = %u\n",
480 mvEthMibCounterRead(pHndl
, ETH_MIB_FRAMES_512_TO_1023_OCTETS
, NULL
));
481 mvOsPrintf("1024...Max ByteFramesReceived = %u\n",
482 mvEthMibCounterRead(pHndl
, ETH_MIB_FRAMES_1024_TO_MAX_OCTETS
, NULL
));
485 /* Print port information */
486 void ethPortStatus(int port
)
490 pHndl
= mvEthPortHndlGet(port
);
493 mvEthPortShow(pHndl
);
497 /* Print port queues information */
498 void ethPortQueues(int port
, int rxQueue
, int txQueue
, int mode
)
502 pHndl
= mvEthPortHndlGet(port
);
505 mvEthQueuesShow(pHndl
, rxQueue
, txQueue
, mode
);
509 void ethUcastSet(int port
, char* macStr
, int queue
)
512 MV_U8 macAddr
[MV_MAC_ADDR_SIZE
];
514 pHndl
= mvEthPortHndlGet(port
);
517 mvMacStrToHex(macStr
, macAddr
);
518 mvEthMacAddrSet(pHndl
, macAddr
, queue
);
523 void ethPortUcastShow(int port
)
525 MV_U32 unicastReg
, macL
, macH
;
528 macL
= MV_REG_READ(ETH_MAC_ADDR_LOW_REG(port
));
529 macH
= MV_REG_READ(ETH_MAC_ADDR_HIGH_REG(port
));
531 mvOsPrintf("\n\t Port #%d Unicast MAC table: %02x:%02x:%02x:%02x:%02x:%02x\n\n",
532 port
, ((macH
>> 24) & 0xff), ((macH
>> 16) & 0xff),
533 ((macH
>> 8) & 0xff), (macH
& 0xff),
534 ((macL
>> 8) & 0xff), (macL
& 0xff) );
538 unicastReg
= MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(port
) + i
*4));
541 MV_U8 macEntry
= (unicastReg
>> (8*j
)) & 0xFF;
543 mvOsPrintf("%X: %8s, Q = %d\n", i
*4+j
,
544 (macEntry
& BIT0
) ? "Accept" : "Reject", (macEntry
>> 1) & 0x7);
549 void ethMcastAdd(int port
, char* macStr
, int queue
)
552 MV_U8 macAddr
[MV_MAC_ADDR_SIZE
];
554 pHndl
= mvEthPortHndlGet(port
);
557 mvMacStrToHex(macStr
, macAddr
);
558 mvEthMcastAddrSet(pHndl
, macAddr
, queue
);
562 void ethPortMcast(int port
)
567 mvOsPrintf("\n\t Port #%d Special (IP) Multicast table: 01:00:5E:00:00:XX\n\n",
570 for(tblIdx
=0; tblIdx
<(256/4); tblIdx
++)
572 regVal
= MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(port
) + tblIdx
*4));
573 for(regIdx
=0; regIdx
<4; regIdx
++)
575 if((regVal
& (0x01 << (regIdx
*8))) != 0)
577 mvOsPrintf("0x%02X: Accepted, rxQ = %d\n",
578 tblIdx
*4+regIdx
, ((regVal
>> (regIdx
*8+1)) & 0x07));
582 mvOsPrintf("\n\t Port #%d Other Multicast table\n\n", port
);
583 for(tblIdx
=0; tblIdx
<(256/4); tblIdx
++)
585 regVal
= MV_REG_READ((ETH_DA_FILTER_OTH_MCAST_BASE(port
) + tblIdx
*4));
586 for(regIdx
=0; regIdx
<4; regIdx
++)
588 if((regVal
& (0x01 << (regIdx
*8))) != 0)
590 mvOsPrintf("Crc8=0x%02X: Accepted, rxQ = %d\n",
591 tblIdx
*4+regIdx
, ((regVal
>> (regIdx
*8+1)) & 0x07));
598 /* Print status of Ethernet port */
599 void mvEthPortShow(void* pHndl
)
601 MV_U32 regValue
, rxCoal
, txCoal
;
602 int speed
, queue
, port
;
603 ETH_PORT_CTRL
* pPortCtrl
= (ETH_PORT_CTRL
*)pHndl
;
605 port
= pPortCtrl
->portNo
;
607 regValue
= MV_REG_READ( ETH_PORT_STATUS_REG(port
) );
609 mvOsPrintf("\n\t ethGiga #%d port Status: 0x%04x = 0x%08x\n\n",
610 port
, ETH_PORT_STATUS_REG(port
), regValue
);
612 mvOsPrintf("descInSram=%d, descSwCoher=%d\n",
613 ethDescInSram
, ethDescSwCoher
);
615 if(regValue
& ETH_GMII_SPEED_1000_MASK
)
617 else if(regValue
& ETH_MII_SPEED_100_MASK
)
622 mvEthCoalGet(pPortCtrl
, &rxCoal
, &txCoal
);
624 /* Link, Speed, Duplex, FlowControl */
625 mvOsPrintf("Link=%s, Speed=%d, Duplex=%s, RxFlowControl=%s",
626 (regValue
& ETH_LINK_UP_MASK
) ? "UP" : "DOWN",
628 (regValue
& ETH_FULL_DUPLEX_MASK
) ? "FULL" : "HALF",
629 (regValue
& ETH_ENABLE_RCV_FLOW_CTRL_MASK
) ? "ENABLE" : "DISABLE");
633 mvOsPrintf("RxCoal = %d usec, TxCoal = %d usec\n",
636 mvOsPrintf("rxDefQ=%d, arpQ=%d, bpduQ=%d, tcpQ=%d, udpQ=%d\n\n",
637 pPortCtrl
->portConfig
.rxDefQ
, pPortCtrl
->portConfig
.rxArpQ
,
638 pPortCtrl
->portConfig
.rxBpduQ
,
639 pPortCtrl
->portConfig
.rxTcpQ
, pPortCtrl
->portConfig
.rxUdpQ
);
641 /* Print all RX and TX queues */
642 for(queue
=0; queue
<MV_ETH_RX_Q_NUM
; queue
++)
644 mvOsPrintf("RX Queue #%d: base=0x%lx, free=%d\n",
645 queue
, (MV_ULONG
)pPortCtrl
->rxQueue
[queue
].pFirstDescr
,
646 mvEthRxResourceGet(pPortCtrl
, queue
) );
649 for(queue
=0; queue
<MV_ETH_TX_Q_NUM
; queue
++)
651 mvOsPrintf("TX Queue #%d: base=0x%lx, free=%d\n",
652 queue
, (MV_ULONG
)pPortCtrl
->txQueue
[queue
].pFirstDescr
,
653 mvEthTxResourceGet(pPortCtrl
, queue
) );
657 /* Print RX and TX queue of the Ethernet port */
658 void mvEthQueuesShow(void* pHndl
, int rxQueue
, int txQueue
, int mode
)
660 ETH_PORT_CTRL
*pPortCtrl
= (ETH_PORT_CTRL
*)pHndl
;
661 ETH_QUEUE_CTRL
*pQueueCtrl
;
663 ETH_RX_DESC
*pRxDescr
;
664 ETH_TX_DESC
*pTxDescr
;
665 int i
, port
= pPortCtrl
->portNo
;
667 if( (rxQueue
>=0) && (rxQueue
< MV_ETH_RX_Q_NUM
) )
669 pQueueCtrl
= &(pPortCtrl
->rxQueue
[rxQueue
]);
670 mvOsPrintf("Port #%d, RX Queue #%d\n\n", port
, rxQueue
);
672 mvOsPrintf("CURR_RX_DESC_PTR : 0x%X = 0x%08x\n",
673 ETH_RX_CUR_DESC_PTR_REG(port
, rxQueue
),
674 MV_REG_READ( ETH_RX_CUR_DESC_PTR_REG(port
, rxQueue
)));
677 if(pQueueCtrl
->pFirstDescr
!= NULL
)
679 mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n",
680 (MV_ULONG
)pQueueCtrl
->pFirstDescr
, (MV_ULONG
)pQueueCtrl
->pLastDescr
,
681 pQueueCtrl
->resource
);
682 mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n",
683 (MV_ULONG
)pQueueCtrl
->pCurrentDescr
,
684 (MV_ULONG
)pQueueCtrl
->pUsedDescr
);
688 pRxDescr
= (ETH_RX_DESC
*)pQueueCtrl
->pFirstDescr
;
692 mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%4d, buf=%08x, pkt=%lx, os=%lx\n",
693 i
, (MV_U32
)pRxDescr
, (MV_U32
)ethDescVirtToPhy(pQueueCtrl
, (MV_U8
*)pRxDescr
),
694 pRxDescr
->cmdSts
, pRxDescr
->byteCnt
, (MV_U32
)pRxDescr
->bufSize
,
695 (unsigned int)pRxDescr
->bufPtr
, (MV_ULONG
)pRxDescr
->returnInfo
,
696 ((MV_PKT_INFO
*)pRxDescr
->returnInfo
)->osInfo
);
698 ETH_DESCR_INV(pPortCtrl
, pRxDescr
);
699 pRxDescr
= RX_NEXT_DESC_PTR(pRxDescr
, pQueueCtrl
);
701 } while (pRxDescr
!= pQueueCtrl
->pFirstDescr
);
705 mvOsPrintf("RX Queue #%d is NOT CREATED\n", rxQueue
);
708 if( (txQueue
>=0) && (txQueue
< MV_ETH_TX_Q_NUM
) )
710 pQueueCtrl
= &(pPortCtrl
->txQueue
[txQueue
]);
711 mvOsPrintf("Port #%d, TX Queue #%d\n\n", port
, txQueue
);
713 regValue
= MV_REG_READ( ETH_TX_CUR_DESC_PTR_REG(port
, txQueue
));
714 mvOsPrintf("CURR_TX_DESC_PTR : 0x%X = 0x%08x\n",
715 ETH_TX_CUR_DESC_PTR_REG(port
, txQueue
), regValue
);
717 if(pQueueCtrl
->pFirstDescr
!= NULL
)
719 mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n",
720 (MV_ULONG
)pQueueCtrl
->pFirstDescr
,
721 (MV_ULONG
)pQueueCtrl
->pLastDescr
,
722 pQueueCtrl
->resource
);
723 mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n",
724 (MV_ULONG
)pQueueCtrl
->pCurrentDescr
,
725 (MV_ULONG
)pQueueCtrl
->pUsedDescr
);
729 pTxDescr
= (ETH_TX_DESC
*)pQueueCtrl
->pFirstDescr
;
733 mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%08x, pkt=%lx, os=%lx\n",
734 i
, (MV_U32
)pTxDescr
, (MV_U32
)ethDescVirtToPhy(pQueueCtrl
, (MV_U8
*)pTxDescr
),
735 pTxDescr
->cmdSts
, pTxDescr
->byteCnt
,
736 (MV_U32
)pTxDescr
->bufPtr
, (MV_ULONG
)pTxDescr
->returnInfo
,
737 pTxDescr
->returnInfo
? (((MV_PKT_INFO
*)pTxDescr
->returnInfo
)->osInfo
) : 0x0);
739 ETH_DESCR_INV(pPortCtrl
, pTxDescr
);
740 pTxDescr
= TX_NEXT_DESC_PTR(pTxDescr
, pQueueCtrl
);
742 } while (pTxDescr
!= pQueueCtrl
->pFirstDescr
);
746 mvOsPrintf("TX Queue #%d is NOT CREATED\n", txQueue
);