2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/version.h>
40 extern const struct ar8xxx_chip ar8327_chip
;
41 extern const struct ar8xxx_chip ar8337_chip
;
43 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
45 #define MIB_DESC(_s , _o, _n) \
52 static const struct ar8xxx_mib_desc ar8216_mibs
[] = {
53 MIB_DESC(1, AR8216_STATS_RXBROAD
, "RxBroad"),
54 MIB_DESC(1, AR8216_STATS_RXPAUSE
, "RxPause"),
55 MIB_DESC(1, AR8216_STATS_RXMULTI
, "RxMulti"),
56 MIB_DESC(1, AR8216_STATS_RXFCSERR
, "RxFcsErr"),
57 MIB_DESC(1, AR8216_STATS_RXALIGNERR
, "RxAlignErr"),
58 MIB_DESC(1, AR8216_STATS_RXRUNT
, "RxRunt"),
59 MIB_DESC(1, AR8216_STATS_RXFRAGMENT
, "RxFragment"),
60 MIB_DESC(1, AR8216_STATS_RX64BYTE
, "Rx64Byte"),
61 MIB_DESC(1, AR8216_STATS_RX128BYTE
, "Rx128Byte"),
62 MIB_DESC(1, AR8216_STATS_RX256BYTE
, "Rx256Byte"),
63 MIB_DESC(1, AR8216_STATS_RX512BYTE
, "Rx512Byte"),
64 MIB_DESC(1, AR8216_STATS_RX1024BYTE
, "Rx1024Byte"),
65 MIB_DESC(1, AR8216_STATS_RXMAXBYTE
, "RxMaxByte"),
66 MIB_DESC(1, AR8216_STATS_RXTOOLONG
, "RxTooLong"),
67 MIB_DESC(2, AR8216_STATS_RXGOODBYTE
, "RxGoodByte"),
68 MIB_DESC(2, AR8216_STATS_RXBADBYTE
, "RxBadByte"),
69 MIB_DESC(1, AR8216_STATS_RXOVERFLOW
, "RxOverFlow"),
70 MIB_DESC(1, AR8216_STATS_FILTERED
, "Filtered"),
71 MIB_DESC(1, AR8216_STATS_TXBROAD
, "TxBroad"),
72 MIB_DESC(1, AR8216_STATS_TXPAUSE
, "TxPause"),
73 MIB_DESC(1, AR8216_STATS_TXMULTI
, "TxMulti"),
74 MIB_DESC(1, AR8216_STATS_TXUNDERRUN
, "TxUnderRun"),
75 MIB_DESC(1, AR8216_STATS_TX64BYTE
, "Tx64Byte"),
76 MIB_DESC(1, AR8216_STATS_TX128BYTE
, "Tx128Byte"),
77 MIB_DESC(1, AR8216_STATS_TX256BYTE
, "Tx256Byte"),
78 MIB_DESC(1, AR8216_STATS_TX512BYTE
, "Tx512Byte"),
79 MIB_DESC(1, AR8216_STATS_TX1024BYTE
, "Tx1024Byte"),
80 MIB_DESC(1, AR8216_STATS_TXMAXBYTE
, "TxMaxByte"),
81 MIB_DESC(1, AR8216_STATS_TXOVERSIZE
, "TxOverSize"),
82 MIB_DESC(2, AR8216_STATS_TXBYTE
, "TxByte"),
83 MIB_DESC(1, AR8216_STATS_TXCOLLISION
, "TxCollision"),
84 MIB_DESC(1, AR8216_STATS_TXABORTCOL
, "TxAbortCol"),
85 MIB_DESC(1, AR8216_STATS_TXMULTICOL
, "TxMultiCol"),
86 MIB_DESC(1, AR8216_STATS_TXSINGLECOL
, "TxSingleCol"),
87 MIB_DESC(1, AR8216_STATS_TXEXCDEFER
, "TxExcDefer"),
88 MIB_DESC(1, AR8216_STATS_TXDEFER
, "TxDefer"),
89 MIB_DESC(1, AR8216_STATS_TXLATECOL
, "TxLateCol"),
92 const struct ar8xxx_mib_desc ar8236_mibs
[39] = {
93 MIB_DESC(1, AR8236_STATS_RXBROAD
, "RxBroad"),
94 MIB_DESC(1, AR8236_STATS_RXPAUSE
, "RxPause"),
95 MIB_DESC(1, AR8236_STATS_RXMULTI
, "RxMulti"),
96 MIB_DESC(1, AR8236_STATS_RXFCSERR
, "RxFcsErr"),
97 MIB_DESC(1, AR8236_STATS_RXALIGNERR
, "RxAlignErr"),
98 MIB_DESC(1, AR8236_STATS_RXRUNT
, "RxRunt"),
99 MIB_DESC(1, AR8236_STATS_RXFRAGMENT
, "RxFragment"),
100 MIB_DESC(1, AR8236_STATS_RX64BYTE
, "Rx64Byte"),
101 MIB_DESC(1, AR8236_STATS_RX128BYTE
, "Rx128Byte"),
102 MIB_DESC(1, AR8236_STATS_RX256BYTE
, "Rx256Byte"),
103 MIB_DESC(1, AR8236_STATS_RX512BYTE
, "Rx512Byte"),
104 MIB_DESC(1, AR8236_STATS_RX1024BYTE
, "Rx1024Byte"),
105 MIB_DESC(1, AR8236_STATS_RX1518BYTE
, "Rx1518Byte"),
106 MIB_DESC(1, AR8236_STATS_RXMAXBYTE
, "RxMaxByte"),
107 MIB_DESC(1, AR8236_STATS_RXTOOLONG
, "RxTooLong"),
108 MIB_DESC(2, AR8236_STATS_RXGOODBYTE
, "RxGoodByte"),
109 MIB_DESC(2, AR8236_STATS_RXBADBYTE
, "RxBadByte"),
110 MIB_DESC(1, AR8236_STATS_RXOVERFLOW
, "RxOverFlow"),
111 MIB_DESC(1, AR8236_STATS_FILTERED
, "Filtered"),
112 MIB_DESC(1, AR8236_STATS_TXBROAD
, "TxBroad"),
113 MIB_DESC(1, AR8236_STATS_TXPAUSE
, "TxPause"),
114 MIB_DESC(1, AR8236_STATS_TXMULTI
, "TxMulti"),
115 MIB_DESC(1, AR8236_STATS_TXUNDERRUN
, "TxUnderRun"),
116 MIB_DESC(1, AR8236_STATS_TX64BYTE
, "Tx64Byte"),
117 MIB_DESC(1, AR8236_STATS_TX128BYTE
, "Tx128Byte"),
118 MIB_DESC(1, AR8236_STATS_TX256BYTE
, "Tx256Byte"),
119 MIB_DESC(1, AR8236_STATS_TX512BYTE
, "Tx512Byte"),
120 MIB_DESC(1, AR8236_STATS_TX1024BYTE
, "Tx1024Byte"),
121 MIB_DESC(1, AR8236_STATS_TX1518BYTE
, "Tx1518Byte"),
122 MIB_DESC(1, AR8236_STATS_TXMAXBYTE
, "TxMaxByte"),
123 MIB_DESC(1, AR8236_STATS_TXOVERSIZE
, "TxOverSize"),
124 MIB_DESC(2, AR8236_STATS_TXBYTE
, "TxByte"),
125 MIB_DESC(1, AR8236_STATS_TXCOLLISION
, "TxCollision"),
126 MIB_DESC(1, AR8236_STATS_TXABORTCOL
, "TxAbortCol"),
127 MIB_DESC(1, AR8236_STATS_TXMULTICOL
, "TxMultiCol"),
128 MIB_DESC(1, AR8236_STATS_TXSINGLECOL
, "TxSingleCol"),
129 MIB_DESC(1, AR8236_STATS_TXEXCDEFER
, "TxExcDefer"),
130 MIB_DESC(1, AR8236_STATS_TXDEFER
, "TxDefer"),
131 MIB_DESC(1, AR8236_STATS_TXLATECOL
, "TxLateCol"),
134 static DEFINE_MUTEX(ar8xxx_dev_list_lock
);
135 static LIST_HEAD(ar8xxx_dev_list
);
137 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
139 ar8xxx_phy_poll_reset(struct mii_bus
*bus
)
141 unsigned int sleep_msecs
= 20;
144 for (elapsed
= sleep_msecs
; elapsed
<= 600;
145 elapsed
+= sleep_msecs
) {
147 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
148 ret
= mdiobus_read(bus
, i
, MII_BMCR
);
151 if (ret
& BMCR_RESET
)
153 if (i
== AR8XXX_NUM_PHYS
- 1) {
154 usleep_range(1000, 2000);
163 ar8xxx_phy_check_aneg(struct phy_device
*phydev
)
167 if (phydev
->autoneg
!= AUTONEG_ENABLE
)
170 * BMCR_ANENABLE might have been cleared
171 * by phy_init_hw in certain kernel versions
172 * therefore check for it
174 ret
= phy_read(phydev
, MII_BMCR
);
177 if (ret
& BMCR_ANENABLE
)
180 dev_info(&phydev
->mdio
.dev
, "ANEG disabled, re-enabling ...\n");
181 ret
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
182 return phy_write(phydev
, MII_BMCR
, ret
);
186 ar8xxx_phy_init(struct ar8xxx_priv
*priv
)
192 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
193 if (priv
->chip
->phy_fixup
)
194 priv
->chip
->phy_fixup(priv
, i
);
196 /* initialize the port itself */
197 mdiobus_write(bus
, i
, MII_ADVERTISE
,
198 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
199 if (ar8xxx_has_gige(priv
))
200 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
201 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
204 ar8xxx_phy_poll_reset(bus
);
208 ar8xxx_mii_read32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
)
210 struct mii_bus
*bus
= priv
->mii_bus
;
213 lo
= bus
->read(bus
, phy_id
, regnum
);
214 hi
= bus
->read(bus
, phy_id
, regnum
+ 1);
216 return (hi
<< 16) | lo
;
220 ar8xxx_mii_write32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
, u32 val
)
222 struct mii_bus
*bus
= priv
->mii_bus
;
226 hi
= (u16
) (val
>> 16);
228 if (priv
->chip
->mii_lo_first
)
230 bus
->write(bus
, phy_id
, regnum
, lo
);
231 bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
233 bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
234 bus
->write(bus
, phy_id
, regnum
, lo
);
239 ar8xxx_read(struct ar8xxx_priv
*priv
, int reg
)
241 struct mii_bus
*bus
= priv
->mii_bus
;
245 split_addr((u32
) reg
, &r1
, &r2
, &page
);
247 mutex_lock(&bus
->mdio_lock
);
249 bus
->write(bus
, 0x18, 0, page
);
250 wait_for_page_switch();
251 val
= ar8xxx_mii_read32(priv
, 0x10 | r2
, r1
);
253 mutex_unlock(&bus
->mdio_lock
);
259 ar8xxx_write(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
261 struct mii_bus
*bus
= priv
->mii_bus
;
264 split_addr((u32
) reg
, &r1
, &r2
, &page
);
266 mutex_lock(&bus
->mdio_lock
);
268 bus
->write(bus
, 0x18, 0, page
);
269 wait_for_page_switch();
270 ar8xxx_mii_write32(priv
, 0x10 | r2
, r1
, val
);
272 mutex_unlock(&bus
->mdio_lock
);
276 ar8xxx_rmw(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
278 struct mii_bus
*bus
= priv
->mii_bus
;
282 split_addr((u32
) reg
, &r1
, &r2
, &page
);
284 mutex_lock(&bus
->mdio_lock
);
286 bus
->write(bus
, 0x18, 0, page
);
287 wait_for_page_switch();
289 ret
= ar8xxx_mii_read32(priv
, 0x10 | r2
, r1
);
292 ar8xxx_mii_write32(priv
, 0x10 | r2
, r1
, ret
);
294 mutex_unlock(&bus
->mdio_lock
);
300 ar8xxx_phy_dbg_write(struct ar8xxx_priv
*priv
, int phy_addr
,
301 u16 dbg_addr
, u16 dbg_data
)
303 struct mii_bus
*bus
= priv
->mii_bus
;
305 mutex_lock(&bus
->mdio_lock
);
306 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
307 bus
->write(bus
, phy_addr
, MII_ATH_DBG_DATA
, dbg_data
);
308 mutex_unlock(&bus
->mdio_lock
);
312 ar8xxx_phy_mmd_prep(struct mii_bus
*bus
, int phy_addr
, u16 addr
, u16 reg
)
314 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
315 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, reg
);
316 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
| 0x4000);
320 ar8xxx_phy_mmd_write(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 reg
, u16 data
)
322 struct mii_bus
*bus
= priv
->mii_bus
;
324 mutex_lock(&bus
->mdio_lock
);
325 ar8xxx_phy_mmd_prep(bus
, phy_addr
, addr
, reg
);
326 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, data
);
327 mutex_unlock(&bus
->mdio_lock
);
331 ar8xxx_phy_mmd_read(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 reg
)
333 struct mii_bus
*bus
= priv
->mii_bus
;
336 mutex_lock(&bus
->mdio_lock
);
337 ar8xxx_phy_mmd_prep(bus
, phy_addr
, addr
, reg
);
338 data
= bus
->read(bus
, phy_addr
, MII_ATH_MMD_DATA
);
339 mutex_unlock(&bus
->mdio_lock
);
345 ar8xxx_reg_wait(struct ar8xxx_priv
*priv
, u32 reg
, u32 mask
, u32 val
,
350 for (i
= 0; i
< timeout
; i
++) {
353 t
= ar8xxx_read(priv
, reg
);
354 if ((t
& mask
) == val
)
357 usleep_range(1000, 2000);
365 ar8xxx_mib_op(struct ar8xxx_priv
*priv
, u32 op
)
367 unsigned mib_func
= priv
->chip
->mib_func
;
370 lockdep_assert_held(&priv
->mib_lock
);
372 /* Capture the hardware statistics for all ports */
373 ar8xxx_rmw(priv
, mib_func
, AR8216_MIB_FUNC
, (op
<< AR8216_MIB_FUNC_S
));
375 /* Wait for the capturing to complete. */
376 ret
= ar8xxx_reg_wait(priv
, mib_func
, AR8216_MIB_BUSY
, 0, 10);
387 ar8xxx_mib_capture(struct ar8xxx_priv
*priv
)
389 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_CAPTURE
);
393 ar8xxx_mib_flush(struct ar8xxx_priv
*priv
)
395 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_FLUSH
);
399 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv
*priv
, int port
, bool flush
)
405 WARN_ON(port
>= priv
->dev
.ports
);
407 lockdep_assert_held(&priv
->mib_lock
);
409 base
= priv
->chip
->reg_port_stats_start
+
410 priv
->chip
->reg_port_stats_length
* port
;
412 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
413 for (i
= 0; i
< priv
->chip
->num_mibs
; i
++) {
414 const struct ar8xxx_mib_desc
*mib
;
417 mib
= &priv
->chip
->mib_decs
[i
];
418 t
= ar8xxx_read(priv
, base
+ mib
->offset
);
419 if (mib
->size
== 2) {
422 hi
= ar8xxx_read(priv
, base
+ mib
->offset
+ 4);
435 ar8216_read_port_link(struct ar8xxx_priv
*priv
, int port
,
436 struct switch_port_link
*link
)
441 memset(link
, '\0', sizeof(*link
));
443 status
= priv
->chip
->read_port_status(priv
, port
);
445 link
->aneg
= !!(status
& AR8216_PORT_STATUS_LINK_AUTO
);
447 link
->link
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
451 if (priv
->get_port_link
) {
454 err
= priv
->get_port_link(port
);
463 link
->duplex
= !!(status
& AR8216_PORT_STATUS_DUPLEX
);
464 link
->tx_flow
= !!(status
& AR8216_PORT_STATUS_TXFLOW
);
465 link
->rx_flow
= !!(status
& AR8216_PORT_STATUS_RXFLOW
);
467 if (link
->aneg
&& link
->duplex
&& priv
->chip
->read_port_eee_status
)
468 link
->eee
= priv
->chip
->read_port_eee_status(priv
, port
);
470 speed
= (status
& AR8216_PORT_STATUS_SPEED
) >>
471 AR8216_PORT_STATUS_SPEED_S
;
474 case AR8216_PORT_SPEED_10M
:
475 link
->speed
= SWITCH_PORT_SPEED_10
;
477 case AR8216_PORT_SPEED_100M
:
478 link
->speed
= SWITCH_PORT_SPEED_100
;
480 case AR8216_PORT_SPEED_1000M
:
481 link
->speed
= SWITCH_PORT_SPEED_1000
;
484 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
489 static struct sk_buff
*
490 ar8216_mangle_tx(struct net_device
*dev
, struct sk_buff
*skb
)
492 struct ar8xxx_priv
*priv
= dev
->phy_ptr
;
501 if (unlikely(skb_headroom(skb
) < 2)) {
502 if (pskb_expand_head(skb
, 2, 0, GFP_ATOMIC
) < 0)
506 buf
= skb_push(skb
, 2);
514 dev_kfree_skb_any(skb
);
519 ar8216_mangle_rx(struct net_device
*dev
, struct sk_buff
*skb
)
521 struct ar8xxx_priv
*priv
;
529 /* don't strip the header if vlan mode is disabled */
533 /* strip header, get vlan id */
537 /* check for vlan header presence */
538 if ((buf
[12 + 2] != 0x81) || (buf
[13 + 2] != 0x00))
543 /* no need to fix up packets coming from a tagged source */
544 if (priv
->vlan_tagged
& (1 << port
))
547 /* lookup port vid from local table, the switch passes an invalid vlan id */
548 vlan
= priv
->vlan_id
[priv
->pvid
[port
]];
551 buf
[14 + 2] |= vlan
>> 8;
552 buf
[15 + 2] = vlan
& 0xff;
556 ar8216_wait_bit(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
562 t
= ar8xxx_read(priv
, reg
);
563 if ((t
& mask
) == val
)
573 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
574 (unsigned int) reg
, t
, mask
, val
);
579 ar8216_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
581 if (ar8216_wait_bit(priv
, AR8216_REG_VTU
, AR8216_VTU_ACTIVE
, 0))
583 if ((op
& AR8216_VTU_OP
) == AR8216_VTU_OP_LOAD
) {
584 val
&= AR8216_VTUDATA_MEMBER
;
585 val
|= AR8216_VTUDATA_VALID
;
586 ar8xxx_write(priv
, AR8216_REG_VTU_DATA
, val
);
588 op
|= AR8216_VTU_ACTIVE
;
589 ar8xxx_write(priv
, AR8216_REG_VTU
, op
);
593 ar8216_vtu_flush(struct ar8xxx_priv
*priv
)
595 ar8216_vtu_op(priv
, AR8216_VTU_OP_FLUSH
, 0);
599 ar8216_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
603 op
= AR8216_VTU_OP_LOAD
| (vid
<< AR8216_VTU_VID_S
);
604 ar8216_vtu_op(priv
, op
, port_mask
);
608 ar8216_atu_flush(struct ar8xxx_priv
*priv
)
612 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_ACTIVE
, 0);
614 ar8xxx_write(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_OP_FLUSH
|
621 ar8216_atu_flush_port(struct ar8xxx_priv
*priv
, int port
)
626 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_ACTIVE
, 0);
628 t
= (port
<< AR8216_ATU_PORT_NUM_S
) | AR8216_ATU_OP_FLUSH_PORT
;
629 t
|= AR8216_ATU_ACTIVE
;
630 ar8xxx_write(priv
, AR8216_REG_ATU_FUNC0
, t
);
637 ar8216_read_port_status(struct ar8xxx_priv
*priv
, int port
)
639 return ar8xxx_read(priv
, AR8216_REG_PORT_STATUS(port
));
643 ar8216_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
650 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
651 if (priv
->vlan_tagged
& (1 << port
))
652 egress
= AR8216_OUT_ADD_VLAN
;
654 egress
= AR8216_OUT_STRIP_VLAN
;
655 ingress
= AR8216_IN_SECURE
;
658 egress
= AR8216_OUT_KEEP
;
659 ingress
= AR8216_IN_PORT_ONLY
;
662 if (chip_is_ar8216(priv
) && priv
->vlan
&& port
== AR8216_PORT_CPU
)
663 header
= AR8216_PORT_CTRL_HEADER
;
667 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
668 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
669 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
670 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
671 AR8216_PORT_CTRL_LEARN
| header
|
672 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
673 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
675 ar8xxx_rmw(priv
, AR8216_REG_PORT_VLAN(port
),
676 AR8216_PORT_VLAN_DEST_PORTS
| AR8216_PORT_VLAN_MODE
|
677 AR8216_PORT_VLAN_DEFAULT_ID
,
678 (members
<< AR8216_PORT_VLAN_DEST_PORTS_S
) |
679 (ingress
<< AR8216_PORT_VLAN_MODE_S
) |
680 (pvid
<< AR8216_PORT_VLAN_DEFAULT_ID_S
));
684 ar8216_hw_init(struct ar8xxx_priv
*priv
)
686 if (priv
->initialized
)
689 ar8xxx_phy_init(priv
);
691 priv
->initialized
= true;
696 ar8216_init_globals(struct ar8xxx_priv
*priv
)
698 /* standard atheros magic */
699 ar8xxx_write(priv
, 0x38, 0xc000050e);
701 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
702 AR8216_GCTRL_MTU
, 1518 + 8 + 2);
706 ar8216_init_port(struct ar8xxx_priv
*priv
, int port
)
708 /* Enable port learning and tx */
709 ar8xxx_write(priv
, AR8216_REG_PORT_CTRL(port
),
710 AR8216_PORT_CTRL_LEARN
|
711 (4 << AR8216_PORT_CTRL_STATE_S
));
713 ar8xxx_write(priv
, AR8216_REG_PORT_VLAN(port
), 0);
715 if (port
== AR8216_PORT_CPU
) {
716 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(port
),
717 AR8216_PORT_STATUS_LINK_UP
|
718 (ar8xxx_has_gige(priv
) ?
719 AR8216_PORT_SPEED_1000M
: AR8216_PORT_SPEED_100M
) |
720 AR8216_PORT_STATUS_TXMAC
|
721 AR8216_PORT_STATUS_RXMAC
|
722 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_RXFLOW
: 0) |
723 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_TXFLOW
: 0) |
724 AR8216_PORT_STATUS_DUPLEX
);
726 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(port
),
727 AR8216_PORT_STATUS_LINK_AUTO
);
732 ar8216_wait_atu_ready(struct ar8xxx_priv
*priv
, u16 r2
, u16 r1
)
736 while (ar8xxx_mii_read32(priv
, r2
, r1
) & AR8216_ATU_ACTIVE
&& --timeout
) {
742 pr_err("ar8216: timeout waiting for atu to become ready\n");
745 static void ar8216_get_arl_entry(struct ar8xxx_priv
*priv
,
746 struct arl_entry
*a
, u32
*status
, enum arl_op op
)
748 struct mii_bus
*bus
= priv
->mii_bus
;
750 u16 r1_func0
, r1_func1
, r1_func2
;
751 u32 t
, val0
, val1
, val2
;
754 split_addr(AR8216_REG_ATU_FUNC0
, &r1_func0
, &r2
, &page
);
757 r1_func1
= (AR8216_REG_ATU_FUNC1
>> 1) & 0x1e;
758 r1_func2
= (AR8216_REG_ATU_FUNC2
>> 1) & 0x1e;
761 case AR8XXX_ARL_INITIALIZE
:
762 /* all ATU registers are on the same page
763 * therefore set page only once
765 bus
->write(bus
, 0x18, 0, page
);
766 wait_for_page_switch();
768 ar8216_wait_atu_ready(priv
, r2
, r1_func0
);
770 ar8xxx_mii_write32(priv
, r2
, r1_func0
, AR8216_ATU_OP_GET_NEXT
);
771 ar8xxx_mii_write32(priv
, r2
, r1_func1
, 0);
772 ar8xxx_mii_write32(priv
, r2
, r1_func2
, 0);
774 case AR8XXX_ARL_GET_NEXT
:
775 t
= ar8xxx_mii_read32(priv
, r2
, r1_func0
);
776 t
|= AR8216_ATU_ACTIVE
;
777 ar8xxx_mii_write32(priv
, r2
, r1_func0
, t
);
778 ar8216_wait_atu_ready(priv
, r2
, r1_func0
);
780 val0
= ar8xxx_mii_read32(priv
, r2
, r1_func0
);
781 val1
= ar8xxx_mii_read32(priv
, r2
, r1_func1
);
782 val2
= ar8xxx_mii_read32(priv
, r2
, r1_func2
);
784 *status
= (val2
& AR8216_ATU_STATUS
) >> AR8216_ATU_STATUS_S
;
789 t
= AR8216_ATU_PORT0
;
790 while (!(val2
& t
) && ++i
< priv
->dev
.ports
)
794 a
->mac
[0] = (val0
& AR8216_ATU_ADDR5
) >> AR8216_ATU_ADDR5_S
;
795 a
->mac
[1] = (val0
& AR8216_ATU_ADDR4
) >> AR8216_ATU_ADDR4_S
;
796 a
->mac
[2] = (val1
& AR8216_ATU_ADDR3
) >> AR8216_ATU_ADDR3_S
;
797 a
->mac
[3] = (val1
& AR8216_ATU_ADDR2
) >> AR8216_ATU_ADDR2_S
;
798 a
->mac
[4] = (val1
& AR8216_ATU_ADDR1
) >> AR8216_ATU_ADDR1_S
;
799 a
->mac
[5] = (val1
& AR8216_ATU_ADDR0
) >> AR8216_ATU_ADDR0_S
;
805 ar8236_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
811 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
812 if (priv
->vlan_tagged
& (1 << port
))
813 egress
= AR8216_OUT_ADD_VLAN
;
815 egress
= AR8216_OUT_STRIP_VLAN
;
816 ingress
= AR8216_IN_SECURE
;
819 egress
= AR8216_OUT_KEEP
;
820 ingress
= AR8216_IN_PORT_ONLY
;
823 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
824 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
825 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
826 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
827 AR8216_PORT_CTRL_LEARN
|
828 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
829 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
831 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN(port
),
832 AR8236_PORT_VLAN_DEFAULT_ID
,
833 (pvid
<< AR8236_PORT_VLAN_DEFAULT_ID_S
));
835 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN2(port
),
836 AR8236_PORT_VLAN2_VLAN_MODE
|
837 AR8236_PORT_VLAN2_MEMBER
,
838 (ingress
<< AR8236_PORT_VLAN2_VLAN_MODE_S
) |
839 (members
<< AR8236_PORT_VLAN2_MEMBER_S
));
843 ar8236_init_globals(struct ar8xxx_priv
*priv
)
845 /* enable jumbo frames */
846 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
847 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
849 /* enable cpu port to receive arp frames */
850 ar8xxx_reg_set(priv
, AR8216_REG_ATU_CTRL
,
851 AR8236_ATU_CTRL_RES
);
853 /* enable cpu port to receive multicast and broadcast frames */
854 ar8xxx_reg_set(priv
, AR8216_REG_FLOOD_MASK
,
855 AR8236_FM_CPU_BROADCAST_EN
| AR8236_FM_CPU_BCAST_FWD_EN
);
857 /* Enable MIB counters */
858 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
859 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
864 ar8316_hw_init(struct ar8xxx_priv
*priv
)
868 val
= ar8xxx_read(priv
, AR8316_REG_POSTRIP
);
870 if (priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
871 if (priv
->port4_phy
) {
872 /* value taken from Ubiquiti RouterStation Pro */
874 pr_info("ar8316: Using port 4 as PHY\n");
877 pr_info("ar8316: Using port 4 as switch port\n");
879 } else if (priv
->phy
->interface
== PHY_INTERFACE_MODE_GMII
) {
880 /* value taken from AVM Fritz!Box 7390 sources */
883 /* no known value for phy interface */
884 pr_err("ar8316: unsupported mii mode: %d.\n",
885 priv
->phy
->interface
);
892 ar8xxx_write(priv
, AR8316_REG_POSTRIP
, newval
);
894 if (priv
->port4_phy
&&
895 priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
896 /* work around for phy4 rgmii mode */
897 ar8xxx_phy_dbg_write(priv
, 4, 0x12, 0x480c);
899 ar8xxx_phy_dbg_write(priv
, 4, 0x0, 0x824e);
901 ar8xxx_phy_dbg_write(priv
, 4, 0x5, 0x3d47);
905 ar8xxx_phy_init(priv
);
908 priv
->initialized
= true;
913 ar8316_init_globals(struct ar8xxx_priv
*priv
)
915 /* standard atheros magic */
916 ar8xxx_write(priv
, 0x38, 0xc000050e);
918 /* enable cpu port to receive multicast and broadcast frames */
919 ar8xxx_write(priv
, AR8216_REG_FLOOD_MASK
, 0x003f003f);
921 /* enable jumbo frames */
922 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
923 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
925 /* Enable MIB counters */
926 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
927 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
932 ar8xxx_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
933 struct switch_val
*val
)
935 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
936 priv
->vlan
= !!val
->value
.i
;
941 ar8xxx_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
942 struct switch_val
*val
)
944 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
945 val
->value
.i
= priv
->vlan
;
951 ar8xxx_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
953 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
955 /* make sure no invalid PVIDs get set */
957 if (vlan
< 0 || vlan
>= dev
->vlans
||
958 port
< 0 || port
>= AR8X16_MAX_PORTS
)
961 priv
->pvid
[port
] = vlan
;
966 ar8xxx_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
968 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
970 if (port
< 0 || port
>= AR8X16_MAX_PORTS
)
973 *vlan
= priv
->pvid
[port
];
978 ar8xxx_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
979 struct switch_val
*val
)
981 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
983 if (val
->port_vlan
>= AR8X16_MAX_VLANS
)
986 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
991 ar8xxx_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
992 struct switch_val
*val
)
994 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
995 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
1000 ar8xxx_sw_get_port_link(struct switch_dev
*dev
, int port
,
1001 struct switch_port_link
*link
)
1003 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1005 ar8216_read_port_link(priv
, port
, link
);
1010 ar8xxx_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1012 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1016 if (val
->port_vlan
>= AR8X16_MAX_VLANS
)
1019 ports
= priv
->vlan_table
[val
->port_vlan
];
1021 for (i
= 0; i
< dev
->ports
; i
++) {
1022 struct switch_port
*p
;
1024 if (!(ports
& (1 << i
)))
1027 p
= &val
->value
.ports
[val
->len
++];
1029 if (priv
->vlan_tagged
& (1 << i
))
1030 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
1038 ar8xxx_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1040 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1041 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1045 for (i
= 0; i
< val
->len
; i
++) {
1046 struct switch_port
*p
= &val
->value
.ports
[i
];
1048 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
1049 priv
->vlan_tagged
|= (1 << p
->id
);
1051 priv
->vlan_tagged
&= ~(1 << p
->id
);
1052 priv
->pvid
[p
->id
] = val
->port_vlan
;
1054 /* make sure that an untagged port does not
1055 * appear in other vlans */
1056 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1057 if (j
== val
->port_vlan
)
1059 priv
->vlan_table
[j
] &= ~(1 << p
->id
);
1069 ar8216_set_mirror_regs(struct ar8xxx_priv
*priv
)
1073 /* reset all mirror registers */
1074 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
1075 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
1076 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
1077 for (port
= 0; port
< AR8216_NUM_PORTS
; port
++) {
1078 ar8xxx_reg_clear(priv
, AR8216_REG_PORT_CTRL(port
),
1079 AR8216_PORT_CTRL_MIRROR_RX
);
1081 ar8xxx_reg_clear(priv
, AR8216_REG_PORT_CTRL(port
),
1082 AR8216_PORT_CTRL_MIRROR_TX
);
1085 /* now enable mirroring if necessary */
1086 if (priv
->source_port
>= AR8216_NUM_PORTS
||
1087 priv
->monitor_port
>= AR8216_NUM_PORTS
||
1088 priv
->source_port
== priv
->monitor_port
) {
1092 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
1093 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
1094 (priv
->monitor_port
<< AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
1096 if (priv
->mirror_rx
)
1097 ar8xxx_reg_set(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
1098 AR8216_PORT_CTRL_MIRROR_RX
);
1100 if (priv
->mirror_tx
)
1101 ar8xxx_reg_set(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
1102 AR8216_PORT_CTRL_MIRROR_TX
);
1106 ar8xxx_age_time_val(int age_time
)
1108 return (age_time
+ AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS
/ 2) /
1109 AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS
;
1113 ar8xxx_set_age_time(struct ar8xxx_priv
*priv
, int reg
)
1115 u32 age_time
= ar8xxx_age_time_val(priv
->arl_age_time
);
1116 ar8xxx_rmw(priv
, reg
, AR8216_ATU_CTRL_AGE_TIME
, age_time
<< AR8216_ATU_CTRL_AGE_TIME_S
);
1120 ar8xxx_sw_hw_apply(struct switch_dev
*dev
)
1122 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1123 const struct ar8xxx_chip
*chip
= priv
->chip
;
1124 u8 portmask
[AR8X16_MAX_PORTS
];
1127 mutex_lock(&priv
->reg_mutex
);
1128 /* flush all vlan translation unit entries */
1129 priv
->chip
->vtu_flush(priv
);
1131 memset(portmask
, 0, sizeof(portmask
));
1133 /* calculate the port destination masks and load vlans
1134 * into the vlan translation unit */
1135 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1136 u8 vp
= priv
->vlan_table
[j
];
1141 for (i
= 0; i
< dev
->ports
; i
++) {
1144 portmask
[i
] |= vp
& ~mask
;
1147 chip
->vtu_load_vlan(priv
, priv
->vlan_id
[j
],
1148 priv
->vlan_table
[j
]);
1152 * isolate all ports, but connect them to the cpu port */
1153 for (i
= 0; i
< dev
->ports
; i
++) {
1154 if (i
== AR8216_PORT_CPU
)
1157 portmask
[i
] = 1 << AR8216_PORT_CPU
;
1158 portmask
[AR8216_PORT_CPU
] |= (1 << i
);
1162 /* update the port destination mask registers and tag settings */
1163 for (i
= 0; i
< dev
->ports
; i
++) {
1164 chip
->setup_port(priv
, i
, portmask
[i
]);
1167 chip
->set_mirror_regs(priv
);
1170 if (chip
->reg_arl_ctrl
)
1171 ar8xxx_set_age_time(priv
, chip
->reg_arl_ctrl
);
1173 mutex_unlock(&priv
->reg_mutex
);
1178 ar8xxx_sw_reset_switch(struct switch_dev
*dev
)
1180 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1181 const struct ar8xxx_chip
*chip
= priv
->chip
;
1184 mutex_lock(&priv
->reg_mutex
);
1185 memset(&priv
->vlan
, 0, sizeof(struct ar8xxx_priv
) -
1186 offsetof(struct ar8xxx_priv
, vlan
));
1188 for (i
= 0; i
< AR8X16_MAX_VLANS
; i
++)
1189 priv
->vlan_id
[i
] = i
;
1191 /* Configure all ports */
1192 for (i
= 0; i
< dev
->ports
; i
++)
1193 chip
->init_port(priv
, i
);
1195 priv
->mirror_rx
= false;
1196 priv
->mirror_tx
= false;
1197 priv
->source_port
= 0;
1198 priv
->monitor_port
= 0;
1199 priv
->arl_age_time
= AR8XXX_DEFAULT_ARL_AGE_TIME
;
1201 chip
->init_globals(priv
);
1202 chip
->atu_flush(priv
);
1204 mutex_unlock(&priv
->reg_mutex
);
1206 return chip
->sw_hw_apply(dev
);
1210 ar8xxx_sw_set_reset_mibs(struct switch_dev
*dev
,
1211 const struct switch_attr
*attr
,
1212 struct switch_val
*val
)
1214 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1218 if (!ar8xxx_has_mib_counters(priv
))
1221 mutex_lock(&priv
->mib_lock
);
1223 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1224 sizeof(*priv
->mib_stats
);
1225 memset(priv
->mib_stats
, '\0', len
);
1226 ret
= ar8xxx_mib_flush(priv
);
1233 mutex_unlock(&priv
->mib_lock
);
1238 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev
*dev
,
1239 const struct switch_attr
*attr
,
1240 struct switch_val
*val
)
1242 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1244 mutex_lock(&priv
->reg_mutex
);
1245 priv
->mirror_rx
= !!val
->value
.i
;
1246 priv
->chip
->set_mirror_regs(priv
);
1247 mutex_unlock(&priv
->reg_mutex
);
1253 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev
*dev
,
1254 const struct switch_attr
*attr
,
1255 struct switch_val
*val
)
1257 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1258 val
->value
.i
= priv
->mirror_rx
;
1263 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev
*dev
,
1264 const struct switch_attr
*attr
,
1265 struct switch_val
*val
)
1267 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1269 mutex_lock(&priv
->reg_mutex
);
1270 priv
->mirror_tx
= !!val
->value
.i
;
1271 priv
->chip
->set_mirror_regs(priv
);
1272 mutex_unlock(&priv
->reg_mutex
);
1278 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev
*dev
,
1279 const struct switch_attr
*attr
,
1280 struct switch_val
*val
)
1282 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1283 val
->value
.i
= priv
->mirror_tx
;
1288 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev
*dev
,
1289 const struct switch_attr
*attr
,
1290 struct switch_val
*val
)
1292 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1294 mutex_lock(&priv
->reg_mutex
);
1295 priv
->monitor_port
= val
->value
.i
;
1296 priv
->chip
->set_mirror_regs(priv
);
1297 mutex_unlock(&priv
->reg_mutex
);
1303 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev
*dev
,
1304 const struct switch_attr
*attr
,
1305 struct switch_val
*val
)
1307 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1308 val
->value
.i
= priv
->monitor_port
;
1313 ar8xxx_sw_set_mirror_source_port(struct switch_dev
*dev
,
1314 const struct switch_attr
*attr
,
1315 struct switch_val
*val
)
1317 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1319 mutex_lock(&priv
->reg_mutex
);
1320 priv
->source_port
= val
->value
.i
;
1321 priv
->chip
->set_mirror_regs(priv
);
1322 mutex_unlock(&priv
->reg_mutex
);
1328 ar8xxx_sw_get_mirror_source_port(struct switch_dev
*dev
,
1329 const struct switch_attr
*attr
,
1330 struct switch_val
*val
)
1332 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1333 val
->value
.i
= priv
->source_port
;
1338 ar8xxx_sw_set_port_reset_mib(struct switch_dev
*dev
,
1339 const struct switch_attr
*attr
,
1340 struct switch_val
*val
)
1342 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1346 if (!ar8xxx_has_mib_counters(priv
))
1349 port
= val
->port_vlan
;
1350 if (port
>= dev
->ports
)
1353 mutex_lock(&priv
->mib_lock
);
1354 ret
= ar8xxx_mib_capture(priv
);
1358 ar8xxx_mib_fetch_port_stat(priv
, port
, true);
1363 mutex_unlock(&priv
->mib_lock
);
1368 ar8xxx_byte_to_str(char *buf
, int len
, u64 byte
)
1373 if (byte
>= 0x40000000) { /* 1 GiB */
1374 b
= byte
* 10 / 0x40000000;
1376 } else if (byte
>= 0x100000) { /* 1 MiB */
1377 b
= byte
* 10 / 0x100000;
1379 } else if (byte
>= 0x400) { /* 1 KiB */
1380 b
= byte
* 10 / 0x400;
1386 if (strcmp(unit
, "Byte"))
1387 snprintf(buf
, len
, "%lu.%lu %s", b
/ 10, b
% 10, unit
);
1389 snprintf(buf
, len
, "%lu %s", b
, unit
);
1393 ar8xxx_sw_get_port_mib(struct switch_dev
*dev
,
1394 const struct switch_attr
*attr
,
1395 struct switch_val
*val
)
1397 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1398 const struct ar8xxx_chip
*chip
= priv
->chip
;
1399 u64
*mib_stats
, mib_data
;
1402 char *buf
= priv
->buf
;
1404 const char *mib_name
;
1406 bool mib_stats_empty
= true;
1408 if (!ar8xxx_has_mib_counters(priv
))
1411 port
= val
->port_vlan
;
1412 if (port
>= dev
->ports
)
1415 mutex_lock(&priv
->mib_lock
);
1416 ret
= ar8xxx_mib_capture(priv
);
1420 ar8xxx_mib_fetch_port_stat(priv
, port
, false);
1422 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1425 mib_stats
= &priv
->mib_stats
[port
* chip
->num_mibs
];
1426 for (i
= 0; i
< chip
->num_mibs
; i
++) {
1427 mib_name
= chip
->mib_decs
[i
].name
;
1428 mib_data
= mib_stats
[i
];
1429 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1430 "%-12s: %llu\n", mib_name
, mib_data
);
1431 if ((!strcmp(mib_name
, "TxByte") ||
1432 !strcmp(mib_name
, "RxGoodByte")) &&
1434 ar8xxx_byte_to_str(buf1
, sizeof(buf1
), mib_data
);
1435 --len
; /* discard newline at the end of buf */
1436 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1439 if (mib_stats_empty
&& mib_data
)
1440 mib_stats_empty
= false;
1443 if (mib_stats_empty
)
1444 len
= snprintf(buf
, sizeof(priv
->buf
), "No MIB data");
1452 mutex_unlock(&priv
->mib_lock
);
1457 ar8xxx_sw_set_arl_age_time(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1458 struct switch_val
*val
)
1460 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1461 int age_time
= val
->value
.i
;
1467 age_time_val
= ar8xxx_age_time_val(age_time
);
1468 if (age_time_val
== 0 || age_time_val
> 0xffff)
1471 priv
->arl_age_time
= age_time
;
1476 ar8xxx_sw_get_arl_age_time(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1477 struct switch_val
*val
)
1479 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1480 val
->value
.i
= priv
->arl_age_time
;
1485 ar8xxx_sw_get_arl_table(struct switch_dev
*dev
,
1486 const struct switch_attr
*attr
,
1487 struct switch_val
*val
)
1489 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1490 struct mii_bus
*bus
= priv
->mii_bus
;
1491 const struct ar8xxx_chip
*chip
= priv
->chip
;
1492 char *buf
= priv
->arl_buf
;
1493 int i
, j
, k
, len
= 0;
1494 struct arl_entry
*a
, *a1
;
1497 if (!chip
->get_arl_entry
)
1500 mutex_lock(&priv
->reg_mutex
);
1501 mutex_lock(&bus
->mdio_lock
);
1503 chip
->get_arl_entry(priv
, NULL
, NULL
, AR8XXX_ARL_INITIALIZE
);
1505 for(i
= 0; i
< AR8XXX_NUM_ARL_RECORDS
; ++i
) {
1506 a
= &priv
->arl_table
[i
];
1508 chip
->get_arl_entry(priv
, a
, &status
, AR8XXX_ARL_GET_NEXT
);
1514 * ARL table can include multiple valid entries
1515 * per MAC, just with differing status codes
1517 for (j
= 0; j
< i
; ++j
) {
1518 a1
= &priv
->arl_table
[j
];
1519 if (a
->port
== a1
->port
&& !memcmp(a
->mac
, a1
->mac
, sizeof(a
->mac
)))
1524 mutex_unlock(&bus
->mdio_lock
);
1526 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1527 "address resolution table\n");
1529 if (i
== AR8XXX_NUM_ARL_RECORDS
)
1530 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1531 "Too many entries found, displaying the first %d only!\n",
1532 AR8XXX_NUM_ARL_RECORDS
);
1534 for (j
= 0; j
< priv
->dev
.ports
; ++j
) {
1535 for (k
= 0; k
< i
; ++k
) {
1536 a
= &priv
->arl_table
[k
];
1539 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1540 "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1542 a
->mac
[5], a
->mac
[4], a
->mac
[3],
1543 a
->mac
[2], a
->mac
[1], a
->mac
[0]);
1550 mutex_unlock(&priv
->reg_mutex
);
1556 ar8xxx_sw_set_flush_arl_table(struct switch_dev
*dev
,
1557 const struct switch_attr
*attr
,
1558 struct switch_val
*val
)
1560 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1563 mutex_lock(&priv
->reg_mutex
);
1564 ret
= priv
->chip
->atu_flush(priv
);
1565 mutex_unlock(&priv
->reg_mutex
);
1571 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev
*dev
,
1572 const struct switch_attr
*attr
,
1573 struct switch_val
*val
)
1575 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1578 port
= val
->port_vlan
;
1579 if (port
>= dev
->ports
)
1582 mutex_lock(&priv
->reg_mutex
);
1583 ret
= priv
->chip
->atu_flush_port(priv
, port
);
1584 mutex_unlock(&priv
->reg_mutex
);
1589 static const struct switch_attr ar8xxx_sw_attr_globals
[] = {
1591 .type
= SWITCH_TYPE_INT
,
1592 .name
= "enable_vlan",
1593 .description
= "Enable VLAN mode",
1594 .set
= ar8xxx_sw_set_vlan
,
1595 .get
= ar8xxx_sw_get_vlan
,
1599 .type
= SWITCH_TYPE_NOVAL
,
1600 .name
= "reset_mibs",
1601 .description
= "Reset all MIB counters",
1602 .set
= ar8xxx_sw_set_reset_mibs
,
1605 .type
= SWITCH_TYPE_INT
,
1606 .name
= "enable_mirror_rx",
1607 .description
= "Enable mirroring of RX packets",
1608 .set
= ar8xxx_sw_set_mirror_rx_enable
,
1609 .get
= ar8xxx_sw_get_mirror_rx_enable
,
1613 .type
= SWITCH_TYPE_INT
,
1614 .name
= "enable_mirror_tx",
1615 .description
= "Enable mirroring of TX packets",
1616 .set
= ar8xxx_sw_set_mirror_tx_enable
,
1617 .get
= ar8xxx_sw_get_mirror_tx_enable
,
1621 .type
= SWITCH_TYPE_INT
,
1622 .name
= "mirror_monitor_port",
1623 .description
= "Mirror monitor port",
1624 .set
= ar8xxx_sw_set_mirror_monitor_port
,
1625 .get
= ar8xxx_sw_get_mirror_monitor_port
,
1626 .max
= AR8216_NUM_PORTS
- 1
1629 .type
= SWITCH_TYPE_INT
,
1630 .name
= "mirror_source_port",
1631 .description
= "Mirror source port",
1632 .set
= ar8xxx_sw_set_mirror_source_port
,
1633 .get
= ar8xxx_sw_get_mirror_source_port
,
1634 .max
= AR8216_NUM_PORTS
- 1
1637 .type
= SWITCH_TYPE_STRING
,
1638 .name
= "arl_table",
1639 .description
= "Get ARL table",
1641 .get
= ar8xxx_sw_get_arl_table
,
1644 .type
= SWITCH_TYPE_NOVAL
,
1645 .name
= "flush_arl_table",
1646 .description
= "Flush ARL table",
1647 .set
= ar8xxx_sw_set_flush_arl_table
,
1651 const struct switch_attr ar8xxx_sw_attr_port
[] = {
1653 .type
= SWITCH_TYPE_NOVAL
,
1654 .name
= "reset_mib",
1655 .description
= "Reset single port MIB counters",
1656 .set
= ar8xxx_sw_set_port_reset_mib
,
1659 .type
= SWITCH_TYPE_STRING
,
1661 .description
= "Get port's MIB counters",
1663 .get
= ar8xxx_sw_get_port_mib
,
1666 .type
= SWITCH_TYPE_NOVAL
,
1667 .name
= "flush_arl_table",
1668 .description
= "Flush port's ARL table entries",
1669 .set
= ar8xxx_sw_set_flush_port_arl_table
,
1673 const struct switch_attr ar8xxx_sw_attr_vlan
[1] = {
1675 .type
= SWITCH_TYPE_INT
,
1677 .description
= "VLAN ID (0-4094)",
1678 .set
= ar8xxx_sw_set_vid
,
1679 .get
= ar8xxx_sw_get_vid
,
1684 static const struct switch_dev_ops ar8xxx_sw_ops
= {
1686 .attr
= ar8xxx_sw_attr_globals
,
1687 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_globals
),
1690 .attr
= ar8xxx_sw_attr_port
,
1691 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
1694 .attr
= ar8xxx_sw_attr_vlan
,
1695 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
1697 .get_port_pvid
= ar8xxx_sw_get_pvid
,
1698 .set_port_pvid
= ar8xxx_sw_set_pvid
,
1699 .get_vlan_ports
= ar8xxx_sw_get_ports
,
1700 .set_vlan_ports
= ar8xxx_sw_set_ports
,
1701 .apply_config
= ar8xxx_sw_hw_apply
,
1702 .reset_switch
= ar8xxx_sw_reset_switch
,
1703 .get_port_link
= ar8xxx_sw_get_port_link
,
1704 /* The following op is disabled as it hogs the CPU and degrades performance.
1705 An implementation has been attempted in 4d8a66d but reading MIB data is slow
1708 The high CPU load has been traced down to the ar8xxx_reg_wait() call in
1709 ar8xxx_mib_op(), which has to usleep_range() till the MIB busy flag set by
1710 the request to update the MIB counter is cleared. */
1712 .get_port_stats
= ar8xxx_sw_get_port_stats
,
1716 static const struct ar8xxx_chip ar8216_chip
= {
1717 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
1719 .reg_port_stats_start
= 0x19000,
1720 .reg_port_stats_length
= 0xa0,
1721 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
1723 .name
= "Atheros AR8216",
1724 .ports
= AR8216_NUM_PORTS
,
1725 .vlans
= AR8216_NUM_VLANS
,
1726 .swops
= &ar8xxx_sw_ops
,
1728 .hw_init
= ar8216_hw_init
,
1729 .init_globals
= ar8216_init_globals
,
1730 .init_port
= ar8216_init_port
,
1731 .setup_port
= ar8216_setup_port
,
1732 .read_port_status
= ar8216_read_port_status
,
1733 .atu_flush
= ar8216_atu_flush
,
1734 .atu_flush_port
= ar8216_atu_flush_port
,
1735 .vtu_flush
= ar8216_vtu_flush
,
1736 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
1737 .set_mirror_regs
= ar8216_set_mirror_regs
,
1738 .get_arl_entry
= ar8216_get_arl_entry
,
1739 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
1741 .num_mibs
= ARRAY_SIZE(ar8216_mibs
),
1742 .mib_decs
= ar8216_mibs
,
1743 .mib_func
= AR8216_REG_MIB_FUNC
1746 static const struct ar8xxx_chip ar8236_chip
= {
1747 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
1749 .reg_port_stats_start
= 0x20000,
1750 .reg_port_stats_length
= 0x100,
1751 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
1753 .name
= "Atheros AR8236",
1754 .ports
= AR8216_NUM_PORTS
,
1755 .vlans
= AR8216_NUM_VLANS
,
1756 .swops
= &ar8xxx_sw_ops
,
1758 .hw_init
= ar8216_hw_init
,
1759 .init_globals
= ar8236_init_globals
,
1760 .init_port
= ar8216_init_port
,
1761 .setup_port
= ar8236_setup_port
,
1762 .read_port_status
= ar8216_read_port_status
,
1763 .atu_flush
= ar8216_atu_flush
,
1764 .atu_flush_port
= ar8216_atu_flush_port
,
1765 .vtu_flush
= ar8216_vtu_flush
,
1766 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
1767 .set_mirror_regs
= ar8216_set_mirror_regs
,
1768 .get_arl_entry
= ar8216_get_arl_entry
,
1769 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
1771 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1772 .mib_decs
= ar8236_mibs
,
1773 .mib_func
= AR8216_REG_MIB_FUNC
1776 static const struct ar8xxx_chip ar8316_chip
= {
1777 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1779 .reg_port_stats_start
= 0x20000,
1780 .reg_port_stats_length
= 0x100,
1781 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
1783 .name
= "Atheros AR8316",
1784 .ports
= AR8216_NUM_PORTS
,
1785 .vlans
= AR8X16_MAX_VLANS
,
1786 .swops
= &ar8xxx_sw_ops
,
1788 .hw_init
= ar8316_hw_init
,
1789 .init_globals
= ar8316_init_globals
,
1790 .init_port
= ar8216_init_port
,
1791 .setup_port
= ar8216_setup_port
,
1792 .read_port_status
= ar8216_read_port_status
,
1793 .atu_flush
= ar8216_atu_flush
,
1794 .atu_flush_port
= ar8216_atu_flush_port
,
1795 .vtu_flush
= ar8216_vtu_flush
,
1796 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
1797 .set_mirror_regs
= ar8216_set_mirror_regs
,
1798 .get_arl_entry
= ar8216_get_arl_entry
,
1799 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
1801 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1802 .mib_decs
= ar8236_mibs
,
1803 .mib_func
= AR8216_REG_MIB_FUNC
1807 ar8xxx_id_chip(struct ar8xxx_priv
*priv
)
1813 val
= ar8xxx_read(priv
, AR8216_REG_CTRL
);
1817 id
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1818 for (i
= 0; i
< AR8X16_PROBE_RETRIES
; i
++) {
1821 val
= ar8xxx_read(priv
, AR8216_REG_CTRL
);
1825 t
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1830 priv
->chip_ver
= (id
& AR8216_CTRL_VERSION
) >> AR8216_CTRL_VERSION_S
;
1831 priv
->chip_rev
= (id
& AR8216_CTRL_REVISION
);
1833 switch (priv
->chip_ver
) {
1834 case AR8XXX_VER_AR8216
:
1835 priv
->chip
= &ar8216_chip
;
1837 case AR8XXX_VER_AR8236
:
1838 priv
->chip
= &ar8236_chip
;
1840 case AR8XXX_VER_AR8316
:
1841 priv
->chip
= &ar8316_chip
;
1843 case AR8XXX_VER_AR8327
:
1844 priv
->chip
= &ar8327_chip
;
1846 case AR8XXX_VER_AR8337
:
1847 priv
->chip
= &ar8337_chip
;
1850 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1851 priv
->chip_ver
, priv
->chip_rev
);
1860 ar8xxx_mib_work_func(struct work_struct
*work
)
1862 struct ar8xxx_priv
*priv
;
1865 priv
= container_of(work
, struct ar8xxx_priv
, mib_work
.work
);
1867 mutex_lock(&priv
->mib_lock
);
1869 err
= ar8xxx_mib_capture(priv
);
1873 ar8xxx_mib_fetch_port_stat(priv
, priv
->mib_next_port
, false);
1876 priv
->mib_next_port
++;
1877 if (priv
->mib_next_port
>= priv
->dev
.ports
)
1878 priv
->mib_next_port
= 0;
1880 mutex_unlock(&priv
->mib_lock
);
1881 schedule_delayed_work(&priv
->mib_work
,
1882 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
1886 ar8xxx_mib_init(struct ar8xxx_priv
*priv
)
1890 if (!ar8xxx_has_mib_counters(priv
))
1893 BUG_ON(!priv
->chip
->mib_decs
|| !priv
->chip
->num_mibs
);
1895 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1896 sizeof(*priv
->mib_stats
);
1897 priv
->mib_stats
= kzalloc(len
, GFP_KERNEL
);
1899 if (!priv
->mib_stats
)
1906 ar8xxx_mib_start(struct ar8xxx_priv
*priv
)
1908 if (!ar8xxx_has_mib_counters(priv
))
1911 schedule_delayed_work(&priv
->mib_work
,
1912 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
1916 ar8xxx_mib_stop(struct ar8xxx_priv
*priv
)
1918 if (!ar8xxx_has_mib_counters(priv
))
1921 cancel_delayed_work_sync(&priv
->mib_work
);
1924 static struct ar8xxx_priv
*
1927 struct ar8xxx_priv
*priv
;
1929 priv
= kzalloc(sizeof(struct ar8xxx_priv
), GFP_KERNEL
);
1933 mutex_init(&priv
->reg_mutex
);
1934 mutex_init(&priv
->mib_lock
);
1935 INIT_DELAYED_WORK(&priv
->mib_work
, ar8xxx_mib_work_func
);
1941 ar8xxx_free(struct ar8xxx_priv
*priv
)
1943 if (priv
->chip
&& priv
->chip
->cleanup
)
1944 priv
->chip
->cleanup(priv
);
1946 kfree(priv
->chip_data
);
1947 kfree(priv
->mib_stats
);
1952 ar8xxx_probe_switch(struct ar8xxx_priv
*priv
)
1954 const struct ar8xxx_chip
*chip
;
1955 struct switch_dev
*swdev
;
1958 ret
= ar8xxx_id_chip(priv
);
1965 swdev
->cpu_port
= AR8216_PORT_CPU
;
1966 swdev
->name
= chip
->name
;
1967 swdev
->vlans
= chip
->vlans
;
1968 swdev
->ports
= chip
->ports
;
1969 swdev
->ops
= chip
->swops
;
1971 ret
= ar8xxx_mib_init(priv
);
1979 ar8xxx_start(struct ar8xxx_priv
*priv
)
1985 ret
= priv
->chip
->hw_init(priv
);
1989 ret
= ar8xxx_sw_reset_switch(&priv
->dev
);
1995 ar8xxx_mib_start(priv
);
2001 ar8xxx_phy_config_init(struct phy_device
*phydev
)
2003 struct ar8xxx_priv
*priv
= phydev
->priv
;
2004 struct net_device
*dev
= phydev
->attached_dev
;
2010 if (priv
->chip
->config_at_probe
)
2011 return ar8xxx_phy_check_aneg(phydev
);
2015 if (phydev
->mdio
.addr
!= 0) {
2016 if (chip_is_ar8316(priv
)) {
2017 /* switch device has been initialized, reinit */
2018 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
2019 priv
->initialized
= false;
2020 priv
->port4_phy
= true;
2021 ar8316_hw_init(priv
);
2028 ret
= ar8xxx_start(priv
);
2032 /* VID fixup only needed on ar8216 */
2033 if (chip_is_ar8216(priv
)) {
2034 dev
->phy_ptr
= priv
;
2035 dev
->priv_flags
|= IFF_NO_IP_ALIGN
;
2036 dev
->eth_mangle_rx
= ar8216_mangle_rx
;
2037 dev
->eth_mangle_tx
= ar8216_mangle_tx
;
2044 ar8xxx_check_link_states(struct ar8xxx_priv
*priv
)
2046 bool link_new
, changed
= false;
2050 mutex_lock(&priv
->reg_mutex
);
2052 for (i
= 0; i
< priv
->dev
.ports
; i
++) {
2053 status
= priv
->chip
->read_port_status(priv
, i
);
2054 link_new
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
2055 if (link_new
== priv
->link_up
[i
])
2058 priv
->link_up
[i
] = link_new
;
2060 /* flush ARL entries for this port if it went down*/
2062 priv
->chip
->atu_flush_port(priv
, i
);
2063 dev_info(&priv
->phy
->mdio
.dev
, "Port %d is %s\n",
2064 i
, link_new
? "up" : "down");
2067 mutex_unlock(&priv
->reg_mutex
);
2073 ar8xxx_phy_read_status(struct phy_device
*phydev
)
2075 struct ar8xxx_priv
*priv
= phydev
->priv
;
2076 struct switch_port_link link
;
2078 /* check for switch port link changes */
2079 if (phydev
->state
== PHY_CHANGELINK
)
2080 ar8xxx_check_link_states(priv
);
2082 if (phydev
->mdio
.addr
!= 0)
2083 return genphy_read_status(phydev
);
2085 ar8216_read_port_link(priv
, phydev
->mdio
.addr
, &link
);
2086 phydev
->link
= !!link
.link
;
2090 switch (link
.speed
) {
2091 case SWITCH_PORT_SPEED_10
:
2092 phydev
->speed
= SPEED_10
;
2094 case SWITCH_PORT_SPEED_100
:
2095 phydev
->speed
= SPEED_100
;
2097 case SWITCH_PORT_SPEED_1000
:
2098 phydev
->speed
= SPEED_1000
;
2103 phydev
->duplex
= link
.duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
2105 phydev
->state
= PHY_RUNNING
;
2106 netif_carrier_on(phydev
->attached_dev
);
2107 phydev
->adjust_link(phydev
->attached_dev
);
2113 ar8xxx_phy_config_aneg(struct phy_device
*phydev
)
2115 if (phydev
->mdio
.addr
== 0)
2118 return genphy_config_aneg(phydev
);
2121 static const u32 ar8xxx_phy_ids
[] = {
2123 0x004dd034, /* AR8327 */
2124 0x004dd036, /* AR8337 */
2127 0x004dd043, /* AR8236 */
2131 ar8xxx_phy_match(u32 phy_id
)
2135 for (i
= 0; i
< ARRAY_SIZE(ar8xxx_phy_ids
); i
++)
2136 if (phy_id
== ar8xxx_phy_ids
[i
])
2143 ar8xxx_is_possible(struct mii_bus
*bus
)
2145 unsigned int i
, found_phys
= 0;
2147 for (i
= 0; i
< 5; i
++) {
2150 phy_id
= mdiobus_read(bus
, i
, MII_PHYSID1
) << 16;
2151 phy_id
|= mdiobus_read(bus
, i
, MII_PHYSID2
);
2152 if (ar8xxx_phy_match(phy_id
)) {
2154 } else if (phy_id
) {
2155 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2156 dev_name(&bus
->dev
), i
, phy_id
);
2159 return !!found_phys
;
2163 ar8xxx_phy_probe(struct phy_device
*phydev
)
2165 struct ar8xxx_priv
*priv
;
2166 struct switch_dev
*swdev
;
2169 /* skip PHYs at unused adresses */
2170 if (phydev
->mdio
.addr
!= 0 && phydev
->mdio
.addr
!= 4)
2173 if (!ar8xxx_is_possible(phydev
->mdio
.bus
))
2176 mutex_lock(&ar8xxx_dev_list_lock
);
2177 list_for_each_entry(priv
, &ar8xxx_dev_list
, list
)
2178 if (priv
->mii_bus
== phydev
->mdio
.bus
)
2181 priv
= ar8xxx_create();
2187 priv
->mii_bus
= phydev
->mdio
.bus
;
2189 ret
= ar8xxx_probe_switch(priv
);
2194 swdev
->alias
= dev_name(&priv
->mii_bus
->dev
);
2195 ret
= register_switch(swdev
, NULL
);
2199 pr_info("%s: %s rev. %u switch registered on %s\n",
2200 swdev
->devname
, swdev
->name
, priv
->chip_rev
,
2201 dev_name(&priv
->mii_bus
->dev
));
2203 list_add(&priv
->list
, &ar8xxx_dev_list
);
2208 if (phydev
->mdio
.addr
== 0) {
2209 if (ar8xxx_has_gige(priv
)) {
2210 phydev
->supported
= SUPPORTED_1000baseT_Full
;
2211 phydev
->advertising
= ADVERTISED_1000baseT_Full
;
2213 phydev
->supported
= SUPPORTED_100baseT_Full
;
2214 phydev
->advertising
= ADVERTISED_100baseT_Full
;
2217 if (priv
->chip
->config_at_probe
) {
2220 ret
= ar8xxx_start(priv
);
2222 goto err_unregister_switch
;
2225 if (ar8xxx_has_gige(priv
)) {
2226 phydev
->supported
|= SUPPORTED_1000baseT_Full
;
2227 phydev
->advertising
|= ADVERTISED_1000baseT_Full
;
2231 phydev
->priv
= priv
;
2233 mutex_unlock(&ar8xxx_dev_list_lock
);
2237 err_unregister_switch
:
2238 if (--priv
->use_count
)
2241 unregister_switch(&priv
->dev
);
2246 mutex_unlock(&ar8xxx_dev_list_lock
);
2251 ar8xxx_phy_detach(struct phy_device
*phydev
)
2253 struct net_device
*dev
= phydev
->attached_dev
;
2258 dev
->phy_ptr
= NULL
;
2259 dev
->priv_flags
&= ~IFF_NO_IP_ALIGN
;
2260 dev
->eth_mangle_rx
= NULL
;
2261 dev
->eth_mangle_tx
= NULL
;
2265 ar8xxx_phy_remove(struct phy_device
*phydev
)
2267 struct ar8xxx_priv
*priv
= phydev
->priv
;
2272 phydev
->priv
= NULL
;
2274 mutex_lock(&ar8xxx_dev_list_lock
);
2276 if (--priv
->use_count
> 0) {
2277 mutex_unlock(&ar8xxx_dev_list_lock
);
2281 list_del(&priv
->list
);
2282 mutex_unlock(&ar8xxx_dev_list_lock
);
2284 unregister_switch(&priv
->dev
);
2285 ar8xxx_mib_stop(priv
);
2290 ar8xxx_phy_soft_reset(struct phy_device
*phydev
)
2292 /* we don't need an extra reset */
2296 static struct phy_driver ar8xxx_phy_driver
[] = {
2298 .phy_id
= 0x004d0000,
2299 .name
= "Atheros AR8216/AR8236/AR8316",
2300 .phy_id_mask
= 0xffff0000,
2301 .features
= PHY_BASIC_FEATURES
,
2302 .probe
= ar8xxx_phy_probe
,
2303 .remove
= ar8xxx_phy_remove
,
2304 .detach
= ar8xxx_phy_detach
,
2305 .config_init
= ar8xxx_phy_config_init
,
2306 .config_aneg
= ar8xxx_phy_config_aneg
,
2307 .read_status
= ar8xxx_phy_read_status
,
2308 .soft_reset
= ar8xxx_phy_soft_reset
,
2312 module_phy_driver(ar8xxx_phy_driver
);
2313 MODULE_LICENSE("GPL");