2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
38 /* size of the vlan table */
39 #define AR8X16_MAX_VLANS 128
40 #define AR8X16_PROBE_RETRIES 10
41 #define AR8X16_MAX_PORTS 8
43 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
47 #define AR8XXX_CAP_GIGE BIT(0)
48 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
51 AR8XXX_VER_AR8216
= 0x01,
52 AR8XXX_VER_AR8236
= 0x03,
53 AR8XXX_VER_AR8316
= 0x10,
54 AR8XXX_VER_AR8327
= 0x12,
57 struct ar8xxx_mib_desc
{
66 int (*hw_init
)(struct ar8216_priv
*priv
);
67 void (*init_globals
)(struct ar8216_priv
*priv
);
68 void (*init_port
)(struct ar8216_priv
*priv
, int port
);
69 void (*setup_port
)(struct ar8216_priv
*priv
, int port
, u32 egress
,
70 u32 ingress
, u32 members
, u32 pvid
);
71 u32 (*read_port_status
)(struct ar8216_priv
*priv
, int port
);
72 int (*atu_flush
)(struct ar8216_priv
*priv
);
73 void (*vtu_flush
)(struct ar8216_priv
*priv
);
74 void (*vtu_load_vlan
)(struct ar8216_priv
*priv
, u32 vid
, u32 port_mask
);
76 const struct ar8xxx_mib_desc
*mib_decs
;
81 struct switch_dev dev
;
82 struct phy_device
*phy
;
83 u32 (*read
)(struct ar8216_priv
*priv
, int reg
);
84 void (*write
)(struct ar8216_priv
*priv
, int reg
, u32 val
);
85 const struct net_device_ops
*ndo_old
;
86 struct net_device_ops ndo
;
87 struct mutex reg_mutex
;
90 const struct ar8xxx_chip
*chip
;
98 struct mutex mib_lock
;
99 struct delayed_work mib_work
;
103 /* all fields below are cleared on reset */
105 u16 vlan_id
[AR8X16_MAX_VLANS
];
106 u8 vlan_table
[AR8X16_MAX_VLANS
];
108 u16 pvid
[AR8X16_MAX_PORTS
];
111 #define MIB_DESC(_s , _o, _n) \
118 static const struct ar8xxx_mib_desc ar8216_mibs
[] = {
119 MIB_DESC(1, AR8216_STATS_RXBROAD
, "RxBroad"),
120 MIB_DESC(1, AR8216_STATS_RXPAUSE
, "RxPause"),
121 MIB_DESC(1, AR8216_STATS_RXMULTI
, "RxMulti"),
122 MIB_DESC(1, AR8216_STATS_RXFCSERR
, "RxFcsErr"),
123 MIB_DESC(1, AR8216_STATS_RXALIGNERR
, "RxAlignErr"),
124 MIB_DESC(1, AR8216_STATS_RXRUNT
, "RxRunt"),
125 MIB_DESC(1, AR8216_STATS_RXFRAGMENT
, "RxFragment"),
126 MIB_DESC(1, AR8216_STATS_RX64BYTE
, "Rx64Byte"),
127 MIB_DESC(1, AR8216_STATS_RX128BYTE
, "Rx128Byte"),
128 MIB_DESC(1, AR8216_STATS_RX256BYTE
, "Rx256Byte"),
129 MIB_DESC(1, AR8216_STATS_RX512BYTE
, "Rx512Byte"),
130 MIB_DESC(1, AR8216_STATS_RX1024BYTE
, "Rx1024Byte"),
131 MIB_DESC(1, AR8216_STATS_RXMAXBYTE
, "RxMaxByte"),
132 MIB_DESC(1, AR8216_STATS_RXTOOLONG
, "RxTooLong"),
133 MIB_DESC(2, AR8216_STATS_RXGOODBYTE
, "RxGoodByte"),
134 MIB_DESC(2, AR8216_STATS_RXBADBYTE
, "RxBadByte"),
135 MIB_DESC(1, AR8216_STATS_RXOVERFLOW
, "RxOverFlow"),
136 MIB_DESC(1, AR8216_STATS_FILTERED
, "Filtered"),
137 MIB_DESC(1, AR8216_STATS_TXBROAD
, "TxBroad"),
138 MIB_DESC(1, AR8216_STATS_TXPAUSE
, "TxPause"),
139 MIB_DESC(1, AR8216_STATS_TXMULTI
, "TxMulti"),
140 MIB_DESC(1, AR8216_STATS_TXUNDERRUN
, "TxUnderRun"),
141 MIB_DESC(1, AR8216_STATS_TX64BYTE
, "Tx64Byte"),
142 MIB_DESC(1, AR8216_STATS_TX128BYTE
, "Tx128Byte"),
143 MIB_DESC(1, AR8216_STATS_TX256BYTE
, "Tx256Byte"),
144 MIB_DESC(1, AR8216_STATS_TX512BYTE
, "Tx512Byte"),
145 MIB_DESC(1, AR8216_STATS_TX1024BYTE
, "Tx1024Byte"),
146 MIB_DESC(1, AR8216_STATS_TXMAXBYTE
, "TxMaxByte"),
147 MIB_DESC(1, AR8216_STATS_TXOVERSIZE
, "TxOverSize"),
148 MIB_DESC(2, AR8216_STATS_TXBYTE
, "TxByte"),
149 MIB_DESC(1, AR8216_STATS_TXCOLLISION
, "TxCollision"),
150 MIB_DESC(1, AR8216_STATS_TXABORTCOL
, "TxAbortCol"),
151 MIB_DESC(1, AR8216_STATS_TXMULTICOL
, "TxMultiCol"),
152 MIB_DESC(1, AR8216_STATS_TXSINGLECOL
, "TxSingleCol"),
153 MIB_DESC(1, AR8216_STATS_TXEXCDEFER
, "TxExcDefer"),
154 MIB_DESC(1, AR8216_STATS_TXDEFER
, "TxDefer"),
155 MIB_DESC(1, AR8216_STATS_TXLATECOL
, "TxLateCol"),
158 static const struct ar8xxx_mib_desc ar8236_mibs
[] = {
159 MIB_DESC(1, AR8236_STATS_RXBROAD
, "RxBroad"),
160 MIB_DESC(1, AR8236_STATS_RXPAUSE
, "RxPause"),
161 MIB_DESC(1, AR8236_STATS_RXMULTI
, "RxMulti"),
162 MIB_DESC(1, AR8236_STATS_RXFCSERR
, "RxFcsErr"),
163 MIB_DESC(1, AR8236_STATS_RXALIGNERR
, "RxAlignErr"),
164 MIB_DESC(1, AR8236_STATS_RXRUNT
, "RxRunt"),
165 MIB_DESC(1, AR8236_STATS_RXFRAGMENT
, "RxFragment"),
166 MIB_DESC(1, AR8236_STATS_RX64BYTE
, "Rx64Byte"),
167 MIB_DESC(1, AR8236_STATS_RX128BYTE
, "Rx128Byte"),
168 MIB_DESC(1, AR8236_STATS_RX256BYTE
, "Rx256Byte"),
169 MIB_DESC(1, AR8236_STATS_RX512BYTE
, "Rx512Byte"),
170 MIB_DESC(1, AR8236_STATS_RX1024BYTE
, "Rx1024Byte"),
171 MIB_DESC(1, AR8236_STATS_RX1518BYTE
, "Rx1518Byte"),
172 MIB_DESC(1, AR8236_STATS_RXMAXBYTE
, "RxMaxByte"),
173 MIB_DESC(1, AR8236_STATS_RXTOOLONG
, "RxTooLong"),
174 MIB_DESC(2, AR8236_STATS_RXGOODBYTE
, "RxGoodByte"),
175 MIB_DESC(2, AR8236_STATS_RXBADBYTE
, "RxBadByte"),
176 MIB_DESC(1, AR8236_STATS_RXOVERFLOW
, "RxOverFlow"),
177 MIB_DESC(1, AR8236_STATS_FILTERED
, "Filtered"),
178 MIB_DESC(1, AR8236_STATS_TXBROAD
, "TxBroad"),
179 MIB_DESC(1, AR8236_STATS_TXPAUSE
, "TxPause"),
180 MIB_DESC(1, AR8236_STATS_TXMULTI
, "TxMulti"),
181 MIB_DESC(1, AR8236_STATS_TXUNDERRUN
, "TxUnderRun"),
182 MIB_DESC(1, AR8236_STATS_TX64BYTE
, "Tx64Byte"),
183 MIB_DESC(1, AR8236_STATS_TX128BYTE
, "Tx128Byte"),
184 MIB_DESC(1, AR8236_STATS_TX256BYTE
, "Tx256Byte"),
185 MIB_DESC(1, AR8236_STATS_TX512BYTE
, "Tx512Byte"),
186 MIB_DESC(1, AR8236_STATS_TX1024BYTE
, "Tx1024Byte"),
187 MIB_DESC(1, AR8236_STATS_TX1518BYTE
, "Tx1518Byte"),
188 MIB_DESC(1, AR8236_STATS_TXMAXBYTE
, "TxMaxByte"),
189 MIB_DESC(1, AR8236_STATS_TXOVERSIZE
, "TxOverSize"),
190 MIB_DESC(2, AR8236_STATS_TXBYTE
, "TxByte"),
191 MIB_DESC(1, AR8236_STATS_TXCOLLISION
, "TxCollision"),
192 MIB_DESC(1, AR8236_STATS_TXABORTCOL
, "TxAbortCol"),
193 MIB_DESC(1, AR8236_STATS_TXMULTICOL
, "TxMultiCol"),
194 MIB_DESC(1, AR8236_STATS_TXSINGLECOL
, "TxSingleCol"),
195 MIB_DESC(1, AR8236_STATS_TXEXCDEFER
, "TxExcDefer"),
196 MIB_DESC(1, AR8236_STATS_TXDEFER
, "TxDefer"),
197 MIB_DESC(1, AR8236_STATS_TXLATECOL
, "TxLateCol"),
200 #define to_ar8216(_dev) container_of(_dev, struct ar8216_priv, dev)
202 static inline bool ar8xxx_has_gige(struct ar8216_priv
*priv
)
204 return priv
->chip
->caps
& AR8XXX_CAP_GIGE
;
207 static inline bool ar8xxx_has_mib_counters(struct ar8216_priv
*priv
)
209 return priv
->chip
->caps
& AR8XXX_CAP_MIB_COUNTERS
;
212 static inline bool chip_is_ar8216(struct ar8216_priv
*priv
)
214 return priv
->chip_ver
== AR8XXX_VER_AR8216
;
217 static inline bool chip_is_ar8236(struct ar8216_priv
*priv
)
219 return priv
->chip_ver
== AR8XXX_VER_AR8236
;
222 static inline bool chip_is_ar8316(struct ar8216_priv
*priv
)
224 return priv
->chip_ver
== AR8XXX_VER_AR8316
;
227 static inline bool chip_is_ar8327(struct ar8216_priv
*priv
)
229 return priv
->chip_ver
== AR8XXX_VER_AR8327
;
233 split_addr(u32 regaddr
, u16
*r1
, u16
*r2
, u16
*page
)
236 *r1
= regaddr
& 0x1e;
242 *page
= regaddr
& 0x1ff;
246 ar8216_mii_read(struct ar8216_priv
*priv
, int reg
)
248 struct phy_device
*phy
= priv
->phy
;
249 struct mii_bus
*bus
= phy
->bus
;
253 split_addr((u32
) reg
, &r1
, &r2
, &page
);
255 mutex_lock(&bus
->mdio_lock
);
257 bus
->write(bus
, 0x18, 0, page
);
258 usleep_range(1000, 2000); /* wait for the page switch to propagate */
259 lo
= bus
->read(bus
, 0x10 | r2
, r1
);
260 hi
= bus
->read(bus
, 0x10 | r2
, r1
+ 1);
262 mutex_unlock(&bus
->mdio_lock
);
264 return (hi
<< 16) | lo
;
268 ar8216_mii_write(struct ar8216_priv
*priv
, int reg
, u32 val
)
270 struct phy_device
*phy
= priv
->phy
;
271 struct mii_bus
*bus
= phy
->bus
;
275 split_addr((u32
) reg
, &r1
, &r2
, &r3
);
277 hi
= (u16
) (val
>> 16);
279 mutex_lock(&bus
->mdio_lock
);
281 bus
->write(bus
, 0x18, 0, r3
);
282 usleep_range(1000, 2000); /* wait for the page switch to propagate */
283 if (priv
->mii_lo_first
) {
284 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
285 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
287 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
288 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
291 mutex_unlock(&bus
->mdio_lock
);
295 ar8216_phy_dbg_write(struct ar8216_priv
*priv
, int phy_addr
,
296 u16 dbg_addr
, u16 dbg_data
)
298 struct mii_bus
*bus
= priv
->phy
->bus
;
300 mutex_lock(&bus
->mdio_lock
);
301 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
302 bus
->write(bus
, phy_addr
, MII_ATH_DBG_DATA
, dbg_data
);
303 mutex_unlock(&bus
->mdio_lock
);
307 ar8216_phy_mmd_write(struct ar8216_priv
*priv
, int phy_addr
, u16 addr
, u16 data
)
309 struct mii_bus
*bus
= priv
->phy
->bus
;
311 mutex_lock(&bus
->mdio_lock
);
312 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
313 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, data
);
314 mutex_unlock(&bus
->mdio_lock
);
318 ar8216_rmw(struct ar8216_priv
*priv
, int reg
, u32 mask
, u32 val
)
322 lockdep_assert_held(&priv
->reg_mutex
);
324 v
= priv
->read(priv
, reg
);
327 priv
->write(priv
, reg
, v
);
333 ar8216_reg_set(struct ar8216_priv
*priv
, int reg
, u32 val
)
337 lockdep_assert_held(&priv
->reg_mutex
);
339 v
= priv
->read(priv
, reg
);
341 priv
->write(priv
, reg
, v
);
345 ar8216_reg_wait(struct ar8216_priv
*priv
, u32 reg
, u32 mask
, u32 val
,
350 for (i
= 0; i
< timeout
; i
++) {
353 t
= priv
->read(priv
, reg
);
354 if ((t
& mask
) == val
)
357 usleep_range(1000, 2000);
364 ar8216_mib_op(struct ar8216_priv
*priv
, u32 op
)
369 lockdep_assert_held(&priv
->mib_lock
);
371 if (chip_is_ar8327(priv
))
372 mib_func
= AR8327_REG_MIB_FUNC
;
374 mib_func
= AR8216_REG_MIB_FUNC
;
376 mutex_lock(&priv
->reg_mutex
);
377 /* Capture the hardware statistics for all ports */
378 ar8216_rmw(priv
, mib_func
, AR8216_MIB_FUNC
, (op
<< AR8216_MIB_FUNC_S
));
379 mutex_unlock(&priv
->reg_mutex
);
381 /* Wait for the capturing to complete. */
382 ret
= ar8216_reg_wait(priv
, mib_func
, AR8216_MIB_BUSY
, 0, 10);
393 ar8216_mib_capture(struct ar8216_priv
*priv
)
395 return ar8216_mib_op(priv
, AR8216_MIB_FUNC_CAPTURE
);
399 ar8216_mib_flush(struct ar8216_priv
*priv
)
401 return ar8216_mib_op(priv
, AR8216_MIB_FUNC_FLUSH
);
405 ar8216_mib_fetch_port_stat(struct ar8216_priv
*priv
, int port
, bool flush
)
411 WARN_ON(port
>= priv
->dev
.ports
);
413 lockdep_assert_held(&priv
->mib_lock
);
415 if (chip_is_ar8327(priv
))
416 base
= AR8327_REG_PORT_STATS_BASE(port
);
417 else if (chip_is_ar8236(priv
) ||
418 chip_is_ar8316(priv
))
419 base
= AR8236_REG_PORT_STATS_BASE(port
);
421 base
= AR8216_REG_PORT_STATS_BASE(port
);
423 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
424 for (i
= 0; i
< priv
->chip
->num_mibs
; i
++) {
425 const struct ar8xxx_mib_desc
*mib
;
428 mib
= &priv
->chip
->mib_decs
[i
];
429 t
= priv
->read(priv
, base
+ mib
->offset
);
430 if (mib
->size
== 2) {
433 hi
= priv
->read(priv
, base
+ mib
->offset
+ 4);
445 ar8216_read_port_link(struct ar8216_priv
*priv
, int port
,
446 struct switch_port_link
*link
)
451 memset(link
, '\0', sizeof(*link
));
453 status
= priv
->chip
->read_port_status(priv
, port
);
455 link
->aneg
= !!(status
& AR8216_PORT_STATUS_LINK_AUTO
);
457 link
->link
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
464 link
->duplex
= !!(status
& AR8216_PORT_STATUS_DUPLEX
);
465 link
->tx_flow
= !!(status
& AR8216_PORT_STATUS_TXFLOW
);
466 link
->rx_flow
= !!(status
& AR8216_PORT_STATUS_RXFLOW
);
468 speed
= (status
& AR8216_PORT_STATUS_SPEED
) >>
469 AR8216_PORT_STATUS_SPEED_S
;
472 case AR8216_PORT_SPEED_10M
:
473 link
->speed
= SWITCH_PORT_SPEED_10
;
475 case AR8216_PORT_SPEED_100M
:
476 link
->speed
= SWITCH_PORT_SPEED_100
;
478 case AR8216_PORT_SPEED_1000M
:
479 link
->speed
= SWITCH_PORT_SPEED_1000
;
482 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
487 static struct sk_buff
*
488 ar8216_mangle_tx(struct net_device
*dev
, struct sk_buff
*skb
)
490 struct ar8216_priv
*priv
= dev
->phy_ptr
;
499 if (unlikely(skb_headroom(skb
) < 2)) {
500 if (pskb_expand_head(skb
, 2, 0, GFP_ATOMIC
) < 0)
504 buf
= skb_push(skb
, 2);
512 dev_kfree_skb_any(skb
);
517 ar8216_mangle_rx(struct net_device
*dev
, struct sk_buff
*skb
)
519 struct ar8216_priv
*priv
;
527 /* don't strip the header if vlan mode is disabled */
531 /* strip header, get vlan id */
535 /* check for vlan header presence */
536 if ((buf
[12 + 2] != 0x81) || (buf
[13 + 2] != 0x00))
541 /* no need to fix up packets coming from a tagged source */
542 if (priv
->vlan_tagged
& (1 << port
))
545 /* lookup port vid from local table, the switch passes an invalid vlan id */
546 vlan
= priv
->vlan_id
[priv
->pvid
[port
]];
549 buf
[14 + 2] |= vlan
>> 8;
550 buf
[15 + 2] = vlan
& 0xff;
554 ar8216_wait_bit(struct ar8216_priv
*priv
, int reg
, u32 mask
, u32 val
)
560 t
= priv
->read(priv
, reg
);
561 if ((t
& mask
) == val
)
570 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
571 (unsigned int) reg
, t
, mask
, val
);
576 ar8216_vtu_op(struct ar8216_priv
*priv
, u32 op
, u32 val
)
578 if (ar8216_wait_bit(priv
, AR8216_REG_VTU
, AR8216_VTU_ACTIVE
, 0))
580 if ((op
& AR8216_VTU_OP
) == AR8216_VTU_OP_LOAD
) {
581 val
&= AR8216_VTUDATA_MEMBER
;
582 val
|= AR8216_VTUDATA_VALID
;
583 priv
->write(priv
, AR8216_REG_VTU_DATA
, val
);
585 op
|= AR8216_VTU_ACTIVE
;
586 priv
->write(priv
, AR8216_REG_VTU
, op
);
590 ar8216_vtu_flush(struct ar8216_priv
*priv
)
592 ar8216_vtu_op(priv
, AR8216_VTU_OP_FLUSH
, 0);
596 ar8216_vtu_load_vlan(struct ar8216_priv
*priv
, u32 vid
, u32 port_mask
)
600 op
= AR8216_VTU_OP_LOAD
| (vid
<< AR8216_VTU_VID_S
);
601 ar8216_vtu_op(priv
, op
, port_mask
);
605 ar8216_atu_flush(struct ar8216_priv
*priv
)
609 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU
, AR8216_ATU_ACTIVE
, 0);
611 priv
->write(priv
, AR8216_REG_ATU
, AR8216_ATU_OP_FLUSH
);
617 ar8216_read_port_status(struct ar8216_priv
*priv
, int port
)
619 return priv
->read(priv
, AR8216_REG_PORT_STATUS(port
));
623 ar8216_setup_port(struct ar8216_priv
*priv
, int port
, u32 egress
, u32 ingress
,
624 u32 members
, u32 pvid
)
628 if (chip_is_ar8216(priv
) && priv
->vlan
&& port
== AR8216_PORT_CPU
)
629 header
= AR8216_PORT_CTRL_HEADER
;
633 ar8216_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
634 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
635 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
636 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
637 AR8216_PORT_CTRL_LEARN
| header
|
638 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
639 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
641 ar8216_rmw(priv
, AR8216_REG_PORT_VLAN(port
),
642 AR8216_PORT_VLAN_DEST_PORTS
| AR8216_PORT_VLAN_MODE
|
643 AR8216_PORT_VLAN_DEFAULT_ID
,
644 (members
<< AR8216_PORT_VLAN_DEST_PORTS_S
) |
645 (ingress
<< AR8216_PORT_VLAN_MODE_S
) |
646 (pvid
<< AR8216_PORT_VLAN_DEFAULT_ID_S
));
650 ar8216_hw_init(struct ar8216_priv
*priv
)
656 ar8216_init_globals(struct ar8216_priv
*priv
)
658 /* standard atheros magic */
659 priv
->write(priv
, 0x38, 0xc000050e);
661 ar8216_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
662 AR8216_GCTRL_MTU
, 1518 + 8 + 2);
666 ar8216_init_port(struct ar8216_priv
*priv
, int port
)
668 /* Enable port learning and tx */
669 priv
->write(priv
, AR8216_REG_PORT_CTRL(port
),
670 AR8216_PORT_CTRL_LEARN
|
671 (4 << AR8216_PORT_CTRL_STATE_S
));
673 priv
->write(priv
, AR8216_REG_PORT_VLAN(port
), 0);
675 if (port
== AR8216_PORT_CPU
) {
676 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
677 AR8216_PORT_STATUS_LINK_UP
|
678 (ar8xxx_has_gige(priv
) ?
679 AR8216_PORT_SPEED_1000M
: AR8216_PORT_SPEED_100M
) |
680 AR8216_PORT_STATUS_TXMAC
|
681 AR8216_PORT_STATUS_RXMAC
|
682 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_RXFLOW
: 0) |
683 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_TXFLOW
: 0) |
684 AR8216_PORT_STATUS_DUPLEX
);
686 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
687 AR8216_PORT_STATUS_LINK_AUTO
);
691 static const struct ar8xxx_chip ar8216_chip
= {
692 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
694 .hw_init
= ar8216_hw_init
,
695 .init_globals
= ar8216_init_globals
,
696 .init_port
= ar8216_init_port
,
697 .setup_port
= ar8216_setup_port
,
698 .read_port_status
= ar8216_read_port_status
,
699 .atu_flush
= ar8216_atu_flush
,
700 .vtu_flush
= ar8216_vtu_flush
,
701 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
703 .num_mibs
= ARRAY_SIZE(ar8216_mibs
),
704 .mib_decs
= ar8216_mibs
,
708 ar8236_setup_port(struct ar8216_priv
*priv
, int port
, u32 egress
, u32 ingress
,
709 u32 members
, u32 pvid
)
711 ar8216_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
712 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
713 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
714 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
715 AR8216_PORT_CTRL_LEARN
|
716 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
717 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
719 ar8216_rmw(priv
, AR8236_REG_PORT_VLAN(port
),
720 AR8236_PORT_VLAN_DEFAULT_ID
,
721 (pvid
<< AR8236_PORT_VLAN_DEFAULT_ID_S
));
723 ar8216_rmw(priv
, AR8236_REG_PORT_VLAN2(port
),
724 AR8236_PORT_VLAN2_VLAN_MODE
|
725 AR8236_PORT_VLAN2_MEMBER
,
726 (ingress
<< AR8236_PORT_VLAN2_VLAN_MODE_S
) |
727 (members
<< AR8236_PORT_VLAN2_MEMBER_S
));
731 ar8236_hw_init(struct ar8216_priv
*priv
)
736 if (priv
->initialized
)
739 /* Initialize the PHYs */
740 bus
= priv
->phy
->bus
;
741 for (i
= 0; i
< 5; i
++) {
742 mdiobus_write(bus
, i
, MII_ADVERTISE
,
743 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
|
744 ADVERTISE_PAUSE_ASYM
);
745 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
749 priv
->initialized
= true;
754 ar8236_init_globals(struct ar8216_priv
*priv
)
756 /* enable jumbo frames */
757 ar8216_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
758 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
760 /* Enable MIB counters */
761 ar8216_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
762 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
766 static const struct ar8xxx_chip ar8236_chip
= {
767 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
768 .hw_init
= ar8236_hw_init
,
769 .init_globals
= ar8236_init_globals
,
770 .init_port
= ar8216_init_port
,
771 .setup_port
= ar8236_setup_port
,
772 .read_port_status
= ar8216_read_port_status
,
773 .atu_flush
= ar8216_atu_flush
,
774 .vtu_flush
= ar8216_vtu_flush
,
775 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
777 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
778 .mib_decs
= ar8236_mibs
,
782 ar8316_hw_init(struct ar8216_priv
*priv
)
788 val
= priv
->read(priv
, 0x8);
790 if (priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
791 if (priv
->port4_phy
) {
792 /* value taken from Ubiquiti RouterStation Pro */
794 printk(KERN_INFO
"ar8316: Using port 4 as PHY\n");
797 printk(KERN_INFO
"ar8316: Using port 4 as switch port\n");
799 } else if (priv
->phy
->interface
== PHY_INTERFACE_MODE_GMII
) {
800 /* value taken from AVM Fritz!Box 7390 sources */
803 /* no known value for phy interface */
804 printk(KERN_ERR
"ar8316: unsupported mii mode: %d.\n",
805 priv
->phy
->interface
);
812 priv
->write(priv
, 0x8, newval
);
814 /* Initialize the ports */
815 bus
= priv
->phy
->bus
;
816 for (i
= 0; i
< 5; i
++) {
817 if ((i
== 4) && priv
->port4_phy
&&
818 priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
819 /* work around for phy4 rgmii mode */
820 ar8216_phy_dbg_write(priv
, i
, 0x12, 0x480c);
822 ar8216_phy_dbg_write(priv
, i
, 0x0, 0x824e);
824 ar8216_phy_dbg_write(priv
, i
, 0x5, 0x3d47);
828 /* initialize the port itself */
829 mdiobus_write(bus
, i
, MII_ADVERTISE
,
830 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
831 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
832 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
837 priv
->initialized
= true;
842 ar8316_init_globals(struct ar8216_priv
*priv
)
844 /* standard atheros magic */
845 priv
->write(priv
, 0x38, 0xc000050e);
847 /* enable cpu port to receive multicast and broadcast frames */
848 priv
->write(priv
, AR8216_REG_FLOOD_MASK
, 0x003f003f);
850 /* enable jumbo frames */
851 ar8216_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
852 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
854 /* Enable MIB counters */
855 ar8216_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
856 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
860 static const struct ar8xxx_chip ar8316_chip
= {
861 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
862 .hw_init
= ar8316_hw_init
,
863 .init_globals
= ar8316_init_globals
,
864 .init_port
= ar8216_init_port
,
865 .setup_port
= ar8216_setup_port
,
866 .read_port_status
= ar8216_read_port_status
,
867 .atu_flush
= ar8216_atu_flush
,
868 .vtu_flush
= ar8216_vtu_flush
,
869 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
871 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
872 .mib_decs
= ar8236_mibs
,
876 ar8327_get_pad_cfg(struct ar8327_pad_cfg
*cfg
)
888 case AR8327_PAD_MAC2MAC_MII
:
889 t
= AR8327_PAD_MAC_MII_EN
;
891 t
|= AR8327_PAD_MAC_MII_RXCLK_SEL
;
893 t
|= AR8327_PAD_MAC_MII_TXCLK_SEL
;
896 case AR8327_PAD_MAC2MAC_GMII
:
897 t
= AR8327_PAD_MAC_GMII_EN
;
899 t
|= AR8327_PAD_MAC_GMII_RXCLK_SEL
;
901 t
|= AR8327_PAD_MAC_GMII_TXCLK_SEL
;
904 case AR8327_PAD_MAC_SGMII
:
905 t
= AR8327_PAD_SGMII_EN
;
908 case AR8327_PAD_MAC2PHY_MII
:
909 t
= AR8327_PAD_PHY_MII_EN
;
911 t
|= AR8327_PAD_PHY_MII_RXCLK_SEL
;
913 t
|= AR8327_PAD_PHY_MII_TXCLK_SEL
;
916 case AR8327_PAD_MAC2PHY_GMII
:
917 t
= AR8327_PAD_PHY_GMII_EN
;
918 if (cfg
->pipe_rxclk_sel
)
919 t
|= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL
;
921 t
|= AR8327_PAD_PHY_GMII_RXCLK_SEL
;
923 t
|= AR8327_PAD_PHY_GMII_TXCLK_SEL
;
926 case AR8327_PAD_MAC_RGMII
:
927 t
= AR8327_PAD_RGMII_EN
;
928 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
929 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
930 if (cfg
->rxclk_delay_en
)
931 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
932 if (cfg
->txclk_delay_en
)
933 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
936 case AR8327_PAD_PHY_GMII
:
937 t
= AR8327_PAD_PHYX_GMII_EN
;
940 case AR8327_PAD_PHY_RGMII
:
941 t
= AR8327_PAD_PHYX_RGMII_EN
;
944 case AR8327_PAD_PHY_MII
:
945 t
= AR8327_PAD_PHYX_MII_EN
;
953 ar8327_phy_fixup(struct ar8216_priv
*priv
, int phy
)
955 switch (priv
->chip_rev
) {
957 /* For 100M waveform */
958 ar8216_phy_dbg_write(priv
, phy
, 0, 0x02ea);
959 /* Turn on Gigabit clock */
960 ar8216_phy_dbg_write(priv
, phy
, 0x3d, 0x68a0);
964 ar8216_phy_mmd_write(priv
, phy
, 0x7, 0x3c);
965 ar8216_phy_mmd_write(priv
, phy
, 0x4007, 0x0);
968 ar8216_phy_mmd_write(priv
, phy
, 0x3, 0x800d);
969 ar8216_phy_mmd_write(priv
, phy
, 0x4003, 0x803f);
971 ar8216_phy_dbg_write(priv
, phy
, 0x3d, 0x6860);
972 ar8216_phy_dbg_write(priv
, phy
, 0x5, 0x2c46);
973 ar8216_phy_dbg_write(priv
, phy
, 0x3c, 0x6000);
979 ar8327_hw_init(struct ar8216_priv
*priv
)
981 struct ar8327_platform_data
*pdata
;
982 struct ar8327_led_cfg
*led_cfg
;
988 pdata
= priv
->phy
->dev
.platform_data
;
992 t
= ar8327_get_pad_cfg(pdata
->pad0_cfg
);
993 priv
->write(priv
, AR8327_REG_PAD0_MODE
, t
);
994 t
= ar8327_get_pad_cfg(pdata
->pad5_cfg
);
995 priv
->write(priv
, AR8327_REG_PAD5_MODE
, t
);
996 t
= ar8327_get_pad_cfg(pdata
->pad6_cfg
);
997 priv
->write(priv
, AR8327_REG_PAD6_MODE
, t
);
999 pos
= priv
->read(priv
, AR8327_REG_POWER_ON_STRIP
);
1002 led_cfg
= pdata
->led_cfg
;
1004 if (led_cfg
->open_drain
)
1005 new_pos
|= AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
1007 new_pos
&= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
1009 priv
->write(priv
, AR8327_REG_LED_CTRL0
, led_cfg
->led_ctrl0
);
1010 priv
->write(priv
, AR8327_REG_LED_CTRL1
, led_cfg
->led_ctrl1
);
1011 priv
->write(priv
, AR8327_REG_LED_CTRL2
, led_cfg
->led_ctrl2
);
1012 priv
->write(priv
, AR8327_REG_LED_CTRL3
, led_cfg
->led_ctrl3
);
1015 if (new_pos
!= pos
) {
1016 new_pos
|= AR8327_POWER_ON_STRIP_POWER_ON_SEL
;
1017 priv
->write(priv
, AR8327_REG_POWER_ON_STRIP
, new_pos
);
1020 bus
= priv
->phy
->bus
;
1021 for (i
= 0; i
< AR8327_NUM_PHYS
; i
++) {
1022 ar8327_phy_fixup(priv
, i
);
1024 /* start aneg on the PHY */
1025 mdiobus_write(bus
, i
, MII_ADVERTISE
, ADVERTISE_ALL
|
1026 ADVERTISE_PAUSE_CAP
|
1027 ADVERTISE_PAUSE_ASYM
);
1028 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
1029 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
1038 ar8327_init_globals(struct ar8216_priv
*priv
)
1042 /* enable CPU port and disable mirror port */
1043 t
= AR8327_FWD_CTRL0_CPU_PORT_EN
|
1044 AR8327_FWD_CTRL0_MIRROR_PORT
;
1045 priv
->write(priv
, AR8327_REG_FWD_CTRL0
, t
);
1047 /* forward multicast and broadcast frames to CPU */
1048 t
= (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_UC_FLOOD_S
) |
1049 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_MC_FLOOD_S
) |
1050 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_BC_FLOOD_S
);
1051 priv
->write(priv
, AR8327_REG_FWD_CTRL1
, t
);
1054 ar8216_rmw(priv
, AR8327_REG_MAX_FRAME_SIZE
,
1055 AR8327_MAX_FRAME_SIZE_MTU
, 1518 + 8 + 2);
1057 /* Enable MIB counters */
1058 ar8216_reg_set(priv
, AR8327_REG_MODULE_EN
,
1059 AR8327_MODULE_EN_MIB
);
1063 ar8327_init_cpuport(struct ar8216_priv
*priv
)
1065 struct ar8327_platform_data
*pdata
;
1066 struct ar8327_port_cfg
*cfg
;
1069 pdata
= priv
->phy
->dev
.platform_data
;
1073 cfg
= &pdata
->cpuport_cfg
;
1074 if (!cfg
->force_link
) {
1075 priv
->write(priv
, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU
),
1076 AR8216_PORT_STATUS_LINK_AUTO
);
1080 t
= AR8216_PORT_STATUS_TXMAC
| AR8216_PORT_STATUS_RXMAC
;
1081 t
|= cfg
->duplex
? AR8216_PORT_STATUS_DUPLEX
: 0;
1082 t
|= cfg
->rxpause
? AR8216_PORT_STATUS_RXFLOW
: 0;
1083 t
|= cfg
->txpause
? AR8216_PORT_STATUS_TXFLOW
: 0;
1084 switch (cfg
->speed
) {
1085 case AR8327_PORT_SPEED_10
:
1086 t
|= AR8216_PORT_SPEED_10M
;
1088 case AR8327_PORT_SPEED_100
:
1089 t
|= AR8216_PORT_SPEED_100M
;
1091 case AR8327_PORT_SPEED_1000
:
1092 t
|= AR8216_PORT_SPEED_1000M
;
1096 priv
->write(priv
, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU
), t
);
1100 ar8327_init_port(struct ar8216_priv
*priv
, int port
)
1104 if (port
== AR8216_PORT_CPU
) {
1105 ar8327_init_cpuport(priv
);
1107 t
= AR8216_PORT_STATUS_LINK_AUTO
;
1108 priv
->write(priv
, AR8327_REG_PORT_STATUS(port
), t
);
1111 priv
->write(priv
, AR8327_REG_PORT_HEADER(port
), 0);
1113 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), 0);
1115 t
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
1116 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
1118 t
= AR8327_PORT_LOOKUP_LEARN
;
1119 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
1120 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
1124 ar8327_read_port_status(struct ar8216_priv
*priv
, int port
)
1126 return priv
->read(priv
, AR8327_REG_PORT_STATUS(port
));
1130 ar8327_atu_flush(struct ar8216_priv
*priv
)
1134 ret
= ar8216_wait_bit(priv
, AR8327_REG_ATU_FUNC
,
1135 AR8327_ATU_FUNC_BUSY
, 0);
1137 priv
->write(priv
, AR8327_REG_ATU_FUNC
,
1138 AR8327_ATU_FUNC_OP_FLUSH
);
1144 ar8327_vtu_op(struct ar8216_priv
*priv
, u32 op
, u32 val
)
1146 if (ar8216_wait_bit(priv
, AR8327_REG_VTU_FUNC1
,
1147 AR8327_VTU_FUNC1_BUSY
, 0))
1150 if ((op
& AR8327_VTU_FUNC1_OP
) == AR8327_VTU_FUNC1_OP_LOAD
)
1151 priv
->write(priv
, AR8327_REG_VTU_FUNC0
, val
);
1153 op
|= AR8327_VTU_FUNC1_BUSY
;
1154 priv
->write(priv
, AR8327_REG_VTU_FUNC1
, op
);
1158 ar8327_vtu_flush(struct ar8216_priv
*priv
)
1160 ar8327_vtu_op(priv
, AR8327_VTU_FUNC1_OP_FLUSH
, 0);
1164 ar8327_vtu_load_vlan(struct ar8216_priv
*priv
, u32 vid
, u32 port_mask
)
1170 op
= AR8327_VTU_FUNC1_OP_LOAD
| (vid
<< AR8327_VTU_FUNC1_VID_S
);
1171 val
= AR8327_VTU_FUNC0_VALID
| AR8327_VTU_FUNC0_IVL
;
1172 for (i
= 0; i
< AR8327_NUM_PORTS
; i
++) {
1175 if ((port_mask
& BIT(i
)) == 0)
1176 mode
= AR8327_VTU_FUNC0_EG_MODE_NOT
;
1177 else if (priv
->vlan
== 0)
1178 mode
= AR8327_VTU_FUNC0_EG_MODE_KEEP
;
1179 else if (priv
->vlan_tagged
& BIT(i
))
1180 mode
= AR8327_VTU_FUNC0_EG_MODE_TAG
;
1182 mode
= AR8327_VTU_FUNC0_EG_MODE_UNTAG
;
1184 val
|= mode
<< AR8327_VTU_FUNC0_EG_MODE_S(i
);
1186 ar8327_vtu_op(priv
, op
, val
);
1190 ar8327_setup_port(struct ar8216_priv
*priv
, int port
, u32 egress
, u32 ingress
,
1191 u32 members
, u32 pvid
)
1196 t
= pvid
<< AR8327_PORT_VLAN0_DEF_SVID_S
;
1197 t
|= pvid
<< AR8327_PORT_VLAN0_DEF_CVID_S
;
1198 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
1200 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNMOD
;
1202 case AR8216_OUT_KEEP
:
1203 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
;
1205 case AR8216_OUT_STRIP_VLAN
:
1206 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNTAG
;
1208 case AR8216_OUT_ADD_VLAN
:
1209 mode
= AR8327_PORT_VLAN1_OUT_MODE_TAG
;
1213 t
= AR8327_PORT_VLAN1_PORT_VLAN_PROP
;
1214 t
|= mode
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
1215 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
1218 t
|= AR8327_PORT_LOOKUP_LEARN
;
1219 t
|= ingress
<< AR8327_PORT_LOOKUP_IN_MODE_S
;
1220 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
1221 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
1224 static const struct ar8xxx_chip ar8327_chip
= {
1225 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1226 .hw_init
= ar8327_hw_init
,
1227 .init_globals
= ar8327_init_globals
,
1228 .init_port
= ar8327_init_port
,
1229 .setup_port
= ar8327_setup_port
,
1230 .read_port_status
= ar8327_read_port_status
,
1231 .atu_flush
= ar8327_atu_flush
,
1232 .vtu_flush
= ar8327_vtu_flush
,
1233 .vtu_load_vlan
= ar8327_vtu_load_vlan
,
1235 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1236 .mib_decs
= ar8236_mibs
,
1240 ar8216_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1241 struct switch_val
*val
)
1243 struct ar8216_priv
*priv
= to_ar8216(dev
);
1244 priv
->vlan
= !!val
->value
.i
;
1249 ar8216_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1250 struct switch_val
*val
)
1252 struct ar8216_priv
*priv
= to_ar8216(dev
);
1253 val
->value
.i
= priv
->vlan
;
1259 ar8216_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
1261 struct ar8216_priv
*priv
= to_ar8216(dev
);
1263 /* make sure no invalid PVIDs get set */
1265 if (vlan
>= dev
->vlans
)
1268 priv
->pvid
[port
] = vlan
;
1273 ar8216_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
1275 struct ar8216_priv
*priv
= to_ar8216(dev
);
1276 *vlan
= priv
->pvid
[port
];
1281 ar8216_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1282 struct switch_val
*val
)
1284 struct ar8216_priv
*priv
= to_ar8216(dev
);
1285 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
1290 ar8216_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1291 struct switch_val
*val
)
1293 struct ar8216_priv
*priv
= to_ar8216(dev
);
1294 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
1299 ar8216_sw_get_port_link(struct switch_dev
*dev
, int port
,
1300 struct switch_port_link
*link
)
1302 struct ar8216_priv
*priv
= to_ar8216(dev
);
1304 ar8216_read_port_link(priv
, port
, link
);
1309 ar8216_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1311 struct ar8216_priv
*priv
= to_ar8216(dev
);
1312 u8 ports
= priv
->vlan_table
[val
->port_vlan
];
1316 for (i
= 0; i
< dev
->ports
; i
++) {
1317 struct switch_port
*p
;
1319 if (!(ports
& (1 << i
)))
1322 p
= &val
->value
.ports
[val
->len
++];
1324 if (priv
->vlan_tagged
& (1 << i
))
1325 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
1333 ar8216_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1335 struct ar8216_priv
*priv
= to_ar8216(dev
);
1336 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1340 for (i
= 0; i
< val
->len
; i
++) {
1341 struct switch_port
*p
= &val
->value
.ports
[i
];
1343 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
1344 priv
->vlan_tagged
|= (1 << p
->id
);
1346 priv
->vlan_tagged
&= ~(1 << p
->id
);
1347 priv
->pvid
[p
->id
] = val
->port_vlan
;
1349 /* make sure that an untagged port does not
1350 * appear in other vlans */
1351 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1352 if (j
== val
->port_vlan
)
1354 priv
->vlan_table
[j
] &= ~(1 << p
->id
);
1364 ar8216_sw_hw_apply(struct switch_dev
*dev
)
1366 struct ar8216_priv
*priv
= to_ar8216(dev
);
1367 u8 portmask
[AR8X16_MAX_PORTS
];
1370 mutex_lock(&priv
->reg_mutex
);
1371 /* flush all vlan translation unit entries */
1372 priv
->chip
->vtu_flush(priv
);
1374 memset(portmask
, 0, sizeof(portmask
));
1376 /* calculate the port destination masks and load vlans
1377 * into the vlan translation unit */
1378 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1379 u8 vp
= priv
->vlan_table
[j
];
1384 for (i
= 0; i
< dev
->ports
; i
++) {
1387 portmask
[i
] |= vp
& ~mask
;
1390 priv
->chip
->vtu_load_vlan(priv
, priv
->vlan_id
[j
],
1391 priv
->vlan_table
[j
]);
1395 * isolate all ports, but connect them to the cpu port */
1396 for (i
= 0; i
< dev
->ports
; i
++) {
1397 if (i
== AR8216_PORT_CPU
)
1400 portmask
[i
] = 1 << AR8216_PORT_CPU
;
1401 portmask
[AR8216_PORT_CPU
] |= (1 << i
);
1405 /* update the port destination mask registers and tag settings */
1406 for (i
= 0; i
< dev
->ports
; i
++) {
1407 int egress
, ingress
;
1411 pvid
= priv
->vlan_id
[priv
->pvid
[i
]];
1412 if (priv
->vlan_tagged
& (1 << i
))
1413 egress
= AR8216_OUT_ADD_VLAN
;
1415 egress
= AR8216_OUT_STRIP_VLAN
;
1416 ingress
= AR8216_IN_SECURE
;
1419 egress
= AR8216_OUT_KEEP
;
1420 ingress
= AR8216_IN_PORT_ONLY
;
1423 priv
->chip
->setup_port(priv
, i
, egress
, ingress
, portmask
[i
],
1426 mutex_unlock(&priv
->reg_mutex
);
1431 ar8216_sw_reset_switch(struct switch_dev
*dev
)
1433 struct ar8216_priv
*priv
= to_ar8216(dev
);
1436 mutex_lock(&priv
->reg_mutex
);
1437 memset(&priv
->vlan
, 0, sizeof(struct ar8216_priv
) -
1438 offsetof(struct ar8216_priv
, vlan
));
1440 for (i
= 0; i
< AR8X16_MAX_VLANS
; i
++)
1441 priv
->vlan_id
[i
] = i
;
1443 /* Configure all ports */
1444 for (i
= 0; i
< dev
->ports
; i
++)
1445 priv
->chip
->init_port(priv
, i
);
1447 priv
->chip
->init_globals(priv
);
1448 mutex_unlock(&priv
->reg_mutex
);
1450 return ar8216_sw_hw_apply(dev
);
1454 ar8216_sw_set_reset_mibs(struct switch_dev
*dev
,
1455 const struct switch_attr
*attr
,
1456 struct switch_val
*val
)
1458 struct ar8216_priv
*priv
= to_ar8216(dev
);
1462 if (!ar8xxx_has_mib_counters(priv
))
1465 mutex_lock(&priv
->mib_lock
);
1467 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1468 sizeof(*priv
->mib_stats
);
1469 memset(priv
->mib_stats
, '\0', len
);
1470 ret
= ar8216_mib_flush(priv
);
1477 mutex_unlock(&priv
->mib_lock
);
1482 ar8216_sw_set_port_reset_mib(struct switch_dev
*dev
,
1483 const struct switch_attr
*attr
,
1484 struct switch_val
*val
)
1486 struct ar8216_priv
*priv
= to_ar8216(dev
);
1490 if (!ar8xxx_has_mib_counters(priv
))
1493 port
= val
->port_vlan
;
1494 if (port
>= dev
->ports
)
1497 mutex_lock(&priv
->mib_lock
);
1498 ret
= ar8216_mib_capture(priv
);
1502 ar8216_mib_fetch_port_stat(priv
, port
, true);
1507 mutex_unlock(&priv
->mib_lock
);
1512 ar8216_sw_get_port_mib(struct switch_dev
*dev
,
1513 const struct switch_attr
*attr
,
1514 struct switch_val
*val
)
1516 struct ar8216_priv
*priv
= to_ar8216(dev
);
1517 const struct ar8xxx_chip
*chip
= priv
->chip
;
1521 char *buf
= priv
->buf
;
1524 if (!ar8xxx_has_mib_counters(priv
))
1527 port
= val
->port_vlan
;
1528 if (port
>= dev
->ports
)
1531 mutex_lock(&priv
->mib_lock
);
1532 ret
= ar8216_mib_capture(priv
);
1536 ar8216_mib_fetch_port_stat(priv
, port
, false);
1538 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1539 "Port %d MIB counters\n",
1542 mib_stats
= &priv
->mib_stats
[port
* chip
->num_mibs
];
1543 for (i
= 0; i
< chip
->num_mibs
; i
++)
1544 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1546 chip
->mib_decs
[i
].name
,
1555 mutex_unlock(&priv
->mib_lock
);
1559 static struct switch_attr ar8216_globals
[] = {
1561 .type
= SWITCH_TYPE_INT
,
1562 .name
= "enable_vlan",
1563 .description
= "Enable VLAN mode",
1564 .set
= ar8216_sw_set_vlan
,
1565 .get
= ar8216_sw_get_vlan
,
1569 .type
= SWITCH_TYPE_NOVAL
,
1570 .name
= "reset_mibs",
1571 .description
= "Reset all MIB counters",
1572 .set
= ar8216_sw_set_reset_mibs
,
1577 static struct switch_attr ar8216_port
[] = {
1579 .type
= SWITCH_TYPE_NOVAL
,
1580 .name
= "reset_mib",
1581 .description
= "Reset single port MIB counters",
1582 .set
= ar8216_sw_set_port_reset_mib
,
1585 .type
= SWITCH_TYPE_STRING
,
1587 .description
= "Get port's MIB counters",
1589 .get
= ar8216_sw_get_port_mib
,
1593 static struct switch_attr ar8216_vlan
[] = {
1595 .type
= SWITCH_TYPE_INT
,
1597 .description
= "VLAN ID (0-4094)",
1598 .set
= ar8216_sw_set_vid
,
1599 .get
= ar8216_sw_get_vid
,
1604 static const struct switch_dev_ops ar8216_sw_ops
= {
1606 .attr
= ar8216_globals
,
1607 .n_attr
= ARRAY_SIZE(ar8216_globals
),
1610 .attr
= ar8216_port
,
1611 .n_attr
= ARRAY_SIZE(ar8216_port
),
1614 .attr
= ar8216_vlan
,
1615 .n_attr
= ARRAY_SIZE(ar8216_vlan
),
1617 .get_port_pvid
= ar8216_sw_get_pvid
,
1618 .set_port_pvid
= ar8216_sw_set_pvid
,
1619 .get_vlan_ports
= ar8216_sw_get_ports
,
1620 .set_vlan_ports
= ar8216_sw_set_ports
,
1621 .apply_config
= ar8216_sw_hw_apply
,
1622 .reset_switch
= ar8216_sw_reset_switch
,
1623 .get_port_link
= ar8216_sw_get_port_link
,
1627 ar8216_id_chip(struct ar8216_priv
*priv
)
1633 val
= ar8216_mii_read(priv
, AR8216_REG_CTRL
);
1637 id
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1638 for (i
= 0; i
< AR8X16_PROBE_RETRIES
; i
++) {
1641 val
= ar8216_mii_read(priv
, AR8216_REG_CTRL
);
1645 t
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1650 priv
->chip_ver
= (id
& AR8216_CTRL_VERSION
) >> AR8216_CTRL_VERSION_S
;
1651 priv
->chip_rev
= (id
& AR8216_CTRL_REVISION
);
1653 switch (priv
->chip_ver
) {
1654 case AR8XXX_VER_AR8216
:
1655 priv
->chip
= &ar8216_chip
;
1657 case AR8XXX_VER_AR8236
:
1658 priv
->chip
= &ar8236_chip
;
1660 case AR8XXX_VER_AR8316
:
1661 priv
->chip
= &ar8316_chip
;
1663 case AR8XXX_VER_AR8327
:
1664 priv
->mii_lo_first
= true;
1665 priv
->chip
= &ar8327_chip
;
1669 "ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n",
1670 priv
->chip_ver
, priv
->chip_rev
,
1671 mdiobus_read(priv
->phy
->bus
, priv
->phy
->addr
, 2),
1672 mdiobus_read(priv
->phy
->bus
, priv
->phy
->addr
, 3));
1681 ar8xxx_mib_work_func(struct work_struct
*work
)
1683 struct ar8216_priv
*priv
;
1686 priv
= container_of(work
, struct ar8216_priv
, mib_work
.work
);
1688 mutex_lock(&priv
->mib_lock
);
1690 err
= ar8216_mib_capture(priv
);
1694 ar8216_mib_fetch_port_stat(priv
, priv
->mib_next_port
, false);
1697 priv
->mib_next_port
++;
1698 if (priv
->mib_next_port
>= priv
->dev
.ports
)
1699 priv
->mib_next_port
= 0;
1701 mutex_unlock(&priv
->mib_lock
);
1702 schedule_delayed_work(&priv
->mib_work
,
1703 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
1707 ar8xxx_mib_init(struct ar8216_priv
*priv
)
1711 if (!ar8xxx_has_mib_counters(priv
))
1714 BUG_ON(!priv
->chip
->mib_decs
|| !priv
->chip
->num_mibs
);
1716 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1717 sizeof(*priv
->mib_stats
);
1718 priv
->mib_stats
= kzalloc(len
, GFP_KERNEL
);
1720 if (!priv
->mib_stats
)
1723 mutex_init(&priv
->mib_lock
);
1724 INIT_DELAYED_WORK(&priv
->mib_work
, ar8xxx_mib_work_func
);
1730 ar8xxx_mib_start(struct ar8216_priv
*priv
)
1732 if (!ar8xxx_has_mib_counters(priv
))
1735 schedule_delayed_work(&priv
->mib_work
,
1736 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
1740 ar8xxx_mib_cleanup(struct ar8216_priv
*priv
)
1742 if (!ar8xxx_has_mib_counters(priv
))
1745 cancel_delayed_work(&priv
->mib_work
);
1746 kfree(priv
->mib_stats
);
1750 ar8216_config_init(struct phy_device
*pdev
)
1752 struct ar8216_priv
*priv
= pdev
->priv
;
1753 struct net_device
*dev
= pdev
->attached_dev
;
1754 struct switch_dev
*swdev
;
1758 priv
= kzalloc(sizeof(struct ar8216_priv
), GFP_KERNEL
);
1765 ret
= ar8216_id_chip(priv
);
1769 if (pdev
->addr
!= 0) {
1770 if (ar8xxx_has_gige(priv
)) {
1771 pdev
->supported
|= SUPPORTED_1000baseT_Full
;
1772 pdev
->advertising
|= ADVERTISED_1000baseT_Full
;
1775 if (chip_is_ar8316(priv
)) {
1776 /* check if we're attaching to the switch twice */
1777 pdev
= pdev
->bus
->phy_map
[0];
1783 /* switch device has not been initialized, reuse priv */
1785 priv
->port4_phy
= true;
1792 /* switch device has been initialized, reinit */
1794 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
1795 priv
->initialized
= false;
1796 priv
->port4_phy
= true;
1797 ar8316_hw_init(priv
);
1805 if (ar8xxx_has_gige(priv
))
1806 pdev
->supported
= SUPPORTED_1000baseT_Full
;
1808 pdev
->supported
= SUPPORTED_100baseT_Full
;
1809 pdev
->advertising
= pdev
->supported
;
1811 mutex_init(&priv
->reg_mutex
);
1812 priv
->read
= ar8216_mii_read
;
1813 priv
->write
= ar8216_mii_write
;
1818 swdev
->cpu_port
= AR8216_PORT_CPU
;
1819 swdev
->ops
= &ar8216_sw_ops
;
1820 swdev
->ports
= AR8216_NUM_PORTS
;
1822 if (chip_is_ar8316(priv
)) {
1823 swdev
->name
= "Atheros AR8316";
1824 swdev
->vlans
= AR8X16_MAX_VLANS
;
1826 if (priv
->port4_phy
) {
1827 /* port 5 connected to the other mac, therefore unusable */
1828 swdev
->ports
= (AR8216_NUM_PORTS
- 1);
1830 } else if (chip_is_ar8236(priv
)) {
1831 swdev
->name
= "Atheros AR8236";
1832 swdev
->vlans
= AR8216_NUM_VLANS
;
1833 swdev
->ports
= AR8216_NUM_PORTS
;
1834 } else if (chip_is_ar8327(priv
)) {
1835 swdev
->name
= "Atheros AR8327";
1836 swdev
->vlans
= AR8X16_MAX_VLANS
;
1837 swdev
->ports
= AR8327_NUM_PORTS
;
1839 swdev
->name
= "Atheros AR8216";
1840 swdev
->vlans
= AR8216_NUM_VLANS
;
1843 ret
= ar8xxx_mib_init(priv
);
1847 ret
= register_switch(&priv
->dev
, pdev
->attached_dev
);
1849 goto err_cleanup_mib
;
1851 printk(KERN_INFO
"%s: %s switch driver attached.\n",
1852 pdev
->attached_dev
->name
, swdev
->name
);
1856 ret
= priv
->chip
->hw_init(priv
);
1858 goto err_cleanup_mib
;
1860 ret
= ar8216_sw_reset_switch(&priv
->dev
);
1862 goto err_cleanup_mib
;
1864 dev
->phy_ptr
= priv
;
1866 /* VID fixup only needed on ar8216 */
1867 if (chip_is_ar8216(priv
) && pdev
->addr
== 0) {
1868 dev
->priv_flags
|= IFF_NO_IP_ALIGN
;
1869 dev
->eth_mangle_rx
= ar8216_mangle_rx
;
1870 dev
->eth_mangle_tx
= ar8216_mangle_tx
;
1875 ar8xxx_mib_start(priv
);
1880 ar8xxx_mib_cleanup(priv
);
1887 ar8216_read_status(struct phy_device
*phydev
)
1889 struct ar8216_priv
*priv
= phydev
->priv
;
1890 struct switch_port_link link
;
1893 if (phydev
->addr
!= 0)
1894 return genphy_read_status(phydev
);
1896 ar8216_read_port_link(priv
, phydev
->addr
, &link
);
1897 phydev
->link
= !!link
.link
;
1901 switch (link
.speed
) {
1902 case SWITCH_PORT_SPEED_10
:
1903 phydev
->speed
= SPEED_10
;
1905 case SWITCH_PORT_SPEED_100
:
1906 phydev
->speed
= SPEED_100
;
1908 case SWITCH_PORT_SPEED_1000
:
1909 phydev
->speed
= SPEED_1000
;
1914 phydev
->duplex
= link
.duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
1916 /* flush the address translation unit */
1917 mutex_lock(&priv
->reg_mutex
);
1918 ret
= priv
->chip
->atu_flush(priv
);
1919 mutex_unlock(&priv
->reg_mutex
);
1921 phydev
->state
= PHY_RUNNING
;
1922 netif_carrier_on(phydev
->attached_dev
);
1923 phydev
->adjust_link(phydev
->attached_dev
);
1929 ar8216_config_aneg(struct phy_device
*phydev
)
1931 if (phydev
->addr
== 0)
1934 return genphy_config_aneg(phydev
);
1938 ar8216_probe(struct phy_device
*pdev
)
1940 struct ar8216_priv
*priv
;
1943 priv
= kzalloc(sizeof(struct ar8216_priv
), GFP_KERNEL
);
1949 ret
= ar8216_id_chip(priv
);
1956 ar8216_remove(struct phy_device
*pdev
)
1958 struct ar8216_priv
*priv
= pdev
->priv
;
1959 struct net_device
*dev
= pdev
->attached_dev
;
1964 dev
->priv_flags
&= ~IFF_NO_IP_ALIGN
;
1965 dev
->eth_mangle_rx
= NULL
;
1966 dev
->eth_mangle_tx
= NULL
;
1968 if (pdev
->addr
== 0)
1969 unregister_switch(&priv
->dev
);
1971 ar8xxx_mib_cleanup(priv
);
1975 static struct phy_driver ar8216_driver
= {
1976 .phy_id
= 0x004d0000,
1977 .name
= "Atheros AR8216/AR8236/AR8316",
1978 .phy_id_mask
= 0xffff0000,
1979 .features
= PHY_BASIC_FEATURES
,
1980 .probe
= ar8216_probe
,
1981 .remove
= ar8216_remove
,
1982 .config_init
= &ar8216_config_init
,
1983 .config_aneg
= &ar8216_config_aneg
,
1984 .read_status
= &ar8216_read_status
,
1985 .driver
= { .owner
= THIS_MODULE
},
1991 return phy_driver_register(&ar8216_driver
);
1997 phy_driver_unregister(&ar8216_driver
);
2000 module_init(ar8216_init
);
2001 module_exit(ar8216_exit
);
2002 MODULE_LICENSE("GPL");