2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
38 /* size of the vlan table */
39 #define AR8X16_MAX_VLANS 128
40 #define AR8X16_PROBE_RETRIES 10
41 #define AR8X16_MAX_PORTS 8
43 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
47 #define AR8XXX_CAP_GIGE BIT(0)
48 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
51 AR8XXX_VER_AR8216
= 0x01,
52 AR8XXX_VER_AR8236
= 0x03,
53 AR8XXX_VER_AR8316
= 0x10,
54 AR8XXX_VER_AR8327
= 0x12,
57 struct ar8xxx_mib_desc
{
66 int (*hw_init
)(struct ar8216_priv
*priv
);
67 void (*init_globals
)(struct ar8216_priv
*priv
);
68 void (*init_port
)(struct ar8216_priv
*priv
, int port
);
69 void (*setup_port
)(struct ar8216_priv
*priv
, int port
, u32 egress
,
70 u32 ingress
, u32 members
, u32 pvid
);
71 u32 (*read_port_status
)(struct ar8216_priv
*priv
, int port
);
72 int (*atu_flush
)(struct ar8216_priv
*priv
);
73 void (*vtu_flush
)(struct ar8216_priv
*priv
);
74 void (*vtu_load_vlan
)(struct ar8216_priv
*priv
, u32 vid
, u32 port_mask
);
76 const struct ar8xxx_mib_desc
*mib_decs
;
81 struct switch_dev dev
;
82 struct mii_bus
*mii_bus
;
83 struct phy_device
*phy
;
84 u32 (*read
)(struct ar8216_priv
*priv
, int reg
);
85 void (*write
)(struct ar8216_priv
*priv
, int reg
, u32 val
);
86 const struct net_device_ops
*ndo_old
;
87 struct net_device_ops ndo
;
88 struct mutex reg_mutex
;
91 const struct ar8xxx_chip
*chip
;
99 struct mutex mib_lock
;
100 struct delayed_work mib_work
;
104 struct list_head list
;
105 unsigned int use_count
;
107 /* all fields below are cleared on reset */
109 u16 vlan_id
[AR8X16_MAX_VLANS
];
110 u8 vlan_table
[AR8X16_MAX_VLANS
];
112 u16 pvid
[AR8X16_MAX_PORTS
];
115 #define MIB_DESC(_s , _o, _n) \
122 static const struct ar8xxx_mib_desc ar8216_mibs
[] = {
123 MIB_DESC(1, AR8216_STATS_RXBROAD
, "RxBroad"),
124 MIB_DESC(1, AR8216_STATS_RXPAUSE
, "RxPause"),
125 MIB_DESC(1, AR8216_STATS_RXMULTI
, "RxMulti"),
126 MIB_DESC(1, AR8216_STATS_RXFCSERR
, "RxFcsErr"),
127 MIB_DESC(1, AR8216_STATS_RXALIGNERR
, "RxAlignErr"),
128 MIB_DESC(1, AR8216_STATS_RXRUNT
, "RxRunt"),
129 MIB_DESC(1, AR8216_STATS_RXFRAGMENT
, "RxFragment"),
130 MIB_DESC(1, AR8216_STATS_RX64BYTE
, "Rx64Byte"),
131 MIB_DESC(1, AR8216_STATS_RX128BYTE
, "Rx128Byte"),
132 MIB_DESC(1, AR8216_STATS_RX256BYTE
, "Rx256Byte"),
133 MIB_DESC(1, AR8216_STATS_RX512BYTE
, "Rx512Byte"),
134 MIB_DESC(1, AR8216_STATS_RX1024BYTE
, "Rx1024Byte"),
135 MIB_DESC(1, AR8216_STATS_RXMAXBYTE
, "RxMaxByte"),
136 MIB_DESC(1, AR8216_STATS_RXTOOLONG
, "RxTooLong"),
137 MIB_DESC(2, AR8216_STATS_RXGOODBYTE
, "RxGoodByte"),
138 MIB_DESC(2, AR8216_STATS_RXBADBYTE
, "RxBadByte"),
139 MIB_DESC(1, AR8216_STATS_RXOVERFLOW
, "RxOverFlow"),
140 MIB_DESC(1, AR8216_STATS_FILTERED
, "Filtered"),
141 MIB_DESC(1, AR8216_STATS_TXBROAD
, "TxBroad"),
142 MIB_DESC(1, AR8216_STATS_TXPAUSE
, "TxPause"),
143 MIB_DESC(1, AR8216_STATS_TXMULTI
, "TxMulti"),
144 MIB_DESC(1, AR8216_STATS_TXUNDERRUN
, "TxUnderRun"),
145 MIB_DESC(1, AR8216_STATS_TX64BYTE
, "Tx64Byte"),
146 MIB_DESC(1, AR8216_STATS_TX128BYTE
, "Tx128Byte"),
147 MIB_DESC(1, AR8216_STATS_TX256BYTE
, "Tx256Byte"),
148 MIB_DESC(1, AR8216_STATS_TX512BYTE
, "Tx512Byte"),
149 MIB_DESC(1, AR8216_STATS_TX1024BYTE
, "Tx1024Byte"),
150 MIB_DESC(1, AR8216_STATS_TXMAXBYTE
, "TxMaxByte"),
151 MIB_DESC(1, AR8216_STATS_TXOVERSIZE
, "TxOverSize"),
152 MIB_DESC(2, AR8216_STATS_TXBYTE
, "TxByte"),
153 MIB_DESC(1, AR8216_STATS_TXCOLLISION
, "TxCollision"),
154 MIB_DESC(1, AR8216_STATS_TXABORTCOL
, "TxAbortCol"),
155 MIB_DESC(1, AR8216_STATS_TXMULTICOL
, "TxMultiCol"),
156 MIB_DESC(1, AR8216_STATS_TXSINGLECOL
, "TxSingleCol"),
157 MIB_DESC(1, AR8216_STATS_TXEXCDEFER
, "TxExcDefer"),
158 MIB_DESC(1, AR8216_STATS_TXDEFER
, "TxDefer"),
159 MIB_DESC(1, AR8216_STATS_TXLATECOL
, "TxLateCol"),
162 static const struct ar8xxx_mib_desc ar8236_mibs
[] = {
163 MIB_DESC(1, AR8236_STATS_RXBROAD
, "RxBroad"),
164 MIB_DESC(1, AR8236_STATS_RXPAUSE
, "RxPause"),
165 MIB_DESC(1, AR8236_STATS_RXMULTI
, "RxMulti"),
166 MIB_DESC(1, AR8236_STATS_RXFCSERR
, "RxFcsErr"),
167 MIB_DESC(1, AR8236_STATS_RXALIGNERR
, "RxAlignErr"),
168 MIB_DESC(1, AR8236_STATS_RXRUNT
, "RxRunt"),
169 MIB_DESC(1, AR8236_STATS_RXFRAGMENT
, "RxFragment"),
170 MIB_DESC(1, AR8236_STATS_RX64BYTE
, "Rx64Byte"),
171 MIB_DESC(1, AR8236_STATS_RX128BYTE
, "Rx128Byte"),
172 MIB_DESC(1, AR8236_STATS_RX256BYTE
, "Rx256Byte"),
173 MIB_DESC(1, AR8236_STATS_RX512BYTE
, "Rx512Byte"),
174 MIB_DESC(1, AR8236_STATS_RX1024BYTE
, "Rx1024Byte"),
175 MIB_DESC(1, AR8236_STATS_RX1518BYTE
, "Rx1518Byte"),
176 MIB_DESC(1, AR8236_STATS_RXMAXBYTE
, "RxMaxByte"),
177 MIB_DESC(1, AR8236_STATS_RXTOOLONG
, "RxTooLong"),
178 MIB_DESC(2, AR8236_STATS_RXGOODBYTE
, "RxGoodByte"),
179 MIB_DESC(2, AR8236_STATS_RXBADBYTE
, "RxBadByte"),
180 MIB_DESC(1, AR8236_STATS_RXOVERFLOW
, "RxOverFlow"),
181 MIB_DESC(1, AR8236_STATS_FILTERED
, "Filtered"),
182 MIB_DESC(1, AR8236_STATS_TXBROAD
, "TxBroad"),
183 MIB_DESC(1, AR8236_STATS_TXPAUSE
, "TxPause"),
184 MIB_DESC(1, AR8236_STATS_TXMULTI
, "TxMulti"),
185 MIB_DESC(1, AR8236_STATS_TXUNDERRUN
, "TxUnderRun"),
186 MIB_DESC(1, AR8236_STATS_TX64BYTE
, "Tx64Byte"),
187 MIB_DESC(1, AR8236_STATS_TX128BYTE
, "Tx128Byte"),
188 MIB_DESC(1, AR8236_STATS_TX256BYTE
, "Tx256Byte"),
189 MIB_DESC(1, AR8236_STATS_TX512BYTE
, "Tx512Byte"),
190 MIB_DESC(1, AR8236_STATS_TX1024BYTE
, "Tx1024Byte"),
191 MIB_DESC(1, AR8236_STATS_TX1518BYTE
, "Tx1518Byte"),
192 MIB_DESC(1, AR8236_STATS_TXMAXBYTE
, "TxMaxByte"),
193 MIB_DESC(1, AR8236_STATS_TXOVERSIZE
, "TxOverSize"),
194 MIB_DESC(2, AR8236_STATS_TXBYTE
, "TxByte"),
195 MIB_DESC(1, AR8236_STATS_TXCOLLISION
, "TxCollision"),
196 MIB_DESC(1, AR8236_STATS_TXABORTCOL
, "TxAbortCol"),
197 MIB_DESC(1, AR8236_STATS_TXMULTICOL
, "TxMultiCol"),
198 MIB_DESC(1, AR8236_STATS_TXSINGLECOL
, "TxSingleCol"),
199 MIB_DESC(1, AR8236_STATS_TXEXCDEFER
, "TxExcDefer"),
200 MIB_DESC(1, AR8236_STATS_TXDEFER
, "TxDefer"),
201 MIB_DESC(1, AR8236_STATS_TXLATECOL
, "TxLateCol"),
204 static DEFINE_MUTEX(ar8xxx_dev_list_lock
);
205 static LIST_HEAD(ar8xxx_dev_list
);
207 static inline struct ar8216_priv
*
208 swdev_to_ar8216(struct switch_dev
*swdev
)
210 return container_of(swdev
, struct ar8216_priv
, dev
);
213 static inline bool ar8xxx_has_gige(struct ar8216_priv
*priv
)
215 return priv
->chip
->caps
& AR8XXX_CAP_GIGE
;
218 static inline bool ar8xxx_has_mib_counters(struct ar8216_priv
*priv
)
220 return priv
->chip
->caps
& AR8XXX_CAP_MIB_COUNTERS
;
223 static inline bool chip_is_ar8216(struct ar8216_priv
*priv
)
225 return priv
->chip_ver
== AR8XXX_VER_AR8216
;
228 static inline bool chip_is_ar8236(struct ar8216_priv
*priv
)
230 return priv
->chip_ver
== AR8XXX_VER_AR8236
;
233 static inline bool chip_is_ar8316(struct ar8216_priv
*priv
)
235 return priv
->chip_ver
== AR8XXX_VER_AR8316
;
238 static inline bool chip_is_ar8327(struct ar8216_priv
*priv
)
240 return priv
->chip_ver
== AR8XXX_VER_AR8327
;
244 split_addr(u32 regaddr
, u16
*r1
, u16
*r2
, u16
*page
)
247 *r1
= regaddr
& 0x1e;
253 *page
= regaddr
& 0x1ff;
257 ar8216_mii_read(struct ar8216_priv
*priv
, int reg
)
259 struct mii_bus
*bus
= priv
->mii_bus
;
263 split_addr((u32
) reg
, &r1
, &r2
, &page
);
265 mutex_lock(&bus
->mdio_lock
);
267 bus
->write(bus
, 0x18, 0, page
);
268 usleep_range(1000, 2000); /* wait for the page switch to propagate */
269 lo
= bus
->read(bus
, 0x10 | r2
, r1
);
270 hi
= bus
->read(bus
, 0x10 | r2
, r1
+ 1);
272 mutex_unlock(&bus
->mdio_lock
);
274 return (hi
<< 16) | lo
;
278 ar8216_mii_write(struct ar8216_priv
*priv
, int reg
, u32 val
)
280 struct mii_bus
*bus
= priv
->mii_bus
;
284 split_addr((u32
) reg
, &r1
, &r2
, &r3
);
286 hi
= (u16
) (val
>> 16);
288 mutex_lock(&bus
->mdio_lock
);
290 bus
->write(bus
, 0x18, 0, r3
);
291 usleep_range(1000, 2000); /* wait for the page switch to propagate */
292 if (priv
->mii_lo_first
) {
293 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
294 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
296 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
297 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
300 mutex_unlock(&bus
->mdio_lock
);
304 ar8216_phy_dbg_write(struct ar8216_priv
*priv
, int phy_addr
,
305 u16 dbg_addr
, u16 dbg_data
)
307 struct mii_bus
*bus
= priv
->mii_bus
;
309 mutex_lock(&bus
->mdio_lock
);
310 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
311 bus
->write(bus
, phy_addr
, MII_ATH_DBG_DATA
, dbg_data
);
312 mutex_unlock(&bus
->mdio_lock
);
316 ar8216_phy_mmd_write(struct ar8216_priv
*priv
, int phy_addr
, u16 addr
, u16 data
)
318 struct mii_bus
*bus
= priv
->mii_bus
;
320 mutex_lock(&bus
->mdio_lock
);
321 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
322 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, data
);
323 mutex_unlock(&bus
->mdio_lock
);
327 ar8216_rmw(struct ar8216_priv
*priv
, int reg
, u32 mask
, u32 val
)
331 lockdep_assert_held(&priv
->reg_mutex
);
333 v
= priv
->read(priv
, reg
);
336 priv
->write(priv
, reg
, v
);
342 ar8216_reg_set(struct ar8216_priv
*priv
, int reg
, u32 val
)
346 lockdep_assert_held(&priv
->reg_mutex
);
348 v
= priv
->read(priv
, reg
);
350 priv
->write(priv
, reg
, v
);
354 ar8216_reg_wait(struct ar8216_priv
*priv
, u32 reg
, u32 mask
, u32 val
,
359 for (i
= 0; i
< timeout
; i
++) {
362 t
= priv
->read(priv
, reg
);
363 if ((t
& mask
) == val
)
366 usleep_range(1000, 2000);
373 ar8216_mib_op(struct ar8216_priv
*priv
, u32 op
)
378 lockdep_assert_held(&priv
->mib_lock
);
380 if (chip_is_ar8327(priv
))
381 mib_func
= AR8327_REG_MIB_FUNC
;
383 mib_func
= AR8216_REG_MIB_FUNC
;
385 mutex_lock(&priv
->reg_mutex
);
386 /* Capture the hardware statistics for all ports */
387 ar8216_rmw(priv
, mib_func
, AR8216_MIB_FUNC
, (op
<< AR8216_MIB_FUNC_S
));
388 mutex_unlock(&priv
->reg_mutex
);
390 /* Wait for the capturing to complete. */
391 ret
= ar8216_reg_wait(priv
, mib_func
, AR8216_MIB_BUSY
, 0, 10);
402 ar8216_mib_capture(struct ar8216_priv
*priv
)
404 return ar8216_mib_op(priv
, AR8216_MIB_FUNC_CAPTURE
);
408 ar8216_mib_flush(struct ar8216_priv
*priv
)
410 return ar8216_mib_op(priv
, AR8216_MIB_FUNC_FLUSH
);
414 ar8216_mib_fetch_port_stat(struct ar8216_priv
*priv
, int port
, bool flush
)
420 WARN_ON(port
>= priv
->dev
.ports
);
422 lockdep_assert_held(&priv
->mib_lock
);
424 if (chip_is_ar8327(priv
))
425 base
= AR8327_REG_PORT_STATS_BASE(port
);
426 else if (chip_is_ar8236(priv
) ||
427 chip_is_ar8316(priv
))
428 base
= AR8236_REG_PORT_STATS_BASE(port
);
430 base
= AR8216_REG_PORT_STATS_BASE(port
);
432 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
433 for (i
= 0; i
< priv
->chip
->num_mibs
; i
++) {
434 const struct ar8xxx_mib_desc
*mib
;
437 mib
= &priv
->chip
->mib_decs
[i
];
438 t
= priv
->read(priv
, base
+ mib
->offset
);
439 if (mib
->size
== 2) {
442 hi
= priv
->read(priv
, base
+ mib
->offset
+ 4);
454 ar8216_read_port_link(struct ar8216_priv
*priv
, int port
,
455 struct switch_port_link
*link
)
460 memset(link
, '\0', sizeof(*link
));
462 status
= priv
->chip
->read_port_status(priv
, port
);
464 link
->aneg
= !!(status
& AR8216_PORT_STATUS_LINK_AUTO
);
466 link
->link
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
473 link
->duplex
= !!(status
& AR8216_PORT_STATUS_DUPLEX
);
474 link
->tx_flow
= !!(status
& AR8216_PORT_STATUS_TXFLOW
);
475 link
->rx_flow
= !!(status
& AR8216_PORT_STATUS_RXFLOW
);
477 speed
= (status
& AR8216_PORT_STATUS_SPEED
) >>
478 AR8216_PORT_STATUS_SPEED_S
;
481 case AR8216_PORT_SPEED_10M
:
482 link
->speed
= SWITCH_PORT_SPEED_10
;
484 case AR8216_PORT_SPEED_100M
:
485 link
->speed
= SWITCH_PORT_SPEED_100
;
487 case AR8216_PORT_SPEED_1000M
:
488 link
->speed
= SWITCH_PORT_SPEED_1000
;
491 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
496 static struct sk_buff
*
497 ar8216_mangle_tx(struct net_device
*dev
, struct sk_buff
*skb
)
499 struct ar8216_priv
*priv
= dev
->phy_ptr
;
508 if (unlikely(skb_headroom(skb
) < 2)) {
509 if (pskb_expand_head(skb
, 2, 0, GFP_ATOMIC
) < 0)
513 buf
= skb_push(skb
, 2);
521 dev_kfree_skb_any(skb
);
526 ar8216_mangle_rx(struct net_device
*dev
, struct sk_buff
*skb
)
528 struct ar8216_priv
*priv
;
536 /* don't strip the header if vlan mode is disabled */
540 /* strip header, get vlan id */
544 /* check for vlan header presence */
545 if ((buf
[12 + 2] != 0x81) || (buf
[13 + 2] != 0x00))
550 /* no need to fix up packets coming from a tagged source */
551 if (priv
->vlan_tagged
& (1 << port
))
554 /* lookup port vid from local table, the switch passes an invalid vlan id */
555 vlan
= priv
->vlan_id
[priv
->pvid
[port
]];
558 buf
[14 + 2] |= vlan
>> 8;
559 buf
[15 + 2] = vlan
& 0xff;
563 ar8216_wait_bit(struct ar8216_priv
*priv
, int reg
, u32 mask
, u32 val
)
569 t
= priv
->read(priv
, reg
);
570 if ((t
& mask
) == val
)
579 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
580 (unsigned int) reg
, t
, mask
, val
);
585 ar8216_vtu_op(struct ar8216_priv
*priv
, u32 op
, u32 val
)
587 if (ar8216_wait_bit(priv
, AR8216_REG_VTU
, AR8216_VTU_ACTIVE
, 0))
589 if ((op
& AR8216_VTU_OP
) == AR8216_VTU_OP_LOAD
) {
590 val
&= AR8216_VTUDATA_MEMBER
;
591 val
|= AR8216_VTUDATA_VALID
;
592 priv
->write(priv
, AR8216_REG_VTU_DATA
, val
);
594 op
|= AR8216_VTU_ACTIVE
;
595 priv
->write(priv
, AR8216_REG_VTU
, op
);
599 ar8216_vtu_flush(struct ar8216_priv
*priv
)
601 ar8216_vtu_op(priv
, AR8216_VTU_OP_FLUSH
, 0);
605 ar8216_vtu_load_vlan(struct ar8216_priv
*priv
, u32 vid
, u32 port_mask
)
609 op
= AR8216_VTU_OP_LOAD
| (vid
<< AR8216_VTU_VID_S
);
610 ar8216_vtu_op(priv
, op
, port_mask
);
614 ar8216_atu_flush(struct ar8216_priv
*priv
)
618 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU
, AR8216_ATU_ACTIVE
, 0);
620 priv
->write(priv
, AR8216_REG_ATU
, AR8216_ATU_OP_FLUSH
);
626 ar8216_read_port_status(struct ar8216_priv
*priv
, int port
)
628 return priv
->read(priv
, AR8216_REG_PORT_STATUS(port
));
632 ar8216_setup_port(struct ar8216_priv
*priv
, int port
, u32 egress
, u32 ingress
,
633 u32 members
, u32 pvid
)
637 if (chip_is_ar8216(priv
) && priv
->vlan
&& port
== AR8216_PORT_CPU
)
638 header
= AR8216_PORT_CTRL_HEADER
;
642 ar8216_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
643 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
644 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
645 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
646 AR8216_PORT_CTRL_LEARN
| header
|
647 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
648 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
650 ar8216_rmw(priv
, AR8216_REG_PORT_VLAN(port
),
651 AR8216_PORT_VLAN_DEST_PORTS
| AR8216_PORT_VLAN_MODE
|
652 AR8216_PORT_VLAN_DEFAULT_ID
,
653 (members
<< AR8216_PORT_VLAN_DEST_PORTS_S
) |
654 (ingress
<< AR8216_PORT_VLAN_MODE_S
) |
655 (pvid
<< AR8216_PORT_VLAN_DEFAULT_ID_S
));
659 ar8216_hw_init(struct ar8216_priv
*priv
)
665 ar8216_init_globals(struct ar8216_priv
*priv
)
667 /* standard atheros magic */
668 priv
->write(priv
, 0x38, 0xc000050e);
670 ar8216_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
671 AR8216_GCTRL_MTU
, 1518 + 8 + 2);
675 ar8216_init_port(struct ar8216_priv
*priv
, int port
)
677 /* Enable port learning and tx */
678 priv
->write(priv
, AR8216_REG_PORT_CTRL(port
),
679 AR8216_PORT_CTRL_LEARN
|
680 (4 << AR8216_PORT_CTRL_STATE_S
));
682 priv
->write(priv
, AR8216_REG_PORT_VLAN(port
), 0);
684 if (port
== AR8216_PORT_CPU
) {
685 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
686 AR8216_PORT_STATUS_LINK_UP
|
687 (ar8xxx_has_gige(priv
) ?
688 AR8216_PORT_SPEED_1000M
: AR8216_PORT_SPEED_100M
) |
689 AR8216_PORT_STATUS_TXMAC
|
690 AR8216_PORT_STATUS_RXMAC
|
691 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_RXFLOW
: 0) |
692 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_TXFLOW
: 0) |
693 AR8216_PORT_STATUS_DUPLEX
);
695 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
696 AR8216_PORT_STATUS_LINK_AUTO
);
700 static const struct ar8xxx_chip ar8216_chip
= {
701 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
703 .hw_init
= ar8216_hw_init
,
704 .init_globals
= ar8216_init_globals
,
705 .init_port
= ar8216_init_port
,
706 .setup_port
= ar8216_setup_port
,
707 .read_port_status
= ar8216_read_port_status
,
708 .atu_flush
= ar8216_atu_flush
,
709 .vtu_flush
= ar8216_vtu_flush
,
710 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
712 .num_mibs
= ARRAY_SIZE(ar8216_mibs
),
713 .mib_decs
= ar8216_mibs
,
717 ar8236_setup_port(struct ar8216_priv
*priv
, int port
, u32 egress
, u32 ingress
,
718 u32 members
, u32 pvid
)
720 ar8216_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
721 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
722 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
723 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
724 AR8216_PORT_CTRL_LEARN
|
725 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
726 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
728 ar8216_rmw(priv
, AR8236_REG_PORT_VLAN(port
),
729 AR8236_PORT_VLAN_DEFAULT_ID
,
730 (pvid
<< AR8236_PORT_VLAN_DEFAULT_ID_S
));
732 ar8216_rmw(priv
, AR8236_REG_PORT_VLAN2(port
),
733 AR8236_PORT_VLAN2_VLAN_MODE
|
734 AR8236_PORT_VLAN2_MEMBER
,
735 (ingress
<< AR8236_PORT_VLAN2_VLAN_MODE_S
) |
736 (members
<< AR8236_PORT_VLAN2_MEMBER_S
));
740 ar8236_hw_init(struct ar8216_priv
*priv
)
745 if (priv
->initialized
)
748 /* Initialize the PHYs */
750 for (i
= 0; i
< 5; i
++) {
751 mdiobus_write(bus
, i
, MII_ADVERTISE
,
752 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
|
753 ADVERTISE_PAUSE_ASYM
);
754 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
758 priv
->initialized
= true;
763 ar8236_init_globals(struct ar8216_priv
*priv
)
765 /* enable jumbo frames */
766 ar8216_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
767 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
769 /* Enable MIB counters */
770 ar8216_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
771 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
775 static const struct ar8xxx_chip ar8236_chip
= {
776 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
777 .hw_init
= ar8236_hw_init
,
778 .init_globals
= ar8236_init_globals
,
779 .init_port
= ar8216_init_port
,
780 .setup_port
= ar8236_setup_port
,
781 .read_port_status
= ar8216_read_port_status
,
782 .atu_flush
= ar8216_atu_flush
,
783 .vtu_flush
= ar8216_vtu_flush
,
784 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
786 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
787 .mib_decs
= ar8236_mibs
,
791 ar8316_hw_init(struct ar8216_priv
*priv
)
797 val
= priv
->read(priv
, AR8316_REG_POSTRIP
);
799 if (priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
800 if (priv
->port4_phy
) {
801 /* value taken from Ubiquiti RouterStation Pro */
803 pr_info("ar8316: Using port 4 as PHY\n");
806 pr_info("ar8316: Using port 4 as switch port\n");
808 } else if (priv
->phy
->interface
== PHY_INTERFACE_MODE_GMII
) {
809 /* value taken from AVM Fritz!Box 7390 sources */
812 /* no known value for phy interface */
813 pr_err("ar8316: unsupported mii mode: %d.\n",
814 priv
->phy
->interface
);
821 priv
->write(priv
, AR8316_REG_POSTRIP
, newval
);
823 /* Initialize the ports */
825 for (i
= 0; i
< 5; i
++) {
826 if ((i
== 4) && priv
->port4_phy
&&
827 priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
828 /* work around for phy4 rgmii mode */
829 ar8216_phy_dbg_write(priv
, i
, 0x12, 0x480c);
831 ar8216_phy_dbg_write(priv
, i
, 0x0, 0x824e);
833 ar8216_phy_dbg_write(priv
, i
, 0x5, 0x3d47);
837 /* initialize the port itself */
838 mdiobus_write(bus
, i
, MII_ADVERTISE
,
839 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
840 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
841 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
847 priv
->initialized
= true;
852 ar8316_init_globals(struct ar8216_priv
*priv
)
854 /* standard atheros magic */
855 priv
->write(priv
, 0x38, 0xc000050e);
857 /* enable cpu port to receive multicast and broadcast frames */
858 priv
->write(priv
, AR8216_REG_FLOOD_MASK
, 0x003f003f);
860 /* enable jumbo frames */
861 ar8216_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
862 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
864 /* Enable MIB counters */
865 ar8216_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
866 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
870 static const struct ar8xxx_chip ar8316_chip
= {
871 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
872 .hw_init
= ar8316_hw_init
,
873 .init_globals
= ar8316_init_globals
,
874 .init_port
= ar8216_init_port
,
875 .setup_port
= ar8216_setup_port
,
876 .read_port_status
= ar8216_read_port_status
,
877 .atu_flush
= ar8216_atu_flush
,
878 .vtu_flush
= ar8216_vtu_flush
,
879 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
881 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
882 .mib_decs
= ar8236_mibs
,
886 ar8327_get_pad_cfg(struct ar8327_pad_cfg
*cfg
)
898 case AR8327_PAD_MAC2MAC_MII
:
899 t
= AR8327_PAD_MAC_MII_EN
;
901 t
|= AR8327_PAD_MAC_MII_RXCLK_SEL
;
903 t
|= AR8327_PAD_MAC_MII_TXCLK_SEL
;
906 case AR8327_PAD_MAC2MAC_GMII
:
907 t
= AR8327_PAD_MAC_GMII_EN
;
909 t
|= AR8327_PAD_MAC_GMII_RXCLK_SEL
;
911 t
|= AR8327_PAD_MAC_GMII_TXCLK_SEL
;
914 case AR8327_PAD_MAC_SGMII
:
915 t
= AR8327_PAD_SGMII_EN
;
918 * WAR for the QUalcomm Atheros AP136 board.
919 * It seems that RGMII TX/RX delay settings needs to be
920 * applied for SGMII mode as well, The ethernet is not
921 * reliable without this.
923 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
924 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
925 if (cfg
->rxclk_delay_en
)
926 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
927 if (cfg
->txclk_delay_en
)
928 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
930 if (cfg
->sgmii_delay_en
)
931 t
|= AR8327_PAD_SGMII_DELAY_EN
;
935 case AR8327_PAD_MAC2PHY_MII
:
936 t
= AR8327_PAD_PHY_MII_EN
;
938 t
|= AR8327_PAD_PHY_MII_RXCLK_SEL
;
940 t
|= AR8327_PAD_PHY_MII_TXCLK_SEL
;
943 case AR8327_PAD_MAC2PHY_GMII
:
944 t
= AR8327_PAD_PHY_GMII_EN
;
945 if (cfg
->pipe_rxclk_sel
)
946 t
|= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL
;
948 t
|= AR8327_PAD_PHY_GMII_RXCLK_SEL
;
950 t
|= AR8327_PAD_PHY_GMII_TXCLK_SEL
;
953 case AR8327_PAD_MAC_RGMII
:
954 t
= AR8327_PAD_RGMII_EN
;
955 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
956 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
957 if (cfg
->rxclk_delay_en
)
958 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
959 if (cfg
->txclk_delay_en
)
960 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
963 case AR8327_PAD_PHY_GMII
:
964 t
= AR8327_PAD_PHYX_GMII_EN
;
967 case AR8327_PAD_PHY_RGMII
:
968 t
= AR8327_PAD_PHYX_RGMII_EN
;
971 case AR8327_PAD_PHY_MII
:
972 t
= AR8327_PAD_PHYX_MII_EN
;
980 ar8327_phy_fixup(struct ar8216_priv
*priv
, int phy
)
982 switch (priv
->chip_rev
) {
984 /* For 100M waveform */
985 ar8216_phy_dbg_write(priv
, phy
, 0, 0x02ea);
986 /* Turn on Gigabit clock */
987 ar8216_phy_dbg_write(priv
, phy
, 0x3d, 0x68a0);
991 ar8216_phy_mmd_write(priv
, phy
, 0x7, 0x3c);
992 ar8216_phy_mmd_write(priv
, phy
, 0x4007, 0x0);
995 ar8216_phy_mmd_write(priv
, phy
, 0x3, 0x800d);
996 ar8216_phy_mmd_write(priv
, phy
, 0x4003, 0x803f);
998 ar8216_phy_dbg_write(priv
, phy
, 0x3d, 0x6860);
999 ar8216_phy_dbg_write(priv
, phy
, 0x5, 0x2c46);
1000 ar8216_phy_dbg_write(priv
, phy
, 0x3c, 0x6000);
1006 ar8327_hw_init(struct ar8216_priv
*priv
)
1008 struct ar8327_platform_data
*pdata
;
1009 struct ar8327_led_cfg
*led_cfg
;
1010 struct mii_bus
*bus
;
1015 pdata
= priv
->phy
->dev
.platform_data
;
1019 t
= ar8327_get_pad_cfg(pdata
->pad0_cfg
);
1020 priv
->write(priv
, AR8327_REG_PAD0_MODE
, t
);
1021 t
= ar8327_get_pad_cfg(pdata
->pad5_cfg
);
1022 priv
->write(priv
, AR8327_REG_PAD5_MODE
, t
);
1023 t
= ar8327_get_pad_cfg(pdata
->pad6_cfg
);
1024 priv
->write(priv
, AR8327_REG_PAD6_MODE
, t
);
1026 pos
= priv
->read(priv
, AR8327_REG_POWER_ON_STRIP
);
1029 led_cfg
= pdata
->led_cfg
;
1031 if (led_cfg
->open_drain
)
1032 new_pos
|= AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
1034 new_pos
&= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
1036 priv
->write(priv
, AR8327_REG_LED_CTRL0
, led_cfg
->led_ctrl0
);
1037 priv
->write(priv
, AR8327_REG_LED_CTRL1
, led_cfg
->led_ctrl1
);
1038 priv
->write(priv
, AR8327_REG_LED_CTRL2
, led_cfg
->led_ctrl2
);
1039 priv
->write(priv
, AR8327_REG_LED_CTRL3
, led_cfg
->led_ctrl3
);
1042 if (new_pos
!= pos
) {
1043 new_pos
|= AR8327_POWER_ON_STRIP_POWER_ON_SEL
;
1044 priv
->write(priv
, AR8327_REG_POWER_ON_STRIP
, new_pos
);
1047 bus
= priv
->mii_bus
;
1048 for (i
= 0; i
< AR8327_NUM_PHYS
; i
++) {
1049 ar8327_phy_fixup(priv
, i
);
1051 /* start aneg on the PHY */
1052 mdiobus_write(bus
, i
, MII_ADVERTISE
, ADVERTISE_ALL
|
1053 ADVERTISE_PAUSE_CAP
|
1054 ADVERTISE_PAUSE_ASYM
);
1055 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
1056 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
1065 ar8327_init_globals(struct ar8216_priv
*priv
)
1069 /* enable CPU port and disable mirror port */
1070 t
= AR8327_FWD_CTRL0_CPU_PORT_EN
|
1071 AR8327_FWD_CTRL0_MIRROR_PORT
;
1072 priv
->write(priv
, AR8327_REG_FWD_CTRL0
, t
);
1074 /* forward multicast and broadcast frames to CPU */
1075 t
= (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_UC_FLOOD_S
) |
1076 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_MC_FLOOD_S
) |
1077 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_BC_FLOOD_S
);
1078 priv
->write(priv
, AR8327_REG_FWD_CTRL1
, t
);
1081 ar8216_rmw(priv
, AR8327_REG_MAX_FRAME_SIZE
,
1082 AR8327_MAX_FRAME_SIZE_MTU
, 1518 + 8 + 2);
1084 /* Enable MIB counters */
1085 ar8216_reg_set(priv
, AR8327_REG_MODULE_EN
,
1086 AR8327_MODULE_EN_MIB
);
1090 ar8327_config_port(struct ar8216_priv
*priv
, unsigned int port
,
1091 struct ar8327_port_cfg
*cfg
)
1095 if (!cfg
|| !cfg
->force_link
) {
1096 priv
->write(priv
, AR8327_REG_PORT_STATUS(port
),
1097 AR8216_PORT_STATUS_LINK_AUTO
);
1101 t
= AR8216_PORT_STATUS_TXMAC
| AR8216_PORT_STATUS_RXMAC
;
1102 t
|= cfg
->duplex
? AR8216_PORT_STATUS_DUPLEX
: 0;
1103 t
|= cfg
->rxpause
? AR8216_PORT_STATUS_RXFLOW
: 0;
1104 t
|= cfg
->txpause
? AR8216_PORT_STATUS_TXFLOW
: 0;
1106 switch (cfg
->speed
) {
1107 case AR8327_PORT_SPEED_10
:
1108 t
|= AR8216_PORT_SPEED_10M
;
1110 case AR8327_PORT_SPEED_100
:
1111 t
|= AR8216_PORT_SPEED_100M
;
1113 case AR8327_PORT_SPEED_1000
:
1114 t
|= AR8216_PORT_SPEED_1000M
;
1118 priv
->write(priv
, AR8327_REG_PORT_STATUS(port
), t
);
1122 ar8327_init_port(struct ar8216_priv
*priv
, int port
)
1124 struct ar8327_platform_data
*pdata
;
1125 struct ar8327_port_cfg
*cfg
;
1128 pdata
= priv
->phy
->dev
.platform_data
;
1130 if (pdata
&& port
== AR8216_PORT_CPU
)
1131 cfg
= &pdata
->port0_cfg
;
1132 else if (pdata
&& port
== 6)
1133 cfg
= &pdata
->port6_cfg
;
1137 ar8327_config_port(priv
, port
, cfg
);
1139 priv
->write(priv
, AR8327_REG_PORT_HEADER(port
), 0);
1141 t
= 1 << AR8327_PORT_VLAN0_DEF_SVID_S
;
1142 t
|= 1 << AR8327_PORT_VLAN0_DEF_CVID_S
;
1143 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
1145 t
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
1146 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
1148 t
= AR8327_PORT_LOOKUP_LEARN
;
1149 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
1150 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
1154 ar8327_read_port_status(struct ar8216_priv
*priv
, int port
)
1156 return priv
->read(priv
, AR8327_REG_PORT_STATUS(port
));
1160 ar8327_atu_flush(struct ar8216_priv
*priv
)
1164 ret
= ar8216_wait_bit(priv
, AR8327_REG_ATU_FUNC
,
1165 AR8327_ATU_FUNC_BUSY
, 0);
1167 priv
->write(priv
, AR8327_REG_ATU_FUNC
,
1168 AR8327_ATU_FUNC_OP_FLUSH
);
1174 ar8327_vtu_op(struct ar8216_priv
*priv
, u32 op
, u32 val
)
1176 if (ar8216_wait_bit(priv
, AR8327_REG_VTU_FUNC1
,
1177 AR8327_VTU_FUNC1_BUSY
, 0))
1180 if ((op
& AR8327_VTU_FUNC1_OP
) == AR8327_VTU_FUNC1_OP_LOAD
)
1181 priv
->write(priv
, AR8327_REG_VTU_FUNC0
, val
);
1183 op
|= AR8327_VTU_FUNC1_BUSY
;
1184 priv
->write(priv
, AR8327_REG_VTU_FUNC1
, op
);
1188 ar8327_vtu_flush(struct ar8216_priv
*priv
)
1190 ar8327_vtu_op(priv
, AR8327_VTU_FUNC1_OP_FLUSH
, 0);
1194 ar8327_vtu_load_vlan(struct ar8216_priv
*priv
, u32 vid
, u32 port_mask
)
1200 op
= AR8327_VTU_FUNC1_OP_LOAD
| (vid
<< AR8327_VTU_FUNC1_VID_S
);
1201 val
= AR8327_VTU_FUNC0_VALID
| AR8327_VTU_FUNC0_IVL
;
1202 for (i
= 0; i
< AR8327_NUM_PORTS
; i
++) {
1205 if ((port_mask
& BIT(i
)) == 0)
1206 mode
= AR8327_VTU_FUNC0_EG_MODE_NOT
;
1207 else if (priv
->vlan
== 0)
1208 mode
= AR8327_VTU_FUNC0_EG_MODE_KEEP
;
1209 else if (priv
->vlan_tagged
& BIT(i
))
1210 mode
= AR8327_VTU_FUNC0_EG_MODE_TAG
;
1212 mode
= AR8327_VTU_FUNC0_EG_MODE_UNTAG
;
1214 val
|= mode
<< AR8327_VTU_FUNC0_EG_MODE_S(i
);
1216 ar8327_vtu_op(priv
, op
, val
);
1220 ar8327_setup_port(struct ar8216_priv
*priv
, int port
, u32 egress
, u32 ingress
,
1221 u32 members
, u32 pvid
)
1226 t
= pvid
<< AR8327_PORT_VLAN0_DEF_SVID_S
;
1227 t
|= pvid
<< AR8327_PORT_VLAN0_DEF_CVID_S
;
1228 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
1230 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNMOD
;
1232 case AR8216_OUT_KEEP
:
1233 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
;
1235 case AR8216_OUT_STRIP_VLAN
:
1236 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNTAG
;
1238 case AR8216_OUT_ADD_VLAN
:
1239 mode
= AR8327_PORT_VLAN1_OUT_MODE_TAG
;
1243 t
= AR8327_PORT_VLAN1_PORT_VLAN_PROP
;
1244 t
|= mode
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
1245 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
1248 t
|= AR8327_PORT_LOOKUP_LEARN
;
1249 t
|= ingress
<< AR8327_PORT_LOOKUP_IN_MODE_S
;
1250 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
1251 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
1254 static const struct ar8xxx_chip ar8327_chip
= {
1255 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1256 .hw_init
= ar8327_hw_init
,
1257 .init_globals
= ar8327_init_globals
,
1258 .init_port
= ar8327_init_port
,
1259 .setup_port
= ar8327_setup_port
,
1260 .read_port_status
= ar8327_read_port_status
,
1261 .atu_flush
= ar8327_atu_flush
,
1262 .vtu_flush
= ar8327_vtu_flush
,
1263 .vtu_load_vlan
= ar8327_vtu_load_vlan
,
1265 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1266 .mib_decs
= ar8236_mibs
,
1270 ar8216_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1271 struct switch_val
*val
)
1273 struct ar8216_priv
*priv
= swdev_to_ar8216(dev
);
1274 priv
->vlan
= !!val
->value
.i
;
1279 ar8216_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1280 struct switch_val
*val
)
1282 struct ar8216_priv
*priv
= swdev_to_ar8216(dev
);
1283 val
->value
.i
= priv
->vlan
;
1289 ar8216_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
1291 struct ar8216_priv
*priv
= swdev_to_ar8216(dev
);
1293 /* make sure no invalid PVIDs get set */
1295 if (vlan
>= dev
->vlans
)
1298 priv
->pvid
[port
] = vlan
;
1303 ar8216_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
1305 struct ar8216_priv
*priv
= swdev_to_ar8216(dev
);
1306 *vlan
= priv
->pvid
[port
];
1311 ar8216_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1312 struct switch_val
*val
)
1314 struct ar8216_priv
*priv
= swdev_to_ar8216(dev
);
1315 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
1320 ar8216_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1321 struct switch_val
*val
)
1323 struct ar8216_priv
*priv
= swdev_to_ar8216(dev
);
1324 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
1329 ar8216_sw_get_port_link(struct switch_dev
*dev
, int port
,
1330 struct switch_port_link
*link
)
1332 struct ar8216_priv
*priv
= swdev_to_ar8216(dev
);
1334 ar8216_read_port_link(priv
, port
, link
);
1339 ar8216_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1341 struct ar8216_priv
*priv
= swdev_to_ar8216(dev
);
1342 u8 ports
= priv
->vlan_table
[val
->port_vlan
];
1346 for (i
= 0; i
< dev
->ports
; i
++) {
1347 struct switch_port
*p
;
1349 if (!(ports
& (1 << i
)))
1352 p
= &val
->value
.ports
[val
->len
++];
1354 if (priv
->vlan_tagged
& (1 << i
))
1355 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
1363 ar8216_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1365 struct ar8216_priv
*priv
= swdev_to_ar8216(dev
);
1366 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1370 for (i
= 0; i
< val
->len
; i
++) {
1371 struct switch_port
*p
= &val
->value
.ports
[i
];
1373 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
1374 priv
->vlan_tagged
|= (1 << p
->id
);
1376 priv
->vlan_tagged
&= ~(1 << p
->id
);
1377 priv
->pvid
[p
->id
] = val
->port_vlan
;
1379 /* make sure that an untagged port does not
1380 * appear in other vlans */
1381 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1382 if (j
== val
->port_vlan
)
1384 priv
->vlan_table
[j
] &= ~(1 << p
->id
);
1394 ar8216_sw_hw_apply(struct switch_dev
*dev
)
1396 struct ar8216_priv
*priv
= swdev_to_ar8216(dev
);
1397 u8 portmask
[AR8X16_MAX_PORTS
];
1400 mutex_lock(&priv
->reg_mutex
);
1401 /* flush all vlan translation unit entries */
1402 priv
->chip
->vtu_flush(priv
);
1404 memset(portmask
, 0, sizeof(portmask
));
1406 /* calculate the port destination masks and load vlans
1407 * into the vlan translation unit */
1408 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1409 u8 vp
= priv
->vlan_table
[j
];
1414 for (i
= 0; i
< dev
->ports
; i
++) {
1417 portmask
[i
] |= vp
& ~mask
;
1420 priv
->chip
->vtu_load_vlan(priv
, priv
->vlan_id
[j
],
1421 priv
->vlan_table
[j
]);
1425 * isolate all ports, but connect them to the cpu port */
1426 for (i
= 0; i
< dev
->ports
; i
++) {
1427 if (i
== AR8216_PORT_CPU
)
1430 portmask
[i
] = 1 << AR8216_PORT_CPU
;
1431 portmask
[AR8216_PORT_CPU
] |= (1 << i
);
1435 /* update the port destination mask registers and tag settings */
1436 for (i
= 0; i
< dev
->ports
; i
++) {
1437 int egress
, ingress
;
1441 pvid
= priv
->vlan_id
[priv
->pvid
[i
]];
1442 if (priv
->vlan_tagged
& (1 << i
))
1443 egress
= AR8216_OUT_ADD_VLAN
;
1445 egress
= AR8216_OUT_STRIP_VLAN
;
1446 ingress
= AR8216_IN_SECURE
;
1449 egress
= AR8216_OUT_KEEP
;
1450 ingress
= AR8216_IN_PORT_ONLY
;
1453 priv
->chip
->setup_port(priv
, i
, egress
, ingress
, portmask
[i
],
1456 mutex_unlock(&priv
->reg_mutex
);
1461 ar8216_sw_reset_switch(struct switch_dev
*dev
)
1463 struct ar8216_priv
*priv
= swdev_to_ar8216(dev
);
1466 mutex_lock(&priv
->reg_mutex
);
1467 memset(&priv
->vlan
, 0, sizeof(struct ar8216_priv
) -
1468 offsetof(struct ar8216_priv
, vlan
));
1470 for (i
= 0; i
< AR8X16_MAX_VLANS
; i
++)
1471 priv
->vlan_id
[i
] = i
;
1473 /* Configure all ports */
1474 for (i
= 0; i
< dev
->ports
; i
++)
1475 priv
->chip
->init_port(priv
, i
);
1477 priv
->chip
->init_globals(priv
);
1478 mutex_unlock(&priv
->reg_mutex
);
1480 return ar8216_sw_hw_apply(dev
);
1484 ar8216_sw_set_reset_mibs(struct switch_dev
*dev
,
1485 const struct switch_attr
*attr
,
1486 struct switch_val
*val
)
1488 struct ar8216_priv
*priv
= swdev_to_ar8216(dev
);
1492 if (!ar8xxx_has_mib_counters(priv
))
1495 mutex_lock(&priv
->mib_lock
);
1497 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1498 sizeof(*priv
->mib_stats
);
1499 memset(priv
->mib_stats
, '\0', len
);
1500 ret
= ar8216_mib_flush(priv
);
1507 mutex_unlock(&priv
->mib_lock
);
1512 ar8216_sw_set_port_reset_mib(struct switch_dev
*dev
,
1513 const struct switch_attr
*attr
,
1514 struct switch_val
*val
)
1516 struct ar8216_priv
*priv
= swdev_to_ar8216(dev
);
1520 if (!ar8xxx_has_mib_counters(priv
))
1523 port
= val
->port_vlan
;
1524 if (port
>= dev
->ports
)
1527 mutex_lock(&priv
->mib_lock
);
1528 ret
= ar8216_mib_capture(priv
);
1532 ar8216_mib_fetch_port_stat(priv
, port
, true);
1537 mutex_unlock(&priv
->mib_lock
);
1542 ar8216_sw_get_port_mib(struct switch_dev
*dev
,
1543 const struct switch_attr
*attr
,
1544 struct switch_val
*val
)
1546 struct ar8216_priv
*priv
= swdev_to_ar8216(dev
);
1547 const struct ar8xxx_chip
*chip
= priv
->chip
;
1551 char *buf
= priv
->buf
;
1554 if (!ar8xxx_has_mib_counters(priv
))
1557 port
= val
->port_vlan
;
1558 if (port
>= dev
->ports
)
1561 mutex_lock(&priv
->mib_lock
);
1562 ret
= ar8216_mib_capture(priv
);
1566 ar8216_mib_fetch_port_stat(priv
, port
, false);
1568 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1569 "Port %d MIB counters\n",
1572 mib_stats
= &priv
->mib_stats
[port
* chip
->num_mibs
];
1573 for (i
= 0; i
< chip
->num_mibs
; i
++)
1574 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1576 chip
->mib_decs
[i
].name
,
1585 mutex_unlock(&priv
->mib_lock
);
1589 static struct switch_attr ar8216_globals
[] = {
1591 .type
= SWITCH_TYPE_INT
,
1592 .name
= "enable_vlan",
1593 .description
= "Enable VLAN mode",
1594 .set
= ar8216_sw_set_vlan
,
1595 .get
= ar8216_sw_get_vlan
,
1599 .type
= SWITCH_TYPE_NOVAL
,
1600 .name
= "reset_mibs",
1601 .description
= "Reset all MIB counters",
1602 .set
= ar8216_sw_set_reset_mibs
,
1607 static struct switch_attr ar8216_port
[] = {
1609 .type
= SWITCH_TYPE_NOVAL
,
1610 .name
= "reset_mib",
1611 .description
= "Reset single port MIB counters",
1612 .set
= ar8216_sw_set_port_reset_mib
,
1615 .type
= SWITCH_TYPE_STRING
,
1617 .description
= "Get port's MIB counters",
1619 .get
= ar8216_sw_get_port_mib
,
1623 static struct switch_attr ar8216_vlan
[] = {
1625 .type
= SWITCH_TYPE_INT
,
1627 .description
= "VLAN ID (0-4094)",
1628 .set
= ar8216_sw_set_vid
,
1629 .get
= ar8216_sw_get_vid
,
1634 static const struct switch_dev_ops ar8216_sw_ops
= {
1636 .attr
= ar8216_globals
,
1637 .n_attr
= ARRAY_SIZE(ar8216_globals
),
1640 .attr
= ar8216_port
,
1641 .n_attr
= ARRAY_SIZE(ar8216_port
),
1644 .attr
= ar8216_vlan
,
1645 .n_attr
= ARRAY_SIZE(ar8216_vlan
),
1647 .get_port_pvid
= ar8216_sw_get_pvid
,
1648 .set_port_pvid
= ar8216_sw_set_pvid
,
1649 .get_vlan_ports
= ar8216_sw_get_ports
,
1650 .set_vlan_ports
= ar8216_sw_set_ports
,
1651 .apply_config
= ar8216_sw_hw_apply
,
1652 .reset_switch
= ar8216_sw_reset_switch
,
1653 .get_port_link
= ar8216_sw_get_port_link
,
1657 ar8216_id_chip(struct ar8216_priv
*priv
)
1663 val
= priv
->read(priv
, AR8216_REG_CTRL
);
1667 id
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1668 for (i
= 0; i
< AR8X16_PROBE_RETRIES
; i
++) {
1671 val
= priv
->read(priv
, AR8216_REG_CTRL
);
1675 t
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1680 priv
->chip_ver
= (id
& AR8216_CTRL_VERSION
) >> AR8216_CTRL_VERSION_S
;
1681 priv
->chip_rev
= (id
& AR8216_CTRL_REVISION
);
1683 switch (priv
->chip_ver
) {
1684 case AR8XXX_VER_AR8216
:
1685 priv
->chip
= &ar8216_chip
;
1687 case AR8XXX_VER_AR8236
:
1688 priv
->chip
= &ar8236_chip
;
1690 case AR8XXX_VER_AR8316
:
1691 priv
->chip
= &ar8316_chip
;
1693 case AR8XXX_VER_AR8327
:
1694 priv
->mii_lo_first
= true;
1695 priv
->chip
= &ar8327_chip
;
1698 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1699 priv
->chip_ver
, priv
->chip_rev
);
1708 ar8xxx_mib_work_func(struct work_struct
*work
)
1710 struct ar8216_priv
*priv
;
1713 priv
= container_of(work
, struct ar8216_priv
, mib_work
.work
);
1715 mutex_lock(&priv
->mib_lock
);
1717 err
= ar8216_mib_capture(priv
);
1721 ar8216_mib_fetch_port_stat(priv
, priv
->mib_next_port
, false);
1724 priv
->mib_next_port
++;
1725 if (priv
->mib_next_port
>= priv
->dev
.ports
)
1726 priv
->mib_next_port
= 0;
1728 mutex_unlock(&priv
->mib_lock
);
1729 schedule_delayed_work(&priv
->mib_work
,
1730 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
1734 ar8xxx_mib_init(struct ar8216_priv
*priv
)
1738 if (!ar8xxx_has_mib_counters(priv
))
1741 BUG_ON(!priv
->chip
->mib_decs
|| !priv
->chip
->num_mibs
);
1743 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1744 sizeof(*priv
->mib_stats
);
1745 priv
->mib_stats
= kzalloc(len
, GFP_KERNEL
);
1747 if (!priv
->mib_stats
)
1754 ar8xxx_mib_start(struct ar8216_priv
*priv
)
1756 if (!ar8xxx_has_mib_counters(priv
))
1759 schedule_delayed_work(&priv
->mib_work
,
1760 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
1764 ar8xxx_mib_stop(struct ar8216_priv
*priv
)
1766 if (!ar8xxx_has_mib_counters(priv
))
1769 cancel_delayed_work(&priv
->mib_work
);
1772 static struct ar8216_priv
*
1775 struct ar8216_priv
*priv
;
1777 priv
= kzalloc(sizeof(struct ar8216_priv
), GFP_KERNEL
);
1781 mutex_init(&priv
->reg_mutex
);
1782 mutex_init(&priv
->mib_lock
);
1783 INIT_DELAYED_WORK(&priv
->mib_work
, ar8xxx_mib_work_func
);
1789 ar8xxx_free(struct ar8216_priv
*priv
)
1791 kfree(priv
->mib_stats
);
1795 static struct ar8216_priv
*
1796 ar8xxx_create_mii(struct mii_bus
*bus
)
1798 struct ar8216_priv
*priv
;
1800 priv
= ar8xxx_create();
1802 priv
->mii_bus
= bus
;
1803 priv
->read
= ar8216_mii_read
;
1804 priv
->write
= ar8216_mii_write
;
1811 ar8xxx_probe_switch(struct ar8216_priv
*priv
)
1813 struct switch_dev
*swdev
;
1816 ret
= ar8216_id_chip(priv
);
1821 swdev
->cpu_port
= AR8216_PORT_CPU
;
1822 swdev
->ops
= &ar8216_sw_ops
;
1824 if (chip_is_ar8316(priv
)) {
1825 swdev
->name
= "Atheros AR8316";
1826 swdev
->vlans
= AR8X16_MAX_VLANS
;
1827 swdev
->ports
= AR8216_NUM_PORTS
;
1828 } else if (chip_is_ar8236(priv
)) {
1829 swdev
->name
= "Atheros AR8236";
1830 swdev
->vlans
= AR8216_NUM_VLANS
;
1831 swdev
->ports
= AR8216_NUM_PORTS
;
1832 } else if (chip_is_ar8327(priv
)) {
1833 swdev
->name
= "Atheros AR8327";
1834 swdev
->vlans
= AR8X16_MAX_VLANS
;
1835 swdev
->ports
= AR8327_NUM_PORTS
;
1837 swdev
->name
= "Atheros AR8216";
1838 swdev
->vlans
= AR8216_NUM_VLANS
;
1839 swdev
->ports
= AR8216_NUM_PORTS
;
1842 ret
= ar8xxx_mib_init(priv
);
1850 ar8216_config_init(struct phy_device
*phydev
)
1852 struct ar8216_priv
*priv
= phydev
->priv
;
1853 struct net_device
*dev
= phydev
->attached_dev
;
1854 struct switch_dev
*swdev
;
1862 if (phydev
->addr
!= 0) {
1863 if (chip_is_ar8316(priv
)) {
1864 /* check if we're attaching to the switch twice */
1865 phydev
= phydev
->bus
->phy_map
[0];
1869 /* switch device has not been initialized, reuse priv */
1870 if (!phydev
->priv
) {
1871 priv
->port4_phy
= true;
1872 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
1876 /* switch device has been initialized, reinit */
1877 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
1878 priv
->initialized
= false;
1879 priv
->port4_phy
= true;
1880 ar8316_hw_init(priv
);
1888 ret
= register_switch(swdev
, phydev
->attached_dev
);
1892 pr_info("%s: %s switch driver attached.\n",
1893 phydev
->attached_dev
->name
, swdev
->name
);
1897 ret
= priv
->chip
->hw_init(priv
);
1899 goto err_unregister_switch
;
1901 ret
= ar8216_sw_reset_switch(&priv
->dev
);
1903 goto err_unregister_switch
;
1905 /* VID fixup only needed on ar8216 */
1906 if (chip_is_ar8216(priv
)) {
1907 dev
->phy_ptr
= priv
;
1908 dev
->priv_flags
|= IFF_NO_IP_ALIGN
;
1909 dev
->eth_mangle_rx
= ar8216_mangle_rx
;
1910 dev
->eth_mangle_tx
= ar8216_mangle_tx
;
1915 ar8xxx_mib_start(priv
);
1919 err_unregister_switch
:
1920 unregister_switch(&priv
->dev
);
1926 ar8216_read_status(struct phy_device
*phydev
)
1928 struct ar8216_priv
*priv
= phydev
->priv
;
1929 struct switch_port_link link
;
1932 if (phydev
->addr
!= 0)
1933 return genphy_read_status(phydev
);
1935 ar8216_read_port_link(priv
, phydev
->addr
, &link
);
1936 phydev
->link
= !!link
.link
;
1940 switch (link
.speed
) {
1941 case SWITCH_PORT_SPEED_10
:
1942 phydev
->speed
= SPEED_10
;
1944 case SWITCH_PORT_SPEED_100
:
1945 phydev
->speed
= SPEED_100
;
1947 case SWITCH_PORT_SPEED_1000
:
1948 phydev
->speed
= SPEED_1000
;
1953 phydev
->duplex
= link
.duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
1955 /* flush the address translation unit */
1956 mutex_lock(&priv
->reg_mutex
);
1957 ret
= priv
->chip
->atu_flush(priv
);
1958 mutex_unlock(&priv
->reg_mutex
);
1960 phydev
->state
= PHY_RUNNING
;
1961 netif_carrier_on(phydev
->attached_dev
);
1962 phydev
->adjust_link(phydev
->attached_dev
);
1968 ar8216_config_aneg(struct phy_device
*phydev
)
1970 if (phydev
->addr
== 0)
1973 return genphy_config_aneg(phydev
);
1976 static const u32 ar8xxx_phy_ids
[] = {
1983 ar8xxx_phy_match(u32 phy_id
)
1987 for (i
= 0; i
< ARRAY_SIZE(ar8xxx_phy_ids
); i
++)
1988 if (phy_id
== ar8xxx_phy_ids
[i
])
1995 ar8xxx_is_possible(struct mii_bus
*bus
)
1999 for (i
= 0; i
< 4; i
++) {
2002 phy_id
= mdiobus_read(bus
, i
, MII_PHYSID1
) << 16;
2003 phy_id
|= mdiobus_read(bus
, i
, MII_PHYSID2
);
2004 if (!ar8xxx_phy_match(phy_id
)) {
2005 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2006 dev_name(&bus
->dev
), i
, phy_id
);
2015 ar8216_probe(struct phy_device
*phydev
)
2017 struct ar8216_priv
*priv
;
2020 /* skip PHYs at unused adresses */
2021 if (phydev
->addr
!= 0 && phydev
->addr
!= 4)
2024 if (!ar8xxx_is_possible(phydev
->bus
))
2027 mutex_lock(&ar8xxx_dev_list_lock
);
2028 list_for_each_entry(priv
, &ar8xxx_dev_list
, list
)
2029 if (priv
->mii_bus
== phydev
->bus
)
2032 priv
= ar8xxx_create_mii(phydev
->bus
);
2038 ret
= ar8xxx_probe_switch(priv
);
2043 if (phydev
->addr
== 0) {
2044 if (ar8xxx_has_gige(priv
)) {
2045 phydev
->supported
= SUPPORTED_1000baseT_Full
;
2046 phydev
->advertising
= ADVERTISED_1000baseT_Full
;
2048 phydev
->supported
= SUPPORTED_100baseT_Full
;
2049 phydev
->advertising
= ADVERTISED_100baseT_Full
;
2052 if (ar8xxx_has_gige(priv
)) {
2053 phydev
->supported
|= SUPPORTED_1000baseT_Full
;
2054 phydev
->advertising
|= ADVERTISED_1000baseT_Full
;
2058 phydev
->priv
= priv
;
2061 list_add(&priv
->list
, &ar8xxx_dev_list
);
2063 mutex_unlock(&ar8xxx_dev_list_lock
);
2070 mutex_unlock(&ar8xxx_dev_list_lock
);
2075 ar8216_detach(struct phy_device
*phydev
)
2077 struct net_device
*dev
= phydev
->attached_dev
;
2082 dev
->phy_ptr
= NULL
;
2083 dev
->priv_flags
&= ~IFF_NO_IP_ALIGN
;
2084 dev
->eth_mangle_rx
= NULL
;
2085 dev
->eth_mangle_tx
= NULL
;
2089 ar8216_remove(struct phy_device
*phydev
)
2091 struct ar8216_priv
*priv
= phydev
->priv
;
2096 phydev
->priv
= NULL
;
2097 if (--priv
->use_count
> 0)
2100 mutex_lock(&ar8xxx_dev_list_lock
);
2101 list_del(&priv
->list
);
2102 mutex_unlock(&ar8xxx_dev_list_lock
);
2104 unregister_switch(&priv
->dev
);
2105 ar8xxx_mib_stop(priv
);
2109 static struct phy_driver ar8216_driver
= {
2110 .phy_id
= 0x004d0000,
2111 .name
= "Atheros AR8216/AR8236/AR8316",
2112 .phy_id_mask
= 0xffff0000,
2113 .features
= PHY_BASIC_FEATURES
,
2114 .probe
= ar8216_probe
,
2115 .remove
= ar8216_remove
,
2116 .detach
= ar8216_detach
,
2117 .config_init
= &ar8216_config_init
,
2118 .config_aneg
= &ar8216_config_aneg
,
2119 .read_status
= &ar8216_read_status
,
2120 .driver
= { .owner
= THIS_MODULE
},
2126 return phy_driver_register(&ar8216_driver
);
2132 phy_driver_unregister(&ar8216_driver
);
2135 module_init(ar8216_init
);
2136 module_exit(ar8216_exit
);
2137 MODULE_LICENSE("GPL");