2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/of_device.h>
37 #include <linux/leds.h>
38 #include <linux/gpio.h>
39 #include <linux/version.h>
43 /* size of the vlan table */
44 #define AR8X16_MAX_VLANS 128
45 #define AR8X16_PROBE_RETRIES 10
46 #define AR8X16_MAX_PORTS 8
48 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
52 #define AR8XXX_CAP_GIGE BIT(0)
53 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
55 #define AR8XXX_NUM_PHYS 5
58 AR8XXX_VER_AR8216
= 0x01,
59 AR8XXX_VER_AR8236
= 0x03,
60 AR8XXX_VER_AR8316
= 0x10,
61 AR8XXX_VER_AR8327
= 0x12,
62 AR8XXX_VER_AR8337
= 0x13,
65 struct ar8xxx_mib_desc
{
74 int (*hw_init
)(struct ar8xxx_priv
*priv
);
75 void (*cleanup
)(struct ar8xxx_priv
*priv
);
77 void (*init_globals
)(struct ar8xxx_priv
*priv
);
78 void (*init_port
)(struct ar8xxx_priv
*priv
, int port
);
79 void (*setup_port
)(struct ar8xxx_priv
*priv
, int port
, u32 members
);
80 u32 (*read_port_status
)(struct ar8xxx_priv
*priv
, int port
);
81 int (*atu_flush
)(struct ar8xxx_priv
*priv
);
82 void (*vtu_flush
)(struct ar8xxx_priv
*priv
);
83 void (*vtu_load_vlan
)(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
);
84 void (*phy_fixup
)(struct ar8xxx_priv
*priv
, int phy
);
86 const struct ar8xxx_mib_desc
*mib_decs
;
90 enum ar8327_led_pattern
{
91 AR8327_LED_PATTERN_OFF
= 0,
92 AR8327_LED_PATTERN_BLINK
,
93 AR8327_LED_PATTERN_ON
,
94 AR8327_LED_PATTERN_RULE
,
97 struct ar8327_led_entry
{
103 struct led_classdev cdev
;
104 struct ar8xxx_priv
*sw_priv
;
109 enum ar8327_led_mode mode
;
113 struct work_struct led_work
;
115 enum ar8327_led_pattern pattern
;
122 struct ar8327_led
**leds
;
123 unsigned int num_leds
;
127 struct switch_dev dev
;
128 struct mii_bus
*mii_bus
;
129 struct phy_device
*phy
;
131 u32 (*read
)(struct ar8xxx_priv
*priv
, int reg
);
132 void (*write
)(struct ar8xxx_priv
*priv
, int reg
, u32 val
);
133 u32 (*rmw
)(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
);
135 int (*get_port_link
)(unsigned port
);
137 const struct net_device_ops
*ndo_old
;
138 struct net_device_ops ndo
;
139 struct mutex reg_mutex
;
142 const struct ar8xxx_chip
*chip
;
144 struct ar8327_data ar8327
;
153 struct mutex mib_lock
;
154 struct delayed_work mib_work
;
158 struct list_head list
;
159 unsigned int use_count
;
161 /* all fields below are cleared on reset */
163 u16 vlan_id
[AR8X16_MAX_VLANS
];
164 u8 vlan_table
[AR8X16_MAX_VLANS
];
166 u16 pvid
[AR8X16_MAX_PORTS
];
175 #define MIB_DESC(_s , _o, _n) \
182 static const struct ar8xxx_mib_desc ar8216_mibs
[] = {
183 MIB_DESC(1, AR8216_STATS_RXBROAD
, "RxBroad"),
184 MIB_DESC(1, AR8216_STATS_RXPAUSE
, "RxPause"),
185 MIB_DESC(1, AR8216_STATS_RXMULTI
, "RxMulti"),
186 MIB_DESC(1, AR8216_STATS_RXFCSERR
, "RxFcsErr"),
187 MIB_DESC(1, AR8216_STATS_RXALIGNERR
, "RxAlignErr"),
188 MIB_DESC(1, AR8216_STATS_RXRUNT
, "RxRunt"),
189 MIB_DESC(1, AR8216_STATS_RXFRAGMENT
, "RxFragment"),
190 MIB_DESC(1, AR8216_STATS_RX64BYTE
, "Rx64Byte"),
191 MIB_DESC(1, AR8216_STATS_RX128BYTE
, "Rx128Byte"),
192 MIB_DESC(1, AR8216_STATS_RX256BYTE
, "Rx256Byte"),
193 MIB_DESC(1, AR8216_STATS_RX512BYTE
, "Rx512Byte"),
194 MIB_DESC(1, AR8216_STATS_RX1024BYTE
, "Rx1024Byte"),
195 MIB_DESC(1, AR8216_STATS_RXMAXBYTE
, "RxMaxByte"),
196 MIB_DESC(1, AR8216_STATS_RXTOOLONG
, "RxTooLong"),
197 MIB_DESC(2, AR8216_STATS_RXGOODBYTE
, "RxGoodByte"),
198 MIB_DESC(2, AR8216_STATS_RXBADBYTE
, "RxBadByte"),
199 MIB_DESC(1, AR8216_STATS_RXOVERFLOW
, "RxOverFlow"),
200 MIB_DESC(1, AR8216_STATS_FILTERED
, "Filtered"),
201 MIB_DESC(1, AR8216_STATS_TXBROAD
, "TxBroad"),
202 MIB_DESC(1, AR8216_STATS_TXPAUSE
, "TxPause"),
203 MIB_DESC(1, AR8216_STATS_TXMULTI
, "TxMulti"),
204 MIB_DESC(1, AR8216_STATS_TXUNDERRUN
, "TxUnderRun"),
205 MIB_DESC(1, AR8216_STATS_TX64BYTE
, "Tx64Byte"),
206 MIB_DESC(1, AR8216_STATS_TX128BYTE
, "Tx128Byte"),
207 MIB_DESC(1, AR8216_STATS_TX256BYTE
, "Tx256Byte"),
208 MIB_DESC(1, AR8216_STATS_TX512BYTE
, "Tx512Byte"),
209 MIB_DESC(1, AR8216_STATS_TX1024BYTE
, "Tx1024Byte"),
210 MIB_DESC(1, AR8216_STATS_TXMAXBYTE
, "TxMaxByte"),
211 MIB_DESC(1, AR8216_STATS_TXOVERSIZE
, "TxOverSize"),
212 MIB_DESC(2, AR8216_STATS_TXBYTE
, "TxByte"),
213 MIB_DESC(1, AR8216_STATS_TXCOLLISION
, "TxCollision"),
214 MIB_DESC(1, AR8216_STATS_TXABORTCOL
, "TxAbortCol"),
215 MIB_DESC(1, AR8216_STATS_TXMULTICOL
, "TxMultiCol"),
216 MIB_DESC(1, AR8216_STATS_TXSINGLECOL
, "TxSingleCol"),
217 MIB_DESC(1, AR8216_STATS_TXEXCDEFER
, "TxExcDefer"),
218 MIB_DESC(1, AR8216_STATS_TXDEFER
, "TxDefer"),
219 MIB_DESC(1, AR8216_STATS_TXLATECOL
, "TxLateCol"),
222 static const struct ar8xxx_mib_desc ar8236_mibs
[] = {
223 MIB_DESC(1, AR8236_STATS_RXBROAD
, "RxBroad"),
224 MIB_DESC(1, AR8236_STATS_RXPAUSE
, "RxPause"),
225 MIB_DESC(1, AR8236_STATS_RXMULTI
, "RxMulti"),
226 MIB_DESC(1, AR8236_STATS_RXFCSERR
, "RxFcsErr"),
227 MIB_DESC(1, AR8236_STATS_RXALIGNERR
, "RxAlignErr"),
228 MIB_DESC(1, AR8236_STATS_RXRUNT
, "RxRunt"),
229 MIB_DESC(1, AR8236_STATS_RXFRAGMENT
, "RxFragment"),
230 MIB_DESC(1, AR8236_STATS_RX64BYTE
, "Rx64Byte"),
231 MIB_DESC(1, AR8236_STATS_RX128BYTE
, "Rx128Byte"),
232 MIB_DESC(1, AR8236_STATS_RX256BYTE
, "Rx256Byte"),
233 MIB_DESC(1, AR8236_STATS_RX512BYTE
, "Rx512Byte"),
234 MIB_DESC(1, AR8236_STATS_RX1024BYTE
, "Rx1024Byte"),
235 MIB_DESC(1, AR8236_STATS_RX1518BYTE
, "Rx1518Byte"),
236 MIB_DESC(1, AR8236_STATS_RXMAXBYTE
, "RxMaxByte"),
237 MIB_DESC(1, AR8236_STATS_RXTOOLONG
, "RxTooLong"),
238 MIB_DESC(2, AR8236_STATS_RXGOODBYTE
, "RxGoodByte"),
239 MIB_DESC(2, AR8236_STATS_RXBADBYTE
, "RxBadByte"),
240 MIB_DESC(1, AR8236_STATS_RXOVERFLOW
, "RxOverFlow"),
241 MIB_DESC(1, AR8236_STATS_FILTERED
, "Filtered"),
242 MIB_DESC(1, AR8236_STATS_TXBROAD
, "TxBroad"),
243 MIB_DESC(1, AR8236_STATS_TXPAUSE
, "TxPause"),
244 MIB_DESC(1, AR8236_STATS_TXMULTI
, "TxMulti"),
245 MIB_DESC(1, AR8236_STATS_TXUNDERRUN
, "TxUnderRun"),
246 MIB_DESC(1, AR8236_STATS_TX64BYTE
, "Tx64Byte"),
247 MIB_DESC(1, AR8236_STATS_TX128BYTE
, "Tx128Byte"),
248 MIB_DESC(1, AR8236_STATS_TX256BYTE
, "Tx256Byte"),
249 MIB_DESC(1, AR8236_STATS_TX512BYTE
, "Tx512Byte"),
250 MIB_DESC(1, AR8236_STATS_TX1024BYTE
, "Tx1024Byte"),
251 MIB_DESC(1, AR8236_STATS_TX1518BYTE
, "Tx1518Byte"),
252 MIB_DESC(1, AR8236_STATS_TXMAXBYTE
, "TxMaxByte"),
253 MIB_DESC(1, AR8236_STATS_TXOVERSIZE
, "TxOverSize"),
254 MIB_DESC(2, AR8236_STATS_TXBYTE
, "TxByte"),
255 MIB_DESC(1, AR8236_STATS_TXCOLLISION
, "TxCollision"),
256 MIB_DESC(1, AR8236_STATS_TXABORTCOL
, "TxAbortCol"),
257 MIB_DESC(1, AR8236_STATS_TXMULTICOL
, "TxMultiCol"),
258 MIB_DESC(1, AR8236_STATS_TXSINGLECOL
, "TxSingleCol"),
259 MIB_DESC(1, AR8236_STATS_TXEXCDEFER
, "TxExcDefer"),
260 MIB_DESC(1, AR8236_STATS_TXDEFER
, "TxDefer"),
261 MIB_DESC(1, AR8236_STATS_TXLATECOL
, "TxLateCol"),
264 static DEFINE_MUTEX(ar8xxx_dev_list_lock
);
265 static LIST_HEAD(ar8xxx_dev_list
);
267 static inline struct ar8xxx_priv
*
268 swdev_to_ar8xxx(struct switch_dev
*swdev
)
270 return container_of(swdev
, struct ar8xxx_priv
, dev
);
273 static inline bool ar8xxx_has_gige(struct ar8xxx_priv
*priv
)
275 return priv
->chip
->caps
& AR8XXX_CAP_GIGE
;
278 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv
*priv
)
280 return priv
->chip
->caps
& AR8XXX_CAP_MIB_COUNTERS
;
283 static inline bool chip_is_ar8216(struct ar8xxx_priv
*priv
)
285 return priv
->chip_ver
== AR8XXX_VER_AR8216
;
288 static inline bool chip_is_ar8236(struct ar8xxx_priv
*priv
)
290 return priv
->chip_ver
== AR8XXX_VER_AR8236
;
293 static inline bool chip_is_ar8316(struct ar8xxx_priv
*priv
)
295 return priv
->chip_ver
== AR8XXX_VER_AR8316
;
298 static inline bool chip_is_ar8327(struct ar8xxx_priv
*priv
)
300 return priv
->chip_ver
== AR8XXX_VER_AR8327
;
303 static inline bool chip_is_ar8337(struct ar8xxx_priv
*priv
)
305 return priv
->chip_ver
== AR8XXX_VER_AR8337
;
309 split_addr(u32 regaddr
, u16
*r1
, u16
*r2
, u16
*page
)
312 *r1
= regaddr
& 0x1e;
318 *page
= regaddr
& 0x1ff;
321 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
323 ar8xxx_phy_poll_reset(struct mii_bus
*bus
)
325 unsigned int sleep_msecs
= 20;
328 for (elapsed
= sleep_msecs
; elapsed
<= 600;
329 elapsed
+= sleep_msecs
) {
331 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
332 ret
= mdiobus_read(bus
, i
, MII_BMCR
);
335 if (ret
& BMCR_RESET
)
337 if (i
== AR8XXX_NUM_PHYS
- 1) {
338 usleep_range(1000, 2000);
347 ar8xxx_phy_check_aneg(struct phy_device
*phydev
)
351 if (phydev
->autoneg
!= AUTONEG_ENABLE
)
354 * BMCR_ANENABLE might have been cleared
355 * by phy_init_hw in certain kernel versions
356 * therefore check for it
358 ret
= phy_read(phydev
, MII_BMCR
);
361 if (ret
& BMCR_ANENABLE
)
364 dev_info(&phydev
->dev
, "ANEG disabled, re-enabling ...\n");
365 ret
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
366 return phy_write(phydev
, MII_BMCR
, ret
);
370 ar8xxx_phy_init(struct ar8xxx_priv
*priv
)
376 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
377 if (priv
->chip
->phy_fixup
)
378 priv
->chip
->phy_fixup(priv
, i
);
380 /* initialize the port itself */
381 mdiobus_write(bus
, i
, MII_ADVERTISE
,
382 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
383 if (ar8xxx_has_gige(priv
))
384 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
385 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
388 ar8xxx_phy_poll_reset(bus
);
392 ar8xxx_mii_read(struct ar8xxx_priv
*priv
, int reg
)
394 struct mii_bus
*bus
= priv
->mii_bus
;
398 split_addr((u32
) reg
, &r1
, &r2
, &page
);
400 mutex_lock(&bus
->mdio_lock
);
402 bus
->write(bus
, 0x18, 0, page
);
403 usleep_range(1000, 2000); /* wait for the page switch to propagate */
404 lo
= bus
->read(bus
, 0x10 | r2
, r1
);
405 hi
= bus
->read(bus
, 0x10 | r2
, r1
+ 1);
407 mutex_unlock(&bus
->mdio_lock
);
409 return (hi
<< 16) | lo
;
413 ar8xxx_mii_write(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
415 struct mii_bus
*bus
= priv
->mii_bus
;
419 split_addr((u32
) reg
, &r1
, &r2
, &r3
);
421 hi
= (u16
) (val
>> 16);
423 mutex_lock(&bus
->mdio_lock
);
425 bus
->write(bus
, 0x18, 0, r3
);
426 usleep_range(1000, 2000); /* wait for the page switch to propagate */
427 if (priv
->mii_lo_first
) {
428 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
429 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
431 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
432 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
435 mutex_unlock(&bus
->mdio_lock
);
439 ar8xxx_mii_rmw(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
441 struct mii_bus
*bus
= priv
->mii_bus
;
446 split_addr((u32
) reg
, &r1
, &r2
, &page
);
448 mutex_lock(&bus
->mdio_lock
);
450 bus
->write(bus
, 0x18, 0, page
);
451 usleep_range(1000, 2000); /* wait for the page switch to propagate */
453 lo
= bus
->read(bus
, 0x10 | r2
, r1
);
454 hi
= bus
->read(bus
, 0x10 | r2
, r1
+ 1);
461 hi
= (u16
) (ret
>> 16);
463 if (priv
->mii_lo_first
) {
464 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
465 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
467 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
468 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
471 mutex_unlock(&bus
->mdio_lock
);
478 ar8xxx_phy_dbg_write(struct ar8xxx_priv
*priv
, int phy_addr
,
479 u16 dbg_addr
, u16 dbg_data
)
481 struct mii_bus
*bus
= priv
->mii_bus
;
483 mutex_lock(&bus
->mdio_lock
);
484 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
485 bus
->write(bus
, phy_addr
, MII_ATH_DBG_DATA
, dbg_data
);
486 mutex_unlock(&bus
->mdio_lock
);
490 ar8xxx_phy_mmd_write(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 data
)
492 struct mii_bus
*bus
= priv
->mii_bus
;
494 mutex_lock(&bus
->mdio_lock
);
495 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
496 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, data
);
497 mutex_unlock(&bus
->mdio_lock
);
501 ar8xxx_rmw(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
503 return priv
->rmw(priv
, reg
, mask
, val
);
507 ar8xxx_reg_set(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
509 priv
->rmw(priv
, reg
, 0, val
);
513 ar8xxx_reg_wait(struct ar8xxx_priv
*priv
, u32 reg
, u32 mask
, u32 val
,
518 for (i
= 0; i
< timeout
; i
++) {
521 t
= priv
->read(priv
, reg
);
522 if ((t
& mask
) == val
)
525 usleep_range(1000, 2000);
532 ar8xxx_mib_op(struct ar8xxx_priv
*priv
, u32 op
)
537 lockdep_assert_held(&priv
->mib_lock
);
539 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
))
540 mib_func
= AR8327_REG_MIB_FUNC
;
542 mib_func
= AR8216_REG_MIB_FUNC
;
544 /* Capture the hardware statistics for all ports */
545 ar8xxx_rmw(priv
, mib_func
, AR8216_MIB_FUNC
, (op
<< AR8216_MIB_FUNC_S
));
547 /* Wait for the capturing to complete. */
548 ret
= ar8xxx_reg_wait(priv
, mib_func
, AR8216_MIB_BUSY
, 0, 10);
559 ar8xxx_mib_capture(struct ar8xxx_priv
*priv
)
561 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_CAPTURE
);
565 ar8xxx_mib_flush(struct ar8xxx_priv
*priv
)
567 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_FLUSH
);
571 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv
*priv
, int port
, bool flush
)
577 WARN_ON(port
>= priv
->dev
.ports
);
579 lockdep_assert_held(&priv
->mib_lock
);
581 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
))
582 base
= AR8327_REG_PORT_STATS_BASE(port
);
583 else if (chip_is_ar8236(priv
) ||
584 chip_is_ar8316(priv
))
585 base
= AR8236_REG_PORT_STATS_BASE(port
);
587 base
= AR8216_REG_PORT_STATS_BASE(port
);
589 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
590 for (i
= 0; i
< priv
->chip
->num_mibs
; i
++) {
591 const struct ar8xxx_mib_desc
*mib
;
594 mib
= &priv
->chip
->mib_decs
[i
];
595 t
= priv
->read(priv
, base
+ mib
->offset
);
596 if (mib
->size
== 2) {
599 hi
= priv
->read(priv
, base
+ mib
->offset
+ 4);
611 ar8216_read_port_link(struct ar8xxx_priv
*priv
, int port
,
612 struct switch_port_link
*link
)
617 memset(link
, '\0', sizeof(*link
));
619 status
= priv
->chip
->read_port_status(priv
, port
);
621 link
->aneg
= !!(status
& AR8216_PORT_STATUS_LINK_AUTO
);
623 link
->link
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
627 if (priv
->get_port_link
) {
630 err
= priv
->get_port_link(port
);
639 link
->duplex
= !!(status
& AR8216_PORT_STATUS_DUPLEX
);
640 link
->tx_flow
= !!(status
& AR8216_PORT_STATUS_TXFLOW
);
641 link
->rx_flow
= !!(status
& AR8216_PORT_STATUS_RXFLOW
);
643 speed
= (status
& AR8216_PORT_STATUS_SPEED
) >>
644 AR8216_PORT_STATUS_SPEED_S
;
647 case AR8216_PORT_SPEED_10M
:
648 link
->speed
= SWITCH_PORT_SPEED_10
;
650 case AR8216_PORT_SPEED_100M
:
651 link
->speed
= SWITCH_PORT_SPEED_100
;
653 case AR8216_PORT_SPEED_1000M
:
654 link
->speed
= SWITCH_PORT_SPEED_1000
;
657 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
662 static struct sk_buff
*
663 ar8216_mangle_tx(struct net_device
*dev
, struct sk_buff
*skb
)
665 struct ar8xxx_priv
*priv
= dev
->phy_ptr
;
674 if (unlikely(skb_headroom(skb
) < 2)) {
675 if (pskb_expand_head(skb
, 2, 0, GFP_ATOMIC
) < 0)
679 buf
= skb_push(skb
, 2);
687 dev_kfree_skb_any(skb
);
692 ar8216_mangle_rx(struct net_device
*dev
, struct sk_buff
*skb
)
694 struct ar8xxx_priv
*priv
;
702 /* don't strip the header if vlan mode is disabled */
706 /* strip header, get vlan id */
710 /* check for vlan header presence */
711 if ((buf
[12 + 2] != 0x81) || (buf
[13 + 2] != 0x00))
716 /* no need to fix up packets coming from a tagged source */
717 if (priv
->vlan_tagged
& (1 << port
))
720 /* lookup port vid from local table, the switch passes an invalid vlan id */
721 vlan
= priv
->vlan_id
[priv
->pvid
[port
]];
724 buf
[14 + 2] |= vlan
>> 8;
725 buf
[15 + 2] = vlan
& 0xff;
729 ar8216_wait_bit(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
735 t
= priv
->read(priv
, reg
);
736 if ((t
& mask
) == val
)
745 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
746 (unsigned int) reg
, t
, mask
, val
);
751 ar8216_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
753 if (ar8216_wait_bit(priv
, AR8216_REG_VTU
, AR8216_VTU_ACTIVE
, 0))
755 if ((op
& AR8216_VTU_OP
) == AR8216_VTU_OP_LOAD
) {
756 val
&= AR8216_VTUDATA_MEMBER
;
757 val
|= AR8216_VTUDATA_VALID
;
758 priv
->write(priv
, AR8216_REG_VTU_DATA
, val
);
760 op
|= AR8216_VTU_ACTIVE
;
761 priv
->write(priv
, AR8216_REG_VTU
, op
);
765 ar8216_vtu_flush(struct ar8xxx_priv
*priv
)
767 ar8216_vtu_op(priv
, AR8216_VTU_OP_FLUSH
, 0);
771 ar8216_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
775 op
= AR8216_VTU_OP_LOAD
| (vid
<< AR8216_VTU_VID_S
);
776 ar8216_vtu_op(priv
, op
, port_mask
);
780 ar8216_atu_flush(struct ar8xxx_priv
*priv
)
784 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU
, AR8216_ATU_ACTIVE
, 0);
786 priv
->write(priv
, AR8216_REG_ATU
, AR8216_ATU_OP_FLUSH
);
792 ar8216_read_port_status(struct ar8xxx_priv
*priv
, int port
)
794 return priv
->read(priv
, AR8216_REG_PORT_STATUS(port
));
798 ar8216_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
805 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
806 if (priv
->vlan_tagged
& (1 << port
))
807 egress
= AR8216_OUT_ADD_VLAN
;
809 egress
= AR8216_OUT_STRIP_VLAN
;
810 ingress
= AR8216_IN_SECURE
;
813 egress
= AR8216_OUT_KEEP
;
814 ingress
= AR8216_IN_PORT_ONLY
;
817 if (chip_is_ar8216(priv
) && priv
->vlan
&& port
== AR8216_PORT_CPU
)
818 header
= AR8216_PORT_CTRL_HEADER
;
822 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
823 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
824 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
825 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
826 AR8216_PORT_CTRL_LEARN
| header
|
827 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
828 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
830 ar8xxx_rmw(priv
, AR8216_REG_PORT_VLAN(port
),
831 AR8216_PORT_VLAN_DEST_PORTS
| AR8216_PORT_VLAN_MODE
|
832 AR8216_PORT_VLAN_DEFAULT_ID
,
833 (members
<< AR8216_PORT_VLAN_DEST_PORTS_S
) |
834 (ingress
<< AR8216_PORT_VLAN_MODE_S
) |
835 (pvid
<< AR8216_PORT_VLAN_DEFAULT_ID_S
));
839 ar8216_hw_init(struct ar8xxx_priv
*priv
)
841 if (priv
->initialized
)
844 ar8xxx_phy_init(priv
);
846 priv
->initialized
= true;
851 ar8216_init_globals(struct ar8xxx_priv
*priv
)
853 /* standard atheros magic */
854 priv
->write(priv
, 0x38, 0xc000050e);
856 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
857 AR8216_GCTRL_MTU
, 1518 + 8 + 2);
861 ar8216_init_port(struct ar8xxx_priv
*priv
, int port
)
863 /* Enable port learning and tx */
864 priv
->write(priv
, AR8216_REG_PORT_CTRL(port
),
865 AR8216_PORT_CTRL_LEARN
|
866 (4 << AR8216_PORT_CTRL_STATE_S
));
868 priv
->write(priv
, AR8216_REG_PORT_VLAN(port
), 0);
870 if (port
== AR8216_PORT_CPU
) {
871 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
872 AR8216_PORT_STATUS_LINK_UP
|
873 (ar8xxx_has_gige(priv
) ?
874 AR8216_PORT_SPEED_1000M
: AR8216_PORT_SPEED_100M
) |
875 AR8216_PORT_STATUS_TXMAC
|
876 AR8216_PORT_STATUS_RXMAC
|
877 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_RXFLOW
: 0) |
878 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_TXFLOW
: 0) |
879 AR8216_PORT_STATUS_DUPLEX
);
881 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
882 AR8216_PORT_STATUS_LINK_AUTO
);
886 static const struct ar8xxx_chip ar8216_chip
= {
887 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
889 .hw_init
= ar8216_hw_init
,
890 .init_globals
= ar8216_init_globals
,
891 .init_port
= ar8216_init_port
,
892 .setup_port
= ar8216_setup_port
,
893 .read_port_status
= ar8216_read_port_status
,
894 .atu_flush
= ar8216_atu_flush
,
895 .vtu_flush
= ar8216_vtu_flush
,
896 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
898 .num_mibs
= ARRAY_SIZE(ar8216_mibs
),
899 .mib_decs
= ar8216_mibs
,
903 ar8236_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
909 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
910 if (priv
->vlan_tagged
& (1 << port
))
911 egress
= AR8216_OUT_ADD_VLAN
;
913 egress
= AR8216_OUT_STRIP_VLAN
;
914 ingress
= AR8216_IN_SECURE
;
917 egress
= AR8216_OUT_KEEP
;
918 ingress
= AR8216_IN_PORT_ONLY
;
921 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
922 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
923 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
924 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
925 AR8216_PORT_CTRL_LEARN
|
926 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
927 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
929 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN(port
),
930 AR8236_PORT_VLAN_DEFAULT_ID
,
931 (pvid
<< AR8236_PORT_VLAN_DEFAULT_ID_S
));
933 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN2(port
),
934 AR8236_PORT_VLAN2_VLAN_MODE
|
935 AR8236_PORT_VLAN2_MEMBER
,
936 (ingress
<< AR8236_PORT_VLAN2_VLAN_MODE_S
) |
937 (members
<< AR8236_PORT_VLAN2_MEMBER_S
));
941 ar8236_init_globals(struct ar8xxx_priv
*priv
)
943 /* enable jumbo frames */
944 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
945 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
947 /* Enable MIB counters */
948 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
949 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
953 static const struct ar8xxx_chip ar8236_chip
= {
954 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
955 .hw_init
= ar8216_hw_init
,
956 .init_globals
= ar8236_init_globals
,
957 .init_port
= ar8216_init_port
,
958 .setup_port
= ar8236_setup_port
,
959 .read_port_status
= ar8216_read_port_status
,
960 .atu_flush
= ar8216_atu_flush
,
961 .vtu_flush
= ar8216_vtu_flush
,
962 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
964 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
965 .mib_decs
= ar8236_mibs
,
969 ar8316_hw_init(struct ar8xxx_priv
*priv
)
973 val
= priv
->read(priv
, AR8316_REG_POSTRIP
);
975 if (priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
976 if (priv
->port4_phy
) {
977 /* value taken from Ubiquiti RouterStation Pro */
979 pr_info("ar8316: Using port 4 as PHY\n");
982 pr_info("ar8316: Using port 4 as switch port\n");
984 } else if (priv
->phy
->interface
== PHY_INTERFACE_MODE_GMII
) {
985 /* value taken from AVM Fritz!Box 7390 sources */
988 /* no known value for phy interface */
989 pr_err("ar8316: unsupported mii mode: %d.\n",
990 priv
->phy
->interface
);
997 priv
->write(priv
, AR8316_REG_POSTRIP
, newval
);
999 if (priv
->port4_phy
&&
1000 priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
1001 /* work around for phy4 rgmii mode */
1002 ar8xxx_phy_dbg_write(priv
, 4, 0x12, 0x480c);
1004 ar8xxx_phy_dbg_write(priv
, 4, 0x0, 0x824e);
1006 ar8xxx_phy_dbg_write(priv
, 4, 0x5, 0x3d47);
1010 ar8xxx_phy_init(priv
);
1013 priv
->initialized
= true;
1018 ar8316_init_globals(struct ar8xxx_priv
*priv
)
1020 /* standard atheros magic */
1021 priv
->write(priv
, 0x38, 0xc000050e);
1023 /* enable cpu port to receive multicast and broadcast frames */
1024 priv
->write(priv
, AR8216_REG_FLOOD_MASK
, 0x003f003f);
1026 /* enable jumbo frames */
1027 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
1028 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
1030 /* Enable MIB counters */
1031 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
1032 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
1036 static const struct ar8xxx_chip ar8316_chip
= {
1037 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1038 .hw_init
= ar8316_hw_init
,
1039 .init_globals
= ar8316_init_globals
,
1040 .init_port
= ar8216_init_port
,
1041 .setup_port
= ar8216_setup_port
,
1042 .read_port_status
= ar8216_read_port_status
,
1043 .atu_flush
= ar8216_atu_flush
,
1044 .vtu_flush
= ar8216_vtu_flush
,
1045 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
1047 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1048 .mib_decs
= ar8236_mibs
,
1052 ar8327_get_pad_cfg(struct ar8327_pad_cfg
*cfg
)
1060 switch (cfg
->mode
) {
1064 case AR8327_PAD_MAC2MAC_MII
:
1065 t
= AR8327_PAD_MAC_MII_EN
;
1067 t
|= AR8327_PAD_MAC_MII_RXCLK_SEL
;
1069 t
|= AR8327_PAD_MAC_MII_TXCLK_SEL
;
1072 case AR8327_PAD_MAC2MAC_GMII
:
1073 t
= AR8327_PAD_MAC_GMII_EN
;
1075 t
|= AR8327_PAD_MAC_GMII_RXCLK_SEL
;
1077 t
|= AR8327_PAD_MAC_GMII_TXCLK_SEL
;
1080 case AR8327_PAD_MAC_SGMII
:
1081 t
= AR8327_PAD_SGMII_EN
;
1084 * WAR for the QUalcomm Atheros AP136 board.
1085 * It seems that RGMII TX/RX delay settings needs to be
1086 * applied for SGMII mode as well, The ethernet is not
1087 * reliable without this.
1089 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
1090 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
1091 if (cfg
->rxclk_delay_en
)
1092 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
1093 if (cfg
->txclk_delay_en
)
1094 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
1096 if (cfg
->sgmii_delay_en
)
1097 t
|= AR8327_PAD_SGMII_DELAY_EN
;
1101 case AR8327_PAD_MAC2PHY_MII
:
1102 t
= AR8327_PAD_PHY_MII_EN
;
1104 t
|= AR8327_PAD_PHY_MII_RXCLK_SEL
;
1106 t
|= AR8327_PAD_PHY_MII_TXCLK_SEL
;
1109 case AR8327_PAD_MAC2PHY_GMII
:
1110 t
= AR8327_PAD_PHY_GMII_EN
;
1111 if (cfg
->pipe_rxclk_sel
)
1112 t
|= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL
;
1114 t
|= AR8327_PAD_PHY_GMII_RXCLK_SEL
;
1116 t
|= AR8327_PAD_PHY_GMII_TXCLK_SEL
;
1119 case AR8327_PAD_MAC_RGMII
:
1120 t
= AR8327_PAD_RGMII_EN
;
1121 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
1122 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
1123 if (cfg
->rxclk_delay_en
)
1124 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
1125 if (cfg
->txclk_delay_en
)
1126 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
1129 case AR8327_PAD_PHY_GMII
:
1130 t
= AR8327_PAD_PHYX_GMII_EN
;
1133 case AR8327_PAD_PHY_RGMII
:
1134 t
= AR8327_PAD_PHYX_RGMII_EN
;
1137 case AR8327_PAD_PHY_MII
:
1138 t
= AR8327_PAD_PHYX_MII_EN
;
1146 ar8327_phy_fixup(struct ar8xxx_priv
*priv
, int phy
)
1148 switch (priv
->chip_rev
) {
1150 /* For 100M waveform */
1151 ar8xxx_phy_dbg_write(priv
, phy
, 0, 0x02ea);
1152 /* Turn on Gigabit clock */
1153 ar8xxx_phy_dbg_write(priv
, phy
, 0x3d, 0x68a0);
1157 ar8xxx_phy_mmd_write(priv
, phy
, 0x7, 0x3c);
1158 ar8xxx_phy_mmd_write(priv
, phy
, 0x4007, 0x0);
1161 ar8xxx_phy_mmd_write(priv
, phy
, 0x3, 0x800d);
1162 ar8xxx_phy_mmd_write(priv
, phy
, 0x4003, 0x803f);
1164 ar8xxx_phy_dbg_write(priv
, phy
, 0x3d, 0x6860);
1165 ar8xxx_phy_dbg_write(priv
, phy
, 0x5, 0x2c46);
1166 ar8xxx_phy_dbg_write(priv
, phy
, 0x3c, 0x6000);
1172 ar8327_get_port_init_status(struct ar8327_port_cfg
*cfg
)
1176 if (!cfg
->force_link
)
1177 return AR8216_PORT_STATUS_LINK_AUTO
;
1179 t
= AR8216_PORT_STATUS_TXMAC
| AR8216_PORT_STATUS_RXMAC
;
1180 t
|= cfg
->duplex
? AR8216_PORT_STATUS_DUPLEX
: 0;
1181 t
|= cfg
->rxpause
? AR8216_PORT_STATUS_RXFLOW
: 0;
1182 t
|= cfg
->txpause
? AR8216_PORT_STATUS_TXFLOW
: 0;
1184 switch (cfg
->speed
) {
1185 case AR8327_PORT_SPEED_10
:
1186 t
|= AR8216_PORT_SPEED_10M
;
1188 case AR8327_PORT_SPEED_100
:
1189 t
|= AR8216_PORT_SPEED_100M
;
1191 case AR8327_PORT_SPEED_1000
:
1192 t
|= AR8216_PORT_SPEED_1000M
;
1199 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
1200 [_num] = { .reg = (_reg), .shift = (_shift) }
1202 static const struct ar8327_led_entry
1203 ar8327_led_map
[AR8327_NUM_LEDS
] = {
1204 AR8327_LED_ENTRY(AR8327_LED_PHY0_0
, 0, 14),
1205 AR8327_LED_ENTRY(AR8327_LED_PHY0_1
, 1, 14),
1206 AR8327_LED_ENTRY(AR8327_LED_PHY0_2
, 2, 14),
1208 AR8327_LED_ENTRY(AR8327_LED_PHY1_0
, 3, 8),
1209 AR8327_LED_ENTRY(AR8327_LED_PHY1_1
, 3, 10),
1210 AR8327_LED_ENTRY(AR8327_LED_PHY1_2
, 3, 12),
1212 AR8327_LED_ENTRY(AR8327_LED_PHY2_0
, 3, 14),
1213 AR8327_LED_ENTRY(AR8327_LED_PHY2_1
, 3, 16),
1214 AR8327_LED_ENTRY(AR8327_LED_PHY2_2
, 3, 18),
1216 AR8327_LED_ENTRY(AR8327_LED_PHY3_0
, 3, 20),
1217 AR8327_LED_ENTRY(AR8327_LED_PHY3_1
, 3, 22),
1218 AR8327_LED_ENTRY(AR8327_LED_PHY3_2
, 3, 24),
1220 AR8327_LED_ENTRY(AR8327_LED_PHY4_0
, 0, 30),
1221 AR8327_LED_ENTRY(AR8327_LED_PHY4_1
, 1, 30),
1222 AR8327_LED_ENTRY(AR8327_LED_PHY4_2
, 2, 30),
1226 ar8327_set_led_pattern(struct ar8xxx_priv
*priv
, unsigned int led_num
,
1227 enum ar8327_led_pattern pattern
)
1229 const struct ar8327_led_entry
*entry
;
1231 entry
= &ar8327_led_map
[led_num
];
1232 ar8xxx_rmw(priv
, AR8327_REG_LED_CTRL(entry
->reg
),
1233 (3 << entry
->shift
), pattern
<< entry
->shift
);
1237 ar8327_led_work_func(struct work_struct
*work
)
1239 struct ar8327_led
*aled
;
1242 aled
= container_of(work
, struct ar8327_led
, led_work
);
1244 spin_lock(&aled
->lock
);
1245 pattern
= aled
->pattern
;
1246 spin_unlock(&aled
->lock
);
1248 ar8327_set_led_pattern(aled
->sw_priv
, aled
->led_num
,
1253 ar8327_led_schedule_change(struct ar8327_led
*aled
, u8 pattern
)
1255 if (aled
->pattern
== pattern
)
1258 aled
->pattern
= pattern
;
1259 schedule_work(&aled
->led_work
);
1262 static inline struct ar8327_led
*
1263 led_cdev_to_ar8327_led(struct led_classdev
*led_cdev
)
1265 return container_of(led_cdev
, struct ar8327_led
, cdev
);
1269 ar8327_led_blink_set(struct led_classdev
*led_cdev
,
1270 unsigned long *delay_on
,
1271 unsigned long *delay_off
)
1273 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
1275 if (*delay_on
== 0 && *delay_off
== 0) {
1280 if (*delay_on
!= 125 || *delay_off
!= 125) {
1282 * The hardware only supports blinking at 4Hz. Fall back
1283 * to software implementation in other cases.
1288 spin_lock(&aled
->lock
);
1290 aled
->enable_hw_mode
= false;
1291 ar8327_led_schedule_change(aled
, AR8327_LED_PATTERN_BLINK
);
1293 spin_unlock(&aled
->lock
);
1299 ar8327_led_set_brightness(struct led_classdev
*led_cdev
,
1300 enum led_brightness brightness
)
1302 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
1306 active
= (brightness
!= LED_OFF
);
1307 active
^= aled
->active_low
;
1309 pattern
= (active
) ? AR8327_LED_PATTERN_ON
:
1310 AR8327_LED_PATTERN_OFF
;
1312 spin_lock(&aled
->lock
);
1314 aled
->enable_hw_mode
= false;
1315 ar8327_led_schedule_change(aled
, pattern
);
1317 spin_unlock(&aled
->lock
);
1321 ar8327_led_enable_hw_mode_show(struct device
*dev
,
1322 struct device_attribute
*attr
,
1325 struct led_classdev
*led_cdev
= dev_get_drvdata(dev
);
1326 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
1329 spin_lock(&aled
->lock
);
1330 ret
+= sprintf(buf
, "%d\n", aled
->enable_hw_mode
);
1331 spin_unlock(&aled
->lock
);
1337 ar8327_led_enable_hw_mode_store(struct device
*dev
,
1338 struct device_attribute
*attr
,
1342 struct led_classdev
*led_cdev
= dev_get_drvdata(dev
);
1343 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
1348 ret
= kstrtou8(buf
, 10, &value
);
1352 spin_lock(&aled
->lock
);
1354 aled
->enable_hw_mode
= !!value
;
1355 if (aled
->enable_hw_mode
)
1356 pattern
= AR8327_LED_PATTERN_RULE
;
1358 pattern
= AR8327_LED_PATTERN_OFF
;
1360 ar8327_led_schedule_change(aled
, pattern
);
1362 spin_unlock(&aled
->lock
);
1367 static DEVICE_ATTR(enable_hw_mode
, S_IRUGO
| S_IWUSR
,
1368 ar8327_led_enable_hw_mode_show
,
1369 ar8327_led_enable_hw_mode_store
);
1372 ar8327_led_register(struct ar8xxx_priv
*priv
, struct ar8327_led
*aled
)
1376 ret
= led_classdev_register(NULL
, &aled
->cdev
);
1380 if (aled
->mode
== AR8327_LED_MODE_HW
) {
1381 ret
= device_create_file(aled
->cdev
.dev
,
1382 &dev_attr_enable_hw_mode
);
1384 goto err_unregister
;
1390 led_classdev_unregister(&aled
->cdev
);
1395 ar8327_led_unregister(struct ar8327_led
*aled
)
1397 if (aled
->mode
== AR8327_LED_MODE_HW
)
1398 device_remove_file(aled
->cdev
.dev
, &dev_attr_enable_hw_mode
);
1400 led_classdev_unregister(&aled
->cdev
);
1401 cancel_work_sync(&aled
->led_work
);
1405 ar8327_led_create(struct ar8xxx_priv
*priv
,
1406 const struct ar8327_led_info
*led_info
)
1408 struct ar8327_data
*data
= &priv
->chip_data
.ar8327
;
1409 struct ar8327_led
*aled
;
1412 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS
))
1415 if (!led_info
->name
)
1418 if (led_info
->led_num
>= AR8327_NUM_LEDS
)
1421 aled
= kzalloc(sizeof(*aled
) + strlen(led_info
->name
) + 1,
1426 aled
->sw_priv
= priv
;
1427 aled
->led_num
= led_info
->led_num
;
1428 aled
->active_low
= led_info
->active_low
;
1429 aled
->mode
= led_info
->mode
;
1431 if (aled
->mode
== AR8327_LED_MODE_HW
)
1432 aled
->enable_hw_mode
= true;
1434 aled
->name
= (char *)(aled
+ 1);
1435 strcpy(aled
->name
, led_info
->name
);
1437 aled
->cdev
.name
= aled
->name
;
1438 aled
->cdev
.brightness_set
= ar8327_led_set_brightness
;
1439 aled
->cdev
.blink_set
= ar8327_led_blink_set
;
1440 aled
->cdev
.default_trigger
= led_info
->default_trigger
;
1442 spin_lock_init(&aled
->lock
);
1443 mutex_init(&aled
->mutex
);
1444 INIT_WORK(&aled
->led_work
, ar8327_led_work_func
);
1446 ret
= ar8327_led_register(priv
, aled
);
1450 data
->leds
[data
->num_leds
++] = aled
;
1460 ar8327_led_destroy(struct ar8327_led
*aled
)
1462 ar8327_led_unregister(aled
);
1467 ar8327_leds_init(struct ar8xxx_priv
*priv
)
1469 struct ar8327_data
*data
;
1472 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS
))
1475 data
= &priv
->chip_data
.ar8327
;
1477 for (i
= 0; i
< data
->num_leds
; i
++) {
1478 struct ar8327_led
*aled
;
1480 aled
= data
->leds
[i
];
1482 if (aled
->enable_hw_mode
)
1483 aled
->pattern
= AR8327_LED_PATTERN_RULE
;
1485 aled
->pattern
= AR8327_LED_PATTERN_OFF
;
1487 ar8327_set_led_pattern(priv
, aled
->led_num
, aled
->pattern
);
1492 ar8327_leds_cleanup(struct ar8xxx_priv
*priv
)
1494 struct ar8327_data
*data
= &priv
->chip_data
.ar8327
;
1497 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS
))
1500 for (i
= 0; i
< data
->num_leds
; i
++) {
1501 struct ar8327_led
*aled
;
1503 aled
= data
->leds
[i
];
1504 ar8327_led_destroy(aled
);
1511 ar8327_hw_config_pdata(struct ar8xxx_priv
*priv
,
1512 struct ar8327_platform_data
*pdata
)
1514 struct ar8327_led_cfg
*led_cfg
;
1515 struct ar8327_data
*data
;
1522 priv
->get_port_link
= pdata
->get_port_link
;
1524 data
= &priv
->chip_data
.ar8327
;
1526 data
->port0_status
= ar8327_get_port_init_status(&pdata
->port0_cfg
);
1527 data
->port6_status
= ar8327_get_port_init_status(&pdata
->port6_cfg
);
1529 t
= ar8327_get_pad_cfg(pdata
->pad0_cfg
);
1530 if (chip_is_ar8337(priv
))
1531 t
|= AR8337_PAD_MAC06_EXCHANGE_EN
;
1533 priv
->write(priv
, AR8327_REG_PAD0_MODE
, t
);
1534 t
= ar8327_get_pad_cfg(pdata
->pad5_cfg
);
1535 priv
->write(priv
, AR8327_REG_PAD5_MODE
, t
);
1536 t
= ar8327_get_pad_cfg(pdata
->pad6_cfg
);
1537 priv
->write(priv
, AR8327_REG_PAD6_MODE
, t
);
1539 pos
= priv
->read(priv
, AR8327_REG_POWER_ON_STRIP
);
1542 led_cfg
= pdata
->led_cfg
;
1544 if (led_cfg
->open_drain
)
1545 new_pos
|= AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
1547 new_pos
&= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
1549 priv
->write(priv
, AR8327_REG_LED_CTRL0
, led_cfg
->led_ctrl0
);
1550 priv
->write(priv
, AR8327_REG_LED_CTRL1
, led_cfg
->led_ctrl1
);
1551 priv
->write(priv
, AR8327_REG_LED_CTRL2
, led_cfg
->led_ctrl2
);
1552 priv
->write(priv
, AR8327_REG_LED_CTRL3
, led_cfg
->led_ctrl3
);
1555 new_pos
|= AR8327_POWER_ON_STRIP_POWER_ON_SEL
;
1558 if (pdata
->sgmii_cfg
) {
1559 t
= pdata
->sgmii_cfg
->sgmii_ctrl
;
1560 if (priv
->chip_rev
== 1)
1561 t
|= AR8327_SGMII_CTRL_EN_PLL
|
1562 AR8327_SGMII_CTRL_EN_RX
|
1563 AR8327_SGMII_CTRL_EN_TX
;
1565 t
&= ~(AR8327_SGMII_CTRL_EN_PLL
|
1566 AR8327_SGMII_CTRL_EN_RX
|
1567 AR8327_SGMII_CTRL_EN_TX
);
1569 priv
->write(priv
, AR8327_REG_SGMII_CTRL
, t
);
1571 if (pdata
->sgmii_cfg
->serdes_aen
)
1572 new_pos
&= ~AR8327_POWER_ON_STRIP_SERDES_AEN
;
1574 new_pos
|= AR8327_POWER_ON_STRIP_SERDES_AEN
;
1577 priv
->write(priv
, AR8327_REG_POWER_ON_STRIP
, new_pos
);
1579 if (pdata
->leds
&& pdata
->num_leds
) {
1582 data
->leds
= kzalloc(pdata
->num_leds
* sizeof(void *),
1587 for (i
= 0; i
< pdata
->num_leds
; i
++)
1588 ar8327_led_create(priv
, &pdata
->leds
[i
]);
1596 ar8327_hw_config_of(struct ar8xxx_priv
*priv
, struct device_node
*np
)
1598 const __be32
*paddr
;
1602 paddr
= of_get_property(np
, "qca,ar8327-initvals", &len
);
1603 if (!paddr
|| len
< (2 * sizeof(*paddr
)))
1606 len
/= sizeof(*paddr
);
1608 for (i
= 0; i
< len
- 1; i
+= 2) {
1612 reg
= be32_to_cpup(paddr
+ i
);
1613 val
= be32_to_cpup(paddr
+ i
+ 1);
1616 case AR8327_REG_PORT_STATUS(0):
1617 priv
->chip_data
.ar8327
.port0_status
= val
;
1619 case AR8327_REG_PORT_STATUS(6):
1620 priv
->chip_data
.ar8327
.port6_status
= val
;
1623 priv
->write(priv
, reg
, val
);
1632 ar8327_hw_config_of(struct ar8xxx_priv
*priv
, struct device_node
*np
)
1639 ar8327_hw_init(struct ar8xxx_priv
*priv
)
1643 if (priv
->phy
->dev
.of_node
)
1644 ret
= ar8327_hw_config_of(priv
, priv
->phy
->dev
.of_node
);
1646 ret
= ar8327_hw_config_pdata(priv
,
1647 priv
->phy
->dev
.platform_data
);
1652 ar8327_leds_init(priv
);
1654 ar8xxx_phy_init(priv
);
1660 ar8327_cleanup(struct ar8xxx_priv
*priv
)
1662 ar8327_leds_cleanup(priv
);
1666 ar8327_init_globals(struct ar8xxx_priv
*priv
)
1670 /* enable CPU port and disable mirror port */
1671 t
= AR8327_FWD_CTRL0_CPU_PORT_EN
|
1672 AR8327_FWD_CTRL0_MIRROR_PORT
;
1673 priv
->write(priv
, AR8327_REG_FWD_CTRL0
, t
);
1675 /* forward multicast and broadcast frames to CPU */
1676 t
= (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_UC_FLOOD_S
) |
1677 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_MC_FLOOD_S
) |
1678 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_BC_FLOOD_S
);
1679 priv
->write(priv
, AR8327_REG_FWD_CTRL1
, t
);
1681 /* enable jumbo frames */
1682 ar8xxx_rmw(priv
, AR8327_REG_MAX_FRAME_SIZE
,
1683 AR8327_MAX_FRAME_SIZE_MTU
, 9018 + 8 + 2);
1685 /* Enable MIB counters */
1686 ar8xxx_reg_set(priv
, AR8327_REG_MODULE_EN
,
1687 AR8327_MODULE_EN_MIB
);
1689 /* Disable EEE on all ports due to stability issues */
1690 t
= priv
->read(priv
, AR8327_REG_EEE_CTRL
);
1691 t
|= AR8327_EEE_CTRL_DISABLE_PHY(0) |
1692 AR8327_EEE_CTRL_DISABLE_PHY(1) |
1693 AR8327_EEE_CTRL_DISABLE_PHY(2) |
1694 AR8327_EEE_CTRL_DISABLE_PHY(3) |
1695 AR8327_EEE_CTRL_DISABLE_PHY(4);
1696 priv
->write(priv
, AR8327_REG_EEE_CTRL
, t
);
1700 ar8327_init_port(struct ar8xxx_priv
*priv
, int port
)
1704 if (port
== AR8216_PORT_CPU
)
1705 t
= priv
->chip_data
.ar8327
.port0_status
;
1707 t
= priv
->chip_data
.ar8327
.port6_status
;
1709 t
= AR8216_PORT_STATUS_LINK_AUTO
;
1711 priv
->write(priv
, AR8327_REG_PORT_STATUS(port
), t
);
1712 priv
->write(priv
, AR8327_REG_PORT_HEADER(port
), 0);
1714 t
= 1 << AR8327_PORT_VLAN0_DEF_SVID_S
;
1715 t
|= 1 << AR8327_PORT_VLAN0_DEF_CVID_S
;
1716 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
1718 t
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
1719 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
1721 t
= AR8327_PORT_LOOKUP_LEARN
;
1722 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
1723 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
1727 ar8327_read_port_status(struct ar8xxx_priv
*priv
, int port
)
1729 return priv
->read(priv
, AR8327_REG_PORT_STATUS(port
));
1733 ar8327_atu_flush(struct ar8xxx_priv
*priv
)
1737 ret
= ar8216_wait_bit(priv
, AR8327_REG_ATU_FUNC
,
1738 AR8327_ATU_FUNC_BUSY
, 0);
1740 priv
->write(priv
, AR8327_REG_ATU_FUNC
,
1741 AR8327_ATU_FUNC_OP_FLUSH
);
1747 ar8327_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
1749 if (ar8216_wait_bit(priv
, AR8327_REG_VTU_FUNC1
,
1750 AR8327_VTU_FUNC1_BUSY
, 0))
1753 if ((op
& AR8327_VTU_FUNC1_OP
) == AR8327_VTU_FUNC1_OP_LOAD
)
1754 priv
->write(priv
, AR8327_REG_VTU_FUNC0
, val
);
1756 op
|= AR8327_VTU_FUNC1_BUSY
;
1757 priv
->write(priv
, AR8327_REG_VTU_FUNC1
, op
);
1761 ar8327_vtu_flush(struct ar8xxx_priv
*priv
)
1763 ar8327_vtu_op(priv
, AR8327_VTU_FUNC1_OP_FLUSH
, 0);
1767 ar8327_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
1773 op
= AR8327_VTU_FUNC1_OP_LOAD
| (vid
<< AR8327_VTU_FUNC1_VID_S
);
1774 val
= AR8327_VTU_FUNC0_VALID
| AR8327_VTU_FUNC0_IVL
;
1775 for (i
= 0; i
< AR8327_NUM_PORTS
; i
++) {
1778 if ((port_mask
& BIT(i
)) == 0)
1779 mode
= AR8327_VTU_FUNC0_EG_MODE_NOT
;
1780 else if (priv
->vlan
== 0)
1781 mode
= AR8327_VTU_FUNC0_EG_MODE_KEEP
;
1782 else if ((priv
->vlan_tagged
& BIT(i
)) || (priv
->vlan_id
[priv
->pvid
[i
]] != vid
))
1783 mode
= AR8327_VTU_FUNC0_EG_MODE_TAG
;
1785 mode
= AR8327_VTU_FUNC0_EG_MODE_UNTAG
;
1787 val
|= mode
<< AR8327_VTU_FUNC0_EG_MODE_S(i
);
1789 ar8327_vtu_op(priv
, op
, val
);
1793 ar8327_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
1796 u32 egress
, ingress
;
1797 u32 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
1800 egress
= AR8327_PORT_VLAN1_OUT_MODE_UNMOD
;
1801 ingress
= AR8216_IN_SECURE
;
1803 egress
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
;
1804 ingress
= AR8216_IN_PORT_ONLY
;
1807 t
= pvid
<< AR8327_PORT_VLAN0_DEF_SVID_S
;
1808 t
|= pvid
<< AR8327_PORT_VLAN0_DEF_CVID_S
;
1809 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
1811 t
= AR8327_PORT_VLAN1_PORT_VLAN_PROP
;
1812 t
|= egress
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
1813 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
1816 t
|= AR8327_PORT_LOOKUP_LEARN
;
1817 t
|= ingress
<< AR8327_PORT_LOOKUP_IN_MODE_S
;
1818 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
1819 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
1822 static const struct ar8xxx_chip ar8327_chip
= {
1823 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1824 .hw_init
= ar8327_hw_init
,
1825 .cleanup
= ar8327_cleanup
,
1826 .init_globals
= ar8327_init_globals
,
1827 .init_port
= ar8327_init_port
,
1828 .setup_port
= ar8327_setup_port
,
1829 .read_port_status
= ar8327_read_port_status
,
1830 .atu_flush
= ar8327_atu_flush
,
1831 .vtu_flush
= ar8327_vtu_flush
,
1832 .vtu_load_vlan
= ar8327_vtu_load_vlan
,
1833 .phy_fixup
= ar8327_phy_fixup
,
1835 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1836 .mib_decs
= ar8236_mibs
,
1840 ar8xxx_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1841 struct switch_val
*val
)
1843 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1844 priv
->vlan
= !!val
->value
.i
;
1849 ar8xxx_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1850 struct switch_val
*val
)
1852 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1853 val
->value
.i
= priv
->vlan
;
1859 ar8xxx_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
1861 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1863 /* make sure no invalid PVIDs get set */
1865 if (vlan
>= dev
->vlans
)
1868 priv
->pvid
[port
] = vlan
;
1873 ar8xxx_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
1875 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1876 *vlan
= priv
->pvid
[port
];
1881 ar8xxx_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1882 struct switch_val
*val
)
1884 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1885 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
1890 ar8xxx_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1891 struct switch_val
*val
)
1893 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1894 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
1899 ar8xxx_sw_get_port_link(struct switch_dev
*dev
, int port
,
1900 struct switch_port_link
*link
)
1902 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1904 ar8216_read_port_link(priv
, port
, link
);
1909 ar8xxx_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1911 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1912 u8 ports
= priv
->vlan_table
[val
->port_vlan
];
1916 for (i
= 0; i
< dev
->ports
; i
++) {
1917 struct switch_port
*p
;
1919 if (!(ports
& (1 << i
)))
1922 p
= &val
->value
.ports
[val
->len
++];
1924 if (priv
->vlan_tagged
& (1 << i
))
1925 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
1933 ar8327_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1935 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1936 u8 ports
= priv
->vlan_table
[val
->port_vlan
];
1940 for (i
= 0; i
< dev
->ports
; i
++) {
1941 struct switch_port
*p
;
1943 if (!(ports
& (1 << i
)))
1946 p
= &val
->value
.ports
[val
->len
++];
1948 if ((priv
->vlan_tagged
& (1 << i
)) || (priv
->pvid
[i
] != val
->port_vlan
))
1949 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
1957 ar8xxx_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1959 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1960 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1964 for (i
= 0; i
< val
->len
; i
++) {
1965 struct switch_port
*p
= &val
->value
.ports
[i
];
1967 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
1968 priv
->vlan_tagged
|= (1 << p
->id
);
1970 priv
->vlan_tagged
&= ~(1 << p
->id
);
1971 priv
->pvid
[p
->id
] = val
->port_vlan
;
1973 /* make sure that an untagged port does not
1974 * appear in other vlans */
1975 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1976 if (j
== val
->port_vlan
)
1978 priv
->vlan_table
[j
] &= ~(1 << p
->id
);
1988 ar8327_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1990 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1991 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1995 for (i
= 0; i
< val
->len
; i
++) {
1996 struct switch_port
*p
= &val
->value
.ports
[i
];
1998 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
1999 if (val
->port_vlan
== priv
->pvid
[p
->id
]) {
2000 priv
->vlan_tagged
|= (1 << p
->id
);
2003 priv
->vlan_tagged
&= ~(1 << p
->id
);
2004 priv
->pvid
[p
->id
] = val
->port_vlan
;
2013 ar8327_set_mirror_regs(struct ar8xxx_priv
*priv
)
2017 /* reset all mirror registers */
2018 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL0
,
2019 AR8327_FWD_CTRL0_MIRROR_PORT
,
2020 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S
));
2021 for (port
= 0; port
< AR8327_NUM_PORTS
; port
++) {
2022 ar8xxx_rmw(priv
, AR8327_REG_PORT_LOOKUP(port
),
2023 AR8327_PORT_LOOKUP_ING_MIRROR_EN
,
2026 ar8xxx_rmw(priv
, AR8327_REG_PORT_HOL_CTRL1(port
),
2027 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
,
2031 /* now enable mirroring if necessary */
2032 if (priv
->source_port
>= AR8327_NUM_PORTS
||
2033 priv
->monitor_port
>= AR8327_NUM_PORTS
||
2034 priv
->source_port
== priv
->monitor_port
) {
2038 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL0
,
2039 AR8327_FWD_CTRL0_MIRROR_PORT
,
2040 (priv
->monitor_port
<< AR8327_FWD_CTRL0_MIRROR_PORT_S
));
2042 if (priv
->mirror_rx
)
2043 ar8xxx_rmw(priv
, AR8327_REG_PORT_LOOKUP(priv
->source_port
),
2044 AR8327_PORT_LOOKUP_ING_MIRROR_EN
,
2045 AR8327_PORT_LOOKUP_ING_MIRROR_EN
);
2047 if (priv
->mirror_tx
)
2048 ar8xxx_rmw(priv
, AR8327_REG_PORT_HOL_CTRL1(priv
->source_port
),
2049 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
,
2050 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
);
2054 ar8216_set_mirror_regs(struct ar8xxx_priv
*priv
)
2058 /* reset all mirror registers */
2059 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
2060 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
2061 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
2062 for (port
= 0; port
< AR8216_NUM_PORTS
; port
++) {
2063 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
2064 AR8216_PORT_CTRL_MIRROR_RX
,
2067 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
2068 AR8216_PORT_CTRL_MIRROR_TX
,
2072 /* now enable mirroring if necessary */
2073 if (priv
->source_port
>= AR8216_NUM_PORTS
||
2074 priv
->monitor_port
>= AR8216_NUM_PORTS
||
2075 priv
->source_port
== priv
->monitor_port
) {
2079 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
2080 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
2081 (priv
->monitor_port
<< AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
2083 if (priv
->mirror_rx
)
2084 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
2085 AR8216_PORT_CTRL_MIRROR_RX
,
2086 AR8216_PORT_CTRL_MIRROR_RX
);
2088 if (priv
->mirror_tx
)
2089 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
2090 AR8216_PORT_CTRL_MIRROR_TX
,
2091 AR8216_PORT_CTRL_MIRROR_TX
);
2095 ar8xxx_set_mirror_regs(struct ar8xxx_priv
*priv
)
2097 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
)) {
2098 ar8327_set_mirror_regs(priv
);
2100 ar8216_set_mirror_regs(priv
);
2105 ar8xxx_sw_hw_apply(struct switch_dev
*dev
)
2107 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2108 u8 portmask
[AR8X16_MAX_PORTS
];
2111 mutex_lock(&priv
->reg_mutex
);
2112 /* flush all vlan translation unit entries */
2113 priv
->chip
->vtu_flush(priv
);
2115 memset(portmask
, 0, sizeof(portmask
));
2117 /* calculate the port destination masks and load vlans
2118 * into the vlan translation unit */
2119 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
2120 u8 vp
= priv
->vlan_table
[j
];
2125 for (i
= 0; i
< dev
->ports
; i
++) {
2128 portmask
[i
] |= vp
& ~mask
;
2131 priv
->chip
->vtu_load_vlan(priv
, priv
->vlan_id
[j
],
2132 priv
->vlan_table
[j
]);
2136 * isolate all ports, but connect them to the cpu port */
2137 for (i
= 0; i
< dev
->ports
; i
++) {
2138 if (i
== AR8216_PORT_CPU
)
2141 portmask
[i
] = 1 << AR8216_PORT_CPU
;
2142 portmask
[AR8216_PORT_CPU
] |= (1 << i
);
2146 /* update the port destination mask registers and tag settings */
2147 for (i
= 0; i
< dev
->ports
; i
++) {
2148 priv
->chip
->setup_port(priv
, i
, portmask
[i
]);
2151 ar8xxx_set_mirror_regs(priv
);
2153 mutex_unlock(&priv
->reg_mutex
);
2158 ar8xxx_sw_reset_switch(struct switch_dev
*dev
)
2160 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2163 mutex_lock(&priv
->reg_mutex
);
2164 memset(&priv
->vlan
, 0, sizeof(struct ar8xxx_priv
) -
2165 offsetof(struct ar8xxx_priv
, vlan
));
2167 for (i
= 0; i
< AR8X16_MAX_VLANS
; i
++)
2168 priv
->vlan_id
[i
] = i
;
2170 /* Configure all ports */
2171 for (i
= 0; i
< dev
->ports
; i
++)
2172 priv
->chip
->init_port(priv
, i
);
2174 priv
->mirror_rx
= false;
2175 priv
->mirror_tx
= false;
2176 priv
->source_port
= 0;
2177 priv
->monitor_port
= 0;
2179 priv
->chip
->init_globals(priv
);
2181 mutex_unlock(&priv
->reg_mutex
);
2183 return ar8xxx_sw_hw_apply(dev
);
2187 ar8xxx_sw_set_reset_mibs(struct switch_dev
*dev
,
2188 const struct switch_attr
*attr
,
2189 struct switch_val
*val
)
2191 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2195 if (!ar8xxx_has_mib_counters(priv
))
2198 mutex_lock(&priv
->mib_lock
);
2200 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
2201 sizeof(*priv
->mib_stats
);
2202 memset(priv
->mib_stats
, '\0', len
);
2203 ret
= ar8xxx_mib_flush(priv
);
2210 mutex_unlock(&priv
->mib_lock
);
2215 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev
*dev
,
2216 const struct switch_attr
*attr
,
2217 struct switch_val
*val
)
2219 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2221 mutex_lock(&priv
->reg_mutex
);
2222 priv
->mirror_rx
= !!val
->value
.i
;
2223 ar8xxx_set_mirror_regs(priv
);
2224 mutex_unlock(&priv
->reg_mutex
);
2230 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev
*dev
,
2231 const struct switch_attr
*attr
,
2232 struct switch_val
*val
)
2234 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2235 val
->value
.i
= priv
->mirror_rx
;
2240 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev
*dev
,
2241 const struct switch_attr
*attr
,
2242 struct switch_val
*val
)
2244 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2246 mutex_lock(&priv
->reg_mutex
);
2247 priv
->mirror_tx
= !!val
->value
.i
;
2248 ar8xxx_set_mirror_regs(priv
);
2249 mutex_unlock(&priv
->reg_mutex
);
2255 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev
*dev
,
2256 const struct switch_attr
*attr
,
2257 struct switch_val
*val
)
2259 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2260 val
->value
.i
= priv
->mirror_tx
;
2265 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev
*dev
,
2266 const struct switch_attr
*attr
,
2267 struct switch_val
*val
)
2269 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2271 mutex_lock(&priv
->reg_mutex
);
2272 priv
->monitor_port
= val
->value
.i
;
2273 ar8xxx_set_mirror_regs(priv
);
2274 mutex_unlock(&priv
->reg_mutex
);
2280 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev
*dev
,
2281 const struct switch_attr
*attr
,
2282 struct switch_val
*val
)
2284 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2285 val
->value
.i
= priv
->monitor_port
;
2290 ar8xxx_sw_set_mirror_source_port(struct switch_dev
*dev
,
2291 const struct switch_attr
*attr
,
2292 struct switch_val
*val
)
2294 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2296 mutex_lock(&priv
->reg_mutex
);
2297 priv
->source_port
= val
->value
.i
;
2298 ar8xxx_set_mirror_regs(priv
);
2299 mutex_unlock(&priv
->reg_mutex
);
2305 ar8xxx_sw_get_mirror_source_port(struct switch_dev
*dev
,
2306 const struct switch_attr
*attr
,
2307 struct switch_val
*val
)
2309 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2310 val
->value
.i
= priv
->source_port
;
2315 ar8xxx_sw_set_port_reset_mib(struct switch_dev
*dev
,
2316 const struct switch_attr
*attr
,
2317 struct switch_val
*val
)
2319 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2323 if (!ar8xxx_has_mib_counters(priv
))
2326 port
= val
->port_vlan
;
2327 if (port
>= dev
->ports
)
2330 mutex_lock(&priv
->mib_lock
);
2331 ret
= ar8xxx_mib_capture(priv
);
2335 ar8xxx_mib_fetch_port_stat(priv
, port
, true);
2340 mutex_unlock(&priv
->mib_lock
);
2345 ar8xxx_sw_get_port_mib(struct switch_dev
*dev
,
2346 const struct switch_attr
*attr
,
2347 struct switch_val
*val
)
2349 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2350 const struct ar8xxx_chip
*chip
= priv
->chip
;
2354 char *buf
= priv
->buf
;
2357 if (!ar8xxx_has_mib_counters(priv
))
2360 port
= val
->port_vlan
;
2361 if (port
>= dev
->ports
)
2364 mutex_lock(&priv
->mib_lock
);
2365 ret
= ar8xxx_mib_capture(priv
);
2369 ar8xxx_mib_fetch_port_stat(priv
, port
, false);
2371 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
2372 "Port %d MIB counters\n",
2375 mib_stats
= &priv
->mib_stats
[port
* chip
->num_mibs
];
2376 for (i
= 0; i
< chip
->num_mibs
; i
++)
2377 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
2379 chip
->mib_decs
[i
].name
,
2388 mutex_unlock(&priv
->mib_lock
);
2392 static struct switch_attr ar8xxx_sw_attr_globals
[] = {
2394 .type
= SWITCH_TYPE_INT
,
2395 .name
= "enable_vlan",
2396 .description
= "Enable VLAN mode",
2397 .set
= ar8xxx_sw_set_vlan
,
2398 .get
= ar8xxx_sw_get_vlan
,
2402 .type
= SWITCH_TYPE_NOVAL
,
2403 .name
= "reset_mibs",
2404 .description
= "Reset all MIB counters",
2405 .set
= ar8xxx_sw_set_reset_mibs
,
2408 .type
= SWITCH_TYPE_INT
,
2409 .name
= "enable_mirror_rx",
2410 .description
= "Enable mirroring of RX packets",
2411 .set
= ar8xxx_sw_set_mirror_rx_enable
,
2412 .get
= ar8xxx_sw_get_mirror_rx_enable
,
2416 .type
= SWITCH_TYPE_INT
,
2417 .name
= "enable_mirror_tx",
2418 .description
= "Enable mirroring of TX packets",
2419 .set
= ar8xxx_sw_set_mirror_tx_enable
,
2420 .get
= ar8xxx_sw_get_mirror_tx_enable
,
2424 .type
= SWITCH_TYPE_INT
,
2425 .name
= "mirror_monitor_port",
2426 .description
= "Mirror monitor port",
2427 .set
= ar8xxx_sw_set_mirror_monitor_port
,
2428 .get
= ar8xxx_sw_get_mirror_monitor_port
,
2429 .max
= AR8216_NUM_PORTS
- 1
2432 .type
= SWITCH_TYPE_INT
,
2433 .name
= "mirror_source_port",
2434 .description
= "Mirror source port",
2435 .set
= ar8xxx_sw_set_mirror_source_port
,
2436 .get
= ar8xxx_sw_get_mirror_source_port
,
2437 .max
= AR8216_NUM_PORTS
- 1
2441 static struct switch_attr ar8327_sw_attr_globals
[] = {
2443 .type
= SWITCH_TYPE_INT
,
2444 .name
= "enable_vlan",
2445 .description
= "Enable VLAN mode",
2446 .set
= ar8xxx_sw_set_vlan
,
2447 .get
= ar8xxx_sw_get_vlan
,
2451 .type
= SWITCH_TYPE_NOVAL
,
2452 .name
= "reset_mibs",
2453 .description
= "Reset all MIB counters",
2454 .set
= ar8xxx_sw_set_reset_mibs
,
2457 .type
= SWITCH_TYPE_INT
,
2458 .name
= "enable_mirror_rx",
2459 .description
= "Enable mirroring of RX packets",
2460 .set
= ar8xxx_sw_set_mirror_rx_enable
,
2461 .get
= ar8xxx_sw_get_mirror_rx_enable
,
2465 .type
= SWITCH_TYPE_INT
,
2466 .name
= "enable_mirror_tx",
2467 .description
= "Enable mirroring of TX packets",
2468 .set
= ar8xxx_sw_set_mirror_tx_enable
,
2469 .get
= ar8xxx_sw_get_mirror_tx_enable
,
2473 .type
= SWITCH_TYPE_INT
,
2474 .name
= "mirror_monitor_port",
2475 .description
= "Mirror monitor port",
2476 .set
= ar8xxx_sw_set_mirror_monitor_port
,
2477 .get
= ar8xxx_sw_get_mirror_monitor_port
,
2478 .max
= AR8327_NUM_PORTS
- 1
2481 .type
= SWITCH_TYPE_INT
,
2482 .name
= "mirror_source_port",
2483 .description
= "Mirror source port",
2484 .set
= ar8xxx_sw_set_mirror_source_port
,
2485 .get
= ar8xxx_sw_get_mirror_source_port
,
2486 .max
= AR8327_NUM_PORTS
- 1
2490 static struct switch_attr ar8xxx_sw_attr_port
[] = {
2492 .type
= SWITCH_TYPE_NOVAL
,
2493 .name
= "reset_mib",
2494 .description
= "Reset single port MIB counters",
2495 .set
= ar8xxx_sw_set_port_reset_mib
,
2498 .type
= SWITCH_TYPE_STRING
,
2500 .description
= "Get port's MIB counters",
2502 .get
= ar8xxx_sw_get_port_mib
,
2506 static struct switch_attr ar8xxx_sw_attr_vlan
[] = {
2508 .type
= SWITCH_TYPE_INT
,
2510 .description
= "VLAN ID (0-4094)",
2511 .set
= ar8xxx_sw_set_vid
,
2512 .get
= ar8xxx_sw_get_vid
,
2517 static const struct switch_dev_ops ar8xxx_sw_ops
= {
2519 .attr
= ar8xxx_sw_attr_globals
,
2520 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_globals
),
2523 .attr
= ar8xxx_sw_attr_port
,
2524 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
2527 .attr
= ar8xxx_sw_attr_vlan
,
2528 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
2530 .get_port_pvid
= ar8xxx_sw_get_pvid
,
2531 .set_port_pvid
= ar8xxx_sw_set_pvid
,
2532 .get_vlan_ports
= ar8xxx_sw_get_ports
,
2533 .set_vlan_ports
= ar8xxx_sw_set_ports
,
2534 .apply_config
= ar8xxx_sw_hw_apply
,
2535 .reset_switch
= ar8xxx_sw_reset_switch
,
2536 .get_port_link
= ar8xxx_sw_get_port_link
,
2539 static const struct switch_dev_ops ar8327_sw_ops
= {
2541 .attr
= ar8327_sw_attr_globals
,
2542 .n_attr
= ARRAY_SIZE(ar8327_sw_attr_globals
),
2545 .attr
= ar8xxx_sw_attr_port
,
2546 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
2549 .attr
= ar8xxx_sw_attr_vlan
,
2550 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
2552 .get_port_pvid
= ar8xxx_sw_get_pvid
,
2553 .set_port_pvid
= ar8xxx_sw_set_pvid
,
2554 .get_vlan_ports
= ar8327_sw_get_ports
,
2555 .set_vlan_ports
= ar8327_sw_set_ports
,
2556 .apply_config
= ar8xxx_sw_hw_apply
,
2557 .reset_switch
= ar8xxx_sw_reset_switch
,
2558 .get_port_link
= ar8xxx_sw_get_port_link
,
2562 ar8xxx_id_chip(struct ar8xxx_priv
*priv
)
2568 val
= priv
->read(priv
, AR8216_REG_CTRL
);
2572 id
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
2573 for (i
= 0; i
< AR8X16_PROBE_RETRIES
; i
++) {
2576 val
= priv
->read(priv
, AR8216_REG_CTRL
);
2580 t
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
2585 priv
->chip_ver
= (id
& AR8216_CTRL_VERSION
) >> AR8216_CTRL_VERSION_S
;
2586 priv
->chip_rev
= (id
& AR8216_CTRL_REVISION
);
2588 switch (priv
->chip_ver
) {
2589 case AR8XXX_VER_AR8216
:
2590 priv
->chip
= &ar8216_chip
;
2592 case AR8XXX_VER_AR8236
:
2593 priv
->chip
= &ar8236_chip
;
2595 case AR8XXX_VER_AR8316
:
2596 priv
->chip
= &ar8316_chip
;
2598 case AR8XXX_VER_AR8327
:
2599 priv
->mii_lo_first
= true;
2600 priv
->chip
= &ar8327_chip
;
2602 case AR8XXX_VER_AR8337
:
2603 priv
->mii_lo_first
= true;
2604 priv
->chip
= &ar8327_chip
;
2607 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2608 priv
->chip_ver
, priv
->chip_rev
);
2617 ar8xxx_mib_work_func(struct work_struct
*work
)
2619 struct ar8xxx_priv
*priv
;
2622 priv
= container_of(work
, struct ar8xxx_priv
, mib_work
.work
);
2624 mutex_lock(&priv
->mib_lock
);
2626 err
= ar8xxx_mib_capture(priv
);
2630 ar8xxx_mib_fetch_port_stat(priv
, priv
->mib_next_port
, false);
2633 priv
->mib_next_port
++;
2634 if (priv
->mib_next_port
>= priv
->dev
.ports
)
2635 priv
->mib_next_port
= 0;
2637 mutex_unlock(&priv
->mib_lock
);
2638 schedule_delayed_work(&priv
->mib_work
,
2639 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
2643 ar8xxx_mib_init(struct ar8xxx_priv
*priv
)
2647 if (!ar8xxx_has_mib_counters(priv
))
2650 BUG_ON(!priv
->chip
->mib_decs
|| !priv
->chip
->num_mibs
);
2652 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
2653 sizeof(*priv
->mib_stats
);
2654 priv
->mib_stats
= kzalloc(len
, GFP_KERNEL
);
2656 if (!priv
->mib_stats
)
2663 ar8xxx_mib_start(struct ar8xxx_priv
*priv
)
2665 if (!ar8xxx_has_mib_counters(priv
))
2668 schedule_delayed_work(&priv
->mib_work
,
2669 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
2673 ar8xxx_mib_stop(struct ar8xxx_priv
*priv
)
2675 if (!ar8xxx_has_mib_counters(priv
))
2678 cancel_delayed_work(&priv
->mib_work
);
2681 static struct ar8xxx_priv
*
2684 struct ar8xxx_priv
*priv
;
2686 priv
= kzalloc(sizeof(struct ar8xxx_priv
), GFP_KERNEL
);
2690 mutex_init(&priv
->reg_mutex
);
2691 mutex_init(&priv
->mib_lock
);
2692 INIT_DELAYED_WORK(&priv
->mib_work
, ar8xxx_mib_work_func
);
2698 ar8xxx_free(struct ar8xxx_priv
*priv
)
2700 if (priv
->chip
&& priv
->chip
->cleanup
)
2701 priv
->chip
->cleanup(priv
);
2703 kfree(priv
->mib_stats
);
2707 static struct ar8xxx_priv
*
2708 ar8xxx_create_mii(struct mii_bus
*bus
)
2710 struct ar8xxx_priv
*priv
;
2712 priv
= ar8xxx_create();
2714 priv
->mii_bus
= bus
;
2715 priv
->read
= ar8xxx_mii_read
;
2716 priv
->write
= ar8xxx_mii_write
;
2717 priv
->rmw
= ar8xxx_mii_rmw
;
2724 ar8xxx_probe_switch(struct ar8xxx_priv
*priv
)
2726 struct switch_dev
*swdev
;
2729 ret
= ar8xxx_id_chip(priv
);
2734 swdev
->cpu_port
= AR8216_PORT_CPU
;
2735 swdev
->ops
= &ar8xxx_sw_ops
;
2737 if (chip_is_ar8316(priv
)) {
2738 swdev
->name
= "Atheros AR8316";
2739 swdev
->vlans
= AR8X16_MAX_VLANS
;
2740 swdev
->ports
= AR8216_NUM_PORTS
;
2741 } else if (chip_is_ar8236(priv
)) {
2742 swdev
->name
= "Atheros AR8236";
2743 swdev
->vlans
= AR8216_NUM_VLANS
;
2744 swdev
->ports
= AR8216_NUM_PORTS
;
2745 } else if (chip_is_ar8327(priv
)) {
2746 swdev
->name
= "Atheros AR8327";
2747 swdev
->vlans
= AR8X16_MAX_VLANS
;
2748 swdev
->ports
= AR8327_NUM_PORTS
;
2749 swdev
->ops
= &ar8327_sw_ops
;
2750 } else if (chip_is_ar8337(priv
)) {
2751 swdev
->name
= "Atheros AR8337";
2752 swdev
->vlans
= AR8X16_MAX_VLANS
;
2753 swdev
->ports
= AR8327_NUM_PORTS
;
2754 swdev
->ops
= &ar8327_sw_ops
;
2756 swdev
->name
= "Atheros AR8216";
2757 swdev
->vlans
= AR8216_NUM_VLANS
;
2758 swdev
->ports
= AR8216_NUM_PORTS
;
2761 ret
= ar8xxx_mib_init(priv
);
2769 ar8xxx_start(struct ar8xxx_priv
*priv
)
2775 ret
= priv
->chip
->hw_init(priv
);
2779 ret
= ar8xxx_sw_reset_switch(&priv
->dev
);
2785 ar8xxx_mib_start(priv
);
2791 ar8xxx_phy_config_init(struct phy_device
*phydev
)
2793 struct ar8xxx_priv
*priv
= phydev
->priv
;
2794 struct net_device
*dev
= phydev
->attached_dev
;
2800 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
))
2801 return ar8xxx_phy_check_aneg(phydev
);
2805 if (phydev
->addr
!= 0) {
2806 if (chip_is_ar8316(priv
)) {
2807 /* switch device has been initialized, reinit */
2808 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
2809 priv
->initialized
= false;
2810 priv
->port4_phy
= true;
2811 ar8316_hw_init(priv
);
2818 ret
= ar8xxx_start(priv
);
2822 /* VID fixup only needed on ar8216 */
2823 if (chip_is_ar8216(priv
)) {
2824 dev
->phy_ptr
= priv
;
2825 dev
->priv_flags
|= IFF_NO_IP_ALIGN
;
2826 dev
->eth_mangle_rx
= ar8216_mangle_rx
;
2827 dev
->eth_mangle_tx
= ar8216_mangle_tx
;
2834 ar8xxx_phy_read_status(struct phy_device
*phydev
)
2836 struct ar8xxx_priv
*priv
= phydev
->priv
;
2837 struct switch_port_link link
;
2840 if (phydev
->addr
!= 0)
2841 return genphy_read_status(phydev
);
2843 ar8216_read_port_link(priv
, phydev
->addr
, &link
);
2844 phydev
->link
= !!link
.link
;
2848 switch (link
.speed
) {
2849 case SWITCH_PORT_SPEED_10
:
2850 phydev
->speed
= SPEED_10
;
2852 case SWITCH_PORT_SPEED_100
:
2853 phydev
->speed
= SPEED_100
;
2855 case SWITCH_PORT_SPEED_1000
:
2856 phydev
->speed
= SPEED_1000
;
2861 phydev
->duplex
= link
.duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
2863 /* flush the address translation unit */
2864 mutex_lock(&priv
->reg_mutex
);
2865 ret
= priv
->chip
->atu_flush(priv
);
2866 mutex_unlock(&priv
->reg_mutex
);
2868 phydev
->state
= PHY_RUNNING
;
2869 netif_carrier_on(phydev
->attached_dev
);
2870 phydev
->adjust_link(phydev
->attached_dev
);
2876 ar8xxx_phy_config_aneg(struct phy_device
*phydev
)
2878 if (phydev
->addr
== 0)
2881 return genphy_config_aneg(phydev
);
2884 static const u32 ar8xxx_phy_ids
[] = {
2886 0x004dd034, /* AR8327 */
2887 0x004dd036, /* AR8337 */
2890 0x004dd043, /* AR8236 */
2894 ar8xxx_phy_match(u32 phy_id
)
2898 for (i
= 0; i
< ARRAY_SIZE(ar8xxx_phy_ids
); i
++)
2899 if (phy_id
== ar8xxx_phy_ids
[i
])
2906 ar8xxx_is_possible(struct mii_bus
*bus
)
2910 for (i
= 0; i
< 4; i
++) {
2913 phy_id
= mdiobus_read(bus
, i
, MII_PHYSID1
) << 16;
2914 phy_id
|= mdiobus_read(bus
, i
, MII_PHYSID2
);
2915 if (!ar8xxx_phy_match(phy_id
)) {
2916 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2917 dev_name(&bus
->dev
), i
, phy_id
);
2926 ar8xxx_phy_probe(struct phy_device
*phydev
)
2928 struct ar8xxx_priv
*priv
;
2929 struct switch_dev
*swdev
;
2932 /* skip PHYs at unused adresses */
2933 if (phydev
->addr
!= 0 && phydev
->addr
!= 4)
2936 if (!ar8xxx_is_possible(phydev
->bus
))
2939 mutex_lock(&ar8xxx_dev_list_lock
);
2940 list_for_each_entry(priv
, &ar8xxx_dev_list
, list
)
2941 if (priv
->mii_bus
== phydev
->bus
)
2944 priv
= ar8xxx_create_mii(phydev
->bus
);
2950 ret
= ar8xxx_probe_switch(priv
);
2955 swdev
->alias
= dev_name(&priv
->mii_bus
->dev
);
2956 ret
= register_switch(swdev
, NULL
);
2960 pr_info("%s: %s rev. %u switch registered on %s\n",
2961 swdev
->devname
, swdev
->name
, priv
->chip_rev
,
2962 dev_name(&priv
->mii_bus
->dev
));
2967 if (phydev
->addr
== 0) {
2968 if (ar8xxx_has_gige(priv
)) {
2969 phydev
->supported
= SUPPORTED_1000baseT_Full
;
2970 phydev
->advertising
= ADVERTISED_1000baseT_Full
;
2972 phydev
->supported
= SUPPORTED_100baseT_Full
;
2973 phydev
->advertising
= ADVERTISED_100baseT_Full
;
2976 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
)) {
2979 ret
= ar8xxx_start(priv
);
2981 goto err_unregister_switch
;
2984 if (ar8xxx_has_gige(priv
)) {
2985 phydev
->supported
|= SUPPORTED_1000baseT_Full
;
2986 phydev
->advertising
|= ADVERTISED_1000baseT_Full
;
2990 phydev
->priv
= priv
;
2992 list_add(&priv
->list
, &ar8xxx_dev_list
);
2994 mutex_unlock(&ar8xxx_dev_list_lock
);
2998 err_unregister_switch
:
2999 if (--priv
->use_count
)
3002 unregister_switch(&priv
->dev
);
3007 mutex_unlock(&ar8xxx_dev_list_lock
);
3012 ar8xxx_phy_detach(struct phy_device
*phydev
)
3014 struct net_device
*dev
= phydev
->attached_dev
;
3019 dev
->phy_ptr
= NULL
;
3020 dev
->priv_flags
&= ~IFF_NO_IP_ALIGN
;
3021 dev
->eth_mangle_rx
= NULL
;
3022 dev
->eth_mangle_tx
= NULL
;
3026 ar8xxx_phy_remove(struct phy_device
*phydev
)
3028 struct ar8xxx_priv
*priv
= phydev
->priv
;
3033 phydev
->priv
= NULL
;
3034 if (--priv
->use_count
> 0)
3037 mutex_lock(&ar8xxx_dev_list_lock
);
3038 list_del(&priv
->list
);
3039 mutex_unlock(&ar8xxx_dev_list_lock
);
3041 unregister_switch(&priv
->dev
);
3042 ar8xxx_mib_stop(priv
);
3046 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,16,0)
3048 ar8xxx_phy_soft_reset(struct phy_device
*phydev
)
3050 /* we don't need an extra reset */
3055 static struct phy_driver ar8xxx_phy_driver
= {
3056 .phy_id
= 0x004d0000,
3057 .name
= "Atheros AR8216/AR8236/AR8316",
3058 .phy_id_mask
= 0xffff0000,
3059 .features
= PHY_BASIC_FEATURES
,
3060 .probe
= ar8xxx_phy_probe
,
3061 .remove
= ar8xxx_phy_remove
,
3062 .detach
= ar8xxx_phy_detach
,
3063 .config_init
= ar8xxx_phy_config_init
,
3064 .config_aneg
= ar8xxx_phy_config_aneg
,
3065 .read_status
= ar8xxx_phy_read_status
,
3066 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,16,0)
3067 .soft_reset
= ar8xxx_phy_soft_reset
,
3069 .driver
= { .owner
= THIS_MODULE
},
3075 return phy_driver_register(&ar8xxx_phy_driver
);
3081 phy_driver_unregister(&ar8xxx_phy_driver
);
3084 module_init(ar8xxx_init
);
3085 module_exit(ar8xxx_exit
);
3086 MODULE_LICENSE("GPL");