2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/of_device.h>
40 /* size of the vlan table */
41 #define AR8X16_MAX_VLANS 128
42 #define AR8X16_PROBE_RETRIES 10
43 #define AR8X16_MAX_PORTS 8
45 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
49 #define AR8XXX_CAP_GIGE BIT(0)
50 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
53 AR8XXX_VER_AR8216
= 0x01,
54 AR8XXX_VER_AR8236
= 0x03,
55 AR8XXX_VER_AR8316
= 0x10,
56 AR8XXX_VER_AR8327
= 0x12,
57 AR8XXX_VER_AR8337
= 0x13,
60 struct ar8xxx_mib_desc
{
69 int (*hw_init
)(struct ar8xxx_priv
*priv
);
70 void (*init_globals
)(struct ar8xxx_priv
*priv
);
71 void (*init_port
)(struct ar8xxx_priv
*priv
, int port
);
72 void (*setup_port
)(struct ar8xxx_priv
*priv
, int port
, u32 egress
,
73 u32 ingress
, u32 members
, u32 pvid
);
74 u32 (*read_port_status
)(struct ar8xxx_priv
*priv
, int port
);
75 int (*atu_flush
)(struct ar8xxx_priv
*priv
);
76 void (*vtu_flush
)(struct ar8xxx_priv
*priv
);
77 void (*vtu_load_vlan
)(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
);
79 const struct ar8xxx_mib_desc
*mib_decs
;
89 struct switch_dev dev
;
90 struct mii_bus
*mii_bus
;
91 struct phy_device
*phy
;
93 u32 (*read
)(struct ar8xxx_priv
*priv
, int reg
);
94 void (*write
)(struct ar8xxx_priv
*priv
, int reg
, u32 val
);
96 int (*get_port_link
)(unsigned port
);
98 const struct net_device_ops
*ndo_old
;
99 struct net_device_ops ndo
;
100 struct mutex reg_mutex
;
103 const struct ar8xxx_chip
*chip
;
105 struct ar8327_data ar8327
;
114 struct mutex mib_lock
;
115 struct delayed_work mib_work
;
119 struct list_head list
;
120 unsigned int use_count
;
122 /* all fields below are cleared on reset */
124 u16 vlan_id
[AR8X16_MAX_VLANS
];
125 u8 vlan_table
[AR8X16_MAX_VLANS
];
127 u16 pvid
[AR8X16_MAX_PORTS
];
136 #define MIB_DESC(_s , _o, _n) \
143 static const struct ar8xxx_mib_desc ar8216_mibs
[] = {
144 MIB_DESC(1, AR8216_STATS_RXBROAD
, "RxBroad"),
145 MIB_DESC(1, AR8216_STATS_RXPAUSE
, "RxPause"),
146 MIB_DESC(1, AR8216_STATS_RXMULTI
, "RxMulti"),
147 MIB_DESC(1, AR8216_STATS_RXFCSERR
, "RxFcsErr"),
148 MIB_DESC(1, AR8216_STATS_RXALIGNERR
, "RxAlignErr"),
149 MIB_DESC(1, AR8216_STATS_RXRUNT
, "RxRunt"),
150 MIB_DESC(1, AR8216_STATS_RXFRAGMENT
, "RxFragment"),
151 MIB_DESC(1, AR8216_STATS_RX64BYTE
, "Rx64Byte"),
152 MIB_DESC(1, AR8216_STATS_RX128BYTE
, "Rx128Byte"),
153 MIB_DESC(1, AR8216_STATS_RX256BYTE
, "Rx256Byte"),
154 MIB_DESC(1, AR8216_STATS_RX512BYTE
, "Rx512Byte"),
155 MIB_DESC(1, AR8216_STATS_RX1024BYTE
, "Rx1024Byte"),
156 MIB_DESC(1, AR8216_STATS_RXMAXBYTE
, "RxMaxByte"),
157 MIB_DESC(1, AR8216_STATS_RXTOOLONG
, "RxTooLong"),
158 MIB_DESC(2, AR8216_STATS_RXGOODBYTE
, "RxGoodByte"),
159 MIB_DESC(2, AR8216_STATS_RXBADBYTE
, "RxBadByte"),
160 MIB_DESC(1, AR8216_STATS_RXOVERFLOW
, "RxOverFlow"),
161 MIB_DESC(1, AR8216_STATS_FILTERED
, "Filtered"),
162 MIB_DESC(1, AR8216_STATS_TXBROAD
, "TxBroad"),
163 MIB_DESC(1, AR8216_STATS_TXPAUSE
, "TxPause"),
164 MIB_DESC(1, AR8216_STATS_TXMULTI
, "TxMulti"),
165 MIB_DESC(1, AR8216_STATS_TXUNDERRUN
, "TxUnderRun"),
166 MIB_DESC(1, AR8216_STATS_TX64BYTE
, "Tx64Byte"),
167 MIB_DESC(1, AR8216_STATS_TX128BYTE
, "Tx128Byte"),
168 MIB_DESC(1, AR8216_STATS_TX256BYTE
, "Tx256Byte"),
169 MIB_DESC(1, AR8216_STATS_TX512BYTE
, "Tx512Byte"),
170 MIB_DESC(1, AR8216_STATS_TX1024BYTE
, "Tx1024Byte"),
171 MIB_DESC(1, AR8216_STATS_TXMAXBYTE
, "TxMaxByte"),
172 MIB_DESC(1, AR8216_STATS_TXOVERSIZE
, "TxOverSize"),
173 MIB_DESC(2, AR8216_STATS_TXBYTE
, "TxByte"),
174 MIB_DESC(1, AR8216_STATS_TXCOLLISION
, "TxCollision"),
175 MIB_DESC(1, AR8216_STATS_TXABORTCOL
, "TxAbortCol"),
176 MIB_DESC(1, AR8216_STATS_TXMULTICOL
, "TxMultiCol"),
177 MIB_DESC(1, AR8216_STATS_TXSINGLECOL
, "TxSingleCol"),
178 MIB_DESC(1, AR8216_STATS_TXEXCDEFER
, "TxExcDefer"),
179 MIB_DESC(1, AR8216_STATS_TXDEFER
, "TxDefer"),
180 MIB_DESC(1, AR8216_STATS_TXLATECOL
, "TxLateCol"),
183 static const struct ar8xxx_mib_desc ar8236_mibs
[] = {
184 MIB_DESC(1, AR8236_STATS_RXBROAD
, "RxBroad"),
185 MIB_DESC(1, AR8236_STATS_RXPAUSE
, "RxPause"),
186 MIB_DESC(1, AR8236_STATS_RXMULTI
, "RxMulti"),
187 MIB_DESC(1, AR8236_STATS_RXFCSERR
, "RxFcsErr"),
188 MIB_DESC(1, AR8236_STATS_RXALIGNERR
, "RxAlignErr"),
189 MIB_DESC(1, AR8236_STATS_RXRUNT
, "RxRunt"),
190 MIB_DESC(1, AR8236_STATS_RXFRAGMENT
, "RxFragment"),
191 MIB_DESC(1, AR8236_STATS_RX64BYTE
, "Rx64Byte"),
192 MIB_DESC(1, AR8236_STATS_RX128BYTE
, "Rx128Byte"),
193 MIB_DESC(1, AR8236_STATS_RX256BYTE
, "Rx256Byte"),
194 MIB_DESC(1, AR8236_STATS_RX512BYTE
, "Rx512Byte"),
195 MIB_DESC(1, AR8236_STATS_RX1024BYTE
, "Rx1024Byte"),
196 MIB_DESC(1, AR8236_STATS_RX1518BYTE
, "Rx1518Byte"),
197 MIB_DESC(1, AR8236_STATS_RXMAXBYTE
, "RxMaxByte"),
198 MIB_DESC(1, AR8236_STATS_RXTOOLONG
, "RxTooLong"),
199 MIB_DESC(2, AR8236_STATS_RXGOODBYTE
, "RxGoodByte"),
200 MIB_DESC(2, AR8236_STATS_RXBADBYTE
, "RxBadByte"),
201 MIB_DESC(1, AR8236_STATS_RXOVERFLOW
, "RxOverFlow"),
202 MIB_DESC(1, AR8236_STATS_FILTERED
, "Filtered"),
203 MIB_DESC(1, AR8236_STATS_TXBROAD
, "TxBroad"),
204 MIB_DESC(1, AR8236_STATS_TXPAUSE
, "TxPause"),
205 MIB_DESC(1, AR8236_STATS_TXMULTI
, "TxMulti"),
206 MIB_DESC(1, AR8236_STATS_TXUNDERRUN
, "TxUnderRun"),
207 MIB_DESC(1, AR8236_STATS_TX64BYTE
, "Tx64Byte"),
208 MIB_DESC(1, AR8236_STATS_TX128BYTE
, "Tx128Byte"),
209 MIB_DESC(1, AR8236_STATS_TX256BYTE
, "Tx256Byte"),
210 MIB_DESC(1, AR8236_STATS_TX512BYTE
, "Tx512Byte"),
211 MIB_DESC(1, AR8236_STATS_TX1024BYTE
, "Tx1024Byte"),
212 MIB_DESC(1, AR8236_STATS_TX1518BYTE
, "Tx1518Byte"),
213 MIB_DESC(1, AR8236_STATS_TXMAXBYTE
, "TxMaxByte"),
214 MIB_DESC(1, AR8236_STATS_TXOVERSIZE
, "TxOverSize"),
215 MIB_DESC(2, AR8236_STATS_TXBYTE
, "TxByte"),
216 MIB_DESC(1, AR8236_STATS_TXCOLLISION
, "TxCollision"),
217 MIB_DESC(1, AR8236_STATS_TXABORTCOL
, "TxAbortCol"),
218 MIB_DESC(1, AR8236_STATS_TXMULTICOL
, "TxMultiCol"),
219 MIB_DESC(1, AR8236_STATS_TXSINGLECOL
, "TxSingleCol"),
220 MIB_DESC(1, AR8236_STATS_TXEXCDEFER
, "TxExcDefer"),
221 MIB_DESC(1, AR8236_STATS_TXDEFER
, "TxDefer"),
222 MIB_DESC(1, AR8236_STATS_TXLATECOL
, "TxLateCol"),
225 static DEFINE_MUTEX(ar8xxx_dev_list_lock
);
226 static LIST_HEAD(ar8xxx_dev_list
);
228 static inline struct ar8xxx_priv
*
229 swdev_to_ar8xxx(struct switch_dev
*swdev
)
231 return container_of(swdev
, struct ar8xxx_priv
, dev
);
234 static inline bool ar8xxx_has_gige(struct ar8xxx_priv
*priv
)
236 return priv
->chip
->caps
& AR8XXX_CAP_GIGE
;
239 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv
*priv
)
241 return priv
->chip
->caps
& AR8XXX_CAP_MIB_COUNTERS
;
244 static inline bool chip_is_ar8216(struct ar8xxx_priv
*priv
)
246 return priv
->chip_ver
== AR8XXX_VER_AR8216
;
249 static inline bool chip_is_ar8236(struct ar8xxx_priv
*priv
)
251 return priv
->chip_ver
== AR8XXX_VER_AR8236
;
254 static inline bool chip_is_ar8316(struct ar8xxx_priv
*priv
)
256 return priv
->chip_ver
== AR8XXX_VER_AR8316
;
259 static inline bool chip_is_ar8327(struct ar8xxx_priv
*priv
)
261 return priv
->chip_ver
== AR8XXX_VER_AR8327
;
264 static inline bool chip_is_ar8337(struct ar8xxx_priv
*priv
)
266 return priv
->chip_ver
== AR8XXX_VER_AR8337
;
270 split_addr(u32 regaddr
, u16
*r1
, u16
*r2
, u16
*page
)
273 *r1
= regaddr
& 0x1e;
279 *page
= regaddr
& 0x1ff;
283 ar8xxx_mii_read(struct ar8xxx_priv
*priv
, int reg
)
285 struct mii_bus
*bus
= priv
->mii_bus
;
289 split_addr((u32
) reg
, &r1
, &r2
, &page
);
291 mutex_lock(&bus
->mdio_lock
);
293 bus
->write(bus
, 0x18, 0, page
);
294 usleep_range(1000, 2000); /* wait for the page switch to propagate */
295 lo
= bus
->read(bus
, 0x10 | r2
, r1
);
296 hi
= bus
->read(bus
, 0x10 | r2
, r1
+ 1);
298 mutex_unlock(&bus
->mdio_lock
);
300 return (hi
<< 16) | lo
;
304 ar8xxx_mii_write(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
306 struct mii_bus
*bus
= priv
->mii_bus
;
310 split_addr((u32
) reg
, &r1
, &r2
, &r3
);
312 hi
= (u16
) (val
>> 16);
314 mutex_lock(&bus
->mdio_lock
);
316 bus
->write(bus
, 0x18, 0, r3
);
317 usleep_range(1000, 2000); /* wait for the page switch to propagate */
318 if (priv
->mii_lo_first
) {
319 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
320 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
322 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
323 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
326 mutex_unlock(&bus
->mdio_lock
);
330 ar8xxx_phy_dbg_write(struct ar8xxx_priv
*priv
, int phy_addr
,
331 u16 dbg_addr
, u16 dbg_data
)
333 struct mii_bus
*bus
= priv
->mii_bus
;
335 mutex_lock(&bus
->mdio_lock
);
336 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
337 bus
->write(bus
, phy_addr
, MII_ATH_DBG_DATA
, dbg_data
);
338 mutex_unlock(&bus
->mdio_lock
);
342 ar8xxx_phy_mmd_write(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 data
)
344 struct mii_bus
*bus
= priv
->mii_bus
;
346 mutex_lock(&bus
->mdio_lock
);
347 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
348 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, data
);
349 mutex_unlock(&bus
->mdio_lock
);
353 ar8xxx_rmw(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
357 lockdep_assert_held(&priv
->reg_mutex
);
359 v
= priv
->read(priv
, reg
);
362 priv
->write(priv
, reg
, v
);
368 ar8xxx_reg_set(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
372 lockdep_assert_held(&priv
->reg_mutex
);
374 v
= priv
->read(priv
, reg
);
376 priv
->write(priv
, reg
, v
);
380 ar8xxx_reg_wait(struct ar8xxx_priv
*priv
, u32 reg
, u32 mask
, u32 val
,
385 for (i
= 0; i
< timeout
; i
++) {
388 t
= priv
->read(priv
, reg
);
389 if ((t
& mask
) == val
)
392 usleep_range(1000, 2000);
399 ar8xxx_mib_op(struct ar8xxx_priv
*priv
, u32 op
)
404 lockdep_assert_held(&priv
->mib_lock
);
406 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
))
407 mib_func
= AR8327_REG_MIB_FUNC
;
409 mib_func
= AR8216_REG_MIB_FUNC
;
411 mutex_lock(&priv
->reg_mutex
);
412 /* Capture the hardware statistics for all ports */
413 ar8xxx_rmw(priv
, mib_func
, AR8216_MIB_FUNC
, (op
<< AR8216_MIB_FUNC_S
));
414 mutex_unlock(&priv
->reg_mutex
);
416 /* Wait for the capturing to complete. */
417 ret
= ar8xxx_reg_wait(priv
, mib_func
, AR8216_MIB_BUSY
, 0, 10);
428 ar8xxx_mib_capture(struct ar8xxx_priv
*priv
)
430 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_CAPTURE
);
434 ar8xxx_mib_flush(struct ar8xxx_priv
*priv
)
436 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_FLUSH
);
440 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv
*priv
, int port
, bool flush
)
446 WARN_ON(port
>= priv
->dev
.ports
);
448 lockdep_assert_held(&priv
->mib_lock
);
450 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
))
451 base
= AR8327_REG_PORT_STATS_BASE(port
);
452 else if (chip_is_ar8236(priv
) ||
453 chip_is_ar8316(priv
))
454 base
= AR8236_REG_PORT_STATS_BASE(port
);
456 base
= AR8216_REG_PORT_STATS_BASE(port
);
458 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
459 for (i
= 0; i
< priv
->chip
->num_mibs
; i
++) {
460 const struct ar8xxx_mib_desc
*mib
;
463 mib
= &priv
->chip
->mib_decs
[i
];
464 t
= priv
->read(priv
, base
+ mib
->offset
);
465 if (mib
->size
== 2) {
468 hi
= priv
->read(priv
, base
+ mib
->offset
+ 4);
480 ar8216_read_port_link(struct ar8xxx_priv
*priv
, int port
,
481 struct switch_port_link
*link
)
486 memset(link
, '\0', sizeof(*link
));
488 status
= priv
->chip
->read_port_status(priv
, port
);
490 link
->aneg
= !!(status
& AR8216_PORT_STATUS_LINK_AUTO
);
492 link
->link
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
496 if (priv
->get_port_link
) {
499 err
= priv
->get_port_link(port
);
508 link
->duplex
= !!(status
& AR8216_PORT_STATUS_DUPLEX
);
509 link
->tx_flow
= !!(status
& AR8216_PORT_STATUS_TXFLOW
);
510 link
->rx_flow
= !!(status
& AR8216_PORT_STATUS_RXFLOW
);
512 speed
= (status
& AR8216_PORT_STATUS_SPEED
) >>
513 AR8216_PORT_STATUS_SPEED_S
;
516 case AR8216_PORT_SPEED_10M
:
517 link
->speed
= SWITCH_PORT_SPEED_10
;
519 case AR8216_PORT_SPEED_100M
:
520 link
->speed
= SWITCH_PORT_SPEED_100
;
522 case AR8216_PORT_SPEED_1000M
:
523 link
->speed
= SWITCH_PORT_SPEED_1000
;
526 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
531 static struct sk_buff
*
532 ar8216_mangle_tx(struct net_device
*dev
, struct sk_buff
*skb
)
534 struct ar8xxx_priv
*priv
= dev
->phy_ptr
;
543 if (unlikely(skb_headroom(skb
) < 2)) {
544 if (pskb_expand_head(skb
, 2, 0, GFP_ATOMIC
) < 0)
548 buf
= skb_push(skb
, 2);
556 dev_kfree_skb_any(skb
);
561 ar8216_mangle_rx(struct net_device
*dev
, struct sk_buff
*skb
)
563 struct ar8xxx_priv
*priv
;
571 /* don't strip the header if vlan mode is disabled */
575 /* strip header, get vlan id */
579 /* check for vlan header presence */
580 if ((buf
[12 + 2] != 0x81) || (buf
[13 + 2] != 0x00))
585 /* no need to fix up packets coming from a tagged source */
586 if (priv
->vlan_tagged
& (1 << port
))
589 /* lookup port vid from local table, the switch passes an invalid vlan id */
590 vlan
= priv
->vlan_id
[priv
->pvid
[port
]];
593 buf
[14 + 2] |= vlan
>> 8;
594 buf
[15 + 2] = vlan
& 0xff;
598 ar8216_wait_bit(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
604 t
= priv
->read(priv
, reg
);
605 if ((t
& mask
) == val
)
614 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
615 (unsigned int) reg
, t
, mask
, val
);
620 ar8216_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
622 if (ar8216_wait_bit(priv
, AR8216_REG_VTU
, AR8216_VTU_ACTIVE
, 0))
624 if ((op
& AR8216_VTU_OP
) == AR8216_VTU_OP_LOAD
) {
625 val
&= AR8216_VTUDATA_MEMBER
;
626 val
|= AR8216_VTUDATA_VALID
;
627 priv
->write(priv
, AR8216_REG_VTU_DATA
, val
);
629 op
|= AR8216_VTU_ACTIVE
;
630 priv
->write(priv
, AR8216_REG_VTU
, op
);
634 ar8216_vtu_flush(struct ar8xxx_priv
*priv
)
636 ar8216_vtu_op(priv
, AR8216_VTU_OP_FLUSH
, 0);
640 ar8216_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
644 op
= AR8216_VTU_OP_LOAD
| (vid
<< AR8216_VTU_VID_S
);
645 ar8216_vtu_op(priv
, op
, port_mask
);
649 ar8216_atu_flush(struct ar8xxx_priv
*priv
)
653 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU
, AR8216_ATU_ACTIVE
, 0);
655 priv
->write(priv
, AR8216_REG_ATU
, AR8216_ATU_OP_FLUSH
);
661 ar8216_read_port_status(struct ar8xxx_priv
*priv
, int port
)
663 return priv
->read(priv
, AR8216_REG_PORT_STATUS(port
));
667 ar8216_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 egress
, u32 ingress
,
668 u32 members
, u32 pvid
)
672 if (chip_is_ar8216(priv
) && priv
->vlan
&& port
== AR8216_PORT_CPU
)
673 header
= AR8216_PORT_CTRL_HEADER
;
677 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
678 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
679 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
680 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
681 AR8216_PORT_CTRL_LEARN
| header
|
682 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
683 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
685 ar8xxx_rmw(priv
, AR8216_REG_PORT_VLAN(port
),
686 AR8216_PORT_VLAN_DEST_PORTS
| AR8216_PORT_VLAN_MODE
|
687 AR8216_PORT_VLAN_DEFAULT_ID
,
688 (members
<< AR8216_PORT_VLAN_DEST_PORTS_S
) |
689 (ingress
<< AR8216_PORT_VLAN_MODE_S
) |
690 (pvid
<< AR8216_PORT_VLAN_DEFAULT_ID_S
));
694 ar8216_hw_init(struct ar8xxx_priv
*priv
)
700 ar8216_init_globals(struct ar8xxx_priv
*priv
)
702 /* standard atheros magic */
703 priv
->write(priv
, 0x38, 0xc000050e);
705 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
706 AR8216_GCTRL_MTU
, 1518 + 8 + 2);
710 ar8216_init_port(struct ar8xxx_priv
*priv
, int port
)
712 /* Enable port learning and tx */
713 priv
->write(priv
, AR8216_REG_PORT_CTRL(port
),
714 AR8216_PORT_CTRL_LEARN
|
715 (4 << AR8216_PORT_CTRL_STATE_S
));
717 priv
->write(priv
, AR8216_REG_PORT_VLAN(port
), 0);
719 if (port
== AR8216_PORT_CPU
) {
720 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
721 AR8216_PORT_STATUS_LINK_UP
|
722 (ar8xxx_has_gige(priv
) ?
723 AR8216_PORT_SPEED_1000M
: AR8216_PORT_SPEED_100M
) |
724 AR8216_PORT_STATUS_TXMAC
|
725 AR8216_PORT_STATUS_RXMAC
|
726 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_RXFLOW
: 0) |
727 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_TXFLOW
: 0) |
728 AR8216_PORT_STATUS_DUPLEX
);
730 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
731 AR8216_PORT_STATUS_LINK_AUTO
);
735 static const struct ar8xxx_chip ar8216_chip
= {
736 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
738 .hw_init
= ar8216_hw_init
,
739 .init_globals
= ar8216_init_globals
,
740 .init_port
= ar8216_init_port
,
741 .setup_port
= ar8216_setup_port
,
742 .read_port_status
= ar8216_read_port_status
,
743 .atu_flush
= ar8216_atu_flush
,
744 .vtu_flush
= ar8216_vtu_flush
,
745 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
747 .num_mibs
= ARRAY_SIZE(ar8216_mibs
),
748 .mib_decs
= ar8216_mibs
,
752 ar8236_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 egress
, u32 ingress
,
753 u32 members
, u32 pvid
)
755 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
756 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
757 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
758 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
759 AR8216_PORT_CTRL_LEARN
|
760 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
761 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
763 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN(port
),
764 AR8236_PORT_VLAN_DEFAULT_ID
,
765 (pvid
<< AR8236_PORT_VLAN_DEFAULT_ID_S
));
767 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN2(port
),
768 AR8236_PORT_VLAN2_VLAN_MODE
|
769 AR8236_PORT_VLAN2_MEMBER
,
770 (ingress
<< AR8236_PORT_VLAN2_VLAN_MODE_S
) |
771 (members
<< AR8236_PORT_VLAN2_MEMBER_S
));
775 ar8236_hw_init(struct ar8xxx_priv
*priv
)
780 if (priv
->initialized
)
783 /* Initialize the PHYs */
785 for (i
= 0; i
< 5; i
++) {
786 mdiobus_write(bus
, i
, MII_ADVERTISE
,
787 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
|
788 ADVERTISE_PAUSE_ASYM
);
789 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
793 priv
->initialized
= true;
798 ar8236_init_globals(struct ar8xxx_priv
*priv
)
800 /* enable jumbo frames */
801 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
802 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
804 /* Enable MIB counters */
805 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
806 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
810 static const struct ar8xxx_chip ar8236_chip
= {
811 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
812 .hw_init
= ar8236_hw_init
,
813 .init_globals
= ar8236_init_globals
,
814 .init_port
= ar8216_init_port
,
815 .setup_port
= ar8236_setup_port
,
816 .read_port_status
= ar8216_read_port_status
,
817 .atu_flush
= ar8216_atu_flush
,
818 .vtu_flush
= ar8216_vtu_flush
,
819 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
821 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
822 .mib_decs
= ar8236_mibs
,
826 ar8316_hw_init(struct ar8xxx_priv
*priv
)
832 val
= priv
->read(priv
, AR8316_REG_POSTRIP
);
834 if (priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
835 if (priv
->port4_phy
) {
836 /* value taken from Ubiquiti RouterStation Pro */
838 pr_info("ar8316: Using port 4 as PHY\n");
841 pr_info("ar8316: Using port 4 as switch port\n");
843 } else if (priv
->phy
->interface
== PHY_INTERFACE_MODE_GMII
) {
844 /* value taken from AVM Fritz!Box 7390 sources */
847 /* no known value for phy interface */
848 pr_err("ar8316: unsupported mii mode: %d.\n",
849 priv
->phy
->interface
);
856 priv
->write(priv
, AR8316_REG_POSTRIP
, newval
);
858 if (priv
->port4_phy
&&
859 priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
860 /* work around for phy4 rgmii mode */
861 ar8xxx_phy_dbg_write(priv
, 4, 0x12, 0x480c);
863 ar8xxx_phy_dbg_write(priv
, 4, 0x0, 0x824e);
865 ar8xxx_phy_dbg_write(priv
, 4, 0x5, 0x3d47);
869 /* Initialize the ports */
871 for (i
= 0; i
< 5; i
++) {
872 /* initialize the port itself */
873 mdiobus_write(bus
, i
, MII_ADVERTISE
,
874 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
875 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
876 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
882 priv
->initialized
= true;
887 ar8316_init_globals(struct ar8xxx_priv
*priv
)
889 /* standard atheros magic */
890 priv
->write(priv
, 0x38, 0xc000050e);
892 /* enable cpu port to receive multicast and broadcast frames */
893 priv
->write(priv
, AR8216_REG_FLOOD_MASK
, 0x003f003f);
895 /* enable jumbo frames */
896 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
897 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
899 /* Enable MIB counters */
900 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
901 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
905 static const struct ar8xxx_chip ar8316_chip
= {
906 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
907 .hw_init
= ar8316_hw_init
,
908 .init_globals
= ar8316_init_globals
,
909 .init_port
= ar8216_init_port
,
910 .setup_port
= ar8216_setup_port
,
911 .read_port_status
= ar8216_read_port_status
,
912 .atu_flush
= ar8216_atu_flush
,
913 .vtu_flush
= ar8216_vtu_flush
,
914 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
916 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
917 .mib_decs
= ar8236_mibs
,
921 ar8327_get_pad_cfg(struct ar8327_pad_cfg
*cfg
)
933 case AR8327_PAD_MAC2MAC_MII
:
934 t
= AR8327_PAD_MAC_MII_EN
;
936 t
|= AR8327_PAD_MAC_MII_RXCLK_SEL
;
938 t
|= AR8327_PAD_MAC_MII_TXCLK_SEL
;
941 case AR8327_PAD_MAC2MAC_GMII
:
942 t
= AR8327_PAD_MAC_GMII_EN
;
944 t
|= AR8327_PAD_MAC_GMII_RXCLK_SEL
;
946 t
|= AR8327_PAD_MAC_GMII_TXCLK_SEL
;
949 case AR8327_PAD_MAC_SGMII
:
950 t
= AR8327_PAD_SGMII_EN
;
953 * WAR for the QUalcomm Atheros AP136 board.
954 * It seems that RGMII TX/RX delay settings needs to be
955 * applied for SGMII mode as well, The ethernet is not
956 * reliable without this.
958 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
959 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
960 if (cfg
->rxclk_delay_en
)
961 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
962 if (cfg
->txclk_delay_en
)
963 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
965 if (cfg
->sgmii_delay_en
)
966 t
|= AR8327_PAD_SGMII_DELAY_EN
;
970 case AR8327_PAD_MAC2PHY_MII
:
971 t
= AR8327_PAD_PHY_MII_EN
;
973 t
|= AR8327_PAD_PHY_MII_RXCLK_SEL
;
975 t
|= AR8327_PAD_PHY_MII_TXCLK_SEL
;
978 case AR8327_PAD_MAC2PHY_GMII
:
979 t
= AR8327_PAD_PHY_GMII_EN
;
980 if (cfg
->pipe_rxclk_sel
)
981 t
|= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL
;
983 t
|= AR8327_PAD_PHY_GMII_RXCLK_SEL
;
985 t
|= AR8327_PAD_PHY_GMII_TXCLK_SEL
;
988 case AR8327_PAD_MAC_RGMII
:
989 t
= AR8327_PAD_RGMII_EN
;
990 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
991 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
992 if (cfg
->rxclk_delay_en
)
993 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
994 if (cfg
->txclk_delay_en
)
995 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
998 case AR8327_PAD_PHY_GMII
:
999 t
= AR8327_PAD_PHYX_GMII_EN
;
1002 case AR8327_PAD_PHY_RGMII
:
1003 t
= AR8327_PAD_PHYX_RGMII_EN
;
1006 case AR8327_PAD_PHY_MII
:
1007 t
= AR8327_PAD_PHYX_MII_EN
;
1015 ar8327_phy_fixup(struct ar8xxx_priv
*priv
, int phy
)
1017 switch (priv
->chip_rev
) {
1019 /* For 100M waveform */
1020 ar8xxx_phy_dbg_write(priv
, phy
, 0, 0x02ea);
1021 /* Turn on Gigabit clock */
1022 ar8xxx_phy_dbg_write(priv
, phy
, 0x3d, 0x68a0);
1026 ar8xxx_phy_mmd_write(priv
, phy
, 0x7, 0x3c);
1027 ar8xxx_phy_mmd_write(priv
, phy
, 0x4007, 0x0);
1030 ar8xxx_phy_mmd_write(priv
, phy
, 0x3, 0x800d);
1031 ar8xxx_phy_mmd_write(priv
, phy
, 0x4003, 0x803f);
1033 ar8xxx_phy_dbg_write(priv
, phy
, 0x3d, 0x6860);
1034 ar8xxx_phy_dbg_write(priv
, phy
, 0x5, 0x2c46);
1035 ar8xxx_phy_dbg_write(priv
, phy
, 0x3c, 0x6000);
1041 ar8327_get_port_init_status(struct ar8327_port_cfg
*cfg
)
1045 if (!cfg
->force_link
)
1046 return AR8216_PORT_STATUS_LINK_AUTO
;
1048 t
= AR8216_PORT_STATUS_TXMAC
| AR8216_PORT_STATUS_RXMAC
;
1049 t
|= cfg
->duplex
? AR8216_PORT_STATUS_DUPLEX
: 0;
1050 t
|= cfg
->rxpause
? AR8216_PORT_STATUS_RXFLOW
: 0;
1051 t
|= cfg
->txpause
? AR8216_PORT_STATUS_TXFLOW
: 0;
1053 switch (cfg
->speed
) {
1054 case AR8327_PORT_SPEED_10
:
1055 t
|= AR8216_PORT_SPEED_10M
;
1057 case AR8327_PORT_SPEED_100
:
1058 t
|= AR8216_PORT_SPEED_100M
;
1060 case AR8327_PORT_SPEED_1000
:
1061 t
|= AR8216_PORT_SPEED_1000M
;
1069 ar8327_hw_config_pdata(struct ar8xxx_priv
*priv
,
1070 struct ar8327_platform_data
*pdata
)
1072 struct ar8327_led_cfg
*led_cfg
;
1073 struct ar8327_data
*data
;
1080 priv
->get_port_link
= pdata
->get_port_link
;
1082 data
= &priv
->chip_data
.ar8327
;
1084 data
->port0_status
= ar8327_get_port_init_status(&pdata
->port0_cfg
);
1085 data
->port6_status
= ar8327_get_port_init_status(&pdata
->port6_cfg
);
1087 t
= ar8327_get_pad_cfg(pdata
->pad0_cfg
);
1088 if (chip_is_ar8337(priv
))
1089 t
|= AR8337_PAD_MAC06_EXCHANGE_EN
;
1091 priv
->write(priv
, AR8327_REG_PAD0_MODE
, t
);
1092 t
= ar8327_get_pad_cfg(pdata
->pad5_cfg
);
1093 priv
->write(priv
, AR8327_REG_PAD5_MODE
, t
);
1094 t
= ar8327_get_pad_cfg(pdata
->pad6_cfg
);
1095 priv
->write(priv
, AR8327_REG_PAD6_MODE
, t
);
1097 pos
= priv
->read(priv
, AR8327_REG_POWER_ON_STRIP
);
1100 led_cfg
= pdata
->led_cfg
;
1102 if (led_cfg
->open_drain
)
1103 new_pos
|= AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
1105 new_pos
&= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
1107 priv
->write(priv
, AR8327_REG_LED_CTRL0
, led_cfg
->led_ctrl0
);
1108 priv
->write(priv
, AR8327_REG_LED_CTRL1
, led_cfg
->led_ctrl1
);
1109 priv
->write(priv
, AR8327_REG_LED_CTRL2
, led_cfg
->led_ctrl2
);
1110 priv
->write(priv
, AR8327_REG_LED_CTRL3
, led_cfg
->led_ctrl3
);
1113 new_pos
|= AR8327_POWER_ON_STRIP_POWER_ON_SEL
;
1116 if (pdata
->sgmii_cfg
) {
1117 t
= pdata
->sgmii_cfg
->sgmii_ctrl
;
1118 if (priv
->chip_rev
== 1)
1119 t
|= AR8327_SGMII_CTRL_EN_PLL
|
1120 AR8327_SGMII_CTRL_EN_RX
|
1121 AR8327_SGMII_CTRL_EN_TX
;
1123 t
&= ~(AR8327_SGMII_CTRL_EN_PLL
|
1124 AR8327_SGMII_CTRL_EN_RX
|
1125 AR8327_SGMII_CTRL_EN_TX
);
1127 priv
->write(priv
, AR8327_REG_SGMII_CTRL
, t
);
1129 if (pdata
->sgmii_cfg
->serdes_aen
)
1130 new_pos
&= ~AR8327_POWER_ON_STRIP_SERDES_AEN
;
1132 new_pos
|= AR8327_POWER_ON_STRIP_SERDES_AEN
;
1135 priv
->write(priv
, AR8327_REG_POWER_ON_STRIP
, new_pos
);
1142 ar8327_hw_config_of(struct ar8xxx_priv
*priv
, struct device_node
*np
)
1144 const __be32
*paddr
;
1148 paddr
= of_get_property(np
, "qca,ar8327-initvals", &len
);
1149 if (!paddr
|| len
< (2 * sizeof(*paddr
)))
1152 len
/= sizeof(*paddr
);
1154 for (i
= 0; i
< len
- 1; i
+= 2) {
1158 reg
= be32_to_cpup(paddr
+ i
);
1159 val
= be32_to_cpup(paddr
+ i
+ 1);
1162 case AR8327_REG_PORT_STATUS(0):
1163 priv
->chip_data
.ar8327
.port0_status
= val
;
1165 case AR8327_REG_PORT_STATUS(6):
1166 priv
->chip_data
.ar8327
.port6_status
= val
;
1169 priv
->write(priv
, reg
, val
);
1178 ar8327_hw_config_of(struct ar8xxx_priv
*priv
, struct device_node
*np
)
1185 ar8327_hw_init(struct ar8xxx_priv
*priv
)
1187 struct mii_bus
*bus
;
1191 if (priv
->phy
->dev
.of_node
)
1192 ret
= ar8327_hw_config_of(priv
, priv
->phy
->dev
.of_node
);
1194 ret
= ar8327_hw_config_pdata(priv
,
1195 priv
->phy
->dev
.platform_data
);
1200 bus
= priv
->mii_bus
;
1201 for (i
= 0; i
< AR8327_NUM_PHYS
; i
++) {
1202 ar8327_phy_fixup(priv
, i
);
1204 /* start aneg on the PHY */
1205 mdiobus_write(bus
, i
, MII_ADVERTISE
, ADVERTISE_ALL
|
1206 ADVERTISE_PAUSE_CAP
|
1207 ADVERTISE_PAUSE_ASYM
);
1208 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
1209 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
1218 ar8327_init_globals(struct ar8xxx_priv
*priv
)
1222 /* enable CPU port and disable mirror port */
1223 t
= AR8327_FWD_CTRL0_CPU_PORT_EN
|
1224 AR8327_FWD_CTRL0_MIRROR_PORT
;
1225 priv
->write(priv
, AR8327_REG_FWD_CTRL0
, t
);
1227 /* forward multicast and broadcast frames to CPU */
1228 t
= (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_UC_FLOOD_S
) |
1229 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_MC_FLOOD_S
) |
1230 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_BC_FLOOD_S
);
1231 priv
->write(priv
, AR8327_REG_FWD_CTRL1
, t
);
1234 ar8xxx_rmw(priv
, AR8327_REG_MAX_FRAME_SIZE
,
1235 AR8327_MAX_FRAME_SIZE_MTU
, 1518 + 8 + 2);
1237 /* Enable MIB counters */
1238 ar8xxx_reg_set(priv
, AR8327_REG_MODULE_EN
,
1239 AR8327_MODULE_EN_MIB
);
1243 ar8327_init_port(struct ar8xxx_priv
*priv
, int port
)
1247 if (port
== AR8216_PORT_CPU
)
1248 t
= priv
->chip_data
.ar8327
.port0_status
;
1250 t
= priv
->chip_data
.ar8327
.port6_status
;
1252 t
= AR8216_PORT_STATUS_LINK_AUTO
;
1254 priv
->write(priv
, AR8327_REG_PORT_STATUS(port
), t
);
1255 priv
->write(priv
, AR8327_REG_PORT_HEADER(port
), 0);
1257 t
= 1 << AR8327_PORT_VLAN0_DEF_SVID_S
;
1258 t
|= 1 << AR8327_PORT_VLAN0_DEF_CVID_S
;
1259 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
1261 t
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
1262 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
1264 t
= AR8327_PORT_LOOKUP_LEARN
;
1265 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
1266 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
1270 ar8327_read_port_status(struct ar8xxx_priv
*priv
, int port
)
1272 return priv
->read(priv
, AR8327_REG_PORT_STATUS(port
));
1276 ar8327_atu_flush(struct ar8xxx_priv
*priv
)
1280 ret
= ar8216_wait_bit(priv
, AR8327_REG_ATU_FUNC
,
1281 AR8327_ATU_FUNC_BUSY
, 0);
1283 priv
->write(priv
, AR8327_REG_ATU_FUNC
,
1284 AR8327_ATU_FUNC_OP_FLUSH
);
1290 ar8327_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
1292 if (ar8216_wait_bit(priv
, AR8327_REG_VTU_FUNC1
,
1293 AR8327_VTU_FUNC1_BUSY
, 0))
1296 if ((op
& AR8327_VTU_FUNC1_OP
) == AR8327_VTU_FUNC1_OP_LOAD
)
1297 priv
->write(priv
, AR8327_REG_VTU_FUNC0
, val
);
1299 op
|= AR8327_VTU_FUNC1_BUSY
;
1300 priv
->write(priv
, AR8327_REG_VTU_FUNC1
, op
);
1304 ar8327_vtu_flush(struct ar8xxx_priv
*priv
)
1306 ar8327_vtu_op(priv
, AR8327_VTU_FUNC1_OP_FLUSH
, 0);
1310 ar8327_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
1316 op
= AR8327_VTU_FUNC1_OP_LOAD
| (vid
<< AR8327_VTU_FUNC1_VID_S
);
1317 val
= AR8327_VTU_FUNC0_VALID
| AR8327_VTU_FUNC0_IVL
;
1318 for (i
= 0; i
< AR8327_NUM_PORTS
; i
++) {
1321 if ((port_mask
& BIT(i
)) == 0)
1322 mode
= AR8327_VTU_FUNC0_EG_MODE_NOT
;
1323 else if (priv
->vlan
== 0)
1324 mode
= AR8327_VTU_FUNC0_EG_MODE_KEEP
;
1325 else if (priv
->vlan_tagged
& BIT(i
))
1326 mode
= AR8327_VTU_FUNC0_EG_MODE_TAG
;
1328 mode
= AR8327_VTU_FUNC0_EG_MODE_UNTAG
;
1330 val
|= mode
<< AR8327_VTU_FUNC0_EG_MODE_S(i
);
1332 ar8327_vtu_op(priv
, op
, val
);
1336 ar8327_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 egress
, u32 ingress
,
1337 u32 members
, u32 pvid
)
1342 t
= pvid
<< AR8327_PORT_VLAN0_DEF_SVID_S
;
1343 t
|= pvid
<< AR8327_PORT_VLAN0_DEF_CVID_S
;
1344 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
1346 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNMOD
;
1348 case AR8216_OUT_KEEP
:
1349 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
;
1351 case AR8216_OUT_STRIP_VLAN
:
1352 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNTAG
;
1354 case AR8216_OUT_ADD_VLAN
:
1355 mode
= AR8327_PORT_VLAN1_OUT_MODE_TAG
;
1359 t
= AR8327_PORT_VLAN1_PORT_VLAN_PROP
;
1360 t
|= mode
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
1361 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
1364 t
|= AR8327_PORT_LOOKUP_LEARN
;
1365 t
|= ingress
<< AR8327_PORT_LOOKUP_IN_MODE_S
;
1366 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
1367 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
1370 static const struct ar8xxx_chip ar8327_chip
= {
1371 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1372 .hw_init
= ar8327_hw_init
,
1373 .init_globals
= ar8327_init_globals
,
1374 .init_port
= ar8327_init_port
,
1375 .setup_port
= ar8327_setup_port
,
1376 .read_port_status
= ar8327_read_port_status
,
1377 .atu_flush
= ar8327_atu_flush
,
1378 .vtu_flush
= ar8327_vtu_flush
,
1379 .vtu_load_vlan
= ar8327_vtu_load_vlan
,
1381 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1382 .mib_decs
= ar8236_mibs
,
1386 ar8xxx_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1387 struct switch_val
*val
)
1389 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1390 priv
->vlan
= !!val
->value
.i
;
1395 ar8xxx_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1396 struct switch_val
*val
)
1398 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1399 val
->value
.i
= priv
->vlan
;
1405 ar8xxx_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
1407 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1409 /* make sure no invalid PVIDs get set */
1411 if (vlan
>= dev
->vlans
)
1414 priv
->pvid
[port
] = vlan
;
1419 ar8xxx_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
1421 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1422 *vlan
= priv
->pvid
[port
];
1427 ar8xxx_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1428 struct switch_val
*val
)
1430 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1431 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
1436 ar8xxx_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1437 struct switch_val
*val
)
1439 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1440 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
1445 ar8xxx_sw_get_port_link(struct switch_dev
*dev
, int port
,
1446 struct switch_port_link
*link
)
1448 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1450 ar8216_read_port_link(priv
, port
, link
);
1455 ar8xxx_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1457 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1458 u8 ports
= priv
->vlan_table
[val
->port_vlan
];
1462 for (i
= 0; i
< dev
->ports
; i
++) {
1463 struct switch_port
*p
;
1465 if (!(ports
& (1 << i
)))
1468 p
= &val
->value
.ports
[val
->len
++];
1470 if (priv
->vlan_tagged
& (1 << i
))
1471 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
1479 ar8xxx_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1481 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1482 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1486 for (i
= 0; i
< val
->len
; i
++) {
1487 struct switch_port
*p
= &val
->value
.ports
[i
];
1489 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
1490 priv
->vlan_tagged
|= (1 << p
->id
);
1492 priv
->vlan_tagged
&= ~(1 << p
->id
);
1493 priv
->pvid
[p
->id
] = val
->port_vlan
;
1495 /* make sure that an untagged port does not
1496 * appear in other vlans */
1497 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1498 if (j
== val
->port_vlan
)
1500 priv
->vlan_table
[j
] &= ~(1 << p
->id
);
1510 ar8327_set_mirror_regs(struct ar8xxx_priv
*priv
)
1514 /* reset all mirror registers */
1515 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL0
,
1516 AR8327_FWD_CTRL0_MIRROR_PORT
,
1517 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S
));
1518 for (port
= 0; port
< AR8327_NUM_PORTS
; port
++) {
1519 ar8xxx_rmw(priv
, AR8327_REG_PORT_LOOKUP(port
),
1520 AR8327_PORT_LOOKUP_ING_MIRROR_EN
,
1523 ar8xxx_rmw(priv
, AR8327_REG_PORT_HOL_CTRL1(port
),
1524 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
,
1528 /* now enable mirroring if necessary */
1529 if (priv
->source_port
>= AR8327_NUM_PORTS
||
1530 priv
->monitor_port
>= AR8327_NUM_PORTS
||
1531 priv
->source_port
== priv
->monitor_port
) {
1535 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL0
,
1536 AR8327_FWD_CTRL0_MIRROR_PORT
,
1537 (priv
->monitor_port
<< AR8327_FWD_CTRL0_MIRROR_PORT_S
));
1539 if (priv
->mirror_rx
)
1540 ar8xxx_rmw(priv
, AR8327_REG_PORT_LOOKUP(priv
->source_port
),
1541 AR8327_PORT_LOOKUP_ING_MIRROR_EN
,
1542 AR8327_PORT_LOOKUP_ING_MIRROR_EN
);
1544 if (priv
->mirror_tx
)
1545 ar8xxx_rmw(priv
, AR8327_REG_PORT_HOL_CTRL1(priv
->source_port
),
1546 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
,
1547 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
);
1551 ar8216_set_mirror_regs(struct ar8xxx_priv
*priv
)
1555 /* reset all mirror registers */
1556 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
1557 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
1558 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
1559 for (port
= 0; port
< AR8216_NUM_PORTS
; port
++) {
1560 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
1561 AR8216_PORT_CTRL_MIRROR_RX
,
1564 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
1565 AR8216_PORT_CTRL_MIRROR_TX
,
1569 /* now enable mirroring if necessary */
1570 if (priv
->source_port
>= AR8216_NUM_PORTS
||
1571 priv
->monitor_port
>= AR8216_NUM_PORTS
||
1572 priv
->source_port
== priv
->monitor_port
) {
1576 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
1577 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
1578 (priv
->monitor_port
<< AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
1580 if (priv
->mirror_rx
)
1581 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
1582 AR8216_PORT_CTRL_MIRROR_RX
,
1583 AR8216_PORT_CTRL_MIRROR_RX
);
1585 if (priv
->mirror_tx
)
1586 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
1587 AR8216_PORT_CTRL_MIRROR_TX
,
1588 AR8216_PORT_CTRL_MIRROR_TX
);
1592 ar8xxx_set_mirror_regs(struct ar8xxx_priv
*priv
)
1594 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
)) {
1595 ar8327_set_mirror_regs(priv
);
1597 ar8216_set_mirror_regs(priv
);
1602 ar8xxx_sw_hw_apply(struct switch_dev
*dev
)
1604 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1605 u8 portmask
[AR8X16_MAX_PORTS
];
1608 mutex_lock(&priv
->reg_mutex
);
1609 /* flush all vlan translation unit entries */
1610 priv
->chip
->vtu_flush(priv
);
1612 memset(portmask
, 0, sizeof(portmask
));
1614 /* calculate the port destination masks and load vlans
1615 * into the vlan translation unit */
1616 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1617 u8 vp
= priv
->vlan_table
[j
];
1622 for (i
= 0; i
< dev
->ports
; i
++) {
1625 portmask
[i
] |= vp
& ~mask
;
1628 priv
->chip
->vtu_load_vlan(priv
, priv
->vlan_id
[j
],
1629 priv
->vlan_table
[j
]);
1633 * isolate all ports, but connect them to the cpu port */
1634 for (i
= 0; i
< dev
->ports
; i
++) {
1635 if (i
== AR8216_PORT_CPU
)
1638 portmask
[i
] = 1 << AR8216_PORT_CPU
;
1639 portmask
[AR8216_PORT_CPU
] |= (1 << i
);
1643 /* update the port destination mask registers and tag settings */
1644 for (i
= 0; i
< dev
->ports
; i
++) {
1645 int egress
, ingress
;
1649 pvid
= priv
->vlan_id
[priv
->pvid
[i
]];
1650 if (priv
->vlan_tagged
& (1 << i
))
1651 egress
= AR8216_OUT_ADD_VLAN
;
1653 egress
= AR8216_OUT_STRIP_VLAN
;
1654 ingress
= AR8216_IN_SECURE
;
1657 egress
= AR8216_OUT_KEEP
;
1658 ingress
= AR8216_IN_PORT_ONLY
;
1661 priv
->chip
->setup_port(priv
, i
, egress
, ingress
, portmask
[i
],
1665 ar8xxx_set_mirror_regs(priv
);
1667 mutex_unlock(&priv
->reg_mutex
);
1672 ar8xxx_sw_reset_switch(struct switch_dev
*dev
)
1674 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1677 mutex_lock(&priv
->reg_mutex
);
1678 memset(&priv
->vlan
, 0, sizeof(struct ar8xxx_priv
) -
1679 offsetof(struct ar8xxx_priv
, vlan
));
1681 for (i
= 0; i
< AR8X16_MAX_VLANS
; i
++)
1682 priv
->vlan_id
[i
] = i
;
1684 /* Configure all ports */
1685 for (i
= 0; i
< dev
->ports
; i
++)
1686 priv
->chip
->init_port(priv
, i
);
1688 priv
->mirror_rx
= false;
1689 priv
->mirror_tx
= false;
1690 priv
->source_port
= 0;
1691 priv
->monitor_port
= 0;
1693 priv
->chip
->init_globals(priv
);
1695 mutex_unlock(&priv
->reg_mutex
);
1697 return ar8xxx_sw_hw_apply(dev
);
1701 ar8xxx_sw_set_reset_mibs(struct switch_dev
*dev
,
1702 const struct switch_attr
*attr
,
1703 struct switch_val
*val
)
1705 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1709 if (!ar8xxx_has_mib_counters(priv
))
1712 mutex_lock(&priv
->mib_lock
);
1714 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1715 sizeof(*priv
->mib_stats
);
1716 memset(priv
->mib_stats
, '\0', len
);
1717 ret
= ar8xxx_mib_flush(priv
);
1724 mutex_unlock(&priv
->mib_lock
);
1729 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev
*dev
,
1730 const struct switch_attr
*attr
,
1731 struct switch_val
*val
)
1733 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1735 mutex_lock(&priv
->reg_mutex
);
1736 priv
->mirror_rx
= !!val
->value
.i
;
1737 ar8xxx_set_mirror_regs(priv
);
1738 mutex_unlock(&priv
->reg_mutex
);
1744 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev
*dev
,
1745 const struct switch_attr
*attr
,
1746 struct switch_val
*val
)
1748 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1749 val
->value
.i
= priv
->mirror_rx
;
1754 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev
*dev
,
1755 const struct switch_attr
*attr
,
1756 struct switch_val
*val
)
1758 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1760 mutex_lock(&priv
->reg_mutex
);
1761 priv
->mirror_tx
= !!val
->value
.i
;
1762 ar8xxx_set_mirror_regs(priv
);
1763 mutex_unlock(&priv
->reg_mutex
);
1769 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev
*dev
,
1770 const struct switch_attr
*attr
,
1771 struct switch_val
*val
)
1773 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1774 val
->value
.i
= priv
->mirror_tx
;
1779 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev
*dev
,
1780 const struct switch_attr
*attr
,
1781 struct switch_val
*val
)
1783 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1785 mutex_lock(&priv
->reg_mutex
);
1786 priv
->monitor_port
= val
->value
.i
;
1787 ar8xxx_set_mirror_regs(priv
);
1788 mutex_unlock(&priv
->reg_mutex
);
1794 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev
*dev
,
1795 const struct switch_attr
*attr
,
1796 struct switch_val
*val
)
1798 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1799 val
->value
.i
= priv
->monitor_port
;
1804 ar8xxx_sw_set_mirror_source_port(struct switch_dev
*dev
,
1805 const struct switch_attr
*attr
,
1806 struct switch_val
*val
)
1808 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1810 mutex_lock(&priv
->reg_mutex
);
1811 priv
->source_port
= val
->value
.i
;
1812 ar8xxx_set_mirror_regs(priv
);
1813 mutex_unlock(&priv
->reg_mutex
);
1819 ar8xxx_sw_get_mirror_source_port(struct switch_dev
*dev
,
1820 const struct switch_attr
*attr
,
1821 struct switch_val
*val
)
1823 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1824 val
->value
.i
= priv
->source_port
;
1829 ar8xxx_sw_set_port_reset_mib(struct switch_dev
*dev
,
1830 const struct switch_attr
*attr
,
1831 struct switch_val
*val
)
1833 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1837 if (!ar8xxx_has_mib_counters(priv
))
1840 port
= val
->port_vlan
;
1841 if (port
>= dev
->ports
)
1844 mutex_lock(&priv
->mib_lock
);
1845 ret
= ar8xxx_mib_capture(priv
);
1849 ar8xxx_mib_fetch_port_stat(priv
, port
, true);
1854 mutex_unlock(&priv
->mib_lock
);
1859 ar8xxx_sw_get_port_mib(struct switch_dev
*dev
,
1860 const struct switch_attr
*attr
,
1861 struct switch_val
*val
)
1863 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1864 const struct ar8xxx_chip
*chip
= priv
->chip
;
1868 char *buf
= priv
->buf
;
1871 if (!ar8xxx_has_mib_counters(priv
))
1874 port
= val
->port_vlan
;
1875 if (port
>= dev
->ports
)
1878 mutex_lock(&priv
->mib_lock
);
1879 ret
= ar8xxx_mib_capture(priv
);
1883 ar8xxx_mib_fetch_port_stat(priv
, port
, false);
1885 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1886 "Port %d MIB counters\n",
1889 mib_stats
= &priv
->mib_stats
[port
* chip
->num_mibs
];
1890 for (i
= 0; i
< chip
->num_mibs
; i
++)
1891 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1893 chip
->mib_decs
[i
].name
,
1902 mutex_unlock(&priv
->mib_lock
);
1906 static struct switch_attr ar8xxx_sw_attr_globals
[] = {
1908 .type
= SWITCH_TYPE_INT
,
1909 .name
= "enable_vlan",
1910 .description
= "Enable VLAN mode",
1911 .set
= ar8xxx_sw_set_vlan
,
1912 .get
= ar8xxx_sw_get_vlan
,
1916 .type
= SWITCH_TYPE_NOVAL
,
1917 .name
= "reset_mibs",
1918 .description
= "Reset all MIB counters",
1919 .set
= ar8xxx_sw_set_reset_mibs
,
1922 .type
= SWITCH_TYPE_INT
,
1923 .name
= "enable_mirror_rx",
1924 .description
= "Enable mirroring of RX packets",
1925 .set
= ar8xxx_sw_set_mirror_rx_enable
,
1926 .get
= ar8xxx_sw_get_mirror_rx_enable
,
1930 .type
= SWITCH_TYPE_INT
,
1931 .name
= "enable_mirror_tx",
1932 .description
= "Enable mirroring of TX packets",
1933 .set
= ar8xxx_sw_set_mirror_tx_enable
,
1934 .get
= ar8xxx_sw_get_mirror_tx_enable
,
1938 .type
= SWITCH_TYPE_INT
,
1939 .name
= "mirror_monitor_port",
1940 .description
= "Mirror monitor port",
1941 .set
= ar8xxx_sw_set_mirror_monitor_port
,
1942 .get
= ar8xxx_sw_get_mirror_monitor_port
,
1943 .max
= AR8216_NUM_PORTS
- 1
1946 .type
= SWITCH_TYPE_INT
,
1947 .name
= "mirror_source_port",
1948 .description
= "Mirror source port",
1949 .set
= ar8xxx_sw_set_mirror_source_port
,
1950 .get
= ar8xxx_sw_get_mirror_source_port
,
1951 .max
= AR8216_NUM_PORTS
- 1
1955 static struct switch_attr ar8327_sw_attr_globals
[] = {
1957 .type
= SWITCH_TYPE_INT
,
1958 .name
= "enable_vlan",
1959 .description
= "Enable VLAN mode",
1960 .set
= ar8xxx_sw_set_vlan
,
1961 .get
= ar8xxx_sw_get_vlan
,
1965 .type
= SWITCH_TYPE_NOVAL
,
1966 .name
= "reset_mibs",
1967 .description
= "Reset all MIB counters",
1968 .set
= ar8xxx_sw_set_reset_mibs
,
1971 .type
= SWITCH_TYPE_INT
,
1972 .name
= "enable_mirror_rx",
1973 .description
= "Enable mirroring of RX packets",
1974 .set
= ar8xxx_sw_set_mirror_rx_enable
,
1975 .get
= ar8xxx_sw_get_mirror_rx_enable
,
1979 .type
= SWITCH_TYPE_INT
,
1980 .name
= "enable_mirror_tx",
1981 .description
= "Enable mirroring of TX packets",
1982 .set
= ar8xxx_sw_set_mirror_tx_enable
,
1983 .get
= ar8xxx_sw_get_mirror_tx_enable
,
1987 .type
= SWITCH_TYPE_INT
,
1988 .name
= "mirror_monitor_port",
1989 .description
= "Mirror monitor port",
1990 .set
= ar8xxx_sw_set_mirror_monitor_port
,
1991 .get
= ar8xxx_sw_get_mirror_monitor_port
,
1992 .max
= AR8327_NUM_PORTS
- 1
1995 .type
= SWITCH_TYPE_INT
,
1996 .name
= "mirror_source_port",
1997 .description
= "Mirror source port",
1998 .set
= ar8xxx_sw_set_mirror_source_port
,
1999 .get
= ar8xxx_sw_get_mirror_source_port
,
2000 .max
= AR8327_NUM_PORTS
- 1
2004 static struct switch_attr ar8xxx_sw_attr_port
[] = {
2006 .type
= SWITCH_TYPE_NOVAL
,
2007 .name
= "reset_mib",
2008 .description
= "Reset single port MIB counters",
2009 .set
= ar8xxx_sw_set_port_reset_mib
,
2012 .type
= SWITCH_TYPE_STRING
,
2014 .description
= "Get port's MIB counters",
2016 .get
= ar8xxx_sw_get_port_mib
,
2020 static struct switch_attr ar8xxx_sw_attr_vlan
[] = {
2022 .type
= SWITCH_TYPE_INT
,
2024 .description
= "VLAN ID (0-4094)",
2025 .set
= ar8xxx_sw_set_vid
,
2026 .get
= ar8xxx_sw_get_vid
,
2031 static const struct switch_dev_ops ar8xxx_sw_ops
= {
2033 .attr
= ar8xxx_sw_attr_globals
,
2034 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_globals
),
2037 .attr
= ar8xxx_sw_attr_port
,
2038 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
2041 .attr
= ar8xxx_sw_attr_vlan
,
2042 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
2044 .get_port_pvid
= ar8xxx_sw_get_pvid
,
2045 .set_port_pvid
= ar8xxx_sw_set_pvid
,
2046 .get_vlan_ports
= ar8xxx_sw_get_ports
,
2047 .set_vlan_ports
= ar8xxx_sw_set_ports
,
2048 .apply_config
= ar8xxx_sw_hw_apply
,
2049 .reset_switch
= ar8xxx_sw_reset_switch
,
2050 .get_port_link
= ar8xxx_sw_get_port_link
,
2053 static const struct switch_dev_ops ar8327_sw_ops
= {
2055 .attr
= ar8327_sw_attr_globals
,
2056 .n_attr
= ARRAY_SIZE(ar8327_sw_attr_globals
),
2059 .attr
= ar8xxx_sw_attr_port
,
2060 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
2063 .attr
= ar8xxx_sw_attr_vlan
,
2064 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
2066 .get_port_pvid
= ar8xxx_sw_get_pvid
,
2067 .set_port_pvid
= ar8xxx_sw_set_pvid
,
2068 .get_vlan_ports
= ar8xxx_sw_get_ports
,
2069 .set_vlan_ports
= ar8xxx_sw_set_ports
,
2070 .apply_config
= ar8xxx_sw_hw_apply
,
2071 .reset_switch
= ar8xxx_sw_reset_switch
,
2072 .get_port_link
= ar8xxx_sw_get_port_link
,
2076 ar8xxx_id_chip(struct ar8xxx_priv
*priv
)
2082 val
= priv
->read(priv
, AR8216_REG_CTRL
);
2086 id
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
2087 for (i
= 0; i
< AR8X16_PROBE_RETRIES
; i
++) {
2090 val
= priv
->read(priv
, AR8216_REG_CTRL
);
2094 t
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
2099 priv
->chip_ver
= (id
& AR8216_CTRL_VERSION
) >> AR8216_CTRL_VERSION_S
;
2100 priv
->chip_rev
= (id
& AR8216_CTRL_REVISION
);
2102 switch (priv
->chip_ver
) {
2103 case AR8XXX_VER_AR8216
:
2104 priv
->chip
= &ar8216_chip
;
2106 case AR8XXX_VER_AR8236
:
2107 priv
->chip
= &ar8236_chip
;
2109 case AR8XXX_VER_AR8316
:
2110 priv
->chip
= &ar8316_chip
;
2112 case AR8XXX_VER_AR8327
:
2113 priv
->mii_lo_first
= true;
2114 priv
->chip
= &ar8327_chip
;
2116 case AR8XXX_VER_AR8337
:
2117 priv
->mii_lo_first
= true;
2118 priv
->chip
= &ar8327_chip
;
2121 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2122 priv
->chip_ver
, priv
->chip_rev
);
2131 ar8xxx_mib_work_func(struct work_struct
*work
)
2133 struct ar8xxx_priv
*priv
;
2136 priv
= container_of(work
, struct ar8xxx_priv
, mib_work
.work
);
2138 mutex_lock(&priv
->mib_lock
);
2140 err
= ar8xxx_mib_capture(priv
);
2144 ar8xxx_mib_fetch_port_stat(priv
, priv
->mib_next_port
, false);
2147 priv
->mib_next_port
++;
2148 if (priv
->mib_next_port
>= priv
->dev
.ports
)
2149 priv
->mib_next_port
= 0;
2151 mutex_unlock(&priv
->mib_lock
);
2152 schedule_delayed_work(&priv
->mib_work
,
2153 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
2157 ar8xxx_mib_init(struct ar8xxx_priv
*priv
)
2161 if (!ar8xxx_has_mib_counters(priv
))
2164 BUG_ON(!priv
->chip
->mib_decs
|| !priv
->chip
->num_mibs
);
2166 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
2167 sizeof(*priv
->mib_stats
);
2168 priv
->mib_stats
= kzalloc(len
, GFP_KERNEL
);
2170 if (!priv
->mib_stats
)
2177 ar8xxx_mib_start(struct ar8xxx_priv
*priv
)
2179 if (!ar8xxx_has_mib_counters(priv
))
2182 schedule_delayed_work(&priv
->mib_work
,
2183 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
2187 ar8xxx_mib_stop(struct ar8xxx_priv
*priv
)
2189 if (!ar8xxx_has_mib_counters(priv
))
2192 cancel_delayed_work(&priv
->mib_work
);
2195 static struct ar8xxx_priv
*
2198 struct ar8xxx_priv
*priv
;
2200 priv
= kzalloc(sizeof(struct ar8xxx_priv
), GFP_KERNEL
);
2204 mutex_init(&priv
->reg_mutex
);
2205 mutex_init(&priv
->mib_lock
);
2206 INIT_DELAYED_WORK(&priv
->mib_work
, ar8xxx_mib_work_func
);
2212 ar8xxx_free(struct ar8xxx_priv
*priv
)
2214 kfree(priv
->mib_stats
);
2218 static struct ar8xxx_priv
*
2219 ar8xxx_create_mii(struct mii_bus
*bus
)
2221 struct ar8xxx_priv
*priv
;
2223 priv
= ar8xxx_create();
2225 priv
->mii_bus
= bus
;
2226 priv
->read
= ar8xxx_mii_read
;
2227 priv
->write
= ar8xxx_mii_write
;
2234 ar8xxx_probe_switch(struct ar8xxx_priv
*priv
)
2236 struct switch_dev
*swdev
;
2239 ret
= ar8xxx_id_chip(priv
);
2244 swdev
->cpu_port
= AR8216_PORT_CPU
;
2245 swdev
->ops
= &ar8xxx_sw_ops
;
2247 if (chip_is_ar8316(priv
)) {
2248 swdev
->name
= "Atheros AR8316";
2249 swdev
->vlans
= AR8X16_MAX_VLANS
;
2250 swdev
->ports
= AR8216_NUM_PORTS
;
2251 } else if (chip_is_ar8236(priv
)) {
2252 swdev
->name
= "Atheros AR8236";
2253 swdev
->vlans
= AR8216_NUM_VLANS
;
2254 swdev
->ports
= AR8216_NUM_PORTS
;
2255 } else if (chip_is_ar8327(priv
)) {
2256 swdev
->name
= "Atheros AR8327";
2257 swdev
->vlans
= AR8X16_MAX_VLANS
;
2258 swdev
->ports
= AR8327_NUM_PORTS
;
2259 swdev
->ops
= &ar8327_sw_ops
;
2260 } else if (chip_is_ar8337(priv
)) {
2261 swdev
->name
= "Atheros AR8337";
2262 swdev
->vlans
= AR8X16_MAX_VLANS
;
2263 swdev
->ports
= AR8327_NUM_PORTS
;
2264 swdev
->ops
= &ar8327_sw_ops
;
2266 swdev
->name
= "Atheros AR8216";
2267 swdev
->vlans
= AR8216_NUM_VLANS
;
2268 swdev
->ports
= AR8216_NUM_PORTS
;
2271 ret
= ar8xxx_mib_init(priv
);
2279 ar8xxx_start(struct ar8xxx_priv
*priv
)
2285 ret
= priv
->chip
->hw_init(priv
);
2289 ret
= ar8xxx_sw_reset_switch(&priv
->dev
);
2295 ar8xxx_mib_start(priv
);
2301 ar8xxx_phy_config_init(struct phy_device
*phydev
)
2303 struct ar8xxx_priv
*priv
= phydev
->priv
;
2304 struct net_device
*dev
= phydev
->attached_dev
;
2310 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
))
2315 if (phydev
->addr
!= 0) {
2316 if (chip_is_ar8316(priv
)) {
2317 /* switch device has been initialized, reinit */
2318 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
2319 priv
->initialized
= false;
2320 priv
->port4_phy
= true;
2321 ar8316_hw_init(priv
);
2328 ret
= ar8xxx_start(priv
);
2332 /* VID fixup only needed on ar8216 */
2333 if (chip_is_ar8216(priv
)) {
2334 dev
->phy_ptr
= priv
;
2335 dev
->priv_flags
|= IFF_NO_IP_ALIGN
;
2336 dev
->eth_mangle_rx
= ar8216_mangle_rx
;
2337 dev
->eth_mangle_tx
= ar8216_mangle_tx
;
2344 ar8xxx_phy_read_status(struct phy_device
*phydev
)
2346 struct ar8xxx_priv
*priv
= phydev
->priv
;
2347 struct switch_port_link link
;
2350 if (phydev
->addr
!= 0)
2351 return genphy_read_status(phydev
);
2353 ar8216_read_port_link(priv
, phydev
->addr
, &link
);
2354 phydev
->link
= !!link
.link
;
2358 switch (link
.speed
) {
2359 case SWITCH_PORT_SPEED_10
:
2360 phydev
->speed
= SPEED_10
;
2362 case SWITCH_PORT_SPEED_100
:
2363 phydev
->speed
= SPEED_100
;
2365 case SWITCH_PORT_SPEED_1000
:
2366 phydev
->speed
= SPEED_1000
;
2371 phydev
->duplex
= link
.duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
2373 /* flush the address translation unit */
2374 mutex_lock(&priv
->reg_mutex
);
2375 ret
= priv
->chip
->atu_flush(priv
);
2376 mutex_unlock(&priv
->reg_mutex
);
2378 phydev
->state
= PHY_RUNNING
;
2379 netif_carrier_on(phydev
->attached_dev
);
2380 phydev
->adjust_link(phydev
->attached_dev
);
2386 ar8xxx_phy_config_aneg(struct phy_device
*phydev
)
2388 if (phydev
->addr
== 0)
2391 return genphy_config_aneg(phydev
);
2394 static const u32 ar8xxx_phy_ids
[] = {
2396 0x004dd034, /* AR8327 */
2397 0x004dd036, /* AR8337 */
2403 ar8xxx_phy_match(u32 phy_id
)
2407 for (i
= 0; i
< ARRAY_SIZE(ar8xxx_phy_ids
); i
++)
2408 if (phy_id
== ar8xxx_phy_ids
[i
])
2415 ar8xxx_is_possible(struct mii_bus
*bus
)
2419 for (i
= 0; i
< 4; i
++) {
2422 phy_id
= mdiobus_read(bus
, i
, MII_PHYSID1
) << 16;
2423 phy_id
|= mdiobus_read(bus
, i
, MII_PHYSID2
);
2424 if (!ar8xxx_phy_match(phy_id
)) {
2425 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2426 dev_name(&bus
->dev
), i
, phy_id
);
2435 ar8xxx_phy_probe(struct phy_device
*phydev
)
2437 struct ar8xxx_priv
*priv
;
2438 struct switch_dev
*swdev
;
2441 /* skip PHYs at unused adresses */
2442 if (phydev
->addr
!= 0 && phydev
->addr
!= 4)
2445 if (!ar8xxx_is_possible(phydev
->bus
))
2448 mutex_lock(&ar8xxx_dev_list_lock
);
2449 list_for_each_entry(priv
, &ar8xxx_dev_list
, list
)
2450 if (priv
->mii_bus
== phydev
->bus
)
2453 priv
= ar8xxx_create_mii(phydev
->bus
);
2459 ret
= ar8xxx_probe_switch(priv
);
2464 swdev
->alias
= dev_name(&priv
->mii_bus
->dev
);
2465 ret
= register_switch(swdev
, NULL
);
2469 pr_info("%s: %s rev. %u switch registered on %s\n",
2470 swdev
->devname
, swdev
->name
, priv
->chip_rev
,
2471 dev_name(&priv
->mii_bus
->dev
));
2476 if (phydev
->addr
== 0) {
2477 if (ar8xxx_has_gige(priv
)) {
2478 phydev
->supported
= SUPPORTED_1000baseT_Full
;
2479 phydev
->advertising
= ADVERTISED_1000baseT_Full
;
2481 phydev
->supported
= SUPPORTED_100baseT_Full
;
2482 phydev
->advertising
= ADVERTISED_100baseT_Full
;
2485 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
)) {
2488 ret
= ar8xxx_start(priv
);
2490 goto err_unregister_switch
;
2493 if (ar8xxx_has_gige(priv
)) {
2494 phydev
->supported
|= SUPPORTED_1000baseT_Full
;
2495 phydev
->advertising
|= ADVERTISED_1000baseT_Full
;
2499 phydev
->priv
= priv
;
2501 list_add(&priv
->list
, &ar8xxx_dev_list
);
2503 mutex_unlock(&ar8xxx_dev_list_lock
);
2507 err_unregister_switch
:
2508 if (--priv
->use_count
)
2511 unregister_switch(&priv
->dev
);
2516 mutex_unlock(&ar8xxx_dev_list_lock
);
2521 ar8xxx_phy_detach(struct phy_device
*phydev
)
2523 struct net_device
*dev
= phydev
->attached_dev
;
2528 dev
->phy_ptr
= NULL
;
2529 dev
->priv_flags
&= ~IFF_NO_IP_ALIGN
;
2530 dev
->eth_mangle_rx
= NULL
;
2531 dev
->eth_mangle_tx
= NULL
;
2535 ar8xxx_phy_remove(struct phy_device
*phydev
)
2537 struct ar8xxx_priv
*priv
= phydev
->priv
;
2542 phydev
->priv
= NULL
;
2543 if (--priv
->use_count
> 0)
2546 mutex_lock(&ar8xxx_dev_list_lock
);
2547 list_del(&priv
->list
);
2548 mutex_unlock(&ar8xxx_dev_list_lock
);
2550 unregister_switch(&priv
->dev
);
2551 ar8xxx_mib_stop(priv
);
2555 static struct phy_driver ar8xxx_phy_driver
= {
2556 .phy_id
= 0x004d0000,
2557 .name
= "Atheros AR8216/AR8236/AR8316",
2558 .phy_id_mask
= 0xffff0000,
2559 .features
= PHY_BASIC_FEATURES
,
2560 .probe
= ar8xxx_phy_probe
,
2561 .remove
= ar8xxx_phy_remove
,
2562 .detach
= ar8xxx_phy_detach
,
2563 .config_init
= ar8xxx_phy_config_init
,
2564 .config_aneg
= ar8xxx_phy_config_aneg
,
2565 .read_status
= ar8xxx_phy_read_status
,
2566 .driver
= { .owner
= THIS_MODULE
},
2572 return phy_driver_register(&ar8xxx_phy_driver
);
2578 phy_driver_unregister(&ar8xxx_phy_driver
);
2581 module_init(ar8xxx_init
);
2582 module_exit(ar8xxx_exit
);
2583 MODULE_LICENSE("GPL");