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kernel: b53: add soft reset for BCM539x switches
[openwrt/openwrt.git] / target / linux / generic / files / drivers / net / phy / b53 / b53_common.c
1 /*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
21 #include <linux/delay.h>
22 #include <linux/export.h>
23 #include <linux/gpio.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/switch.h>
27 #include <linux/platform_data/b53.h>
28
29 #include "b53_regs.h"
30 #include "b53_priv.h"
31
32 /* buffer size needed for displaying all MIBs with max'd values */
33 #define B53_BUF_SIZE 1188
34
35 struct b53_mib_desc {
36 u8 size;
37 u8 offset;
38 const char *name;
39 };
40
41
42 /* BCM5365 MIB counters */
43 static const struct b53_mib_desc b53_mibs_65[] = {
44 { 8, 0x00, "TxOctets" },
45 { 4, 0x08, "TxDropPkts" },
46 { 4, 0x10, "TxBroadcastPkts" },
47 { 4, 0x14, "TxMulticastPkts" },
48 { 4, 0x18, "TxUnicastPkts" },
49 { 4, 0x1c, "TxCollisions" },
50 { 4, 0x20, "TxSingleCollision" },
51 { 4, 0x24, "TxMultipleCollision" },
52 { 4, 0x28, "TxDeferredTransmit" },
53 { 4, 0x2c, "TxLateCollision" },
54 { 4, 0x30, "TxExcessiveCollision" },
55 { 4, 0x38, "TxPausePkts" },
56 { 8, 0x44, "RxOctets" },
57 { 4, 0x4c, "RxUndersizePkts" },
58 { 4, 0x50, "RxPausePkts" },
59 { 4, 0x54, "Pkts64Octets" },
60 { 4, 0x58, "Pkts65to127Octets" },
61 { 4, 0x5c, "Pkts128to255Octets" },
62 { 4, 0x60, "Pkts256to511Octets" },
63 { 4, 0x64, "Pkts512to1023Octets" },
64 { 4, 0x68, "Pkts1024to1522Octets" },
65 { 4, 0x6c, "RxOversizePkts" },
66 { 4, 0x70, "RxJabbers" },
67 { 4, 0x74, "RxAlignmentErrors" },
68 { 4, 0x78, "RxFCSErrors" },
69 { 8, 0x7c, "RxGoodOctets" },
70 { 4, 0x84, "RxDropPkts" },
71 { 4, 0x88, "RxUnicastPkts" },
72 { 4, 0x8c, "RxMulticastPkts" },
73 { 4, 0x90, "RxBroadcastPkts" },
74 { 4, 0x94, "RxSAChanges" },
75 { 4, 0x98, "RxFragments" },
76 { },
77 };
78
79 /* BCM63xx MIB counters */
80 static const struct b53_mib_desc b53_mibs_63xx[] = {
81 { 8, 0x00, "TxOctets" },
82 { 4, 0x08, "TxDropPkts" },
83 { 4, 0x0c, "TxQoSPkts" },
84 { 4, 0x10, "TxBroadcastPkts" },
85 { 4, 0x14, "TxMulticastPkts" },
86 { 4, 0x18, "TxUnicastPkts" },
87 { 4, 0x1c, "TxCollisions" },
88 { 4, 0x20, "TxSingleCollision" },
89 { 4, 0x24, "TxMultipleCollision" },
90 { 4, 0x28, "TxDeferredTransmit" },
91 { 4, 0x2c, "TxLateCollision" },
92 { 4, 0x30, "TxExcessiveCollision" },
93 { 4, 0x38, "TxPausePkts" },
94 { 8, 0x3c, "TxQoSOctets" },
95 { 8, 0x44, "RxOctets" },
96 { 4, 0x4c, "RxUndersizePkts" },
97 { 4, 0x50, "RxPausePkts" },
98 { 4, 0x54, "Pkts64Octets" },
99 { 4, 0x58, "Pkts65to127Octets" },
100 { 4, 0x5c, "Pkts128to255Octets" },
101 { 4, 0x60, "Pkts256to511Octets" },
102 { 4, 0x64, "Pkts512to1023Octets" },
103 { 4, 0x68, "Pkts1024to1522Octets" },
104 { 4, 0x6c, "RxOversizePkts" },
105 { 4, 0x70, "RxJabbers" },
106 { 4, 0x74, "RxAlignmentErrors" },
107 { 4, 0x78, "RxFCSErrors" },
108 { 8, 0x7c, "RxGoodOctets" },
109 { 4, 0x84, "RxDropPkts" },
110 { 4, 0x88, "RxUnicastPkts" },
111 { 4, 0x8c, "RxMulticastPkts" },
112 { 4, 0x90, "RxBroadcastPkts" },
113 { 4, 0x94, "RxSAChanges" },
114 { 4, 0x98, "RxFragments" },
115 { 4, 0xa0, "RxSymbolErrors" },
116 { 4, 0xa4, "RxQoSPkts" },
117 { 8, 0xa8, "RxQoSOctets" },
118 { 4, 0xb0, "Pkts1523to2047Octets" },
119 { 4, 0xb4, "Pkts2048to4095Octets" },
120 { 4, 0xb8, "Pkts4096to8191Octets" },
121 { 4, 0xbc, "Pkts8192to9728Octets" },
122 { 4, 0xc0, "RxDiscarded" },
123 { }
124 };
125
126 /* MIB counters */
127 static const struct b53_mib_desc b53_mibs[] = {
128 { 8, 0x00, "TxOctets" },
129 { 4, 0x08, "TxDropPkts" },
130 { 4, 0x10, "TxBroadcastPkts" },
131 { 4, 0x14, "TxMulticastPkts" },
132 { 4, 0x18, "TxUnicastPkts" },
133 { 4, 0x1c, "TxCollisions" },
134 { 4, 0x20, "TxSingleCollision" },
135 { 4, 0x24, "TxMultipleCollision" },
136 { 4, 0x28, "TxDeferredTransmit" },
137 { 4, 0x2c, "TxLateCollision" },
138 { 4, 0x30, "TxExcessiveCollision" },
139 { 4, 0x38, "TxPausePkts" },
140 { 8, 0x50, "RxOctets" },
141 { 4, 0x58, "RxUndersizePkts" },
142 { 4, 0x5c, "RxPausePkts" },
143 { 4, 0x60, "Pkts64Octets" },
144 { 4, 0x64, "Pkts65to127Octets" },
145 { 4, 0x68, "Pkts128to255Octets" },
146 { 4, 0x6c, "Pkts256to511Octets" },
147 { 4, 0x70, "Pkts512to1023Octets" },
148 { 4, 0x74, "Pkts1024to1522Octets" },
149 { 4, 0x78, "RxOversizePkts" },
150 { 4, 0x7c, "RxJabbers" },
151 { 4, 0x80, "RxAlignmentErrors" },
152 { 4, 0x84, "RxFCSErrors" },
153 { 8, 0x88, "RxGoodOctets" },
154 { 4, 0x90, "RxDropPkts" },
155 { 4, 0x94, "RxUnicastPkts" },
156 { 4, 0x98, "RxMulticastPkts" },
157 { 4, 0x9c, "RxBroadcastPkts" },
158 { 4, 0xa0, "RxSAChanges" },
159 { 4, 0xa4, "RxFragments" },
160 { 4, 0xa8, "RxJumboPkts" },
161 { 4, 0xac, "RxSymbolErrors" },
162 { 4, 0xc0, "RxDiscarded" },
163 { }
164 };
165
166 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
167 {
168 unsigned int i;
169
170 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
171
172 for (i = 0; i < 10; i++) {
173 u8 vta;
174
175 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
176 if (!(vta & VTA_START_CMD))
177 return 0;
178
179 usleep_range(100, 200);
180 }
181
182 return -EIO;
183 }
184
185 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, u16 members,
186 u16 untag)
187 {
188 if (is5325(dev)) {
189 u32 entry = 0;
190
191 if (members)
192 entry = (untag << VA_UNTAG_S) | members | VA_VALID_25;
193
194 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
195 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
196 VTA_RW_STATE_WR | VTA_RW_OP_EN);
197 } else if (is5365(dev)) {
198 u16 entry = 0;
199
200 if (members)
201 entry = (untag << VA_UNTAG_S) | members | VA_VALID_65;
202
203 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
204 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
205 VTA_RW_STATE_WR | VTA_RW_OP_EN);
206 } else {
207 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
208 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
209 (untag << VTE_UNTAG_S) | members);
210
211 b53_do_vlan_op(dev, VTA_CMD_WRITE);
212 }
213 }
214
215 void b53_set_forwarding(struct b53_device *dev, int enable)
216 {
217 u8 mgmt;
218
219 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
220
221 if (enable)
222 mgmt |= SM_SW_FWD_EN;
223 else
224 mgmt &= ~SM_SW_FWD_EN;
225
226 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
227 }
228
229 static void b53_enable_vlan(struct b53_device *dev, int enable)
230 {
231 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
232
233 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
234 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
235 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
236
237 if (is5325(dev) || is5365(dev)) {
238 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
239 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
240 } else if (is63xx(dev)) {
241 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
242 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
243 } else {
244 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
245 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
246 }
247
248 mgmt &= ~SM_SW_FWD_MODE;
249
250 if (enable) {
251 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
252 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
253 vc4 &= ~VC4_ING_VID_CHECK_MASK;
254 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
255 vc5 |= VC5_DROP_VTABLE_MISS;
256
257 if (is5325(dev))
258 vc0 &= ~VC0_RESERVED_1;
259
260 if (is5325(dev) || is5365(dev))
261 vc1 |= VC1_RX_MCST_TAG_EN;
262
263 if (!is5325(dev) && !is5365(dev)) {
264 if (dev->allow_vid_4095)
265 vc5 |= VC5_VID_FFF_EN;
266 else
267 vc5 &= ~VC5_VID_FFF_EN;
268 }
269 } else {
270 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
271 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
272 vc4 &= ~VC4_ING_VID_CHECK_MASK;
273 vc5 &= ~VC5_DROP_VTABLE_MISS;
274
275 if (is5325(dev) || is5365(dev))
276 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
277 else
278 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
279
280 if (is5325(dev) || is5365(dev))
281 vc1 &= ~VC1_RX_MCST_TAG_EN;
282
283 if (!is5325(dev) && !is5365(dev))
284 vc5 &= ~VC5_VID_FFF_EN;
285 }
286
287 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
288 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
289
290 if (is5325(dev) || is5365(dev)) {
291 /* enable the high 8 bit vid check on 5325 */
292 if (is5325(dev) && enable)
293 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
294 VC3_HIGH_8BIT_EN);
295 else
296 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
297
298 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
299 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
300 } else if (is63xx(dev)) {
301 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
302 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
303 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
304 } else {
305 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
306 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
307 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
308 }
309
310 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
311 }
312
313 static int b53_set_jumbo(struct b53_device *dev, int enable, int allow_10_100)
314 {
315 u32 port_mask = 0;
316 u16 max_size = JMS_MIN_SIZE;
317
318 if (is5325(dev) || is5365(dev))
319 return -EINVAL;
320
321 if (enable) {
322 port_mask = dev->enabled_ports;
323 max_size = JMS_MAX_SIZE;
324 if (allow_10_100)
325 port_mask |= JPM_10_100_JUMBO_EN;
326 }
327
328 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
329 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
330 }
331
332 static int b53_flush_arl(struct b53_device *dev)
333 {
334 unsigned int i;
335
336 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
337 FAST_AGE_DONE | FAST_AGE_DYNAMIC | FAST_AGE_STATIC);
338
339 for (i = 0; i < 10; i++) {
340 u8 fast_age_ctrl;
341
342 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
343 &fast_age_ctrl);
344
345 if (!(fast_age_ctrl & FAST_AGE_DONE))
346 return 0;
347
348 mdelay(1);
349 }
350
351 pr_warn("time out while flushing ARL\n");
352
353 return -EINVAL;
354 }
355
356 static void b53_enable_ports(struct b53_device *dev)
357 {
358 unsigned i;
359
360 b53_for_each_port(dev, i) {
361 u8 port_ctrl;
362 u16 pvlan_mask;
363
364 /*
365 * prevent leaking packets between wan and lan in unmanaged
366 * mode through port vlans.
367 */
368 if (dev->enable_vlan || is_cpu_port(dev, i))
369 pvlan_mask = 0x1ff;
370 else if (is531x5(dev))
371 /* BCM53115 may use a different port as cpu port */
372 pvlan_mask = BIT(dev->sw_dev.cpu_port);
373 else
374 pvlan_mask = BIT(B53_CPU_PORT);
375
376 /* BCM5325 CPU port is at 8 */
377 if ((is5325(dev) || is5365(dev)) && i == B53_CPU_PORT_25)
378 i = B53_CPU_PORT;
379
380 if (dev->chip_id == BCM5398_DEVICE_ID && (i == 6 || i == 7))
381 /* disable unused ports 6 & 7 */
382 port_ctrl = PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
383 else if (i == B53_CPU_PORT)
384 port_ctrl = PORT_CTRL_RX_BCST_EN |
385 PORT_CTRL_RX_MCST_EN |
386 PORT_CTRL_RX_UCST_EN;
387 else
388 port_ctrl = 0;
389
390 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i),
391 pvlan_mask);
392
393 /* port state is handled by bcm63xx_enet driver */
394 if (!is63xx(dev))
395 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(i),
396 port_ctrl);
397 }
398 }
399
400 static void b53_enable_mib(struct b53_device *dev)
401 {
402 u8 gc;
403
404 b53_read8(dev, B53_CTRL_PAGE, B53_GLOBAL_CONFIG, &gc);
405
406 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
407
408 b53_write8(dev, B53_CTRL_PAGE, B53_GLOBAL_CONFIG, gc);
409 }
410
411 static int b53_apply(struct b53_device *dev)
412 {
413 int i;
414
415 /* clear all vlan entries */
416 if (is5325(dev) || is5365(dev)) {
417 for (i = 1; i < dev->sw_dev.vlans; i++)
418 b53_set_vlan_entry(dev, i, 0, 0);
419 } else {
420 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
421 }
422
423 b53_enable_vlan(dev, dev->enable_vlan);
424
425 /* fill VLAN table */
426 if (dev->enable_vlan) {
427 for (i = 0; i < dev->sw_dev.vlans; i++) {
428 struct b53_vlan *vlan = &dev->vlans[i];
429
430 if (!vlan->members)
431 continue;
432
433 b53_set_vlan_entry(dev, i, vlan->members, vlan->untag);
434 }
435
436 b53_for_each_port(dev, i)
437 b53_write16(dev, B53_VLAN_PAGE,
438 B53_VLAN_PORT_DEF_TAG(i),
439 dev->ports[i].pvid);
440 } else {
441 b53_for_each_port(dev, i)
442 b53_write16(dev, B53_VLAN_PAGE,
443 B53_VLAN_PORT_DEF_TAG(i), 1);
444
445 }
446
447 b53_enable_ports(dev);
448
449 if (!is5325(dev) && !is5365(dev))
450 b53_set_jumbo(dev, dev->enable_jumbo, 1);
451
452 return 0;
453 }
454
455 void b53_switch_reset_gpio(struct b53_device *dev)
456 {
457 int gpio = dev->reset_gpio;
458
459 if (gpio < 0)
460 return;
461
462 /*
463 * Reset sequence: RESET low(50ms)->high(20ms)
464 */
465 gpio_set_value(gpio, 0);
466 mdelay(50);
467
468 gpio_set_value(gpio, 1);
469 mdelay(20);
470
471 dev->current_page = 0xff;
472 }
473
474 static int b53_switch_reset(struct b53_device *dev)
475 {
476 u8 mgmt;
477
478 b53_switch_reset_gpio(dev);
479
480 if (is539x(dev)) {
481 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
482 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
483 }
484
485 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
486
487 if (!(mgmt & SM_SW_FWD_EN)) {
488 mgmt &= ~SM_SW_FWD_MODE;
489 mgmt |= SM_SW_FWD_EN;
490
491 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
492 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
493
494 if (!(mgmt & SM_SW_FWD_EN)) {
495 pr_err("Failed to enable switch!\n");
496 return -EINVAL;
497 }
498 }
499
500 /* enable all ports */
501 b53_enable_ports(dev);
502
503 /* configure MII port if necessary */
504 if (is5325(dev)) {
505 u8 mii_port_override;
506
507 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
508 &mii_port_override);
509 /* reverse mii needs to be enabled */
510 if (!(mii_port_override & PORT_OVERRIDE_RV_MII_25)) {
511 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
512 mii_port_override | PORT_OVERRIDE_RV_MII_25);
513 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
514 &mii_port_override);
515
516 if (!(mii_port_override & PORT_OVERRIDE_RV_MII_25)) {
517 pr_err("Failed to enable reverse MII mode\n");
518 return -EINVAL;
519 }
520 }
521 } else if (is531x5(dev) && dev->sw_dev.cpu_port == B53_CPU_PORT) {
522 u8 mii_port_override;
523
524 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
525 &mii_port_override);
526 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
527 mii_port_override | PORT_OVERRIDE_EN |
528 PORT_OVERRIDE_LINK);
529 }
530
531 b53_enable_mib(dev);
532
533 return b53_flush_arl(dev);
534 }
535
536 /*
537 * Swconfig glue functions
538 */
539
540 static int b53_global_get_vlan_enable(struct switch_dev *dev,
541 const struct switch_attr *attr,
542 struct switch_val *val)
543 {
544 struct b53_device *priv = sw_to_b53(dev);
545
546 val->value.i = priv->enable_vlan;
547
548 return 0;
549 }
550
551 static int b53_global_set_vlan_enable(struct switch_dev *dev,
552 const struct switch_attr *attr,
553 struct switch_val *val)
554 {
555 struct b53_device *priv = sw_to_b53(dev);
556
557 priv->enable_vlan = val->value.i;
558
559 return 0;
560 }
561
562 static int b53_global_get_jumbo_enable(struct switch_dev *dev,
563 const struct switch_attr *attr,
564 struct switch_val *val)
565 {
566 struct b53_device *priv = sw_to_b53(dev);
567
568 val->value.i = priv->enable_jumbo;
569
570 return 0;
571 }
572
573 static int b53_global_set_jumbo_enable(struct switch_dev *dev,
574 const struct switch_attr *attr,
575 struct switch_val *val)
576 {
577 struct b53_device *priv = sw_to_b53(dev);
578
579 priv->enable_jumbo = val->value.i;
580
581 return 0;
582 }
583
584 static int b53_global_get_4095_enable(struct switch_dev *dev,
585 const struct switch_attr *attr,
586 struct switch_val *val)
587 {
588 struct b53_device *priv = sw_to_b53(dev);
589
590 val->value.i = priv->allow_vid_4095;
591
592 return 0;
593 }
594
595 static int b53_global_set_4095_enable(struct switch_dev *dev,
596 const struct switch_attr *attr,
597 struct switch_val *val)
598 {
599 struct b53_device *priv = sw_to_b53(dev);
600
601 priv->allow_vid_4095 = val->value.i;
602
603 return 0;
604 }
605
606 static int b53_global_get_ports(struct switch_dev *dev,
607 const struct switch_attr *attr,
608 struct switch_val *val)
609 {
610 struct b53_device *priv = sw_to_b53(dev);
611
612 val->len = snprintf(priv->buf, B53_BUF_SIZE, "0x%04x",
613 priv->enabled_ports);
614 val->value.s = priv->buf;
615
616 return 0;
617 }
618
619 static int b53_port_get_pvid(struct switch_dev *dev, int port, int *val)
620 {
621 struct b53_device *priv = sw_to_b53(dev);
622
623 *val = priv->ports[port].pvid;
624
625 return 0;
626 }
627
628 static int b53_port_set_pvid(struct switch_dev *dev, int port, int val)
629 {
630 struct b53_device *priv = sw_to_b53(dev);
631
632 if (val > 15 && is5325(priv))
633 return -EINVAL;
634 if (val == 4095 && !priv->allow_vid_4095)
635 return -EINVAL;
636
637 priv->ports[port].pvid = val;
638
639 return 0;
640 }
641
642 static int b53_vlan_get_ports(struct switch_dev *dev, struct switch_val *val)
643 {
644 struct b53_device *priv = sw_to_b53(dev);
645 struct switch_port *port = &val->value.ports[0];
646 struct b53_vlan *vlan = &priv->vlans[val->port_vlan];
647 int i;
648
649 val->len = 0;
650
651 if (!vlan->members)
652 return 0;
653
654 for (i = 0; i < dev->ports; i++) {
655 if (!(vlan->members & BIT(i)))
656 continue;
657
658
659 if (!(vlan->untag & BIT(i)))
660 port->flags = BIT(SWITCH_PORT_FLAG_TAGGED);
661 else
662 port->flags = 0;
663
664 port->id = i;
665 val->len++;
666 port++;
667 }
668
669 return 0;
670 }
671
672 static int b53_vlan_set_ports(struct switch_dev *dev, struct switch_val *val)
673 {
674 struct b53_device *priv = sw_to_b53(dev);
675 struct switch_port *port;
676 struct b53_vlan *vlan = &priv->vlans[val->port_vlan];
677 int i;
678
679 /* only BCM5325 and BCM5365 supports VID 0 */
680 if (val->port_vlan == 0 && !is5325(priv) && !is5365(priv))
681 return -EINVAL;
682
683 /* VLAN 4095 needs special handling */
684 if (val->port_vlan == 4095 && !priv->allow_vid_4095)
685 return -EINVAL;
686
687 port = &val->value.ports[0];
688 vlan->members = 0;
689 vlan->untag = 0;
690 for (i = 0; i < val->len; i++, port++) {
691 vlan->members |= BIT(port->id);
692
693 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED))) {
694 vlan->untag |= BIT(port->id);
695 priv->ports[port->id].pvid = val->port_vlan;
696 };
697 }
698
699 /* ignore disabled ports */
700 vlan->members &= priv->enabled_ports;
701 vlan->untag &= priv->enabled_ports;
702
703 return 0;
704 }
705
706 static int b53_port_get_link(struct switch_dev *dev, int port,
707 struct switch_port_link *link)
708 {
709 struct b53_device *priv = sw_to_b53(dev);
710
711 if (is_cpu_port(priv, port)) {
712 link->link = 1;
713 link->duplex = 1;
714 link->speed = is5325(priv) || is5365(priv) ?
715 SWITCH_PORT_SPEED_100 : SWITCH_PORT_SPEED_1000;
716 link->aneg = 0;
717 } else if (priv->enabled_ports & BIT(port)) {
718 u32 speed;
719 u16 lnk, duplex;
720
721 b53_read16(priv, B53_STAT_PAGE, B53_LINK_STAT, &lnk);
722 b53_read16(priv, B53_STAT_PAGE, priv->duplex_reg, &duplex);
723
724 lnk = (lnk >> port) & 1;
725 duplex = (duplex >> port) & 1;
726
727 if (is5325(priv) || is5365(priv)) {
728 u16 tmp;
729
730 b53_read16(priv, B53_STAT_PAGE, B53_SPEED_STAT, &tmp);
731 speed = SPEED_PORT_FE(tmp, port);
732 } else {
733 b53_read32(priv, B53_STAT_PAGE, B53_SPEED_STAT, &speed);
734 speed = SPEED_PORT_GE(speed, port);
735 }
736
737 link->link = lnk;
738 if (lnk) {
739 link->duplex = duplex;
740 switch (speed) {
741 case SPEED_STAT_10M:
742 link->speed = SWITCH_PORT_SPEED_10;
743 break;
744 case SPEED_STAT_100M:
745 link->speed = SWITCH_PORT_SPEED_100;
746 break;
747 case SPEED_STAT_1000M:
748 link->speed = SWITCH_PORT_SPEED_1000;
749 break;
750 }
751 }
752
753 link->aneg = 1;
754 } else {
755 link->link = 0;
756 }
757
758 return 0;
759
760 }
761
762 static int b53_global_reset_switch(struct switch_dev *dev)
763 {
764 struct b53_device *priv = sw_to_b53(dev);
765
766 /* reset vlans */
767 priv->enable_vlan = 0;
768 priv->enable_jumbo = 0;
769 priv->allow_vid_4095 = 0;
770
771 memset(priv->vlans, 0, sizeof(priv->vlans) * dev->vlans);
772 memset(priv->ports, 0, sizeof(priv->ports) * dev->ports);
773
774 return b53_switch_reset(priv);
775 }
776
777 static int b53_global_apply_config(struct switch_dev *dev)
778 {
779 struct b53_device *priv = sw_to_b53(dev);
780
781 /* disable switching */
782 b53_set_forwarding(priv, 0);
783
784 b53_apply(priv);
785
786 /* enable switching */
787 b53_set_forwarding(priv, 1);
788
789 return 0;
790 }
791
792
793 static int b53_global_reset_mib(struct switch_dev *dev,
794 const struct switch_attr *attr,
795 struct switch_val *val)
796 {
797 struct b53_device *priv = sw_to_b53(dev);
798 u8 gc;
799
800 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
801
802 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
803 mdelay(1);
804 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
805 mdelay(1);
806
807 return 0;
808 }
809
810 static int b53_port_get_mib(struct switch_dev *sw_dev,
811 const struct switch_attr *attr,
812 struct switch_val *val)
813 {
814 struct b53_device *dev = sw_to_b53(sw_dev);
815 const struct b53_mib_desc *mibs;
816 int port = val->port_vlan;
817 int len = 0;
818
819 if (!(BIT(port) & dev->enabled_ports))
820 return -1;
821
822 if (is5365(dev)) {
823 if (port == 5)
824 port = 8;
825
826 mibs = b53_mibs_65;
827 } else if (is63xx(dev)) {
828 mibs = b53_mibs_63xx;
829 } else {
830 mibs = b53_mibs;
831 }
832
833 dev->buf[0] = 0;
834
835 for (; mibs->size > 0; mibs++) {
836 u64 val;
837
838 if (mibs->size == 8) {
839 b53_read64(dev, B53_MIB_PAGE(port), mibs->offset, &val);
840 } else {
841 u32 val32;
842
843 b53_read32(dev, B53_MIB_PAGE(port), mibs->offset,
844 &val32);
845 val = val32;
846 }
847
848 len += snprintf(dev->buf + len, B53_BUF_SIZE - len,
849 "%-20s: %llu\n", mibs->name, val);
850 }
851
852 val->len = len;
853 val->value.s = dev->buf;
854
855 return 0;
856 }
857
858 static struct switch_attr b53_global_ops_25[] = {
859 {
860 .type = SWITCH_TYPE_INT,
861 .name = "enable_vlan",
862 .description = "Enable VLAN mode",
863 .set = b53_global_set_vlan_enable,
864 .get = b53_global_get_vlan_enable,
865 .max = 1,
866 },
867 {
868 .type = SWITCH_TYPE_STRING,
869 .name = "ports",
870 .description = "Available ports (as bitmask)",
871 .get = b53_global_get_ports,
872 },
873 };
874
875 static struct switch_attr b53_global_ops_65[] = {
876 {
877 .type = SWITCH_TYPE_INT,
878 .name = "enable_vlan",
879 .description = "Enable VLAN mode",
880 .set = b53_global_set_vlan_enable,
881 .get = b53_global_get_vlan_enable,
882 .max = 1,
883 },
884 {
885 .type = SWITCH_TYPE_STRING,
886 .name = "ports",
887 .description = "Available ports (as bitmask)",
888 .get = b53_global_get_ports,
889 },
890 {
891 .type = SWITCH_TYPE_INT,
892 .name = "reset_mib",
893 .description = "Reset MIB counters",
894 .set = b53_global_reset_mib,
895 },
896 };
897
898 static struct switch_attr b53_global_ops[] = {
899 {
900 .type = SWITCH_TYPE_INT,
901 .name = "enable_vlan",
902 .description = "Enable VLAN mode",
903 .set = b53_global_set_vlan_enable,
904 .get = b53_global_get_vlan_enable,
905 .max = 1,
906 },
907 {
908 .type = SWITCH_TYPE_STRING,
909 .name = "ports",
910 .description = "Available Ports (as bitmask)",
911 .get = b53_global_get_ports,
912 },
913 {
914 .type = SWITCH_TYPE_INT,
915 .name = "reset_mib",
916 .description = "Reset MIB counters",
917 .set = b53_global_reset_mib,
918 },
919 {
920 .type = SWITCH_TYPE_INT,
921 .name = "enable_jumbo",
922 .description = "Enable Jumbo Frames",
923 .set = b53_global_set_jumbo_enable,
924 .get = b53_global_get_jumbo_enable,
925 .max = 1,
926 },
927 {
928 .type = SWITCH_TYPE_INT,
929 .name = "allow_vid_4095",
930 .description = "Allow VID 4095",
931 .set = b53_global_set_4095_enable,
932 .get = b53_global_get_4095_enable,
933 .max = 1,
934 },
935 };
936
937 static struct switch_attr b53_port_ops[] = {
938 {
939 .type = SWITCH_TYPE_STRING,
940 .name = "mib",
941 .description = "Get port's MIB counters",
942 .get = b53_port_get_mib,
943 },
944 };
945
946 static struct switch_attr b53_no_ops[] = {
947 };
948
949 static const struct switch_dev_ops b53_switch_ops_25 = {
950 .attr_global = {
951 .attr = b53_global_ops_25,
952 .n_attr = ARRAY_SIZE(b53_global_ops_25),
953 },
954 .attr_port = {
955 .attr = b53_no_ops,
956 .n_attr = ARRAY_SIZE(b53_no_ops),
957 },
958 .attr_vlan = {
959 .attr = b53_no_ops,
960 .n_attr = ARRAY_SIZE(b53_no_ops),
961 },
962
963 .get_vlan_ports = b53_vlan_get_ports,
964 .set_vlan_ports = b53_vlan_set_ports,
965 .get_port_pvid = b53_port_get_pvid,
966 .set_port_pvid = b53_port_set_pvid,
967 .apply_config = b53_global_apply_config,
968 .reset_switch = b53_global_reset_switch,
969 .get_port_link = b53_port_get_link,
970 };
971
972 static const struct switch_dev_ops b53_switch_ops_65 = {
973 .attr_global = {
974 .attr = b53_global_ops_65,
975 .n_attr = ARRAY_SIZE(b53_global_ops_65),
976 },
977 .attr_port = {
978 .attr = b53_port_ops,
979 .n_attr = ARRAY_SIZE(b53_port_ops),
980 },
981 .attr_vlan = {
982 .attr = b53_no_ops,
983 .n_attr = ARRAY_SIZE(b53_no_ops),
984 },
985
986 .get_vlan_ports = b53_vlan_get_ports,
987 .set_vlan_ports = b53_vlan_set_ports,
988 .get_port_pvid = b53_port_get_pvid,
989 .set_port_pvid = b53_port_set_pvid,
990 .apply_config = b53_global_apply_config,
991 .reset_switch = b53_global_reset_switch,
992 .get_port_link = b53_port_get_link,
993 };
994
995 static const struct switch_dev_ops b53_switch_ops = {
996 .attr_global = {
997 .attr = b53_global_ops,
998 .n_attr = ARRAY_SIZE(b53_global_ops),
999 },
1000 .attr_port = {
1001 .attr = b53_port_ops,
1002 .n_attr = ARRAY_SIZE(b53_port_ops),
1003 },
1004 .attr_vlan = {
1005 .attr = b53_no_ops,
1006 .n_attr = ARRAY_SIZE(b53_no_ops),
1007 },
1008
1009 .get_vlan_ports = b53_vlan_get_ports,
1010 .set_vlan_ports = b53_vlan_set_ports,
1011 .get_port_pvid = b53_port_get_pvid,
1012 .set_port_pvid = b53_port_set_pvid,
1013 .apply_config = b53_global_apply_config,
1014 .reset_switch = b53_global_reset_switch,
1015 .get_port_link = b53_port_get_link,
1016 };
1017
1018 struct b53_chip_data {
1019 u32 chip_id;
1020 const char *dev_name;
1021 const char *alias;
1022 u16 vlans;
1023 u16 enabled_ports;
1024 u8 cpu_port;
1025 u8 vta_regs[3];
1026 u8 duplex_reg;
1027 u8 jumbo_pm_reg;
1028 u8 jumbo_size_reg;
1029 const struct switch_dev_ops *sw_ops;
1030 };
1031
1032 #define B53_VTA_REGS \
1033 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1034 #define B53_VTA_REGS_9798 \
1035 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1036 #define B53_VTA_REGS_63XX \
1037 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1038
1039 static const struct b53_chip_data b53_switch_chips[] = {
1040 {
1041 .chip_id = BCM5325_DEVICE_ID,
1042 .dev_name = "BCM5325",
1043 .alias = "bcm5325",
1044 .vlans = 16,
1045 .enabled_ports = 0x1f,
1046 .cpu_port = B53_CPU_PORT_25,
1047 .duplex_reg = B53_DUPLEX_STAT_FE,
1048 .sw_ops = &b53_switch_ops_25,
1049 },
1050 {
1051 .chip_id = BCM5365_DEVICE_ID,
1052 .dev_name = "BCM5365",
1053 .alias = "bcm5365",
1054 .vlans = 256,
1055 .enabled_ports = 0x1f,
1056 .cpu_port = B53_CPU_PORT_25,
1057 .duplex_reg = B53_DUPLEX_STAT_FE,
1058 .sw_ops = &b53_switch_ops_65,
1059 },
1060 {
1061 .chip_id = BCM5395_DEVICE_ID,
1062 .dev_name = "BCM5395",
1063 .alias = "bcm5395",
1064 .vlans = 4096,
1065 .enabled_ports = 0x1f,
1066 .cpu_port = B53_CPU_PORT,
1067 .vta_regs = B53_VTA_REGS,
1068 .duplex_reg = B53_DUPLEX_STAT_GE,
1069 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1070 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1071 .sw_ops = &b53_switch_ops,
1072 },
1073 {
1074 .chip_id = BCM5397_DEVICE_ID,
1075 .dev_name = "BCM5397",
1076 .alias = "bcm5397",
1077 .vlans = 4096,
1078 .enabled_ports = 0x1f,
1079 .cpu_port = B53_CPU_PORT,
1080 .vta_regs = B53_VTA_REGS_9798,
1081 .duplex_reg = B53_DUPLEX_STAT_GE,
1082 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1083 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1084 .sw_ops = &b53_switch_ops,
1085 },
1086 {
1087 .chip_id = BCM5398_DEVICE_ID,
1088 .dev_name = "BCM5398",
1089 .alias = "bcm5398",
1090 .vlans = 4096,
1091 .enabled_ports = 0x7f,
1092 .cpu_port = B53_CPU_PORT,
1093 .vta_regs = B53_VTA_REGS_9798,
1094 .duplex_reg = B53_DUPLEX_STAT_GE,
1095 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1096 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1097 .sw_ops = &b53_switch_ops,
1098 },
1099 {
1100 .chip_id = BCM53115_DEVICE_ID,
1101 .dev_name = "BCM53115",
1102 .alias = "bcm53115",
1103 .vlans = 4096,
1104 .enabled_ports = 0x1f,
1105 .vta_regs = B53_VTA_REGS,
1106 .cpu_port = B53_CPU_PORT,
1107 .duplex_reg = B53_DUPLEX_STAT_GE,
1108 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1109 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1110 .sw_ops = &b53_switch_ops,
1111 },
1112 {
1113 .chip_id = BCM53125_DEVICE_ID,
1114 .dev_name = "BCM53125",
1115 .alias = "bcm53125",
1116 .vlans = 4096,
1117 .enabled_ports = 0x1f,
1118 .cpu_port = B53_CPU_PORT,
1119 .vta_regs = B53_VTA_REGS,
1120 .duplex_reg = B53_DUPLEX_STAT_GE,
1121 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1122 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1123 .sw_ops = &b53_switch_ops,
1124 },
1125 {
1126 .chip_id = BCM63XX_DEVICE_ID,
1127 .dev_name = "BCM63xx",
1128 .alias = "bcm63xx",
1129 .vlans = 4096,
1130 .enabled_ports = 0, /* pdata must provide them */
1131 .cpu_port = B53_CPU_PORT,
1132 .vta_regs = B53_VTA_REGS_63XX,
1133 .duplex_reg = B53_DUPLEX_STAT_63XX,
1134 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1135 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1136 .sw_ops = &b53_switch_ops,
1137 },
1138 };
1139
1140 int b53_switch_init(struct b53_device *dev)
1141 {
1142 struct switch_dev *sw_dev = &dev->sw_dev;
1143 unsigned i;
1144 int ret;
1145
1146 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1147 const struct b53_chip_data *chip = &b53_switch_chips[i];
1148
1149 if (chip->chip_id == dev->chip_id) {
1150 sw_dev->name = chip->dev_name;
1151 if (!sw_dev->alias)
1152 sw_dev->alias = chip->alias;
1153 if (!dev->enabled_ports)
1154 dev->enabled_ports = chip->enabled_ports;
1155 dev->duplex_reg = chip->duplex_reg;
1156 dev->vta_regs[0] = chip->vta_regs[0];
1157 dev->vta_regs[1] = chip->vta_regs[1];
1158 dev->vta_regs[2] = chip->vta_regs[2];
1159 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
1160 sw_dev->ops = chip->sw_ops;
1161 sw_dev->cpu_port = chip->cpu_port;
1162 sw_dev->vlans = chip->vlans;
1163 break;
1164 }
1165 }
1166
1167 if (!sw_dev->name)
1168 return -EINVAL;
1169
1170 /* check which BCM5325x version we have */
1171 if (is5325(dev)) {
1172 u8 vc4;
1173
1174 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1175
1176 /* check reserved bits */
1177 switch (vc4 & 3) {
1178 case 1:
1179 /* BCM5325E */
1180 break;
1181 case 3:
1182 /* BCM5325F - do not use port 4 */
1183 dev->enabled_ports &= ~BIT(4);
1184 break;
1185 default:
1186 /* On the BCM47XX SoCs this is the supported internal switch.*/
1187 #ifndef CONFIG_BCM47XX
1188 /* BCM5325M */
1189 return -EINVAL;
1190 #else
1191 break;
1192 #endif
1193 }
1194 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1195 u64 strap_value;
1196
1197 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1198 /* use second IMP port if GMII is enabled */
1199 if (strap_value & SV_GMII_CTRL_115)
1200 sw_dev->cpu_port = 5;
1201 }
1202
1203 /* cpu port is always last */
1204 sw_dev->ports = sw_dev->cpu_port + 1;
1205 dev->enabled_ports |= BIT(sw_dev->cpu_port);
1206
1207 dev->ports = devm_kzalloc(dev->dev,
1208 sizeof(struct b53_port) * sw_dev->ports,
1209 GFP_KERNEL);
1210 if (!dev->ports)
1211 return -ENOMEM;
1212
1213 dev->vlans = devm_kzalloc(dev->dev,
1214 sizeof(struct b53_vlan) * sw_dev->vlans,
1215 GFP_KERNEL);
1216 if (!dev->vlans)
1217 return -ENOMEM;
1218
1219 dev->buf = devm_kzalloc(dev->dev, B53_BUF_SIZE, GFP_KERNEL);
1220 if (!dev->buf)
1221 return -ENOMEM;
1222
1223 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1224 if (dev->reset_gpio >= 0) {
1225 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, GPIOF_OUT_INIT_HIGH, "robo_reset");
1226 if (ret)
1227 return ret;
1228 }
1229
1230 return b53_switch_reset(dev);
1231 }
1232
1233 struct b53_device *b53_switch_alloc(struct device *base, struct b53_io_ops *ops,
1234 void *priv)
1235 {
1236 struct b53_device *dev;
1237
1238 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
1239 if (!dev)
1240 return NULL;
1241
1242 dev->dev = base;
1243 dev->ops = ops;
1244 dev->priv = priv;
1245 mutex_init(&dev->reg_mutex);
1246
1247 return dev;
1248 }
1249 EXPORT_SYMBOL(b53_switch_alloc);
1250
1251 int b53_switch_detect(struct b53_device *dev)
1252 {
1253 u32 id32;
1254 u16 tmp;
1255 u8 id8;
1256 int ret;
1257
1258 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
1259 if (ret)
1260 return ret;
1261
1262 switch (id8) {
1263 case 0:
1264 /*
1265 * BCM5325 and BCM5365 do not have this register so reads
1266 * return 0. But the read operation did succeed, so assume
1267 * this is one of them.
1268 *
1269 * Next check if we can write to the 5325's VTA register; for
1270 * 5365 it is read only.
1271 */
1272
1273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
1274 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
1275
1276 if (tmp == 0xf)
1277 dev->chip_id = BCM5325_DEVICE_ID;
1278 else
1279 dev->chip_id = BCM5365_DEVICE_ID;
1280 break;
1281 case BCM5395_DEVICE_ID:
1282 case BCM5397_DEVICE_ID:
1283 case BCM5398_DEVICE_ID:
1284 dev->chip_id = id8;
1285 break;
1286 default:
1287 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
1288 if (ret)
1289 return ret;
1290
1291 switch (id32) {
1292 case BCM53115_DEVICE_ID:
1293 case BCM53125_DEVICE_ID:
1294 dev->chip_id = id32;
1295 break;
1296 default:
1297 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
1298 id8, id32);
1299 return -ENODEV;
1300 }
1301 }
1302
1303 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, &dev->core_rev);
1304 }
1305 EXPORT_SYMBOL(b53_switch_detect);
1306
1307 int b53_switch_register(struct b53_device *dev)
1308 {
1309 int ret;
1310
1311 if (dev->pdata) {
1312 dev->chip_id = dev->pdata->chip_id;
1313 dev->enabled_ports = dev->pdata->enabled_ports;
1314 dev->sw_dev.alias = dev->pdata->alias;
1315 }
1316
1317 if (!dev->chip_id && b53_switch_detect(dev))
1318 return -EINVAL;
1319
1320 ret = b53_switch_init(dev);
1321 if (ret)
1322 return ret;
1323
1324 pr_info("found switch: %s, rev %i\n", dev->sw_dev.name, dev->core_rev);
1325
1326 return register_switch(&dev->sw_dev, NULL);
1327 }
1328 EXPORT_SYMBOL(b53_switch_register);
1329
1330 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
1331 MODULE_DESCRIPTION("B53 switch library");
1332 MODULE_LICENSE("Dual BSD/GPL");
OpenWrt Source Repository