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[openwrt/openwrt.git] / target / linux / generic / files / drivers / net / phy / rtl8367b.c
1 /*
2 * Platform driver for the Realtek RTL8367R-VB ethernet switches
3 *
4 * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/of.h>
15 #include <linux/of_platform.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/rtl8367.h>
19
20 #include "rtl8366_smi.h"
21
22 #define RTL8367B_RESET_DELAY 1000 /* msecs*/
23
24 #define RTL8367B_PHY_ADDR_MAX 8
25 #define RTL8367B_PHY_REG_MAX 31
26
27 #define RTL8367B_VID_MASK 0x3fff
28 #define RTL8367B_FID_MASK 0xf
29 #define RTL8367B_UNTAG_MASK 0xff
30 #define RTL8367B_MEMBER_MASK 0xff
31
32 #define RTL8367B_PORT_MISC_CFG_REG(_p) (0x000e + 0x20 * (_p))
33 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_SHIFT 4
34 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_MASK 0x3
35 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_ORIGINAL 0
36 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_KEEP 1
37 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_PRI 2
38 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_REAL 3
39
40 #define RTL8367B_BYPASS_LINE_RATE_REG 0x03f7
41
42 #define RTL8367B_TA_CTRL_REG 0x0500 /*GOOD*/
43 #define RTL8367B_TA_CTRL_SPA_SHIFT 8
44 #define RTL8367B_TA_CTRL_SPA_MASK 0x7
45 #define RTL8367B_TA_CTRL_METHOD BIT(4)/*GOOD*/
46 #define RTL8367B_TA_CTRL_CMD_SHIFT 3
47 #define RTL8367B_TA_CTRL_CMD_READ 0
48 #define RTL8367B_TA_CTRL_CMD_WRITE 1
49 #define RTL8367B_TA_CTRL_TABLE_SHIFT 0 /*GOOD*/
50 #define RTL8367B_TA_CTRL_TABLE_ACLRULE 1
51 #define RTL8367B_TA_CTRL_TABLE_ACLACT 2
52 #define RTL8367B_TA_CTRL_TABLE_CVLAN 3
53 #define RTL8367B_TA_CTRL_TABLE_L2 4
54 #define RTL8367B_TA_CTRL_CVLAN_READ \
55 ((RTL8367B_TA_CTRL_CMD_READ << RTL8367B_TA_CTRL_CMD_SHIFT) | \
56 RTL8367B_TA_CTRL_TABLE_CVLAN)
57 #define RTL8367B_TA_CTRL_CVLAN_WRITE \
58 ((RTL8367B_TA_CTRL_CMD_WRITE << RTL8367B_TA_CTRL_CMD_SHIFT) | \
59 RTL8367B_TA_CTRL_TABLE_CVLAN)
60
61 #define RTL8367B_TA_ADDR_REG 0x0501/*GOOD*/
62 #define RTL8367B_TA_ADDR_MASK 0x3fff/*GOOD*/
63
64 #define RTL8367B_TA_LUT_REG 0x0502/*GOOD*/
65
66 #define RTL8367B_TA_WRDATA_REG(_x) (0x0510 + (_x))/*GOOD*/
67 #define RTL8367B_TA_VLAN_NUM_WORDS 2
68 #define RTL8367B_TA_VLAN_VID_MASK RTL8367B_VID_MASK
69 #define RTL8367B_TA_VLAN0_MEMBER_SHIFT 0
70 #define RTL8367B_TA_VLAN0_MEMBER_MASK RTL8367B_MEMBER_MASK
71 #define RTL8367B_TA_VLAN0_UNTAG_SHIFT 8
72 #define RTL8367B_TA_VLAN0_UNTAG_MASK RTL8367B_MEMBER_MASK
73 #define RTL8367B_TA_VLAN1_FID_SHIFT 0
74 #define RTL8367B_TA_VLAN1_FID_MASK RTL8367B_FID_MASK
75
76 #define RTL8367B_TA_RDDATA_REG(_x) (0x0520 + (_x))/*GOOD*/
77
78 #define RTL8367B_VLAN_PVID_CTRL_REG(_p) (0x0700 + (_p) / 2) /*GOOD*/
79 #define RTL8367B_VLAN_PVID_CTRL_MASK 0x1f /*GOOD*/
80 #define RTL8367B_VLAN_PVID_CTRL_SHIFT(_p) (8 * ((_p) % 2)) /*GOOD*/
81
82 #define RTL8367B_VLAN_MC_BASE(_x) (0x0728 + (_x) * 4) /*GOOD*/
83 #define RTL8367B_VLAN_MC_NUM_WORDS 4 /*GOOD*/
84 #define RTL8367B_VLAN_MC0_MEMBER_SHIFT 0/*GOOD*/
85 #define RTL8367B_VLAN_MC0_MEMBER_MASK RTL8367B_MEMBER_MASK/*GOOD*/
86 #define RTL8367B_VLAN_MC1_FID_SHIFT 0/*GOOD*/
87 #define RTL8367B_VLAN_MC1_FID_MASK RTL8367B_FID_MASK/*GOOD*/
88 #define RTL8367B_VLAN_MC3_EVID_SHIFT 0/*GOOD*/
89 #define RTL8367B_VLAN_MC3_EVID_MASK RTL8367B_VID_MASK/*GOOD*/
90
91 #define RTL8367B_VLAN_CTRL_REG 0x07a8 /*GOOD*/
92 #define RTL8367B_VLAN_CTRL_ENABLE BIT(0)
93
94 #define RTL8367B_VLAN_INGRESS_REG 0x07a9 /*GOOD*/
95
96 #define RTL8367B_PORT_ISOLATION_REG(_p) (0x08a2 + (_p)) /*GOOD*/
97
98 #define RTL8367B_MIB_COUNTER_REG(_x) (0x1000 + (_x)) /*GOOD*/
99 #define RTL8367B_MIB_COUNTER_PORT_OFFSET 0x007c /*GOOD*/
100
101 #define RTL8367B_MIB_ADDRESS_REG 0x1004 /*GOOD*/
102
103 #define RTL8367B_MIB_CTRL0_REG(_x) (0x1005 + (_x)) /*GOOD*/
104 #define RTL8367B_MIB_CTRL0_GLOBAL_RESET_MASK BIT(11) /*GOOD*/
105 #define RTL8367B_MIB_CTRL0_QM_RESET_MASK BIT(10) /*GOOD*/
106 #define RTL8367B_MIB_CTRL0_PORT_RESET_MASK(_p) BIT(2 + (_p)) /*GOOD*/
107 #define RTL8367B_MIB_CTRL0_RESET_MASK BIT(1) /*GOOD*/
108 #define RTL8367B_MIB_CTRL0_BUSY_MASK BIT(0) /*GOOD*/
109
110 #define RTL8367B_SWC0_REG 0x1200/*GOOD*/
111 #define RTL8367B_SWC0_MAX_LENGTH_SHIFT 13/*GOOD*/
112 #define RTL8367B_SWC0_MAX_LENGTH(_x) ((_x) << 13) /*GOOD*/
113 #define RTL8367B_SWC0_MAX_LENGTH_MASK RTL8367B_SWC0_MAX_LENGTH(0x3)
114 #define RTL8367B_SWC0_MAX_LENGTH_1522 RTL8367B_SWC0_MAX_LENGTH(0)
115 #define RTL8367B_SWC0_MAX_LENGTH_1536 RTL8367B_SWC0_MAX_LENGTH(1)
116 #define RTL8367B_SWC0_MAX_LENGTH_1552 RTL8367B_SWC0_MAX_LENGTH(2)
117 #define RTL8367B_SWC0_MAX_LENGTH_16000 RTL8367B_SWC0_MAX_LENGTH(3)
118
119 #define RTL8367B_CHIP_NUMBER_REG 0x1300/*GOOD*/
120
121 #define RTL8367B_CHIP_VER_REG 0x1301/*GOOD*/
122 #define RTL8367B_CHIP_VER_RLVID_SHIFT 12/*GOOD*/
123 #define RTL8367B_CHIP_VER_RLVID_MASK 0xf/*GOOD*/
124 #define RTL8367B_CHIP_VER_MCID_SHIFT 8/*GOOD*/
125 #define RTL8367B_CHIP_VER_MCID_MASK 0xf/*GOOD*/
126 #define RTL8367B_CHIP_VER_BOID_SHIFT 4/*GOOD*/
127 #define RTL8367B_CHIP_VER_BOID_MASK 0xf/*GOOD*/
128 #define RTL8367B_CHIP_VER_AFE_SHIFT 0/*GOOD*/
129 #define RTL8367B_CHIP_VER_AFE_MASK 0x1/*GOOD*/
130
131 #define RTL8367B_CHIP_MODE_REG 0x1302
132 #define RTL8367B_CHIP_MODE_MASK 0x7
133
134 #define RTL8367B_CHIP_DEBUG0_REG 0x1303
135 #define RTL8367B_CHIP_DEBUG0_DUMMY0(_x) BIT(8 + (_x))
136
137 #define RTL8367B_CHIP_DEBUG1_REG 0x1304
138
139 #define RTL8367B_DIS_REG 0x1305
140 #define RTL8367B_DIS_SKIP_MII_RXER(_x) BIT(12 + (_x))
141 #define RTL8367B_DIS_RGMII_SHIFT(_x) (4 * (_x))
142 #define RTL8367B_DIS_RGMII_MASK 0x7
143
144 #define RTL8367B_EXT_RGMXF_REG(_x) (0x1306 + (_x))
145 #define RTL8367B_EXT_RGMXF_DUMMY0_SHIFT 5
146 #define RTL8367B_EXT_RGMXF_DUMMY0_MASK 0x7ff
147 #define RTL8367B_EXT_RGMXF_TXDELAY_SHIFT 3
148 #define RTL8367B_EXT_RGMXF_TXDELAY_MASK 1
149 #define RTL8367B_EXT_RGMXF_RXDELAY_MASK 0x7
150
151 #define RTL8367B_DI_FORCE_REG(_x) (0x1310 + (_x))
152 #define RTL8367B_DI_FORCE_MODE BIT(12)
153 #define RTL8367B_DI_FORCE_NWAY BIT(7)
154 #define RTL8367B_DI_FORCE_TXPAUSE BIT(6)
155 #define RTL8367B_DI_FORCE_RXPAUSE BIT(5)
156 #define RTL8367B_DI_FORCE_LINK BIT(4)
157 #define RTL8367B_DI_FORCE_DUPLEX BIT(2)
158 #define RTL8367B_DI_FORCE_SPEED_MASK 3
159 #define RTL8367B_DI_FORCE_SPEED_10 0
160 #define RTL8367B_DI_FORCE_SPEED_100 1
161 #define RTL8367B_DI_FORCE_SPEED_1000 2
162
163 #define RTL8367B_MAC_FORCE_REG(_x) (0x1312 + (_x))
164
165 #define RTL8367B_CHIP_RESET_REG 0x1322 /*GOOD*/
166 #define RTL8367B_CHIP_RESET_SW BIT(1) /*GOOD*/
167 #define RTL8367B_CHIP_RESET_HW BIT(0) /*GOOD*/
168
169 #define RTL8367B_PORT_STATUS_REG(_p) (0x1352 + (_p)) /*GOOD*/
170 #define RTL8367B_PORT_STATUS_EN_1000_SPI BIT(11) /*GOOD*/
171 #define RTL8367B_PORT_STATUS_EN_100_SPI BIT(10)/*GOOD*/
172 #define RTL8367B_PORT_STATUS_NWAY_FAULT BIT(9)/*GOOD*/
173 #define RTL8367B_PORT_STATUS_LINK_MASTER BIT(8)/*GOOD*/
174 #define RTL8367B_PORT_STATUS_NWAY BIT(7)/*GOOD*/
175 #define RTL8367B_PORT_STATUS_TXPAUSE BIT(6)/*GOOD*/
176 #define RTL8367B_PORT_STATUS_RXPAUSE BIT(5)/*GOOD*/
177 #define RTL8367B_PORT_STATUS_LINK BIT(4)/*GOOD*/
178 #define RTL8367B_PORT_STATUS_DUPLEX BIT(2)/*GOOD*/
179 #define RTL8367B_PORT_STATUS_SPEED_MASK 0x0003/*GOOD*/
180 #define RTL8367B_PORT_STATUS_SPEED_10 0/*GOOD*/
181 #define RTL8367B_PORT_STATUS_SPEED_100 1/*GOOD*/
182 #define RTL8367B_PORT_STATUS_SPEED_1000 2/*GOOD*/
183
184 #define RTL8367B_RTL_MAGIC_ID_REG 0x13c2
185 #define RTL8367B_RTL_MAGIC_ID_VAL 0x0249
186
187 #define RTL8367B_IA_CTRL_REG 0x1f00
188 #define RTL8367B_IA_CTRL_RW(_x) ((_x) << 1)
189 #define RTL8367B_IA_CTRL_RW_READ RTL8367B_IA_CTRL_RW(0)
190 #define RTL8367B_IA_CTRL_RW_WRITE RTL8367B_IA_CTRL_RW(1)
191 #define RTL8367B_IA_CTRL_CMD_MASK BIT(0)
192
193 #define RTL8367B_IA_STATUS_REG 0x1f01
194 #define RTL8367B_IA_STATUS_PHY_BUSY BIT(2)
195 #define RTL8367B_IA_STATUS_SDS_BUSY BIT(1)
196 #define RTL8367B_IA_STATUS_MDX_BUSY BIT(0)
197
198 #define RTL8367B_IA_ADDRESS_REG 0x1f02
199 #define RTL8367B_IA_WRITE_DATA_REG 0x1f03
200 #define RTL8367B_IA_READ_DATA_REG 0x1f04
201
202 #define RTL8367B_INTERNAL_PHY_REG(_a, _r) (0x2000 + 32 * (_a) + (_r))
203
204 #define RTL8367B_NUM_MIB_COUNTERS 58
205
206 #define RTL8367B_CPU_PORT_NUM 5
207 #define RTL8367B_NUM_PORTS 8
208 #define RTL8367B_NUM_VLANS 32
209 #define RTL8367B_NUM_VIDS 4096
210 #define RTL8367B_PRIORITYMAX 7
211 #define RTL8367B_FIDMAX 7
212
213 #define RTL8367B_PORT_0 BIT(0)
214 #define RTL8367B_PORT_1 BIT(1)
215 #define RTL8367B_PORT_2 BIT(2)
216 #define RTL8367B_PORT_3 BIT(3)
217 #define RTL8367B_PORT_4 BIT(4)
218 #define RTL8367B_PORT_E0 BIT(5) /* External port 0 */
219 #define RTL8367B_PORT_E1 BIT(6) /* External port 1 */
220 #define RTL8367B_PORT_E2 BIT(7) /* External port 2 */
221
222 #define RTL8367B_PORTS_ALL \
223 (RTL8367B_PORT_0 | RTL8367B_PORT_1 | RTL8367B_PORT_2 | \
224 RTL8367B_PORT_3 | RTL8367B_PORT_4 | RTL8367B_PORT_E0 | \
225 RTL8367B_PORT_E1 | RTL8367B_PORT_E2)
226
227 #define RTL8367B_PORTS_ALL_BUT_CPU \
228 (RTL8367B_PORT_0 | RTL8367B_PORT_1 | RTL8367B_PORT_2 | \
229 RTL8367B_PORT_3 | RTL8367B_PORT_4 | RTL8367B_PORT_E1 | \
230 RTL8367B_PORT_E2)
231
232 struct rtl8367b_initval {
233 u16 reg;
234 u16 val;
235 };
236
237 static struct rtl8366_mib_counter
238 rtl8367b_mib_counters[RTL8367B_NUM_MIB_COUNTERS] = {
239 {0, 0, 4, "ifInOctets" },
240 {0, 4, 2, "dot3StatsFCSErrors" },
241 {0, 6, 2, "dot3StatsSymbolErrors" },
242 {0, 8, 2, "dot3InPauseFrames" },
243 {0, 10, 2, "dot3ControlInUnknownOpcodes" },
244 {0, 12, 2, "etherStatsFragments" },
245 {0, 14, 2, "etherStatsJabbers" },
246 {0, 16, 2, "ifInUcastPkts" },
247 {0, 18, 2, "etherStatsDropEvents" },
248 {0, 20, 2, "ifInMulticastPkts" },
249 {0, 22, 2, "ifInBroadcastPkts" },
250 {0, 24, 2, "inMldChecksumError" },
251 {0, 26, 2, "inIgmpChecksumError" },
252 {0, 28, 2, "inMldSpecificQuery" },
253 {0, 30, 2, "inMldGeneralQuery" },
254 {0, 32, 2, "inIgmpSpecificQuery" },
255 {0, 34, 2, "inIgmpGeneralQuery" },
256 {0, 36, 2, "inMldLeaves" },
257 {0, 38, 2, "inIgmpLeaves" },
258
259 {0, 40, 4, "etherStatsOctets" },
260 {0, 44, 2, "etherStatsUnderSizePkts" },
261 {0, 46, 2, "etherOversizeStats" },
262 {0, 48, 2, "etherStatsPkts64Octets" },
263 {0, 50, 2, "etherStatsPkts65to127Octets" },
264 {0, 52, 2, "etherStatsPkts128to255Octets" },
265 {0, 54, 2, "etherStatsPkts256to511Octets" },
266 {0, 56, 2, "etherStatsPkts512to1023Octets" },
267 {0, 58, 2, "etherStatsPkts1024to1518Octets" },
268
269 {0, 60, 4, "ifOutOctets" },
270 {0, 64, 2, "dot3StatsSingleCollisionFrames" },
271 {0, 66, 2, "dot3StatMultipleCollisionFrames" },
272 {0, 68, 2, "dot3sDeferredTransmissions" },
273 {0, 70, 2, "dot3StatsLateCollisions" },
274 {0, 72, 2, "etherStatsCollisions" },
275 {0, 74, 2, "dot3StatsExcessiveCollisions" },
276 {0, 76, 2, "dot3OutPauseFrames" },
277 {0, 78, 2, "ifOutDiscards" },
278 {0, 80, 2, "dot1dTpPortInDiscards" },
279 {0, 82, 2, "ifOutUcastPkts" },
280 {0, 84, 2, "ifOutMulticastPkts" },
281 {0, 86, 2, "ifOutBroadcastPkts" },
282 {0, 88, 2, "outOampduPkts" },
283 {0, 90, 2, "inOampduPkts" },
284 {0, 92, 2, "inIgmpJoinsSuccess" },
285 {0, 94, 2, "inIgmpJoinsFail" },
286 {0, 96, 2, "inMldJoinsSuccess" },
287 {0, 98, 2, "inMldJoinsFail" },
288 {0, 100, 2, "inReportSuppressionDrop" },
289 {0, 102, 2, "inLeaveSuppressionDrop" },
290 {0, 104, 2, "outIgmpReports" },
291 {0, 106, 2, "outIgmpLeaves" },
292 {0, 108, 2, "outIgmpGeneralQuery" },
293 {0, 110, 2, "outIgmpSpecificQuery" },
294 {0, 112, 2, "outMldReports" },
295 {0, 114, 2, "outMldLeaves" },
296 {0, 116, 2, "outMldGeneralQuery" },
297 {0, 118, 2, "outMldSpecificQuery" },
298 {0, 120, 2, "inKnownMulticastPkts" },
299 };
300
301 #define REG_RD(_smi, _reg, _val) \
302 do { \
303 err = rtl8366_smi_read_reg(_smi, _reg, _val); \
304 if (err) \
305 return err; \
306 } while (0)
307
308 #define REG_WR(_smi, _reg, _val) \
309 do { \
310 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
311 if (err) \
312 return err; \
313 } while (0)
314
315 #define REG_RMW(_smi, _reg, _mask, _val) \
316 do { \
317 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
318 if (err) \
319 return err; \
320 } while (0)
321
322 static const struct rtl8367b_initval rtl8367r_vb_initvals_0[] = {
323 {0x1B03, 0x0876}, {0x1200, 0x7FC4}, {0x0301, 0x0026}, {0x1722, 0x0E14},
324 {0x205F, 0x0002}, {0x2059, 0x1A00}, {0x205F, 0x0000}, {0x207F, 0x0002},
325 {0x2077, 0x0000}, {0x2078, 0x0000}, {0x2079, 0x0000}, {0x207A, 0x0000},
326 {0x207B, 0x0000}, {0x207F, 0x0000}, {0x205F, 0x0002}, {0x2053, 0x0000},
327 {0x2054, 0x0000}, {0x2055, 0x0000}, {0x2056, 0x0000}, {0x2057, 0x0000},
328 {0x205F, 0x0000}, {0x12A4, 0x110A}, {0x12A6, 0x150A}, {0x13F1, 0x0013},
329 {0x13F4, 0x0010}, {0x13F5, 0x0000}, {0x0018, 0x0F00}, {0x0038, 0x0F00},
330 {0x0058, 0x0F00}, {0x0078, 0x0F00}, {0x0098, 0x0F00}, {0x12B6, 0x0C02},
331 {0x12B7, 0x030F}, {0x12B8, 0x11FF}, {0x12BC, 0x0004}, {0x1362, 0x0115},
332 {0x1363, 0x0002}, {0x1363, 0x0000}, {0x133F, 0x0030}, {0x133E, 0x000E},
333 {0x221F, 0x0007}, {0x221E, 0x002D}, {0x2218, 0xF030}, {0x221F, 0x0007},
334 {0x221E, 0x0023}, {0x2216, 0x0005}, {0x2215, 0x00B9}, {0x2219, 0x0044},
335 {0x2215, 0x00BA}, {0x2219, 0x0020}, {0x2215, 0x00BB}, {0x2219, 0x00C1},
336 {0x2215, 0x0148}, {0x2219, 0x0096}, {0x2215, 0x016E}, {0x2219, 0x0026},
337 {0x2216, 0x0000}, {0x2216, 0x0000}, {0x221E, 0x002D}, {0x2218, 0xF010},
338 {0x221F, 0x0007}, {0x221E, 0x0020}, {0x2215, 0x0D00}, {0x221F, 0x0000},
339 {0x221F, 0x0000}, {0x2217, 0x2160}, {0x221F, 0x0001}, {0x2210, 0xF25E},
340 {0x221F, 0x0007}, {0x221E, 0x0042}, {0x2215, 0x0F00}, {0x2215, 0x0F00},
341 {0x2216, 0x7408}, {0x2215, 0x0E00}, {0x2215, 0x0F00}, {0x2215, 0x0F01},
342 {0x2216, 0x4000}, {0x2215, 0x0E01}, {0x2215, 0x0F01}, {0x2215, 0x0F02},
343 {0x2216, 0x9400}, {0x2215, 0x0E02}, {0x2215, 0x0F02}, {0x2215, 0x0F03},
344 {0x2216, 0x7408}, {0x2215, 0x0E03}, {0x2215, 0x0F03}, {0x2215, 0x0F04},
345 {0x2216, 0x4008}, {0x2215, 0x0E04}, {0x2215, 0x0F04}, {0x2215, 0x0F05},
346 {0x2216, 0x9400}, {0x2215, 0x0E05}, {0x2215, 0x0F05}, {0x2215, 0x0F06},
347 {0x2216, 0x0803}, {0x2215, 0x0E06}, {0x2215, 0x0F06}, {0x2215, 0x0D00},
348 {0x2215, 0x0100}, {0x221F, 0x0001}, {0x2210, 0xF05E}, {0x221F, 0x0000},
349 {0x2217, 0x2100}, {0x221F, 0x0000}, {0x220D, 0x0003}, {0x220E, 0x0015},
350 {0x220D, 0x4003}, {0x220E, 0x0006}, {0x221F, 0x0000}, {0x2200, 0x1340},
351 {0x133F, 0x0010}, {0x12A0, 0x0058}, {0x12A1, 0x0058}, {0x133E, 0x000E},
352 {0x133F, 0x0030}, {0x221F, 0x0000}, {0x2210, 0x0166}, {0x221F, 0x0000},
353 {0x133E, 0x000E}, {0x133F, 0x0010}, {0x133F, 0x0030}, {0x133E, 0x000E},
354 {0x221F, 0x0005}, {0x2205, 0xFFF6}, {0x2206, 0x0080}, {0x2205, 0x8B6E},
355 {0x2206, 0x0000}, {0x220F, 0x0100}, {0x2205, 0x8000}, {0x2206, 0x0280},
356 {0x2206, 0x28F7}, {0x2206, 0x00E0}, {0x2206, 0xFFF7}, {0x2206, 0xA080},
357 {0x2206, 0x02AE}, {0x2206, 0xF602}, {0x2206, 0x0153}, {0x2206, 0x0201},
358 {0x2206, 0x6602}, {0x2206, 0x80B9}, {0x2206, 0xE08B}, {0x2206, 0x8CE1},
359 {0x2206, 0x8B8D}, {0x2206, 0x1E01}, {0x2206, 0xE18B}, {0x2206, 0x8E1E},
360 {0x2206, 0x01A0}, {0x2206, 0x00E7}, {0x2206, 0xAEDB}, {0x2206, 0xEEE0},
361 {0x2206, 0x120E}, {0x2206, 0xEEE0}, {0x2206, 0x1300}, {0x2206, 0xEEE0},
362 {0x2206, 0x2001}, {0x2206, 0xEEE0}, {0x2206, 0x2166}, {0x2206, 0xEEE0},
363 {0x2206, 0xC463}, {0x2206, 0xEEE0}, {0x2206, 0xC5E8}, {0x2206, 0xEEE0},
364 {0x2206, 0xC699}, {0x2206, 0xEEE0}, {0x2206, 0xC7C2}, {0x2206, 0xEEE0},
365 {0x2206, 0xC801}, {0x2206, 0xEEE0}, {0x2206, 0xC913}, {0x2206, 0xEEE0},
366 {0x2206, 0xCA30}, {0x2206, 0xEEE0}, {0x2206, 0xCB3E}, {0x2206, 0xEEE0},
367 {0x2206, 0xDCE1}, {0x2206, 0xEEE0}, {0x2206, 0xDD00}, {0x2206, 0xEEE2},
368 {0x2206, 0x0001}, {0x2206, 0xEEE2}, {0x2206, 0x0100}, {0x2206, 0xEEE4},
369 {0x2206, 0x8860}, {0x2206, 0xEEE4}, {0x2206, 0x8902}, {0x2206, 0xEEE4},
370 {0x2206, 0x8C00}, {0x2206, 0xEEE4}, {0x2206, 0x8D30}, {0x2206, 0xEEEA},
371 {0x2206, 0x1480}, {0x2206, 0xEEEA}, {0x2206, 0x1503}, {0x2206, 0xEEEA},
372 {0x2206, 0xC600}, {0x2206, 0xEEEA}, {0x2206, 0xC706}, {0x2206, 0xEE85},
373 {0x2206, 0xEE00}, {0x2206, 0xEE85}, {0x2206, 0xEF00}, {0x2206, 0xEE8B},
374 {0x2206, 0x6750}, {0x2206, 0xEE8B}, {0x2206, 0x6632}, {0x2206, 0xEE8A},
375 {0x2206, 0xD448}, {0x2206, 0xEE8A}, {0x2206, 0xD548}, {0x2206, 0xEE8A},
376 {0x2206, 0xD649}, {0x2206, 0xEE8A}, {0x2206, 0xD7F8}, {0x2206, 0xEE8B},
377 {0x2206, 0x85E2}, {0x2206, 0xEE8B}, {0x2206, 0x8700}, {0x2206, 0xEEFF},
378 {0x2206, 0xF600}, {0x2206, 0xEEFF}, {0x2206, 0xF7FC}, {0x2206, 0x04F8},
379 {0x2206, 0xE08B}, {0x2206, 0x8EAD}, {0x2206, 0x2023}, {0x2206, 0xF620},
380 {0x2206, 0xE48B}, {0x2206, 0x8E02}, {0x2206, 0x2877}, {0x2206, 0x0225},
381 {0x2206, 0xC702}, {0x2206, 0x26A1}, {0x2206, 0x0281}, {0x2206, 0xB302},
382 {0x2206, 0x8496}, {0x2206, 0x0202}, {0x2206, 0xA102}, {0x2206, 0x27F1},
383 {0x2206, 0x0228}, {0x2206, 0xF902}, {0x2206, 0x2AA0}, {0x2206, 0x0282},
384 {0x2206, 0xB8E0}, {0x2206, 0x8B8E}, {0x2206, 0xAD21}, {0x2206, 0x08F6},
385 {0x2206, 0x21E4}, {0x2206, 0x8B8E}, {0x2206, 0x0202}, {0x2206, 0x80E0},
386 {0x2206, 0x8B8E}, {0x2206, 0xAD22}, {0x2206, 0x05F6}, {0x2206, 0x22E4},
387 {0x2206, 0x8B8E}, {0x2206, 0xE08B}, {0x2206, 0x8EAD}, {0x2206, 0x2305},
388 {0x2206, 0xF623}, {0x2206, 0xE48B}, {0x2206, 0x8EE0}, {0x2206, 0x8B8E},
389 {0x2206, 0xAD24}, {0x2206, 0x08F6}, {0x2206, 0x24E4}, {0x2206, 0x8B8E},
390 {0x2206, 0x0227}, {0x2206, 0x6AE0}, {0x2206, 0x8B8E}, {0x2206, 0xAD25},
391 {0x2206, 0x05F6}, {0x2206, 0x25E4}, {0x2206, 0x8B8E}, {0x2206, 0xE08B},
392 {0x2206, 0x8EAD}, {0x2206, 0x260B}, {0x2206, 0xF626}, {0x2206, 0xE48B},
393 {0x2206, 0x8E02}, {0x2206, 0x830D}, {0x2206, 0x021D}, {0x2206, 0x6BE0},
394 {0x2206, 0x8B8E}, {0x2206, 0xAD27}, {0x2206, 0x05F6}, {0x2206, 0x27E4},
395 {0x2206, 0x8B8E}, {0x2206, 0x0281}, {0x2206, 0x4402}, {0x2206, 0x045C},
396 {0x2206, 0xFC04}, {0x2206, 0xF8E0}, {0x2206, 0x8B83}, {0x2206, 0xAD23},
397 {0x2206, 0x30E0}, {0x2206, 0xE022}, {0x2206, 0xE1E0}, {0x2206, 0x2359},
398 {0x2206, 0x02E0}, {0x2206, 0x85EF}, {0x2206, 0xE585}, {0x2206, 0xEFAC},
399 {0x2206, 0x2907}, {0x2206, 0x1F01}, {0x2206, 0x9E51}, {0x2206, 0xAD29},
400 {0x2206, 0x20E0}, {0x2206, 0x8B83}, {0x2206, 0xAD21}, {0x2206, 0x06E1},
401 {0x2206, 0x8B84}, {0x2206, 0xAD28}, {0x2206, 0x42E0}, {0x2206, 0x8B85},
402 {0x2206, 0xAD21}, {0x2206, 0x06E1}, {0x2206, 0x8B84}, {0x2206, 0xAD29},
403 {0x2206, 0x36BF}, {0x2206, 0x34BF}, {0x2206, 0x022C}, {0x2206, 0x31AE},
404 {0x2206, 0x2EE0}, {0x2206, 0x8B83}, {0x2206, 0xAD21}, {0x2206, 0x10E0},
405 {0x2206, 0x8B84}, {0x2206, 0xF620}, {0x2206, 0xE48B}, {0x2206, 0x84EE},
406 {0x2206, 0x8ADA}, {0x2206, 0x00EE}, {0x2206, 0x8ADB}, {0x2206, 0x00E0},
407 {0x2206, 0x8B85}, {0x2206, 0xAD21}, {0x2206, 0x0CE0}, {0x2206, 0x8B84},
408 {0x2206, 0xF621}, {0x2206, 0xE48B}, {0x2206, 0x84EE}, {0x2206, 0x8B72},
409 {0x2206, 0xFFBF}, {0x2206, 0x34C2}, {0x2206, 0x022C}, {0x2206, 0x31FC},
410 {0x2206, 0x04F8}, {0x2206, 0xFAEF}, {0x2206, 0x69E0}, {0x2206, 0x8B85},
411 {0x2206, 0xAD21}, {0x2206, 0x42E0}, {0x2206, 0xE022}, {0x2206, 0xE1E0},
412 {0x2206, 0x2358}, {0x2206, 0xC059}, {0x2206, 0x021E}, {0x2206, 0x01E1},
413 {0x2206, 0x8B72}, {0x2206, 0x1F10}, {0x2206, 0x9E2F}, {0x2206, 0xE48B},
414 {0x2206, 0x72AD}, {0x2206, 0x2123}, {0x2206, 0xE18B}, {0x2206, 0x84F7},
415 {0x2206, 0x29E5}, {0x2206, 0x8B84}, {0x2206, 0xAC27}, {0x2206, 0x10AC},
416 {0x2206, 0x2605}, {0x2206, 0x0205}, {0x2206, 0x23AE}, {0x2206, 0x1602},
417 {0x2206, 0x0535}, {0x2206, 0x0282}, {0x2206, 0x30AE}, {0x2206, 0x0E02},
418 {0x2206, 0x056A}, {0x2206, 0x0282}, {0x2206, 0x75AE}, {0x2206, 0x0602},
419 {0x2206, 0x04DC}, {0x2206, 0x0282}, {0x2206, 0x04EF}, {0x2206, 0x96FE},
420 {0x2206, 0xFC04}, {0x2206, 0xF8F9}, {0x2206, 0xE08B}, {0x2206, 0x87AD},
421 {0x2206, 0x2321}, {0x2206, 0xE0EA}, {0x2206, 0x14E1}, {0x2206, 0xEA15},
422 {0x2206, 0xAD26}, {0x2206, 0x18F6}, {0x2206, 0x27E4}, {0x2206, 0xEA14},
423 {0x2206, 0xE5EA}, {0x2206, 0x15F6}, {0x2206, 0x26E4}, {0x2206, 0xEA14},
424 {0x2206, 0xE5EA}, {0x2206, 0x15F7}, {0x2206, 0x27E4}, {0x2206, 0xEA14},
425 {0x2206, 0xE5EA}, {0x2206, 0x15FD}, {0x2206, 0xFC04}, {0x2206, 0xF8F9},
426 {0x2206, 0xE08B}, {0x2206, 0x87AD}, {0x2206, 0x233A}, {0x2206, 0xAD22},
427 {0x2206, 0x37E0}, {0x2206, 0xE020}, {0x2206, 0xE1E0}, {0x2206, 0x21AC},
428 {0x2206, 0x212E}, {0x2206, 0xE0EA}, {0x2206, 0x14E1}, {0x2206, 0xEA15},
429 {0x2206, 0xF627}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},
430 {0x2206, 0xE2EA}, {0x2206, 0x12E3}, {0x2206, 0xEA13}, {0x2206, 0x5A8F},
431 {0x2206, 0x6A20}, {0x2206, 0xE6EA}, {0x2206, 0x12E7}, {0x2206, 0xEA13},
432 {0x2206, 0xF726}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},
433 {0x2206, 0xF727}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},
434 {0x2206, 0xFDFC}, {0x2206, 0x04F8}, {0x2206, 0xF9E0}, {0x2206, 0x8B87},
435 {0x2206, 0xAD23}, {0x2206, 0x38AD}, {0x2206, 0x2135}, {0x2206, 0xE0E0},
436 {0x2206, 0x20E1}, {0x2206, 0xE021}, {0x2206, 0xAC21}, {0x2206, 0x2CE0},
437 {0x2206, 0xEA14}, {0x2206, 0xE1EA}, {0x2206, 0x15F6}, {0x2206, 0x27E4},
438 {0x2206, 0xEA14}, {0x2206, 0xE5EA}, {0x2206, 0x15E2}, {0x2206, 0xEA12},
439 {0x2206, 0xE3EA}, {0x2206, 0x135A}, {0x2206, 0x8FE6}, {0x2206, 0xEA12},
440 {0x2206, 0xE7EA}, {0x2206, 0x13F7}, {0x2206, 0x26E4}, {0x2206, 0xEA14},
441 {0x2206, 0xE5EA}, {0x2206, 0x15F7}, {0x2206, 0x27E4}, {0x2206, 0xEA14},
442 {0x2206, 0xE5EA}, {0x2206, 0x15FD}, {0x2206, 0xFC04}, {0x2206, 0xF8FA},
443 {0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AD}, {0x2206, 0x2146},
444 {0x2206, 0xE0E0}, {0x2206, 0x22E1}, {0x2206, 0xE023}, {0x2206, 0x58C0},
445 {0x2206, 0x5902}, {0x2206, 0x1E01}, {0x2206, 0xE18B}, {0x2206, 0x651F},
446 {0x2206, 0x109E}, {0x2206, 0x33E4}, {0x2206, 0x8B65}, {0x2206, 0xAD21},
447 {0x2206, 0x22AD}, {0x2206, 0x272A}, {0x2206, 0xD400}, {0x2206, 0x01BF},
448 {0x2206, 0x34F2}, {0x2206, 0x022C}, {0x2206, 0xA2BF}, {0x2206, 0x34F5},
449 {0x2206, 0x022C}, {0x2206, 0xE0E0}, {0x2206, 0x8B67}, {0x2206, 0x1B10},
450 {0x2206, 0xAA14}, {0x2206, 0xE18B}, {0x2206, 0x660D}, {0x2206, 0x1459},
451 {0x2206, 0x0FAE}, {0x2206, 0x05E1}, {0x2206, 0x8B66}, {0x2206, 0x590F},
452 {0x2206, 0xBF85}, {0x2206, 0x6102}, {0x2206, 0x2CA2}, {0x2206, 0xEF96},
453 {0x2206, 0xFEFC}, {0x2206, 0x04F8}, {0x2206, 0xF9FA}, {0x2206, 0xFBEF},
454 {0x2206, 0x79E2}, {0x2206, 0x8AD2}, {0x2206, 0xAC19}, {0x2206, 0x2DE0},
455 {0x2206, 0xE036}, {0x2206, 0xE1E0}, {0x2206, 0x37EF}, {0x2206, 0x311F},
456 {0x2206, 0x325B}, {0x2206, 0x019E}, {0x2206, 0x1F7A}, {0x2206, 0x0159},
457 {0x2206, 0x019F}, {0x2206, 0x0ABF}, {0x2206, 0x348E}, {0x2206, 0x022C},
458 {0x2206, 0x31F6}, {0x2206, 0x06AE}, {0x2206, 0x0FF6}, {0x2206, 0x0302},
459 {0x2206, 0x0470}, {0x2206, 0xF703}, {0x2206, 0xF706}, {0x2206, 0xBF34},
460 {0x2206, 0x9302}, {0x2206, 0x2C31}, {0x2206, 0xAC1A}, {0x2206, 0x25E0},
461 {0x2206, 0xE022}, {0x2206, 0xE1E0}, {0x2206, 0x23EF}, {0x2206, 0x300D},
462 {0x2206, 0x311F}, {0x2206, 0x325B}, {0x2206, 0x029E}, {0x2206, 0x157A},
463 {0x2206, 0x0258}, {0x2206, 0xC4A0}, {0x2206, 0x0408}, {0x2206, 0xBF34},
464 {0x2206, 0x9E02}, {0x2206, 0x2C31}, {0x2206, 0xAE06}, {0x2206, 0xBF34},
465 {0x2206, 0x9C02}, {0x2206, 0x2C31}, {0x2206, 0xAC1B}, {0x2206, 0x4AE0},
466 {0x2206, 0xE012}, {0x2206, 0xE1E0}, {0x2206, 0x13EF}, {0x2206, 0x300D},
467 {0x2206, 0x331F}, {0x2206, 0x325B}, {0x2206, 0x1C9E}, {0x2206, 0x3AEF},
468 {0x2206, 0x325B}, {0x2206, 0x1C9F}, {0x2206, 0x09BF}, {0x2206, 0x3498},
469 {0x2206, 0x022C}, {0x2206, 0x3102}, {0x2206, 0x83C5}, {0x2206, 0x5A03},
470 {0x2206, 0x0D03}, {0x2206, 0x581C}, {0x2206, 0x1E20}, {0x2206, 0x0207},
471 {0x2206, 0xA0A0}, {0x2206, 0x000E}, {0x2206, 0x0284}, {0x2206, 0x17AD},
472 {0x2206, 0x1817}, {0x2206, 0xBF34}, {0x2206, 0x9A02}, {0x2206, 0x2C31},
473 {0x2206, 0xAE0F}, {0x2206, 0xBF34}, {0x2206, 0xC802}, {0x2206, 0x2C31},
474 {0x2206, 0xBF34}, {0x2206, 0xC502}, {0x2206, 0x2C31}, {0x2206, 0x0284},
475 {0x2206, 0x52E6}, {0x2206, 0x8AD2}, {0x2206, 0xEF97}, {0x2206, 0xFFFE},
476 {0x2206, 0xFDFC}, {0x2206, 0x04F8}, {0x2206, 0xBF34}, {0x2206, 0xDA02},
477 {0x2206, 0x2CE0}, {0x2206, 0xE58A}, {0x2206, 0xD3BF}, {0x2206, 0x34D4},
478 {0x2206, 0x022C}, {0x2206, 0xE00C}, {0x2206, 0x1159}, {0x2206, 0x02E0},
479 {0x2206, 0x8AD3}, {0x2206, 0x1E01}, {0x2206, 0xE48A}, {0x2206, 0xD3D1},
480 {0x2206, 0x00BF}, {0x2206, 0x34DA}, {0x2206, 0x022C}, {0x2206, 0xA2D1},
481 {0x2206, 0x01BF}, {0x2206, 0x34D4}, {0x2206, 0x022C}, {0x2206, 0xA2BF},
482 {0x2206, 0x34CB}, {0x2206, 0x022C}, {0x2206, 0xE0E5}, {0x2206, 0x8ACE},
483 {0x2206, 0xBF85}, {0x2206, 0x6702}, {0x2206, 0x2CE0}, {0x2206, 0xE58A},
484 {0x2206, 0xCFBF}, {0x2206, 0x8564}, {0x2206, 0x022C}, {0x2206, 0xE0E5},
485 {0x2206, 0x8AD0}, {0x2206, 0xBF85}, {0x2206, 0x6A02}, {0x2206, 0x2CE0},
486 {0x2206, 0xE58A}, {0x2206, 0xD1FC}, {0x2206, 0x04F8}, {0x2206, 0xE18A},
487 {0x2206, 0xD1BF}, {0x2206, 0x856A}, {0x2206, 0x022C}, {0x2206, 0xA2E1},
488 {0x2206, 0x8AD0}, {0x2206, 0xBF85}, {0x2206, 0x6402}, {0x2206, 0x2CA2},
489 {0x2206, 0xE18A}, {0x2206, 0xCFBF}, {0x2206, 0x8567}, {0x2206, 0x022C},
490 {0x2206, 0xA2E1}, {0x2206, 0x8ACE}, {0x2206, 0xBF34}, {0x2206, 0xCB02},
491 {0x2206, 0x2CA2}, {0x2206, 0xE18A}, {0x2206, 0xD3BF}, {0x2206, 0x34DA},
492 {0x2206, 0x022C}, {0x2206, 0xA2E1}, {0x2206, 0x8AD3}, {0x2206, 0x0D11},
493 {0x2206, 0xBF34}, {0x2206, 0xD402}, {0x2206, 0x2CA2}, {0x2206, 0xFC04},
494 {0x2206, 0xF9A0}, {0x2206, 0x0405}, {0x2206, 0xE38A}, {0x2206, 0xD4AE},
495 {0x2206, 0x13A0}, {0x2206, 0x0805}, {0x2206, 0xE38A}, {0x2206, 0xD5AE},
496 {0x2206, 0x0BA0}, {0x2206, 0x0C05}, {0x2206, 0xE38A}, {0x2206, 0xD6AE},
497 {0x2206, 0x03E3}, {0x2206, 0x8AD7}, {0x2206, 0xEF13}, {0x2206, 0xBF34},
498 {0x2206, 0xCB02}, {0x2206, 0x2CA2}, {0x2206, 0xEF13}, {0x2206, 0x0D11},
499 {0x2206, 0xBF85}, {0x2206, 0x6702}, {0x2206, 0x2CA2}, {0x2206, 0xEF13},
500 {0x2206, 0x0D14}, {0x2206, 0xBF85}, {0x2206, 0x6402}, {0x2206, 0x2CA2},
501 {0x2206, 0xEF13}, {0x2206, 0x0D17}, {0x2206, 0xBF85}, {0x2206, 0x6A02},
502 {0x2206, 0x2CA2}, {0x2206, 0xFD04}, {0x2206, 0xF8E0}, {0x2206, 0x8B85},
503 {0x2206, 0xAD27}, {0x2206, 0x2DE0}, {0x2206, 0xE036}, {0x2206, 0xE1E0},
504 {0x2206, 0x37E1}, {0x2206, 0x8B73}, {0x2206, 0x1F10}, {0x2206, 0x9E20},
505 {0x2206, 0xE48B}, {0x2206, 0x73AC}, {0x2206, 0x200B}, {0x2206, 0xAC21},
506 {0x2206, 0x0DAC}, {0x2206, 0x250F}, {0x2206, 0xAC27}, {0x2206, 0x0EAE},
507 {0x2206, 0x0F02}, {0x2206, 0x84CC}, {0x2206, 0xAE0A}, {0x2206, 0x0284},
508 {0x2206, 0xD1AE}, {0x2206, 0x05AE}, {0x2206, 0x0302}, {0x2206, 0x84D8},
509 {0x2206, 0xFC04}, {0x2206, 0xEE8B}, {0x2206, 0x6800}, {0x2206, 0x0402},
510 {0x2206, 0x84E5}, {0x2206, 0x0285}, {0x2206, 0x2804}, {0x2206, 0x0285},
511 {0x2206, 0x4904}, {0x2206, 0xEE8B}, {0x2206, 0x6800}, {0x2206, 0xEE8B},
512 {0x2206, 0x6902}, {0x2206, 0x04F8}, {0x2206, 0xF9E0}, {0x2206, 0x8B85},
513 {0x2206, 0xAD26}, {0x2206, 0x38D0}, {0x2206, 0x0B02}, {0x2206, 0x2B4D},
514 {0x2206, 0x5882}, {0x2206, 0x7882}, {0x2206, 0x9F2D}, {0x2206, 0xE08B},
515 {0x2206, 0x68E1}, {0x2206, 0x8B69}, {0x2206, 0x1F10}, {0x2206, 0x9EC8},
516 {0x2206, 0x10E4}, {0x2206, 0x8B68}, {0x2206, 0xE0E0}, {0x2206, 0x00E1},
517 {0x2206, 0xE001}, {0x2206, 0xF727}, {0x2206, 0xE4E0}, {0x2206, 0x00E5},
518 {0x2206, 0xE001}, {0x2206, 0xE2E0}, {0x2206, 0x20E3}, {0x2206, 0xE021},
519 {0x2206, 0xAD30}, {0x2206, 0xF7F6}, {0x2206, 0x27E4}, {0x2206, 0xE000},
520 {0x2206, 0xE5E0}, {0x2206, 0x01FD}, {0x2206, 0xFC04}, {0x2206, 0xF8FA},
521 {0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AD}, {0x2206, 0x2212},
522 {0x2206, 0xE0E0}, {0x2206, 0x14E1}, {0x2206, 0xE015}, {0x2206, 0xAD26},
523 {0x2206, 0x9CE1}, {0x2206, 0x85E0}, {0x2206, 0xBF85}, {0x2206, 0x6D02},
524 {0x2206, 0x2CA2}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x04F8},
525 {0x2206, 0xFAEF}, {0x2206, 0x69E0}, {0x2206, 0x8B86}, {0x2206, 0xAD22},
526 {0x2206, 0x09E1}, {0x2206, 0x85E1}, {0x2206, 0xBF85}, {0x2206, 0x6D02},
527 {0x2206, 0x2CA2}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x0464},
528 {0x2206, 0xE48C}, {0x2206, 0xFDE4}, {0x2206, 0x80CA}, {0x2206, 0xE480},
529 {0x2206, 0x66E0}, {0x2206, 0x8E70}, {0x2206, 0xE076}, {0x2205, 0xE142},
530 {0x2206, 0x0701}, {0x2205, 0xE140}, {0x2206, 0x0405}, {0x220F, 0x0000},
531 {0x221F, 0x0000}, {0x2200, 0x1340}, {0x133E, 0x000E}, {0x133F, 0x0010},
532 {0x13EB, 0x11BB}
533 };
534
535 static const struct rtl8367b_initval rtl8367r_vb_initvals_1[] = {
536 {0x1B03, 0x0876}, {0x1200, 0x7FC4}, {0x1305, 0xC000}, {0x121E, 0x03CA},
537 {0x1233, 0x0352}, {0x1234, 0x0064}, {0x1237, 0x0096}, {0x1238, 0x0078},
538 {0x1239, 0x0084}, {0x123A, 0x0030}, {0x205F, 0x0002}, {0x2059, 0x1A00},
539 {0x205F, 0x0000}, {0x207F, 0x0002}, {0x2077, 0x0000}, {0x2078, 0x0000},
540 {0x2079, 0x0000}, {0x207A, 0x0000}, {0x207B, 0x0000}, {0x207F, 0x0000},
541 {0x205F, 0x0002}, {0x2053, 0x0000}, {0x2054, 0x0000}, {0x2055, 0x0000},
542 {0x2056, 0x0000}, {0x2057, 0x0000}, {0x205F, 0x0000}, {0x133F, 0x0030},
543 {0x133E, 0x000E}, {0x221F, 0x0005}, {0x2205, 0x8B86}, {0x2206, 0x800E},
544 {0x221F, 0x0000}, {0x133F, 0x0010}, {0x12A3, 0x2200}, {0x6107, 0xE58B},
545 {0x6103, 0xA970}, {0x0018, 0x0F00}, {0x0038, 0x0F00}, {0x0058, 0x0F00},
546 {0x0078, 0x0F00}, {0x0098, 0x0F00}, {0x133F, 0x0030}, {0x133E, 0x000E},
547 {0x221F, 0x0005}, {0x2205, 0x8B6E}, {0x2206, 0x0000}, {0x220F, 0x0100},
548 {0x2205, 0xFFF6}, {0x2206, 0x0080}, {0x2205, 0x8000}, {0x2206, 0x0280},
549 {0x2206, 0x2BF7}, {0x2206, 0x00E0}, {0x2206, 0xFFF7}, {0x2206, 0xA080},
550 {0x2206, 0x02AE}, {0x2206, 0xF602}, {0x2206, 0x0153}, {0x2206, 0x0201},
551 {0x2206, 0x6602}, {0x2206, 0x8044}, {0x2206, 0x0201}, {0x2206, 0x7CE0},
552 {0x2206, 0x8B8C}, {0x2206, 0xE18B}, {0x2206, 0x8D1E}, {0x2206, 0x01E1},
553 {0x2206, 0x8B8E}, {0x2206, 0x1E01}, {0x2206, 0xA000}, {0x2206, 0xE4AE},
554 {0x2206, 0xD8EE}, {0x2206, 0x85C0}, {0x2206, 0x00EE}, {0x2206, 0x85C1},
555 {0x2206, 0x00EE}, {0x2206, 0x8AFC}, {0x2206, 0x07EE}, {0x2206, 0x8AFD},
556 {0x2206, 0x73EE}, {0x2206, 0xFFF6}, {0x2206, 0x00EE}, {0x2206, 0xFFF7},
557 {0x2206, 0xFC04}, {0x2206, 0xF8E0}, {0x2206, 0x8B8E}, {0x2206, 0xAD20},
558 {0x2206, 0x0302}, {0x2206, 0x8050}, {0x2206, 0xFC04}, {0x2206, 0xF8F9},
559 {0x2206, 0xE08B}, {0x2206, 0x85AD}, {0x2206, 0x2548}, {0x2206, 0xE08A},
560 {0x2206, 0xE4E1}, {0x2206, 0x8AE5}, {0x2206, 0x7C00}, {0x2206, 0x009E},
561 {0x2206, 0x35EE}, {0x2206, 0x8AE4}, {0x2206, 0x00EE}, {0x2206, 0x8AE5},
562 {0x2206, 0x00E0}, {0x2206, 0x8AFC}, {0x2206, 0xE18A}, {0x2206, 0xFDE2},
563 {0x2206, 0x85C0}, {0x2206, 0xE385}, {0x2206, 0xC102}, {0x2206, 0x2DAC},
564 {0x2206, 0xAD20}, {0x2206, 0x12EE}, {0x2206, 0x8AE4}, {0x2206, 0x03EE},
565 {0x2206, 0x8AE5}, {0x2206, 0xB7EE}, {0x2206, 0x85C0}, {0x2206, 0x00EE},
566 {0x2206, 0x85C1}, {0x2206, 0x00AE}, {0x2206, 0x1115}, {0x2206, 0xE685},
567 {0x2206, 0xC0E7}, {0x2206, 0x85C1}, {0x2206, 0xAE08}, {0x2206, 0xEE85},
568 {0x2206, 0xC000}, {0x2206, 0xEE85}, {0x2206, 0xC100}, {0x2206, 0xFDFC},
569 {0x2206, 0x0400}, {0x2205, 0xE142}, {0x2206, 0x0701}, {0x2205, 0xE140},
570 {0x2206, 0x0405}, {0x220F, 0x0000}, {0x221F, 0x0000}, {0x133E, 0x000E},
571 {0x133F, 0x0010}, {0x13EB, 0x11BB}, {0x207F, 0x0002}, {0x2073, 0x1D22},
572 {0x207F, 0x0000}, {0x133F, 0x0030}, {0x133E, 0x000E}, {0x2200, 0x1340},
573 {0x133E, 0x000E}, {0x133F, 0x0010},
574 };
575
576 static int rtl8367b_write_initvals(struct rtl8366_smi *smi,
577 const struct rtl8367b_initval *initvals,
578 int count)
579 {
580 int err;
581 int i;
582
583 for (i = 0; i < count; i++)
584 REG_WR(smi, initvals[i].reg, initvals[i].val);
585
586 return 0;
587 }
588
589 static int rtl8367b_read_phy_reg(struct rtl8366_smi *smi,
590 u32 phy_addr, u32 phy_reg, u32 *val)
591 {
592 int timeout;
593 u32 data;
594 int err;
595
596 if (phy_addr > RTL8367B_PHY_ADDR_MAX)
597 return -EINVAL;
598
599 if (phy_reg > RTL8367B_PHY_REG_MAX)
600 return -EINVAL;
601
602 REG_RD(smi, RTL8367B_IA_STATUS_REG, &data);
603 if (data & RTL8367B_IA_STATUS_PHY_BUSY)
604 return -ETIMEDOUT;
605
606 /* prepare address */
607 REG_WR(smi, RTL8367B_IA_ADDRESS_REG,
608 RTL8367B_INTERNAL_PHY_REG(phy_addr, phy_reg));
609
610 /* send read command */
611 REG_WR(smi, RTL8367B_IA_CTRL_REG,
612 RTL8367B_IA_CTRL_CMD_MASK | RTL8367B_IA_CTRL_RW_READ);
613
614 timeout = 5;
615 do {
616 REG_RD(smi, RTL8367B_IA_STATUS_REG, &data);
617 if ((data & RTL8367B_IA_STATUS_PHY_BUSY) == 0)
618 break;
619
620 if (timeout--) {
621 dev_err(smi->parent, "phy read timed out\n");
622 return -ETIMEDOUT;
623 }
624
625 udelay(1);
626 } while (1);
627
628 /* read data */
629 REG_RD(smi, RTL8367B_IA_READ_DATA_REG, val);
630
631 dev_dbg(smi->parent, "phy_read: addr:%02x, reg:%02x, val:%04x\n",
632 phy_addr, phy_reg, *val);
633 return 0;
634 }
635
636 static int rtl8367b_write_phy_reg(struct rtl8366_smi *smi,
637 u32 phy_addr, u32 phy_reg, u32 val)
638 {
639 int timeout;
640 u32 data;
641 int err;
642
643 dev_dbg(smi->parent, "phy_write: addr:%02x, reg:%02x, val:%04x\n",
644 phy_addr, phy_reg, val);
645
646 if (phy_addr > RTL8367B_PHY_ADDR_MAX)
647 return -EINVAL;
648
649 if (phy_reg > RTL8367B_PHY_REG_MAX)
650 return -EINVAL;
651
652 REG_RD(smi, RTL8367B_IA_STATUS_REG, &data);
653 if (data & RTL8367B_IA_STATUS_PHY_BUSY)
654 return -ETIMEDOUT;
655
656 /* preapre data */
657 REG_WR(smi, RTL8367B_IA_WRITE_DATA_REG, val);
658
659 /* prepare address */
660 REG_WR(smi, RTL8367B_IA_ADDRESS_REG,
661 RTL8367B_INTERNAL_PHY_REG(phy_addr, phy_reg));
662
663 /* send write command */
664 REG_WR(smi, RTL8367B_IA_CTRL_REG,
665 RTL8367B_IA_CTRL_CMD_MASK | RTL8367B_IA_CTRL_RW_WRITE);
666
667 timeout = 5;
668 do {
669 REG_RD(smi, RTL8367B_IA_STATUS_REG, &data);
670 if ((data & RTL8367B_IA_STATUS_PHY_BUSY) == 0)
671 break;
672
673 if (timeout--) {
674 dev_err(smi->parent, "phy write timed out\n");
675 return -ETIMEDOUT;
676 }
677
678 udelay(1);
679 } while (1);
680
681 return 0;
682 }
683
684 static int rtl8367b_init_regs(struct rtl8366_smi *smi)
685 {
686 const struct rtl8367b_initval *initvals;
687 u32 chip_ver;
688 u32 rlvid;
689 int count;
690 int err;
691
692 REG_WR(smi, RTL8367B_RTL_MAGIC_ID_REG, RTL8367B_RTL_MAGIC_ID_VAL);
693 REG_RD(smi, RTL8367B_CHIP_VER_REG, &chip_ver);
694
695 rlvid = (chip_ver >> RTL8367B_CHIP_VER_RLVID_SHIFT) &
696 RTL8367B_CHIP_VER_RLVID_MASK;
697
698 switch (rlvid) {
699 case 0:
700 initvals = rtl8367r_vb_initvals_0;
701 count = ARRAY_SIZE(rtl8367r_vb_initvals_0);
702 break;
703
704 case 1:
705 initvals = rtl8367r_vb_initvals_1;
706 count = ARRAY_SIZE(rtl8367r_vb_initvals_1);
707 break;
708
709 default:
710 dev_err(smi->parent, "unknow rlvid %u\n", rlvid);
711 return -ENODEV;
712 }
713
714 /* TODO: disable RLTP */
715
716 return rtl8367b_write_initvals(smi, initvals, count);
717 }
718
719 static int rtl8367b_reset_chip(struct rtl8366_smi *smi)
720 {
721 int timeout = 10;
722 int err;
723 u32 data;
724
725 REG_WR(smi, RTL8367B_CHIP_RESET_REG, RTL8367B_CHIP_RESET_HW);
726 msleep(RTL8367B_RESET_DELAY);
727
728 do {
729 REG_RD(smi, RTL8367B_CHIP_RESET_REG, &data);
730 if (!(data & RTL8367B_CHIP_RESET_HW))
731 break;
732
733 msleep(1);
734 } while (--timeout);
735
736 if (!timeout) {
737 dev_err(smi->parent, "chip reset timed out\n");
738 return -ETIMEDOUT;
739 }
740
741 return 0;
742 }
743
744 static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id,
745 enum rtl8367_extif_mode mode)
746 {
747 int err;
748
749 /* set port mode */
750 switch (mode) {
751 case RTL8367_EXTIF_MODE_RGMII:
752 case RTL8367_EXTIF_MODE_RGMII_33V:
753 REG_WR(smi, RTL8367B_CHIP_DEBUG0_REG, 0x0367);
754 REG_WR(smi, RTL8367B_CHIP_DEBUG1_REG, 0x7777);
755 break;
756
757 case RTL8367_EXTIF_MODE_TMII_MAC:
758 case RTL8367_EXTIF_MODE_TMII_PHY:
759 REG_RMW(smi, RTL8367B_BYPASS_LINE_RATE_REG,
760 BIT((id + 1) % 2), BIT((id + 1) % 2));
761 break;
762
763 case RTL8367_EXTIF_MODE_GMII:
764 REG_RMW(smi, RTL8367B_CHIP_DEBUG0_REG,
765 RTL8367B_CHIP_DEBUG0_DUMMY0(id),
766 RTL8367B_CHIP_DEBUG0_DUMMY0(id));
767 REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), BIT(6), BIT(6));
768 break;
769
770 case RTL8367_EXTIF_MODE_MII_MAC:
771 case RTL8367_EXTIF_MODE_MII_PHY:
772 case RTL8367_EXTIF_MODE_DISABLED:
773 REG_RMW(smi, RTL8367B_BYPASS_LINE_RATE_REG,
774 BIT((id + 1) % 2), 0);
775 REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), BIT(6), 0);
776 break;
777
778 default:
779 dev_err(smi->parent,
780 "invalid mode for external interface %d\n", id);
781 return -EINVAL;
782 }
783
784 REG_RMW(smi, RTL8367B_DIS_REG,
785 RTL8367B_DIS_RGMII_MASK << RTL8367B_DIS_RGMII_SHIFT(id),
786 mode << RTL8367B_DIS_RGMII_SHIFT(id));
787
788 return 0;
789 }
790
791 static int rtl8367b_extif_set_force(struct rtl8366_smi *smi, int id,
792 struct rtl8367_port_ability *pa)
793 {
794 u32 mask;
795 u32 val;
796 int err;
797
798 mask = (RTL8367B_DI_FORCE_MODE |
799 RTL8367B_DI_FORCE_NWAY |
800 RTL8367B_DI_FORCE_TXPAUSE |
801 RTL8367B_DI_FORCE_RXPAUSE |
802 RTL8367B_DI_FORCE_LINK |
803 RTL8367B_DI_FORCE_DUPLEX |
804 RTL8367B_DI_FORCE_SPEED_MASK);
805
806 val = pa->speed;
807 val |= pa->force_mode ? RTL8367B_DI_FORCE_MODE : 0;
808 val |= pa->nway ? RTL8367B_DI_FORCE_NWAY : 0;
809 val |= pa->txpause ? RTL8367B_DI_FORCE_TXPAUSE : 0;
810 val |= pa->rxpause ? RTL8367B_DI_FORCE_RXPAUSE : 0;
811 val |= pa->link ? RTL8367B_DI_FORCE_LINK : 0;
812 val |= pa->duplex ? RTL8367B_DI_FORCE_DUPLEX : 0;
813
814 REG_RMW(smi, RTL8367B_DI_FORCE_REG(id), mask, val);
815
816 return 0;
817 }
818
819 static int rtl8367b_extif_set_rgmii_delay(struct rtl8366_smi *smi, int id,
820 unsigned txdelay, unsigned rxdelay)
821 {
822 u32 mask;
823 u32 val;
824 int err;
825
826 mask = (RTL8367B_EXT_RGMXF_RXDELAY_MASK |
827 (RTL8367B_EXT_RGMXF_TXDELAY_MASK <<
828 RTL8367B_EXT_RGMXF_TXDELAY_SHIFT));
829
830 val = rxdelay;
831 val |= txdelay << RTL8367B_EXT_RGMXF_TXDELAY_SHIFT;
832
833 REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), mask, val);
834
835 return 0;
836 }
837
838 static int rtl8367b_extif_init(struct rtl8366_smi *smi, int id,
839 struct rtl8367_extif_config *cfg)
840 {
841 enum rtl8367_extif_mode mode;
842 int err;
843
844 mode = (cfg) ? cfg->mode : RTL8367_EXTIF_MODE_DISABLED;
845
846 err = rtl8367b_extif_set_mode(smi, id, mode);
847 if (err)
848 return err;
849
850 if (mode != RTL8367_EXTIF_MODE_DISABLED) {
851 err = rtl8367b_extif_set_force(smi, id, &cfg->ability);
852 if (err)
853 return err;
854
855 err = rtl8367b_extif_set_rgmii_delay(smi, id, cfg->txdelay,
856 cfg->rxdelay);
857 if (err)
858 return err;
859 }
860
861 return 0;
862 }
863
864 static int rtl8367b_setup(struct rtl8366_smi *smi)
865 {
866 struct rtl8367_platform_data *pdata;
867 int err;
868 int i;
869
870 pdata = smi->parent->platform_data;
871
872 err = rtl8367b_init_regs(smi);
873 if (err)
874 return err;
875
876 /* initialize external interfaces */
877 err = rtl8367b_extif_init(smi, 0, pdata->extif0_cfg);
878 if (err)
879 return err;
880
881 err = rtl8367b_extif_init(smi, 1, pdata->extif1_cfg);
882 if (err)
883 return err;
884
885 /* set maximum packet length to 1536 bytes */
886 REG_RMW(smi, RTL8367B_SWC0_REG, RTL8367B_SWC0_MAX_LENGTH_MASK,
887 RTL8367B_SWC0_MAX_LENGTH_1536);
888
889 /*
890 * discard VLAN tagged packets if the port is not a member of
891 * the VLAN with which the packets is associated.
892 */
893 REG_WR(smi, RTL8367B_VLAN_INGRESS_REG, RTL8367B_PORTS_ALL);
894
895 /*
896 * Setup egress tag mode for each port.
897 */
898 for (i = 0; i < RTL8367B_NUM_PORTS; i++)
899 REG_RMW(smi,
900 RTL8367B_PORT_MISC_CFG_REG(i),
901 RTL8367B_PORT_MISC_CFG_EGRESS_MODE_MASK <<
902 RTL8367B_PORT_MISC_CFG_EGRESS_MODE_SHIFT,
903 RTL8367B_PORT_MISC_CFG_EGRESS_MODE_ORIGINAL <<
904 RTL8367B_PORT_MISC_CFG_EGRESS_MODE_SHIFT);
905
906 return 0;
907 }
908
909 static int rtl8367b_get_mib_counter(struct rtl8366_smi *smi, int counter,
910 int port, unsigned long long *val)
911 {
912 struct rtl8366_mib_counter *mib;
913 int offset;
914 int i;
915 int err;
916 u32 addr, data;
917 u64 mibvalue;
918
919 if (port > RTL8367B_NUM_PORTS ||
920 counter >= RTL8367B_NUM_MIB_COUNTERS)
921 return -EINVAL;
922
923 mib = &rtl8367b_mib_counters[counter];
924 addr = RTL8367B_MIB_COUNTER_PORT_OFFSET * port + mib->offset;
925
926 /*
927 * Writing access counter address first
928 * then ASIC will prepare 64bits counter wait for being retrived
929 */
930 REG_WR(smi, RTL8367B_MIB_ADDRESS_REG, addr >> 2);
931
932 /* read MIB control register */
933 REG_RD(smi, RTL8367B_MIB_CTRL0_REG(0), &data);
934
935 if (data & RTL8367B_MIB_CTRL0_BUSY_MASK)
936 return -EBUSY;
937
938 if (data & RTL8367B_MIB_CTRL0_RESET_MASK)
939 return -EIO;
940
941 if (mib->length == 4)
942 offset = 3;
943 else
944 offset = (mib->offset + 1) % 4;
945
946 mibvalue = 0;
947 for (i = 0; i < mib->length; i++) {
948 REG_RD(smi, RTL8367B_MIB_COUNTER_REG(offset - i), &data);
949 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
950 }
951
952 *val = mibvalue;
953 return 0;
954 }
955
956 static int rtl8367b_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
957 struct rtl8366_vlan_4k *vlan4k)
958 {
959 u32 data[RTL8367B_TA_VLAN_NUM_WORDS];
960 int err;
961 int i;
962
963 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
964
965 if (vid >= RTL8367B_NUM_VIDS)
966 return -EINVAL;
967
968 /* write VID */
969 REG_WR(smi, RTL8367B_TA_ADDR_REG, vid);
970
971 /* write table access control word */
972 REG_WR(smi, RTL8367B_TA_CTRL_REG, RTL8367B_TA_CTRL_CVLAN_READ);
973
974 for (i = 0; i < ARRAY_SIZE(data); i++)
975 REG_RD(smi, RTL8367B_TA_RDDATA_REG(i), &data[i]);
976
977 vlan4k->vid = vid;
978 vlan4k->member = (data[0] >> RTL8367B_TA_VLAN0_MEMBER_SHIFT) &
979 RTL8367B_TA_VLAN0_MEMBER_MASK;
980 vlan4k->untag = (data[0] >> RTL8367B_TA_VLAN0_UNTAG_SHIFT) &
981 RTL8367B_TA_VLAN0_UNTAG_MASK;
982 vlan4k->fid = (data[1] >> RTL8367B_TA_VLAN1_FID_SHIFT) &
983 RTL8367B_TA_VLAN1_FID_MASK;
984
985 return 0;
986 }
987
988 static int rtl8367b_set_vlan_4k(struct rtl8366_smi *smi,
989 const struct rtl8366_vlan_4k *vlan4k)
990 {
991 u32 data[RTL8367B_TA_VLAN_NUM_WORDS];
992 int err;
993 int i;
994
995 if (vlan4k->vid >= RTL8367B_NUM_VIDS ||
996 vlan4k->member > RTL8367B_TA_VLAN0_MEMBER_MASK ||
997 vlan4k->untag > RTL8367B_UNTAG_MASK ||
998 vlan4k->fid > RTL8367B_FIDMAX)
999 return -EINVAL;
1000
1001 memset(data, 0, sizeof(data));
1002
1003 data[0] = (vlan4k->member & RTL8367B_TA_VLAN0_MEMBER_MASK) <<
1004 RTL8367B_TA_VLAN0_MEMBER_SHIFT;
1005 data[0] |= (vlan4k->untag & RTL8367B_TA_VLAN0_UNTAG_MASK) <<
1006 RTL8367B_TA_VLAN0_UNTAG_SHIFT;
1007 data[1] = (vlan4k->fid & RTL8367B_TA_VLAN1_FID_MASK) <<
1008 RTL8367B_TA_VLAN1_FID_SHIFT;
1009
1010 for (i = 0; i < ARRAY_SIZE(data); i++)
1011 REG_WR(smi, RTL8367B_TA_WRDATA_REG(i), data[i]);
1012
1013 /* write VID */
1014 REG_WR(smi, RTL8367B_TA_ADDR_REG,
1015 vlan4k->vid & RTL8367B_TA_VLAN_VID_MASK);
1016
1017 /* write table access control word */
1018 REG_WR(smi, RTL8367B_TA_CTRL_REG, RTL8367B_TA_CTRL_CVLAN_WRITE);
1019
1020 return 0;
1021 }
1022
1023 static int rtl8367b_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
1024 struct rtl8366_vlan_mc *vlanmc)
1025 {
1026 u32 data[RTL8367B_VLAN_MC_NUM_WORDS];
1027 int err;
1028 int i;
1029
1030 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
1031
1032 if (index >= RTL8367B_NUM_VLANS)
1033 return -EINVAL;
1034
1035 for (i = 0; i < ARRAY_SIZE(data); i++)
1036 REG_RD(smi, RTL8367B_VLAN_MC_BASE(index) + i, &data[i]);
1037
1038 vlanmc->member = (data[0] >> RTL8367B_VLAN_MC0_MEMBER_SHIFT) &
1039 RTL8367B_VLAN_MC0_MEMBER_MASK;
1040 vlanmc->fid = (data[1] >> RTL8367B_VLAN_MC1_FID_SHIFT) &
1041 RTL8367B_VLAN_MC1_FID_MASK;
1042 vlanmc->vid = (data[3] >> RTL8367B_VLAN_MC3_EVID_SHIFT) &
1043 RTL8367B_VLAN_MC3_EVID_MASK;
1044
1045 return 0;
1046 }
1047
1048 static int rtl8367b_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
1049 const struct rtl8366_vlan_mc *vlanmc)
1050 {
1051 u32 data[RTL8367B_VLAN_MC_NUM_WORDS];
1052 int err;
1053 int i;
1054
1055 if (index >= RTL8367B_NUM_VLANS ||
1056 vlanmc->vid >= RTL8367B_NUM_VIDS ||
1057 vlanmc->priority > RTL8367B_PRIORITYMAX ||
1058 vlanmc->member > RTL8367B_VLAN_MC0_MEMBER_MASK ||
1059 vlanmc->untag > RTL8367B_UNTAG_MASK ||
1060 vlanmc->fid > RTL8367B_FIDMAX)
1061 return -EINVAL;
1062
1063 data[0] = (vlanmc->member & RTL8367B_VLAN_MC0_MEMBER_MASK) <<
1064 RTL8367B_VLAN_MC0_MEMBER_SHIFT;
1065 data[1] = (vlanmc->fid & RTL8367B_VLAN_MC1_FID_MASK) <<
1066 RTL8367B_VLAN_MC1_FID_SHIFT;
1067 data[2] = 0;
1068 data[3] = (vlanmc->vid & RTL8367B_VLAN_MC3_EVID_MASK) <<
1069 RTL8367B_VLAN_MC3_EVID_SHIFT;
1070
1071 for (i = 0; i < ARRAY_SIZE(data); i++)
1072 REG_WR(smi, RTL8367B_VLAN_MC_BASE(index) + i, data[i]);
1073
1074 return 0;
1075 }
1076
1077 static int rtl8367b_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
1078 {
1079 u32 data;
1080 int err;
1081
1082 if (port >= RTL8367B_NUM_PORTS)
1083 return -EINVAL;
1084
1085 REG_RD(smi, RTL8367B_VLAN_PVID_CTRL_REG(port), &data);
1086
1087 *val = (data >> RTL8367B_VLAN_PVID_CTRL_SHIFT(port)) &
1088 RTL8367B_VLAN_PVID_CTRL_MASK;
1089
1090 return 0;
1091 }
1092
1093 static int rtl8367b_set_mc_index(struct rtl8366_smi *smi, int port, int index)
1094 {
1095 if (port >= RTL8367B_NUM_PORTS || index >= RTL8367B_NUM_VLANS)
1096 return -EINVAL;
1097
1098 return rtl8366_smi_rmwr(smi, RTL8367B_VLAN_PVID_CTRL_REG(port),
1099 RTL8367B_VLAN_PVID_CTRL_MASK <<
1100 RTL8367B_VLAN_PVID_CTRL_SHIFT(port),
1101 (index & RTL8367B_VLAN_PVID_CTRL_MASK) <<
1102 RTL8367B_VLAN_PVID_CTRL_SHIFT(port));
1103 }
1104
1105 static int rtl8367b_enable_vlan(struct rtl8366_smi *smi, int enable)
1106 {
1107 return rtl8366_smi_rmwr(smi, RTL8367B_VLAN_CTRL_REG,
1108 RTL8367B_VLAN_CTRL_ENABLE,
1109 (enable) ? RTL8367B_VLAN_CTRL_ENABLE : 0);
1110 }
1111
1112 static int rtl8367b_enable_vlan4k(struct rtl8366_smi *smi, int enable)
1113 {
1114 return 0;
1115 }
1116
1117 static int rtl8367b_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
1118 {
1119 unsigned max = RTL8367B_NUM_VLANS;
1120
1121 if (smi->vlan4k_enabled)
1122 max = RTL8367B_NUM_VIDS - 1;
1123
1124 if (vlan == 0 || vlan >= max)
1125 return 0;
1126
1127 return 1;
1128 }
1129
1130 static int rtl8367b_enable_port(struct rtl8366_smi *smi, int port, int enable)
1131 {
1132 int err;
1133
1134 REG_WR(smi, RTL8367B_PORT_ISOLATION_REG(port),
1135 (enable) ? RTL8367B_PORTS_ALL : 0);
1136
1137 return 0;
1138 }
1139
1140 static int rtl8367b_sw_reset_mibs(struct switch_dev *dev,
1141 const struct switch_attr *attr,
1142 struct switch_val *val)
1143 {
1144 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1145
1146 return rtl8366_smi_rmwr(smi, RTL8367B_MIB_CTRL0_REG(0), 0,
1147 RTL8367B_MIB_CTRL0_GLOBAL_RESET_MASK);
1148 }
1149
1150 static int rtl8367b_sw_get_port_link(struct switch_dev *dev,
1151 int port,
1152 struct switch_port_link *link)
1153 {
1154 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1155 u32 data = 0;
1156 u32 speed;
1157
1158 if (port >= RTL8367B_NUM_PORTS)
1159 return -EINVAL;
1160
1161 rtl8366_smi_read_reg(smi, RTL8367B_PORT_STATUS_REG(port), &data);
1162
1163 link->link = !!(data & RTL8367B_PORT_STATUS_LINK);
1164 if (!link->link)
1165 return 0;
1166
1167 link->duplex = !!(data & RTL8367B_PORT_STATUS_DUPLEX);
1168 link->rx_flow = !!(data & RTL8367B_PORT_STATUS_RXPAUSE);
1169 link->tx_flow = !!(data & RTL8367B_PORT_STATUS_TXPAUSE);
1170 link->aneg = !!(data & RTL8367B_PORT_STATUS_NWAY);
1171
1172 speed = (data & RTL8367B_PORT_STATUS_SPEED_MASK);
1173 switch (speed) {
1174 case 0:
1175 link->speed = SWITCH_PORT_SPEED_10;
1176 break;
1177 case 1:
1178 link->speed = SWITCH_PORT_SPEED_100;
1179 break;
1180 case 2:
1181 link->speed = SWITCH_PORT_SPEED_1000;
1182 break;
1183 default:
1184 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
1185 break;
1186 }
1187
1188 return 0;
1189 }
1190
1191 static int rtl8367b_sw_get_max_length(struct switch_dev *dev,
1192 const struct switch_attr *attr,
1193 struct switch_val *val)
1194 {
1195 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1196 u32 data;
1197
1198 rtl8366_smi_read_reg(smi, RTL8367B_SWC0_REG, &data);
1199 val->value.i = (data & RTL8367B_SWC0_MAX_LENGTH_MASK) >>
1200 RTL8367B_SWC0_MAX_LENGTH_SHIFT;
1201
1202 return 0;
1203 }
1204
1205 static int rtl8367b_sw_set_max_length(struct switch_dev *dev,
1206 const struct switch_attr *attr,
1207 struct switch_val *val)
1208 {
1209 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1210 u32 max_len;
1211
1212 switch (val->value.i) {
1213 case 0:
1214 max_len = RTL8367B_SWC0_MAX_LENGTH_1522;
1215 break;
1216 case 1:
1217 max_len = RTL8367B_SWC0_MAX_LENGTH_1536;
1218 break;
1219 case 2:
1220 max_len = RTL8367B_SWC0_MAX_LENGTH_1552;
1221 break;
1222 case 3:
1223 max_len = RTL8367B_SWC0_MAX_LENGTH_16000;
1224 break;
1225 default:
1226 return -EINVAL;
1227 }
1228
1229 return rtl8366_smi_rmwr(smi, RTL8367B_SWC0_REG,
1230 RTL8367B_SWC0_MAX_LENGTH_MASK, max_len);
1231 }
1232
1233
1234 static int rtl8367b_sw_reset_port_mibs(struct switch_dev *dev,
1235 const struct switch_attr *attr,
1236 struct switch_val *val)
1237 {
1238 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1239 int port;
1240
1241 port = val->port_vlan;
1242 if (port >= RTL8367B_NUM_PORTS)
1243 return -EINVAL;
1244
1245 return rtl8366_smi_rmwr(smi, RTL8367B_MIB_CTRL0_REG(port / 8), 0,
1246 RTL8367B_MIB_CTRL0_PORT_RESET_MASK(port % 8));
1247 }
1248
1249 static struct switch_attr rtl8367b_globals[] = {
1250 {
1251 .type = SWITCH_TYPE_INT,
1252 .name = "enable_vlan",
1253 .description = "Enable VLAN mode",
1254 .set = rtl8366_sw_set_vlan_enable,
1255 .get = rtl8366_sw_get_vlan_enable,
1256 .max = 1,
1257 .ofs = 1
1258 }, {
1259 .type = SWITCH_TYPE_INT,
1260 .name = "enable_vlan4k",
1261 .description = "Enable VLAN 4K mode",
1262 .set = rtl8366_sw_set_vlan_enable,
1263 .get = rtl8366_sw_get_vlan_enable,
1264 .max = 1,
1265 .ofs = 2
1266 }, {
1267 .type = SWITCH_TYPE_NOVAL,
1268 .name = "reset_mibs",
1269 .description = "Reset all MIB counters",
1270 .set = rtl8367b_sw_reset_mibs,
1271 }, {
1272 .type = SWITCH_TYPE_INT,
1273 .name = "max_length",
1274 .description = "Get/Set the maximum length of valid packets"
1275 "(0:1522, 1:1536, 2:1552, 3:16000)",
1276 .set = rtl8367b_sw_set_max_length,
1277 .get = rtl8367b_sw_get_max_length,
1278 .max = 3,
1279 }
1280 };
1281
1282 static struct switch_attr rtl8367b_port[] = {
1283 {
1284 .type = SWITCH_TYPE_NOVAL,
1285 .name = "reset_mib",
1286 .description = "Reset single port MIB counters",
1287 .set = rtl8367b_sw_reset_port_mibs,
1288 }, {
1289 .type = SWITCH_TYPE_STRING,
1290 .name = "mib",
1291 .description = "Get MIB counters for port",
1292 .max = 33,
1293 .set = NULL,
1294 .get = rtl8366_sw_get_port_mib,
1295 },
1296 };
1297
1298 static struct switch_attr rtl8367b_vlan[] = {
1299 {
1300 .type = SWITCH_TYPE_STRING,
1301 .name = "info",
1302 .description = "Get vlan information",
1303 .max = 1,
1304 .set = NULL,
1305 .get = rtl8366_sw_get_vlan_info,
1306 },
1307 };
1308
1309 static const struct switch_dev_ops rtl8367b_sw_ops = {
1310 .attr_global = {
1311 .attr = rtl8367b_globals,
1312 .n_attr = ARRAY_SIZE(rtl8367b_globals),
1313 },
1314 .attr_port = {
1315 .attr = rtl8367b_port,
1316 .n_attr = ARRAY_SIZE(rtl8367b_port),
1317 },
1318 .attr_vlan = {
1319 .attr = rtl8367b_vlan,
1320 .n_attr = ARRAY_SIZE(rtl8367b_vlan),
1321 },
1322
1323 .get_vlan_ports = rtl8366_sw_get_vlan_ports,
1324 .set_vlan_ports = rtl8366_sw_set_vlan_ports,
1325 .get_port_pvid = rtl8366_sw_get_port_pvid,
1326 .set_port_pvid = rtl8366_sw_set_port_pvid,
1327 .reset_switch = rtl8366_sw_reset_switch,
1328 .get_port_link = rtl8367b_sw_get_port_link,
1329 };
1330
1331 static int rtl8367b_switch_init(struct rtl8366_smi *smi)
1332 {
1333 struct switch_dev *dev = &smi->sw_dev;
1334 int err;
1335
1336 dev->name = "RTL8367B";
1337 dev->cpu_port = RTL8367B_CPU_PORT_NUM;
1338 dev->ports = RTL8367B_NUM_PORTS;
1339 dev->vlans = RTL8367B_NUM_VIDS;
1340 dev->ops = &rtl8367b_sw_ops;
1341 dev->alias = dev_name(smi->parent);
1342
1343 err = register_switch(dev, NULL);
1344 if (err)
1345 dev_err(smi->parent, "switch registration failed\n");
1346
1347 return err;
1348 }
1349
1350 static void rtl8367b_switch_cleanup(struct rtl8366_smi *smi)
1351 {
1352 unregister_switch(&smi->sw_dev);
1353 }
1354
1355 static int rtl8367b_mii_read(struct mii_bus *bus, int addr, int reg)
1356 {
1357 struct rtl8366_smi *smi = bus->priv;
1358 u32 val = 0;
1359 int err;
1360
1361 err = rtl8367b_read_phy_reg(smi, addr, reg, &val);
1362 if (err)
1363 return 0xffff;
1364
1365 return val;
1366 }
1367
1368 static int rtl8367b_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1369 {
1370 struct rtl8366_smi *smi = bus->priv;
1371 u32 t;
1372 int err;
1373
1374 err = rtl8367b_write_phy_reg(smi, addr, reg, val);
1375 if (err)
1376 return err;
1377
1378 /* flush write */
1379 (void) rtl8367b_read_phy_reg(smi, addr, reg, &t);
1380
1381 return err;
1382 }
1383
1384 static int __devinit rtl8367b_detect(struct rtl8366_smi *smi)
1385 {
1386 const char *chip_name;
1387 u32 chip_num;
1388 u32 chip_ver;
1389 u32 chip_mode;
1390 int ret;
1391
1392 /* TODO: improve chip detection */
1393 rtl8366_smi_write_reg(smi, RTL8367B_RTL_MAGIC_ID_REG,
1394 RTL8367B_RTL_MAGIC_ID_VAL);
1395
1396 ret = rtl8366_smi_read_reg(smi, RTL8367B_CHIP_NUMBER_REG, &chip_num);
1397 if (ret) {
1398 dev_err(smi->parent, "unable to read %s register\n",
1399 "chip number");
1400 return ret;
1401 }
1402
1403 ret = rtl8366_smi_read_reg(smi, RTL8367B_CHIP_VER_REG, &chip_ver);
1404 if (ret) {
1405 dev_err(smi->parent, "unable to read %s register\n",
1406 "chip version");
1407 return ret;
1408 }
1409
1410 ret = rtl8366_smi_read_reg(smi, RTL8367B_CHIP_MODE_REG, &chip_mode);
1411 if (ret) {
1412 dev_err(smi->parent, "unable to read %s register\n",
1413 "chip mode");
1414 return ret;
1415 }
1416
1417 switch (chip_ver) {
1418 case 0x1000:
1419 chip_name = "8367RB";
1420 break;
1421 case 0x1010:
1422 chip_name = "8367R-VB";
1423 break;
1424 default:
1425 dev_err(smi->parent,
1426 "unknown chip num:%04x ver:%04x, mode:%04x\n",
1427 chip_num, chip_ver, chip_mode);
1428 return -ENODEV;
1429 }
1430
1431 dev_info(smi->parent, "RTL%s chip found\n", chip_name);
1432
1433 return 0;
1434 }
1435
1436 static struct rtl8366_smi_ops rtl8367b_smi_ops = {
1437 .detect = rtl8367b_detect,
1438 .reset_chip = rtl8367b_reset_chip,
1439 .setup = rtl8367b_setup,
1440
1441 .mii_read = rtl8367b_mii_read,
1442 .mii_write = rtl8367b_mii_write,
1443
1444 .get_vlan_mc = rtl8367b_get_vlan_mc,
1445 .set_vlan_mc = rtl8367b_set_vlan_mc,
1446 .get_vlan_4k = rtl8367b_get_vlan_4k,
1447 .set_vlan_4k = rtl8367b_set_vlan_4k,
1448 .get_mc_index = rtl8367b_get_mc_index,
1449 .set_mc_index = rtl8367b_set_mc_index,
1450 .get_mib_counter = rtl8367b_get_mib_counter,
1451 .is_vlan_valid = rtl8367b_is_vlan_valid,
1452 .enable_vlan = rtl8367b_enable_vlan,
1453 .enable_vlan4k = rtl8367b_enable_vlan4k,
1454 .enable_port = rtl8367b_enable_port,
1455 };
1456
1457 static int __devinit rtl8367b_probe(struct platform_device *pdev)
1458 {
1459 struct rtl8367_platform_data *pdata;
1460 struct rtl8366_smi *smi;
1461 int err;
1462
1463 smi = rtl8366_smi_probe(pdev);
1464 if (!smi)
1465 return -ENODEV;
1466
1467 smi->clk_delay = 1500;
1468 smi->cmd_read = 0xb9;
1469 smi->cmd_write = 0xb8;
1470 smi->ops = &rtl8367b_smi_ops;
1471 smi->cpu_port = RTL8367B_CPU_PORT_NUM;
1472 smi->num_ports = RTL8367B_NUM_PORTS;
1473 smi->num_vlan_mc = RTL8367B_NUM_VLANS;
1474 smi->mib_counters = rtl8367b_mib_counters;
1475 smi->num_mib_counters = ARRAY_SIZE(rtl8367b_mib_counters);
1476
1477 err = rtl8366_smi_init(smi);
1478 if (err)
1479 goto err_free_smi;
1480
1481 platform_set_drvdata(pdev, smi);
1482
1483 err = rtl8367b_switch_init(smi);
1484 if (err)
1485 goto err_clear_drvdata;
1486
1487 return 0;
1488
1489 err_clear_drvdata:
1490 platform_set_drvdata(pdev, NULL);
1491 rtl8366_smi_cleanup(smi);
1492 err_free_smi:
1493 kfree(smi);
1494 err_out:
1495 return err;
1496 }
1497
1498 static int __devexit rtl8367b_remove(struct platform_device *pdev)
1499 {
1500 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1501
1502 if (smi) {
1503 rtl8367b_switch_cleanup(smi);
1504 platform_set_drvdata(pdev, NULL);
1505 rtl8366_smi_cleanup(smi);
1506 kfree(smi);
1507 }
1508
1509 return 0;
1510 }
1511
1512 static void rtl8367b_shutdown(struct platform_device *pdev)
1513 {
1514 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1515
1516 if (smi)
1517 rtl8367b_reset_chip(smi);
1518 }
1519
1520 #ifdef CONFIG_OF
1521 static const struct of_device_id rtl8367b_match[] = {
1522 { .compatible = "rtl8367b" },
1523 {},
1524 };
1525 MODULE_DEVICE_TABLE(of, rtl8367b_match);
1526 #endif
1527
1528 static struct platform_driver rtl8367b_driver = {
1529 .driver = {
1530 .name = RTL8367B_DRIVER_NAME,
1531 .owner = THIS_MODULE,
1532 #ifdef CONFIG_OF
1533 .of_match_table = of_match_ptr(rtl8367b_match),
1534 #endif
1535 },
1536 .probe = rtl8367b_probe,
1537 .remove = __devexit_p(rtl8367b_remove),
1538 .shutdown = rtl8367b_shutdown,
1539 };
1540
1541 module_platform_driver(rtl8367b_driver);
1542
1543 MODULE_DESCRIPTION(RTL8367B_DRIVER_DESC);
1544 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1545 MODULE_LICENSE("GPL v2");
1546 MODULE_ALIAS("platform:" RTL8367B_DRIVER_NAME);
1547
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