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Add missing bracket in MAP-E FMR kernel support
[openwrt/openwrt.git] / target / linux / generic / patches-3.10 / 025-bcma_backport.patch
1 --- a/drivers/bcma/Kconfig
2 +++ b/drivers/bcma/Kconfig
3 @@ -26,6 +26,7 @@ config BCMA_HOST_PCI_POSSIBLE
4 config BCMA_HOST_PCI
5 bool "Support for BCMA on PCI-host bus"
6 depends on BCMA_HOST_PCI_POSSIBLE
7 + default y
8
9 config BCMA_DRIVER_PCI_HOSTMODE
10 bool "Driver for PCI core working in hostmode"
11 @@ -34,8 +35,14 @@ config BCMA_DRIVER_PCI_HOSTMODE
12 PCI core hostmode operation (external PCI bus).
13
14 config BCMA_HOST_SOC
15 - bool
16 - depends on BCMA_DRIVER_MIPS
17 + bool "Support for BCMA in a SoC"
18 + depends on BCMA
19 + help
20 + Host interface for a Broadcom AIX bus directly mapped into
21 + the memory. This only works with the Broadcom SoCs from the
22 + BCM47XX line.
23 +
24 + If unsure, say N
25
26 config BCMA_DRIVER_MIPS
27 bool "BCMA Broadcom MIPS core driver"
28 @@ -68,6 +75,7 @@ config BCMA_DRIVER_GMAC_CMN
29 config BCMA_DRIVER_GPIO
30 bool "BCMA GPIO driver"
31 depends on BCMA && GPIOLIB
32 + select IRQ_DOMAIN if BCMA_HOST_SOC
33 help
34 Driver to provide access to the GPIO pins of the bcma bus.
35
36 --- a/drivers/bcma/bcma_private.h
37 +++ b/drivers/bcma/bcma_private.h
38 @@ -22,6 +22,8 @@
39 struct bcma_bus;
40
41 /* main.c */
42 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
43 + int timeout);
44 int bcma_bus_register(struct bcma_bus *bus);
45 void bcma_bus_unregister(struct bcma_bus *bus);
46 int __init bcma_bus_early_register(struct bcma_bus *bus,
47 @@ -31,8 +33,6 @@ int __init bcma_bus_early_register(struc
48 int bcma_bus_suspend(struct bcma_bus *bus);
49 int bcma_bus_resume(struct bcma_bus *bus);
50 #endif
51 -struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
52 - u8 unit);
53
54 /* scan.c */
55 int bcma_bus_scan(struct bcma_bus *bus);
56 --- a/drivers/bcma/core.c
57 +++ b/drivers/bcma/core.c
58 @@ -9,6 +9,25 @@
59 #include <linux/export.h>
60 #include <linux/bcma/bcma.h>
61
62 +static bool bcma_core_wait_value(struct bcma_device *core, u16 reg, u32 mask,
63 + u32 value, int timeout)
64 +{
65 + unsigned long deadline = jiffies + timeout;
66 + u32 val;
67 +
68 + do {
69 + val = bcma_aread32(core, reg);
70 + if ((val & mask) == value)
71 + return true;
72 + cpu_relax();
73 + udelay(10);
74 + } while (!time_after_eq(jiffies, deadline));
75 +
76 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
77 +
78 + return false;
79 +}
80 +
81 bool bcma_core_is_enabled(struct bcma_device *core)
82 {
83 if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC))
84 @@ -25,13 +44,15 @@ void bcma_core_disable(struct bcma_devic
85 if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
86 return;
87
88 - bcma_awrite32(core, BCMA_IOCTL, flags);
89 - bcma_aread32(core, BCMA_IOCTL);
90 - udelay(10);
91 + bcma_core_wait_value(core, BCMA_RESET_ST, ~0, 0, 300);
92
93 bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
94 bcma_aread32(core, BCMA_RESET_CTL);
95 udelay(1);
96 +
97 + bcma_awrite32(core, BCMA_IOCTL, flags);
98 + bcma_aread32(core, BCMA_IOCTL);
99 + udelay(10);
100 }
101 EXPORT_SYMBOL_GPL(bcma_core_disable);
102
103 @@ -43,6 +64,7 @@ int bcma_core_enable(struct bcma_device
104 bcma_aread32(core, BCMA_IOCTL);
105
106 bcma_awrite32(core, BCMA_RESET_CTL, 0);
107 + bcma_aread32(core, BCMA_RESET_CTL);
108 udelay(1);
109
110 bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
111 --- a/drivers/bcma/driver_chipcommon.c
112 +++ b/drivers/bcma/driver_chipcommon.c
113 @@ -140,8 +140,15 @@ void bcma_core_chipcommon_init(struct bc
114 bcma_core_chipcommon_early_init(cc);
115
116 if (cc->core->id.rev >= 20) {
117 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
118 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
119 + u32 pullup = 0, pulldown = 0;
120 +
121 + if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) {
122 + pullup = 0x402e0;
123 + pulldown = 0x20500;
124 + }
125 +
126 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup);
127 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown);
128 }
129
130 if (cc->capabilities & BCMA_CC_CAP_PMU)
131 --- a/drivers/bcma/driver_chipcommon_pmu.c
132 +++ b/drivers/bcma/driver_chipcommon_pmu.c
133 @@ -56,6 +56,109 @@ void bcma_chipco_regctl_maskset(struct b
134 }
135 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
136
137 +static u32 bcma_pmu_xtalfreq(struct bcma_drv_cc *cc)
138 +{
139 + u32 ilp_ctl, alp_hz;
140 +
141 + if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) &
142 + BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
143 + return 0;
144 +
145 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
146 + BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
147 + usleep_range(1000, 2000);
148 +
149 + ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
150 + ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
151 +
152 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
153 +
154 + alp_hz = ilp_ctl * 32768 / 4;
155 + return (alp_hz + 50000) / 100000 * 100;
156 +}
157 +
158 +static void bcma_pmu2_pll_init0(struct bcma_drv_cc *cc, u32 xtalfreq)
159 +{
160 + struct bcma_bus *bus = cc->core->bus;
161 + u32 freq_tgt_target = 0, freq_tgt_current;
162 + u32 pll0, mask;
163 +
164 + switch (bus->chipinfo.id) {
165 + case BCMA_CHIP_ID_BCM43142:
166 + /* pmu2_xtaltab0_adfll_485 */
167 + switch (xtalfreq) {
168 + case 12000:
169 + freq_tgt_target = 0x50D52;
170 + break;
171 + case 20000:
172 + freq_tgt_target = 0x307FE;
173 + break;
174 + case 26000:
175 + freq_tgt_target = 0x254EA;
176 + break;
177 + case 37400:
178 + freq_tgt_target = 0x19EF8;
179 + break;
180 + case 52000:
181 + freq_tgt_target = 0x12A75;
182 + break;
183 + }
184 + break;
185 + }
186 +
187 + if (!freq_tgt_target) {
188 + bcma_err(bus, "Unknown TGT frequency for xtalfreq %d\n",
189 + xtalfreq);
190 + return;
191 + }
192 +
193 + pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0);
194 + freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >>
195 + BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
196 +
197 + if (freq_tgt_current == freq_tgt_target) {
198 + bcma_debug(bus, "Target TGT frequency already set\n");
199 + return;
200 + }
201 +
202 + /* Turn off PLL */
203 + switch (bus->chipinfo.id) {
204 + case BCMA_CHIP_ID_BCM43142:
205 + mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
206 + BCMA_RES_4314_MACPHY_CLK_AVAIL);
207 +
208 + bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
209 + bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
210 + bcma_wait_value(cc->core, BCMA_CLKCTLST,
211 + BCMA_CLKCTLST_HAVEHT, 0, 20000);
212 + break;
213 + }
214 +
215 + pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK;
216 + pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
217 + bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0);
218 +
219 + /* Flush */
220 + if (cc->pmu.rev >= 2)
221 + bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
222 +
223 + /* TODO: Do we need to update OTP? */
224 +}
225 +
226 +static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
227 +{
228 + struct bcma_bus *bus = cc->core->bus;
229 + u32 xtalfreq = bcma_pmu_xtalfreq(cc);
230 +
231 + switch (bus->chipinfo.id) {
232 + case BCMA_CHIP_ID_BCM43142:
233 + if (xtalfreq == 0)
234 + xtalfreq = 20000;
235 + bcma_pmu2_pll_init0(cc, xtalfreq);
236 + break;
237 + }
238 +}
239 +
240 static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
241 {
242 struct bcma_bus *bus = cc->core->bus;
243 @@ -66,6 +169,25 @@ static void bcma_pmu_resources_init(stru
244 min_msk = 0x200D;
245 max_msk = 0xFFFF;
246 break;
247 + case BCMA_CHIP_ID_BCM43142:
248 + min_msk = BCMA_RES_4314_LPLDO_PU |
249 + BCMA_RES_4314_PMU_SLEEP_DIS |
250 + BCMA_RES_4314_PMU_BG_PU |
251 + BCMA_RES_4314_CBUCK_LPOM_PU |
252 + BCMA_RES_4314_CBUCK_PFM_PU |
253 + BCMA_RES_4314_CLDO_PU |
254 + BCMA_RES_4314_LPLDO2_LVM |
255 + BCMA_RES_4314_WL_PMU_PU |
256 + BCMA_RES_4314_LDO3P3_PU |
257 + BCMA_RES_4314_OTP_PU |
258 + BCMA_RES_4314_WL_PWRSW_PU |
259 + BCMA_RES_4314_LQ_AVAIL |
260 + BCMA_RES_4314_LOGIC_RET |
261 + BCMA_RES_4314_MEM_SLEEP |
262 + BCMA_RES_4314_MACPHY_RET |
263 + BCMA_RES_4314_WL_CORE_READY;
264 + max_msk = 0x3FFFFFFF;
265 + break;
266 default:
267 bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
268 bus->chipinfo.id);
269 @@ -165,6 +287,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c
270 bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
271 BCMA_CC_PMU_CTL_NOILPONW);
272
273 + bcma_pmu_pll_init(cc);
274 bcma_pmu_resources_init(cc);
275 bcma_pmu_workarounds(cc);
276 }
277 --- a/drivers/bcma/driver_chipcommon_sflash.c
278 +++ b/drivers/bcma/driver_chipcommon_sflash.c
279 @@ -30,7 +30,7 @@ struct bcma_sflash_tbl_e {
280 u16 numblocks;
281 };
282
283 -static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
284 +static const struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
285 { "M25P20", 0x11, 0x10000, 4, },
286 { "M25P40", 0x12, 0x10000, 8, },
287
288 @@ -38,10 +38,10 @@ static struct bcma_sflash_tbl_e bcma_sfl
289 { "M25P32", 0x15, 0x10000, 64, },
290 { "M25P64", 0x16, 0x10000, 128, },
291 { "M25FL128", 0x17, 0x10000, 256, },
292 - { 0 },
293 + { NULL },
294 };
295
296 -static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
297 +static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
298 { "SST25WF512", 1, 0x1000, 16, },
299 { "SST25VF512", 0x48, 0x1000, 16, },
300 { "SST25WF010", 2, 0x1000, 32, },
301 @@ -56,10 +56,10 @@ static struct bcma_sflash_tbl_e bcma_sfl
302 { "SST25VF016", 0x41, 0x1000, 512, },
303 { "SST25VF032", 0x4a, 0x1000, 1024, },
304 { "SST25VF064", 0x4b, 0x1000, 2048, },
305 - { 0 },
306 + { NULL },
307 };
308
309 -static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
310 +static const struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
311 { "AT45DB011", 0xc, 256, 512, },
312 { "AT45DB021", 0x14, 256, 1024, },
313 { "AT45DB041", 0x1c, 256, 2048, },
314 @@ -67,7 +67,7 @@ static struct bcma_sflash_tbl_e bcma_sfl
315 { "AT45DB161", 0x2c, 512, 4096, },
316 { "AT45DB321", 0x34, 512, 8192, },
317 { "AT45DB642", 0x3c, 1024, 8192, },
318 - { 0 },
319 + { NULL },
320 };
321
322 static void bcma_sflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
323 @@ -89,7 +89,7 @@ int bcma_sflash_init(struct bcma_drv_cc
324 {
325 struct bcma_bus *bus = cc->core->bus;
326 struct bcma_sflash *sflash = &cc->sflash;
327 - struct bcma_sflash_tbl_e *e;
328 + const struct bcma_sflash_tbl_e *e;
329 u32 id, id2;
330
331 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
332 --- a/drivers/bcma/driver_gpio.c
333 +++ b/drivers/bcma/driver_gpio.c
334 @@ -9,6 +9,9 @@
335 */
336
337 #include <linux/gpio.h>
338 +#include <linux/irq.h>
339 +#include <linux/interrupt.h>
340 +#include <linux/irqdomain.h>
341 #include <linux/export.h>
342 #include <linux/bcma/bcma.h>
343
344 @@ -73,19 +76,136 @@ static void bcma_gpio_free(struct gpio_c
345 bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
346 }
347
348 +#if IS_BUILTIN(CONFIG_BCMA_HOST_SOC)
349 static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
350 {
351 struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
352
353 if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
354 - return bcma_core_irq(cc->core);
355 + return irq_find_mapping(cc->irq_domain, gpio);
356 else
357 return -EINVAL;
358 }
359
360 +static void bcma_gpio_irq_unmask(struct irq_data *d)
361 +{
362 + struct bcma_drv_cc *cc = irq_data_get_irq_chip_data(d);
363 + int gpio = irqd_to_hwirq(d);
364 + u32 val = bcma_chipco_gpio_in(cc, BIT(gpio));
365 +
366 + bcma_chipco_gpio_polarity(cc, BIT(gpio), val);
367 + bcma_chipco_gpio_intmask(cc, BIT(gpio), BIT(gpio));
368 +}
369 +
370 +static void bcma_gpio_irq_mask(struct irq_data *d)
371 +{
372 + struct bcma_drv_cc *cc = irq_data_get_irq_chip_data(d);
373 + int gpio = irqd_to_hwirq(d);
374 +
375 + bcma_chipco_gpio_intmask(cc, BIT(gpio), 0);
376 +}
377 +
378 +static struct irq_chip bcma_gpio_irq_chip = {
379 + .name = "BCMA-GPIO",
380 + .irq_mask = bcma_gpio_irq_mask,
381 + .irq_unmask = bcma_gpio_irq_unmask,
382 +};
383 +
384 +static irqreturn_t bcma_gpio_irq_handler(int irq, void *dev_id)
385 +{
386 + struct bcma_drv_cc *cc = dev_id;
387 + u32 val = bcma_cc_read32(cc, BCMA_CC_GPIOIN);
388 + u32 mask = bcma_cc_read32(cc, BCMA_CC_GPIOIRQ);
389 + u32 pol = bcma_cc_read32(cc, BCMA_CC_GPIOPOL);
390 + unsigned long irqs = (val ^ pol) & mask;
391 + int gpio;
392 +
393 + if (!irqs)
394 + return IRQ_NONE;
395 +
396 + for_each_set_bit(gpio, &irqs, cc->gpio.ngpio)
397 + generic_handle_irq(bcma_gpio_to_irq(&cc->gpio, gpio));
398 + bcma_chipco_gpio_polarity(cc, irqs, val & irqs);
399 +
400 + return IRQ_HANDLED;
401 +}
402 +
403 +static int bcma_gpio_irq_domain_init(struct bcma_drv_cc *cc)
404 +{
405 + struct gpio_chip *chip = &cc->gpio;
406 + int gpio, hwirq, err;
407 +
408 + if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
409 + return 0;
410 +
411 + cc->irq_domain = irq_domain_add_linear(NULL, chip->ngpio,
412 + &irq_domain_simple_ops, cc);
413 + if (!cc->irq_domain) {
414 + err = -ENODEV;
415 + goto err_irq_domain;
416 + }
417 + for (gpio = 0; gpio < chip->ngpio; gpio++) {
418 + int irq = irq_create_mapping(cc->irq_domain, gpio);
419 +
420 + irq_set_chip_data(irq, cc);
421 + irq_set_chip_and_handler(irq, &bcma_gpio_irq_chip,
422 + handle_simple_irq);
423 + }
424 +
425 + hwirq = bcma_core_irq(cc->core);
426 + err = request_irq(hwirq, bcma_gpio_irq_handler, IRQF_SHARED, "gpio",
427 + cc);
428 + if (err)
429 + goto err_req_irq;
430 +
431 + bcma_chipco_gpio_intmask(cc, ~0, 0);
432 + bcma_cc_set32(cc, BCMA_CC_IRQMASK, BCMA_CC_IRQ_GPIO);
433 +
434 + return 0;
435 +
436 +err_req_irq:
437 + for (gpio = 0; gpio < chip->ngpio; gpio++) {
438 + int irq = irq_find_mapping(cc->irq_domain, gpio);
439 +
440 + irq_dispose_mapping(irq);
441 + }
442 + irq_domain_remove(cc->irq_domain);
443 +err_irq_domain:
444 + return err;
445 +}
446 +
447 +static void bcma_gpio_irq_domain_exit(struct bcma_drv_cc *cc)
448 +{
449 + struct gpio_chip *chip = &cc->gpio;
450 + int gpio;
451 +
452 + if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
453 + return;
454 +
455 + bcma_cc_mask32(cc, BCMA_CC_IRQMASK, ~BCMA_CC_IRQ_GPIO);
456 + free_irq(bcma_core_irq(cc->core), cc);
457 + for (gpio = 0; gpio < chip->ngpio; gpio++) {
458 + int irq = irq_find_mapping(cc->irq_domain, gpio);
459 +
460 + irq_dispose_mapping(irq);
461 + }
462 + irq_domain_remove(cc->irq_domain);
463 +}
464 +#else
465 +static int bcma_gpio_irq_domain_init(struct bcma_drv_cc *cc)
466 +{
467 + return 0;
468 +}
469 +
470 +static void bcma_gpio_irq_domain_exit(struct bcma_drv_cc *cc)
471 +{
472 +}
473 +#endif
474 +
475 int bcma_gpio_init(struct bcma_drv_cc *cc)
476 {
477 struct gpio_chip *chip = &cc->gpio;
478 + int err;
479
480 chip->label = "bcma_gpio";
481 chip->owner = THIS_MODULE;
482 @@ -95,8 +215,17 @@ int bcma_gpio_init(struct bcma_drv_cc *c
483 chip->set = bcma_gpio_set_value;
484 chip->direction_input = bcma_gpio_direction_input;
485 chip->direction_output = bcma_gpio_direction_output;
486 +#if IS_BUILTIN(CONFIG_BCMA_HOST_SOC)
487 chip->to_irq = bcma_gpio_to_irq;
488 - chip->ngpio = 16;
489 +#endif
490 + switch (cc->core->bus->chipinfo.id) {
491 + case BCMA_CHIP_ID_BCM5357:
492 + chip->ngpio = 32;
493 + break;
494 + default:
495 + chip->ngpio = 16;
496 + }
497 +
498 /* There is just one SoC in one device and its GPIO addresses should be
499 * deterministic to address them more easily. The other buses could get
500 * a random base number. */
501 @@ -105,10 +234,21 @@ int bcma_gpio_init(struct bcma_drv_cc *c
502 else
503 chip->base = -1;
504
505 - return gpiochip_add(chip);
506 + err = bcma_gpio_irq_domain_init(cc);
507 + if (err)
508 + return err;
509 +
510 + err = gpiochip_add(chip);
511 + if (err) {
512 + bcma_gpio_irq_domain_exit(cc);
513 + return err;
514 + }
515 +
516 + return 0;
517 }
518
519 int bcma_gpio_unregister(struct bcma_drv_cc *cc)
520 {
521 + bcma_gpio_irq_domain_exit(cc);
522 return gpiochip_remove(&cc->gpio);
523 }
524 --- a/drivers/bcma/driver_pci.c
525 +++ b/drivers/bcma/driver_pci.c
526 @@ -31,7 +31,7 @@ static void bcma_pcie_write(struct bcma_
527 pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
528 }
529
530 -static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
531 +static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u16 phy)
532 {
533 u32 v;
534 int i;
535 @@ -55,7 +55,7 @@ static void bcma_pcie_mdio_set_phy(struc
536 }
537 }
538
539 -static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
540 +static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u16 device, u8 address)
541 {
542 int max_retries = 10;
543 u16 ret = 0;
544 @@ -98,7 +98,7 @@ static u16 bcma_pcie_mdio_read(struct bc
545 return ret;
546 }
547
548 -static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
549 +static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u16 device,
550 u8 address, u16 data)
551 {
552 int max_retries = 10;
553 @@ -137,6 +137,13 @@ static void bcma_pcie_mdio_write(struct
554 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
555 }
556
557 +static u16 bcma_pcie_mdio_writeread(struct bcma_drv_pci *pc, u16 device,
558 + u8 address, u16 data)
559 +{
560 + bcma_pcie_mdio_write(pc, device, address, data);
561 + return bcma_pcie_mdio_read(pc, device, address);
562 +}
563 +
564 /**************************************************
565 * Workarounds.
566 **************************************************/
567 @@ -229,6 +236,32 @@ void bcma_core_pci_init(struct bcma_drv_
568 bcma_core_pci_clientmode_init(pc);
569 }
570
571 +void bcma_core_pci_power_save(struct bcma_bus *bus, bool up)
572 +{
573 + struct bcma_drv_pci *pc;
574 + u16 data;
575 +
576 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
577 + return;
578 +
579 + pc = &bus->drv_pci[0];
580 +
581 + if (pc->core->id.rev >= 15 && pc->core->id.rev <= 20) {
582 + data = up ? 0x74 : 0x7C;
583 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
584 + BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7F64);
585 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
586 + BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
587 + } else if (pc->core->id.rev >= 21 && pc->core->id.rev <= 22) {
588 + data = up ? 0x75 : 0x7D;
589 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
590 + BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7E65);
591 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
592 + BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
593 + }
594 +}
595 +EXPORT_SYMBOL_GPL(bcma_core_pci_power_save);
596 +
597 int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
598 bool enable)
599 {
600 @@ -262,7 +295,7 @@ out:
601 }
602 EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
603
604 -void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
605 +static void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
606 {
607 u32 w;
608
609 @@ -274,4 +307,29 @@ void bcma_core_pci_extend_L1timer(struct
610 bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w);
611 bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
612 }
613 -EXPORT_SYMBOL_GPL(bcma_core_pci_extend_L1timer);
614 +
615 +void bcma_core_pci_up(struct bcma_bus *bus)
616 +{
617 + struct bcma_drv_pci *pc;
618 +
619 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
620 + return;
621 +
622 + pc = &bus->drv_pci[0];
623 +
624 + bcma_core_pci_extend_L1timer(pc, true);
625 +}
626 +EXPORT_SYMBOL_GPL(bcma_core_pci_up);
627 +
628 +void bcma_core_pci_down(struct bcma_bus *bus)
629 +{
630 + struct bcma_drv_pci *pc;
631 +
632 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
633 + return;
634 +
635 + pc = &bus->drv_pci[0];
636 +
637 + bcma_core_pci_extend_L1timer(pc, false);
638 +}
639 +EXPORT_SYMBOL_GPL(bcma_core_pci_down);
640 --- a/drivers/bcma/driver_pci_host.c
641 +++ b/drivers/bcma/driver_pci_host.c
642 @@ -581,6 +581,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI
643 int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
644 {
645 struct bcma_drv_pci_host *pc_host;
646 + int readrq;
647
648 if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
649 /* This is not a device on the PCI-core bridge. */
650 @@ -595,6 +596,11 @@ int bcma_core_pci_plat_dev_init(struct p
651 dev->irq = bcma_core_irq(pc_host->pdev->core);
652 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
653
654 + readrq = pcie_get_readrq(dev);
655 + if (readrq > 128) {
656 + pr_info("change PCIe max read request size from %i to 128\n", readrq);
657 + pcie_set_readrq(dev, 128);
658 + }
659 return 0;
660 }
661 EXPORT_SYMBOL(bcma_core_pci_plat_dev_init);
662 --- a/drivers/bcma/host_pci.c
663 +++ b/drivers/bcma/host_pci.c
664 @@ -188,8 +188,11 @@ static int bcma_host_pci_probe(struct pc
665 pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
666
667 /* SSB needed additional powering up, do we have any AMBA PCI cards? */
668 - if (!pci_is_pcie(dev))
669 - bcma_err(bus, "PCI card detected, report problems.\n");
670 + if (!pci_is_pcie(dev)) {
671 + bcma_err(bus, "PCI card detected, they are not supported.\n");
672 + err = -ENXIO;
673 + goto err_pci_release_regions;
674 + }
675
676 /* Map MMIO */
677 err = -ENOMEM;
678 @@ -235,7 +238,6 @@ static void bcma_host_pci_remove(struct
679 pci_release_regions(dev);
680 pci_disable_device(dev);
681 kfree(bus);
682 - pci_set_drvdata(dev, NULL);
683 }
684
685 #ifdef CONFIG_PM_SLEEP
686 @@ -267,14 +269,16 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
687
688 #endif /* CONFIG_PM_SLEEP */
689
690 -static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
691 +static const struct pci_device_id bcma_pci_bridge_tbl[] = {
692 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
693 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4313) },
694 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) },
695 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
696 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
697 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
698 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
699 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
700 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
701 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
702 { 0, },
703 };
704 --- a/drivers/bcma/main.c
705 +++ b/drivers/bcma/main.c
706 @@ -69,28 +69,36 @@ static u16 bcma_cc_core_id(struct bcma_b
707 return BCMA_CORE_CHIPCOMMON;
708 }
709
710 -struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
711 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
712 + u8 unit)
713 {
714 struct bcma_device *core;
715
716 list_for_each_entry(core, &bus->cores, list) {
717 - if (core->id.id == coreid)
718 + if (core->id.id == coreid && core->core_unit == unit)
719 return core;
720 }
721 return NULL;
722 }
723 -EXPORT_SYMBOL_GPL(bcma_find_core);
724 +EXPORT_SYMBOL_GPL(bcma_find_core_unit);
725
726 -struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
727 - u8 unit)
728 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
729 + int timeout)
730 {
731 - struct bcma_device *core;
732 + unsigned long deadline = jiffies + timeout;
733 + u32 val;
734
735 - list_for_each_entry(core, &bus->cores, list) {
736 - if (core->id.id == coreid && core->core_unit == unit)
737 - return core;
738 - }
739 - return NULL;
740 + do {
741 + val = bcma_read32(core, reg);
742 + if ((val & mask) == value)
743 + return true;
744 + cpu_relax();
745 + udelay(10);
746 + } while (!time_after_eq(jiffies, deadline));
747 +
748 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
749 +
750 + return false;
751 }
752
753 static void bcma_release_core_dev(struct device *dev)
754 @@ -148,6 +156,7 @@ static int bcma_register_cores(struct bc
755 bcma_err(bus,
756 "Could not register dev for core 0x%03X\n",
757 core->id.id);
758 + put_device(&core->dev);
759 continue;
760 }
761 core->dev_registered = true;
762 @@ -218,7 +227,7 @@ int bcma_bus_register(struct bcma_bus *b
763 err = bcma_bus_scan(bus);
764 if (err) {
765 bcma_err(bus, "Failed to scan: %d\n", err);
766 - return -1;
767 + return err;
768 }
769
770 /* Early init CC core */
771 --- a/drivers/bcma/scan.c
772 +++ b/drivers/bcma/scan.c
773 @@ -32,6 +32,18 @@ static const struct bcma_device_id_name
774 { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
775 { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
776 { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
777 + { BCMA_CORE_PCIEG2, "PCIe Gen 2" },
778 + { BCMA_CORE_DMA, "DMA" },
779 + { BCMA_CORE_SDIO3, "SDIO3" },
780 + { BCMA_CORE_USB20, "USB 2.0" },
781 + { BCMA_CORE_USB30, "USB 3.0" },
782 + { BCMA_CORE_A9JTAG, "ARM Cortex A9 JTAG" },
783 + { BCMA_CORE_DDR23, "Denali DDR2/DDR3 memory controller" },
784 + { BCMA_CORE_ROM, "ROM" },
785 + { BCMA_CORE_NAND, "NAND flash controller" },
786 + { BCMA_CORE_QSPI, "SPI flash controller" },
787 + { BCMA_CORE_CHIPCOMMON_B, "Chipcommon B" },
788 + { BCMA_CORE_ARMCA9, "ARM Cortex A9 core (ihost)" },
789 { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
790 { BCMA_CORE_ALTA, "ALTA (I2S)" },
791 { BCMA_CORE_INVALID, "Invalid" },
792 @@ -201,7 +213,7 @@ static s32 bcma_erom_get_mst_port(struct
793 return ent;
794 }
795
796 -static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
797 +static u32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
798 u32 type, u8 port)
799 {
800 u32 addrl, addrh, sizel, sizeh = 0;
801 @@ -213,7 +225,7 @@ static s32 bcma_erom_get_addr_desc(struc
802 ((ent & SCAN_ADDR_TYPE) != type) ||
803 (((ent & SCAN_ADDR_PORT) >> SCAN_ADDR_PORT_SHIFT) != port)) {
804 bcma_erom_push_ent(eromptr);
805 - return -EINVAL;
806 + return (u32)-EINVAL;
807 }
808
809 addrl = ent & SCAN_ADDR_ADDR;
810 @@ -257,11 +269,13 @@ static struct bcma_device *bcma_find_cor
811 return NULL;
812 }
813
814 +#define IS_ERR_VALUE_U32(x) ((x) >= (u32)-MAX_ERRNO)
815 +
816 static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
817 struct bcma_device_id *match, int core_num,
818 struct bcma_device *core)
819 {
820 - s32 tmp;
821 + u32 tmp;
822 u8 i, j;
823 s32 cia, cib;
824 u8 ports[2], wrappers[2];
825 @@ -339,11 +353,11 @@ static int bcma_get_next_core(struct bcm
826 * the main register space for the core
827 */
828 tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0);
829 - if (tmp <= 0) {
830 + if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) {
831 /* Try again to see if it is a bridge */
832 tmp = bcma_erom_get_addr_desc(bus, eromptr,
833 SCAN_ADDR_TYPE_BRIDGE, 0);
834 - if (tmp <= 0) {
835 + if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) {
836 return -EILSEQ;
837 } else {
838 bcma_info(bus, "Bridge found\n");
839 @@ -357,7 +371,7 @@ static int bcma_get_next_core(struct bcm
840 for (j = 0; ; j++) {
841 tmp = bcma_erom_get_addr_desc(bus, eromptr,
842 SCAN_ADDR_TYPE_SLAVE, i);
843 - if (tmp < 0) {
844 + if (IS_ERR_VALUE_U32(tmp)) {
845 /* no more entries for port _i_ */
846 /* pr_debug("erom: slave port %d "
847 * "has %d descriptors\n", i, j); */
848 @@ -374,7 +388,7 @@ static int bcma_get_next_core(struct bcm
849 for (j = 0; ; j++) {
850 tmp = bcma_erom_get_addr_desc(bus, eromptr,
851 SCAN_ADDR_TYPE_MWRAP, i);
852 - if (tmp < 0) {
853 + if (IS_ERR_VALUE_U32(tmp)) {
854 /* no more entries for port _i_ */
855 /* pr_debug("erom: master wrapper %d "
856 * "has %d descriptors\n", i, j); */
857 @@ -392,7 +406,7 @@ static int bcma_get_next_core(struct bcm
858 for (j = 0; ; j++) {
859 tmp = bcma_erom_get_addr_desc(bus, eromptr,
860 SCAN_ADDR_TYPE_SWRAP, i + hack);
861 - if (tmp < 0) {
862 + if (IS_ERR_VALUE_U32(tmp)) {
863 /* no more entries for port _i_ */
864 /* pr_debug("erom: master wrapper %d "
865 * has %d descriptors\n", i, j); */
866 --- a/drivers/bcma/sprom.c
867 +++ b/drivers/bcma/sprom.c
868 @@ -72,12 +72,12 @@ fail:
869 * R/W ops.
870 **************************************************/
871
872 -static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom)
873 +static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom,
874 + size_t words)
875 {
876 int i;
877 - for (i = 0; i < SSB_SPROMSIZE_WORDS_R4; i++)
878 - sprom[i] = bcma_read16(bus->drv_cc.core,
879 - offset + (i * 2));
880 + for (i = 0; i < words; i++)
881 + sprom[i] = bcma_read16(bus->drv_cc.core, offset + (i * 2));
882 }
883
884 /**************************************************
885 @@ -124,29 +124,29 @@ static inline u8 bcma_crc8(u8 crc, u8 da
886 return t[crc ^ data];
887 }
888
889 -static u8 bcma_sprom_crc(const u16 *sprom)
890 +static u8 bcma_sprom_crc(const u16 *sprom, size_t words)
891 {
892 int word;
893 u8 crc = 0xFF;
894
895 - for (word = 0; word < SSB_SPROMSIZE_WORDS_R4 - 1; word++) {
896 + for (word = 0; word < words - 1; word++) {
897 crc = bcma_crc8(crc, sprom[word] & 0x00FF);
898 crc = bcma_crc8(crc, (sprom[word] & 0xFF00) >> 8);
899 }
900 - crc = bcma_crc8(crc, sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & 0x00FF);
901 + crc = bcma_crc8(crc, sprom[words - 1] & 0x00FF);
902 crc ^= 0xFF;
903
904 return crc;
905 }
906
907 -static int bcma_sprom_check_crc(const u16 *sprom)
908 +static int bcma_sprom_check_crc(const u16 *sprom, size_t words)
909 {
910 u8 crc;
911 u8 expected_crc;
912 u16 tmp;
913
914 - crc = bcma_sprom_crc(sprom);
915 - tmp = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_CRC;
916 + crc = bcma_sprom_crc(sprom, words);
917 + tmp = sprom[words - 1] & SSB_SPROM_REVISION_CRC;
918 expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
919 if (crc != expected_crc)
920 return -EPROTO;
921 @@ -154,21 +154,25 @@ static int bcma_sprom_check_crc(const u1
922 return 0;
923 }
924
925 -static int bcma_sprom_valid(const u16 *sprom)
926 +static int bcma_sprom_valid(struct bcma_bus *bus, const u16 *sprom,
927 + size_t words)
928 {
929 u16 revision;
930 int err;
931
932 - err = bcma_sprom_check_crc(sprom);
933 + err = bcma_sprom_check_crc(sprom, words);
934 if (err)
935 return err;
936
937 - revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_REV;
938 - if (revision != 8 && revision != 9) {
939 + revision = sprom[words - 1] & SSB_SPROM_REVISION_REV;
940 + if (revision != 8 && revision != 9 && revision != 10) {
941 pr_err("Unsupported SPROM revision: %d\n", revision);
942 return -ENOENT;
943 }
944
945 + bus->sprom.revision = revision;
946 + bcma_debug(bus, "Found SPROM revision %d\n", revision);
947 +
948 return 0;
949 }
950
951 @@ -208,9 +212,6 @@ static void bcma_sprom_extract_r8(struct
952 BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
953 ARRAY_SIZE(bus->sprom.core_pwr_info));
954
955 - bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
956 - SSB_SPROM_REVISION_REV;
957 -
958 for (i = 0; i < 3; i++) {
959 v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
960 *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
961 @@ -502,7 +503,7 @@ static bool bcma_sprom_onchip_available(
962 case BCMA_CHIP_ID_BCM4331:
963 present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
964 break;
965 -
966 + case BCMA_CHIP_ID_BCM43142:
967 case BCMA_CHIP_ID_BCM43224:
968 case BCMA_CHIP_ID_BCM43225:
969 /* for these chips OTP is always available */
970 @@ -550,7 +551,9 @@ int bcma_sprom_get(struct bcma_bus *bus)
971 {
972 u16 offset = BCMA_CC_SPROM;
973 u16 *sprom;
974 - int err = 0;
975 + size_t sprom_sizes[] = { SSB_SPROMSIZE_WORDS_R4,
976 + SSB_SPROMSIZE_WORDS_R10, };
977 + int i, err = 0;
978
979 if (!bus->drv_cc.core)
980 return -EOPNOTSUPP;
981 @@ -579,32 +582,37 @@ int bcma_sprom_get(struct bcma_bus *bus)
982 }
983 }
984
985 - sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
986 - GFP_KERNEL);
987 - if (!sprom)
988 - return -ENOMEM;
989 -
990 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
991 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
992 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
993
994 bcma_debug(bus, "SPROM offset 0x%x\n", offset);
995 - bcma_sprom_read(bus, offset, sprom);
996 + for (i = 0; i < ARRAY_SIZE(sprom_sizes); i++) {
997 + size_t words = sprom_sizes[i];
998 +
999 + sprom = kcalloc(words, sizeof(u16), GFP_KERNEL);
1000 + if (!sprom)
1001 + return -ENOMEM;
1002 +
1003 + bcma_sprom_read(bus, offset, sprom, words);
1004 + err = bcma_sprom_valid(bus, sprom, words);
1005 + if (!err)
1006 + break;
1007 +
1008 + kfree(sprom);
1009 + }
1010
1011 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
1012 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
1013 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
1014
1015 - err = bcma_sprom_valid(sprom);
1016 if (err) {
1017 - bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
1018 + bcma_warn(bus, "Invalid SPROM read from the PCIe card, trying to use fallback SPROM\n");
1019 err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
1020 - goto out;
1021 + } else {
1022 + bcma_sprom_extract_r8(bus, sprom);
1023 + kfree(sprom);
1024 }
1025
1026 - bcma_sprom_extract_r8(bus, sprom);
1027 -
1028 -out:
1029 - kfree(sprom);
1030 return err;
1031 }
1032 --- a/include/linux/bcma/bcma.h
1033 +++ b/include/linux/bcma/bcma.h
1034 @@ -72,7 +72,19 @@ struct bcma_host_ops {
1035 /* Core-ID values. */
1036 #define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
1037 #define BCMA_CORE_4706_CHIPCOMMON 0x500
1038 +#define BCMA_CORE_PCIEG2 0x501
1039 +#define BCMA_CORE_DMA 0x502
1040 +#define BCMA_CORE_SDIO3 0x503
1041 +#define BCMA_CORE_USB20 0x504
1042 +#define BCMA_CORE_USB30 0x505
1043 +#define BCMA_CORE_A9JTAG 0x506
1044 +#define BCMA_CORE_DDR23 0x507
1045 +#define BCMA_CORE_ROM 0x508
1046 +#define BCMA_CORE_NAND 0x509
1047 +#define BCMA_CORE_QSPI 0x50A
1048 +#define BCMA_CORE_CHIPCOMMON_B 0x50B
1049 #define BCMA_CORE_4706_SOC_RAM 0x50E
1050 +#define BCMA_CORE_ARMCA9 0x510
1051 #define BCMA_CORE_4706_MAC_GBIT 0x52D
1052 #define BCMA_CORE_AMEMC 0x52E /* DDR1/2 memory controller core */
1053 #define BCMA_CORE_ALTA 0x534 /* I2S core */
1054 @@ -144,6 +156,7 @@ struct bcma_host_ops {
1055
1056 /* Chip IDs of PCIe devices */
1057 #define BCMA_CHIP_ID_BCM4313 0x4313
1058 +#define BCMA_CHIP_ID_BCM43142 43142
1059 #define BCMA_CHIP_ID_BCM43224 43224
1060 #define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
1061 #define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
1062 @@ -176,6 +189,11 @@ struct bcma_host_ops {
1063 #define BCMA_PKG_ID_BCM5357 11
1064 #define BCMA_CHIP_ID_BCM53572 53572
1065 #define BCMA_PKG_ID_BCM47188 9
1066 +#define BCMA_CHIP_ID_BCM4707 53010
1067 +#define BCMA_PKG_ID_BCM4707 1
1068 +#define BCMA_PKG_ID_BCM4708 2
1069 +#define BCMA_PKG_ID_BCM4709 0
1070 +#define BCMA_CHIP_ID_BCM53018 53018
1071
1072 /* Board types (on PCI usually equals to the subsystem dev id) */
1073 /* BCM4313 */
1074 @@ -400,7 +418,14 @@ static inline void bcma_maskset16(struct
1075 bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
1076 }
1077
1078 -extern struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid);
1079 +extern struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
1080 + u8 unit);
1081 +static inline struct bcma_device *bcma_find_core(struct bcma_bus *bus,
1082 + u16 coreid)
1083 +{
1084 + return bcma_find_core_unit(bus, coreid, 0);
1085 +}
1086 +
1087 extern bool bcma_core_is_enabled(struct bcma_device *core);
1088 extern void bcma_core_disable(struct bcma_device *core, u32 flags);
1089 extern int bcma_core_enable(struct bcma_device *core, u32 flags);
1090 --- a/include/linux/bcma/bcma_driver_chipcommon.h
1091 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
1092 @@ -330,6 +330,8 @@
1093 #define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
1094 #define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
1095 #define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
1096 +#define BCMA_CC_PMU_STAT_EXT_LPO_AVAIL 0x00000100
1097 +#define BCMA_CC_PMU_STAT_WDRESET 0x00000080
1098 #define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
1099 #define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
1100 #define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
1101 @@ -355,6 +357,11 @@
1102 #define BCMA_CC_REGCTL_DATA 0x065C
1103 #define BCMA_CC_PLLCTL_ADDR 0x0660
1104 #define BCMA_CC_PLLCTL_DATA 0x0664
1105 +#define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
1106 +#define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */
1107 +#define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF
1108 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_MASK 0x80000000
1109 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT 31
1110 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
1111 /* NAND flash MLC controller registers (corerev >= 38) */
1112 #define BCMA_CC_NAND_REVISION 0x0C00
1113 @@ -435,6 +442,23 @@
1114 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
1115 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
1116
1117 +/* PMU rev 15 */
1118 +#define BCMA_CC_PMU15_PLL_PLLCTL0 0
1119 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_MASK 0x00000003
1120 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_SHIFT 0
1121 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC
1122 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT 2
1123 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000
1124 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_SHIFT 22
1125 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_MASK 0x07000000
1126 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_SHIFT 24
1127 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000
1128 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_SHIFT 27
1129 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_MASK 0x40000000
1130 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_SHIFT 30
1131 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000
1132 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_SHIFT 31
1133 +
1134 /* ALP clock on pre-PMU chips */
1135 #define BCMA_CC_PMU_ALP_CLOCK 20000000
1136 /* HT clock for systems with PMU-enabled chipcommon */
1137 @@ -507,6 +531,37 @@
1138 #define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
1139 #define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
1140
1141 +#define BCMA_RES_4314_LPLDO_PU BIT(0)
1142 +#define BCMA_RES_4314_PMU_SLEEP_DIS BIT(1)
1143 +#define BCMA_RES_4314_PMU_BG_PU BIT(2)
1144 +#define BCMA_RES_4314_CBUCK_LPOM_PU BIT(3)
1145 +#define BCMA_RES_4314_CBUCK_PFM_PU BIT(4)
1146 +#define BCMA_RES_4314_CLDO_PU BIT(5)
1147 +#define BCMA_RES_4314_LPLDO2_LVM BIT(6)
1148 +#define BCMA_RES_4314_WL_PMU_PU BIT(7)
1149 +#define BCMA_RES_4314_LNLDO_PU BIT(8)
1150 +#define BCMA_RES_4314_LDO3P3_PU BIT(9)
1151 +#define BCMA_RES_4314_OTP_PU BIT(10)
1152 +#define BCMA_RES_4314_XTAL_PU BIT(11)
1153 +#define BCMA_RES_4314_WL_PWRSW_PU BIT(12)
1154 +#define BCMA_RES_4314_LQ_AVAIL BIT(13)
1155 +#define BCMA_RES_4314_LOGIC_RET BIT(14)
1156 +#define BCMA_RES_4314_MEM_SLEEP BIT(15)
1157 +#define BCMA_RES_4314_MACPHY_RET BIT(16)
1158 +#define BCMA_RES_4314_WL_CORE_READY BIT(17)
1159 +#define BCMA_RES_4314_ILP_REQ BIT(18)
1160 +#define BCMA_RES_4314_ALP_AVAIL BIT(19)
1161 +#define BCMA_RES_4314_MISC_PWRSW_PU BIT(20)
1162 +#define BCMA_RES_4314_SYNTH_PWRSW_PU BIT(21)
1163 +#define BCMA_RES_4314_RX_PWRSW_PU BIT(22)
1164 +#define BCMA_RES_4314_RADIO_PU BIT(23)
1165 +#define BCMA_RES_4314_VCO_LDO_PU BIT(24)
1166 +#define BCMA_RES_4314_AFE_LDO_PU BIT(25)
1167 +#define BCMA_RES_4314_RX_LDO_PU BIT(26)
1168 +#define BCMA_RES_4314_TX_LDO_PU BIT(27)
1169 +#define BCMA_RES_4314_HT_AVAIL BIT(28)
1170 +#define BCMA_RES_4314_MACPHY_CLK_AVAIL BIT(29)
1171 +
1172 /* Data for the PMU, if available.
1173 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
1174 */
1175 @@ -585,6 +640,7 @@ struct bcma_drv_cc {
1176 spinlock_t gpio_lock;
1177 #ifdef CONFIG_BCMA_DRIVER_GPIO
1178 struct gpio_chip gpio;
1179 + struct irq_domain *irq_domain;
1180 #endif
1181 };
1182
1183 --- a/include/linux/bcma/bcma_driver_pci.h
1184 +++ b/include/linux/bcma/bcma_driver_pci.h
1185 @@ -181,10 +181,31 @@ struct pci_dev;
1186
1187 #define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8
1188
1189 +#define BCMA_CORE_PCI_
1190 +
1191 +/* MDIO devices (SERDES modules) */
1192 +#define BCMA_CORE_PCI_MDIO_IEEE0 0x000
1193 +#define BCMA_CORE_PCI_MDIO_IEEE1 0x001
1194 +#define BCMA_CORE_PCI_MDIO_BLK0 0x800
1195 +#define BCMA_CORE_PCI_MDIO_BLK1 0x801
1196 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT0 0x16
1197 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT1 0x17
1198 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT2 0x18
1199 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT3 0x19
1200 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT4 0x1A
1201 +#define BCMA_CORE_PCI_MDIO_BLK2 0x802
1202 +#define BCMA_CORE_PCI_MDIO_BLK3 0x803
1203 +#define BCMA_CORE_PCI_MDIO_BLK4 0x804
1204 +#define BCMA_CORE_PCI_MDIO_TXPLL 0x808 /* TXPLL register block idx */
1205 +#define BCMA_CORE_PCI_MDIO_TXCTRL0 0x820
1206 +#define BCMA_CORE_PCI_MDIO_SERDESID 0x831
1207 +#define BCMA_CORE_PCI_MDIO_RXCTRL0 0x840
1208 +
1209 /* PCIE Root Capability Register bits (Host mode only) */
1210 #define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
1211
1212 struct bcma_drv_pci;
1213 +struct bcma_bus;
1214
1215 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
1216 struct bcma_drv_pci_host {
1217 @@ -219,7 +240,9 @@ struct bcma_drv_pci {
1218 extern void bcma_core_pci_init(struct bcma_drv_pci *pc);
1219 extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
1220 struct bcma_device *core, bool enable);
1221 -extern void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend);
1222 +extern void bcma_core_pci_up(struct bcma_bus *bus);
1223 +extern void bcma_core_pci_down(struct bcma_bus *bus);
1224 +extern void bcma_core_pci_power_save(struct bcma_bus *bus, bool up);
1225
1226 extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
1227 extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
1228 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
1229 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
1230 @@ -679,27 +679,6 @@ bool ai_clkctl_cc(struct si_pub *sih, en
1231 return mode == BCMA_CLKMODE_FAST;
1232 }
1233
1234 -void ai_pci_up(struct si_pub *sih)
1235 -{
1236 - struct si_info *sii;
1237 -
1238 - sii = container_of(sih, struct si_info, pub);
1239 -
1240 - if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
1241 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], true);
1242 -}
1243 -
1244 -/* Unconfigure and/or apply various WARs when going down */
1245 -void ai_pci_down(struct si_pub *sih)
1246 -{
1247 - struct si_info *sii;
1248 -
1249 - sii = container_of(sih, struct si_info, pub);
1250 -
1251 - if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
1252 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], false);
1253 -}
1254 -
1255 /* Enable BT-COEX & Ex-PA for 4313 */
1256 void ai_epa_4313war(struct si_pub *sih)
1257 {
1258 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
1259 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
1260 @@ -183,9 +183,6 @@ extern u16 ai_clkctl_fast_pwrup_delay(st
1261 extern bool ai_clkctl_cc(struct si_pub *sih, enum bcma_clkmode mode);
1262 extern bool ai_deviceremoved(struct si_pub *sih);
1263
1264 -extern void ai_pci_down(struct si_pub *sih);
1265 -extern void ai_pci_up(struct si_pub *sih);
1266 -
1267 /* Enable Ex-PA for 4313 */
1268 extern void ai_epa_4313war(struct si_pub *sih);
1269
1270 --- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
1271 +++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
1272 @@ -4667,7 +4667,7 @@ static int brcms_b_attach(struct brcms_c
1273 brcms_c_coredisable(wlc_hw);
1274
1275 /* Match driver "down" state */
1276 - ai_pci_down(wlc_hw->sih);
1277 + bcma_core_pci_down(wlc_hw->d11core->bus);
1278
1279 /* turn off pll and xtal to match driver "down" state */
1280 brcms_b_xtal(wlc_hw, OFF);
1281 @@ -5010,12 +5010,12 @@ static int brcms_b_up_prep(struct brcms_
1282 */
1283 if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
1284 /* put SB PCI in down state again */
1285 - ai_pci_down(wlc_hw->sih);
1286 + bcma_core_pci_down(wlc_hw->d11core->bus);
1287 brcms_b_xtal(wlc_hw, OFF);
1288 return -ENOMEDIUM;
1289 }
1290
1291 - ai_pci_up(wlc_hw->sih);
1292 + bcma_core_pci_up(wlc_hw->d11core->bus);
1293
1294 /* reset the d11 core */
1295 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
1296 @@ -5212,7 +5212,7 @@ static int brcms_b_down_finish(struct br
1297
1298 /* turn off primary xtal and pll */
1299 if (!wlc_hw->noreset) {
1300 - ai_pci_down(wlc_hw->sih);
1301 + bcma_core_pci_down(wlc_hw->d11core->bus);
1302 brcms_b_xtal(wlc_hw, OFF);
1303 }
1304 }
OpenWrt Source Repository