target/linux/generic/patches-3.13/025-bcma_backport.patch

   1 --- a/drivers/bcma/Kconfig
   2 +++ b/drivers/bcma/Kconfig
   3 @@ -75,6 +75,7 @@ config BCMA_DRIVER_GMAC_CMN
   4  config BCMA_DRIVER_GPIO
   5         bool "BCMA GPIO driver"
   6         depends on BCMA && GPIOLIB
   7 +       select IRQ_DOMAIN if BCMA_HOST_SOC
   8         help
   9           Driver to provide access to the GPIO pins of the bcma bus.
  10
  11 --- a/drivers/bcma/Makefile
  12 +++ b/drivers/bcma/Makefile
  13 @@ -3,6 +3,7 @@ bcma-y                                  += driver_chipcommon.o driver
  14  bcma-$(CONFIG_BCMA_SFLASH)             += driver_chipcommon_sflash.o
  15  bcma-$(CONFIG_BCMA_NFLASH)             += driver_chipcommon_nflash.o
  16  bcma-y                                 += driver_pci.o
  17 +bcma-y                                 += driver_pcie2.o
  18  bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE)        += driver_pci_host.o
  19  bcma-$(CONFIG_BCMA_DRIVER_MIPS)                += driver_mips.o
  20  bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN)    += driver_gmac_cmn.o
  21 --- a/drivers/bcma/bcma_private.h
  22 +++ b/drivers/bcma/bcma_private.h
  23 @@ -33,8 +33,6 @@ int __init bcma_bus_early_register(struc
  24  int bcma_bus_suspend(struct bcma_bus *bus);
  25  int bcma_bus_resume(struct bcma_bus *bus);
  26  #endif
  27 -struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
  28 -                                       u8 unit);
  29
  30  /* scan.c */
  31  int bcma_bus_scan(struct bcma_bus *bus);
  32 --- a/drivers/bcma/driver_chipcommon_pmu.c
  33 +++ b/drivers/bcma/driver_chipcommon_pmu.c
  34 @@ -603,6 +603,8 @@ void bcma_pmu_spuravoid_pllupdate(struct
  35                 tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
  36                 break;
  37
  38 +       case BCMA_CHIP_ID_BCM43131:
  39 +       case BCMA_CHIP_ID_BCM43217:
  40         case BCMA_CHIP_ID_BCM43227:
  41         case BCMA_CHIP_ID_BCM43228:
  42         case BCMA_CHIP_ID_BCM43428:
  43 --- a/drivers/bcma/driver_chipcommon_sflash.c
  44 +++ b/drivers/bcma/driver_chipcommon_sflash.c
  45 @@ -38,7 +38,7 @@ static const struct bcma_sflash_tbl_e bc
  46         { "M25P32", 0x15, 0x10000, 64, },
  47         { "M25P64", 0x16, 0x10000, 128, },
  48         { "M25FL128", 0x17, 0x10000, 256, },
  49 -       { 0 },
  50 +       { NULL },
  51  };
  52
  53  static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
  54 @@ -56,7 +56,7 @@ static const struct bcma_sflash_tbl_e bc
  55         { "SST25VF016", 0x41, 0x1000, 512, },
  56         { "SST25VF032", 0x4a, 0x1000, 1024, },
  57         { "SST25VF064", 0x4b, 0x1000, 2048, },
  58 -       { 0 },
  59 +       { NULL },
  60  };
  61
  62  static const struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
  63 @@ -67,7 +67,7 @@ static const struct bcma_sflash_tbl_e bc
  64         { "AT45DB161", 0x2c, 512, 4096, },
  65         { "AT45DB321", 0x34, 512, 8192, },
  66         { "AT45DB642", 0x3c, 1024, 8192, },
  67 -       { 0 },
  68 +       { NULL },
  69  };
  70
  71  static void bcma_sflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
  72 --- a/drivers/bcma/driver_gpio.c
  73 +++ b/drivers/bcma/driver_gpio.c
  74 @@ -9,6 +9,9 @@
  75   */
  76
  77  #include <linux/gpio.h>
  78 +#include <linux/irq.h>
  79 +#include <linux/interrupt.h>
  80 +#include <linux/irqdomain.h>
  81  #include <linux/export.h>
  82  #include <linux/bcma/bcma.h>
  83
  84 @@ -73,19 +76,136 @@ static void bcma_gpio_free(struct gpio_c
  85         bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
  86  }
  87
  88 +#if IS_BUILTIN(CONFIG_BCMA_HOST_SOC)
  89  static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
  90  {
  91         struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
  92
  93         if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
  94 -               return bcma_core_irq(cc->core);
  95 +               return irq_find_mapping(cc->irq_domain, gpio);
  96         else
  97                 return -EINVAL;
  98  }
  99
 100 +static void bcma_gpio_irq_unmask(struct irq_data *d)
 101 +{
 102 +       struct bcma_drv_cc *cc = irq_data_get_irq_chip_data(d);
 103 +       int gpio = irqd_to_hwirq(d);
 104 +       u32 val = bcma_chipco_gpio_in(cc, BIT(gpio));
 105 +
 106 +       bcma_chipco_gpio_polarity(cc, BIT(gpio), val);
 107 +       bcma_chipco_gpio_intmask(cc, BIT(gpio), BIT(gpio));
 108 +}
 109 +
 110 +static void bcma_gpio_irq_mask(struct irq_data *d)
 111 +{
 112 +       struct bcma_drv_cc *cc = irq_data_get_irq_chip_data(d);
 113 +       int gpio = irqd_to_hwirq(d);
 114 +
 115 +       bcma_chipco_gpio_intmask(cc, BIT(gpio), 0);
 116 +}
 117 +
 118 +static struct irq_chip bcma_gpio_irq_chip = {
 119 +       .name           = "BCMA-GPIO",
 120 +       .irq_mask       = bcma_gpio_irq_mask,
 121 +       .irq_unmask     = bcma_gpio_irq_unmask,
 122 +};
 123 +
 124 +static irqreturn_t bcma_gpio_irq_handler(int irq, void *dev_id)
 125 +{
 126 +       struct bcma_drv_cc *cc = dev_id;
 127 +       u32 val = bcma_cc_read32(cc, BCMA_CC_GPIOIN);
 128 +       u32 mask = bcma_cc_read32(cc, BCMA_CC_GPIOIRQ);
 129 +       u32 pol = bcma_cc_read32(cc, BCMA_CC_GPIOPOL);
 130 +       unsigned long irqs = (val ^ pol) & mask;
 131 +       int gpio;
 132 +
 133 +       if (!irqs)
 134 +               return IRQ_NONE;
 135 +
 136 +       for_each_set_bit(gpio, &irqs, cc->gpio.ngpio)
 137 +               generic_handle_irq(bcma_gpio_to_irq(&cc->gpio, gpio));
 138 +       bcma_chipco_gpio_polarity(cc, irqs, val & irqs);
 139 +
 140 +       return IRQ_HANDLED;
 141 +}
 142 +
 143 +static int bcma_gpio_irq_domain_init(struct bcma_drv_cc *cc)
 144 +{
 145 +       struct gpio_chip *chip = &cc->gpio;
 146 +       int gpio, hwirq, err;
 147 +
 148 +       if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
 149 +               return 0;
 150 +
 151 +       cc->irq_domain = irq_domain_add_linear(NULL, chip->ngpio,
 152 +                                              &irq_domain_simple_ops, cc);
 153 +       if (!cc->irq_domain) {
 154 +               err = -ENODEV;
 155 +               goto err_irq_domain;
 156 +       }
 157 +       for (gpio = 0; gpio < chip->ngpio; gpio++) {
 158 +               int irq = irq_create_mapping(cc->irq_domain, gpio);
 159 +
 160 +               irq_set_chip_data(irq, cc);
 161 +               irq_set_chip_and_handler(irq, &bcma_gpio_irq_chip,
 162 +                                        handle_simple_irq);
 163 +       }
 164 +
 165 +       hwirq = bcma_core_irq(cc->core);
 166 +       err = request_irq(hwirq, bcma_gpio_irq_handler, IRQF_SHARED, "gpio",
 167 +                         cc);
 168 +       if (err)
 169 +               goto err_req_irq;
 170 +
 171 +       bcma_chipco_gpio_intmask(cc, ~0, 0);
 172 +       bcma_cc_set32(cc, BCMA_CC_IRQMASK, BCMA_CC_IRQ_GPIO);
 173 +
 174 +       return 0;
 175 +
 176 +err_req_irq:
 177 +       for (gpio = 0; gpio < chip->ngpio; gpio++) {
 178 +               int irq = irq_find_mapping(cc->irq_domain, gpio);
 179 +
 180 +               irq_dispose_mapping(irq);
 181 +       }
 182 +       irq_domain_remove(cc->irq_domain);
 183 +err_irq_domain:
 184 +       return err;
 185 +}
 186 +
 187 +static void bcma_gpio_irq_domain_exit(struct bcma_drv_cc *cc)
 188 +{
 189 +       struct gpio_chip *chip = &cc->gpio;
 190 +       int gpio;
 191 +
 192 +       if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
 193 +               return;
 194 +
 195 +       bcma_cc_mask32(cc, BCMA_CC_IRQMASK, ~BCMA_CC_IRQ_GPIO);
 196 +       free_irq(bcma_core_irq(cc->core), cc);
 197 +       for (gpio = 0; gpio < chip->ngpio; gpio++) {
 198 +               int irq = irq_find_mapping(cc->irq_domain, gpio);
 199 +
 200 +               irq_dispose_mapping(irq);
 201 +       }
 202 +       irq_domain_remove(cc->irq_domain);
 203 +}
 204 +#else
 205 +static int bcma_gpio_irq_domain_init(struct bcma_drv_cc *cc)
 206 +{
 207 +       return 0;
 208 +}
 209 +
 210 +static void bcma_gpio_irq_domain_exit(struct bcma_drv_cc *cc)
 211 +{
 212 +}
 213 +#endif
 214 +
 215  int bcma_gpio_init(struct bcma_drv_cc *cc)
 216  {
 217         struct gpio_chip *chip = &cc->gpio;
 218 +       int err;
 219
 220         chip->label             = "bcma_gpio";
 221         chip->owner             = THIS_MODULE;
 222 @@ -95,8 +215,18 @@ int bcma_gpio_init(struct bcma_drv_cc *c
 223         chip->set               = bcma_gpio_set_value;
 224         chip->direction_input   = bcma_gpio_direction_input;
 225         chip->direction_output  = bcma_gpio_direction_output;
 226 +#if IS_BUILTIN(CONFIG_BCMA_HOST_SOC)
 227         chip->to_irq            = bcma_gpio_to_irq;
 228 -       chip->ngpio             = 16;
 229 +#endif
 230 +       switch (cc->core->bus->chipinfo.id) {
 231 +       case BCMA_CHIP_ID_BCM5357:
 232 +       case BCMA_CHIP_ID_BCM53572:
 233 +               chip->ngpio     = 32;
 234 +               break;
 235 +       default:
 236 +               chip->ngpio     = 16;
 237 +       }
 238 +
 239         /* There is just one SoC in one device and its GPIO addresses should be
 240          * deterministic to address them more easily. The other buses could get
 241          * a random base number. */
 242 @@ -105,10 +235,21 @@ int bcma_gpio_init(struct bcma_drv_cc *c
 243         else
 244                 chip->base              = -1;
 245
 246 -       return gpiochip_add(chip);
 247 +       err = bcma_gpio_irq_domain_init(cc);
 248 +       if (err)
 249 +               return err;
 250 +
 251 +       err = gpiochip_add(chip);
 252 +       if (err) {
 253 +               bcma_gpio_irq_domain_exit(cc);
 254 +               return err;
 255 +       }
 256 +
 257 +       return 0;
 258  }
 259
 260  int bcma_gpio_unregister(struct bcma_drv_cc *cc)
 261  {
 262 +       bcma_gpio_irq_domain_exit(cc);
 263         return gpiochip_remove(&cc->gpio);
 264  }
 265 --- /dev/null
 266 +++ b/drivers/bcma/driver_pcie2.c
 267 @@ -0,0 +1,175 @@
 268 +/*
 269 + * Broadcom specific AMBA
 270 + * PCIe Gen 2 Core
 271 + *
 272 + * Copyright 2014, Broadcom Corporation
 273 + * Copyright 2014, Rafał Miłecki <zajec5@gmail.com>
 274 + *
 275 + * Licensed under the GNU/GPL. See COPYING for details.
 276 + */
 277 +
 278 +#include "bcma_private.h"
 279 +#include <linux/bcma/bcma.h>
 280 +
 281 +/**************************************************
 282 + * R/W ops.
 283 + **************************************************/
 284 +
 285 +#if 0
 286 +static u32 bcma_core_pcie2_cfg_read(struct bcma_drv_pcie2 *pcie2, u32 addr)
 287 +{
 288 +       pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
 289 +       pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR);
 290 +       return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
 291 +}
 292 +#endif
 293 +
 294 +static void bcma_core_pcie2_cfg_write(struct bcma_drv_pcie2 *pcie2, u32 addr,
 295 +                                     u32 val)
 296 +{
 297 +       pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
 298 +       pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, val);
 299 +}
 300 +
 301 +/**************************************************
 302 + * Init.
 303 + **************************************************/
 304 +
 305 +static u32 bcma_core_pcie2_war_delay_perst_enab(struct bcma_drv_pcie2 *pcie2,
 306 +                                               bool enable)
 307 +{
 308 +       u32 val;
 309 +
 310 +       /* restore back to default */
 311 +       val = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
 312 +       val |= PCIE2_CLKC_DLYPERST;
 313 +       val &= ~PCIE2_CLKC_DISSPROMLD;
 314 +       if (enable) {
 315 +               val &= ~PCIE2_CLKC_DLYPERST;
 316 +               val |= PCIE2_CLKC_DISSPROMLD;
 317 +       }
 318 +       pcie2_write32(pcie2, (BCMA_CORE_PCIE2_CLK_CONTROL), val);
 319 +       /* flush */
 320 +       return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
 321 +}
 322 +
 323 +static void bcma_core_pcie2_set_ltr_vals(struct bcma_drv_pcie2 *pcie2)
 324 +{
 325 +       /* LTR0 */
 326 +       pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x844);
 327 +       pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x883c883c);
 328 +       /* LTR1 */
 329 +       pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x848);
 330 +       pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x88648864);
 331 +       /* LTR2 */
 332 +       pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x84C);
 333 +       pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x90039003);
 334 +}
 335 +
 336 +static void bcma_core_pcie2_hw_ltr_war(struct bcma_drv_pcie2 *pcie2)
 337 +{
 338 +       u8 core_rev = pcie2->core->id.rev;
 339 +       u32 devstsctr2;
 340 +
 341 +       if (core_rev < 2 || core_rev == 10 || core_rev > 13)
 342 +               return;
 343 +
 344 +       pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
 345 +                     PCIE2_CAP_DEVSTSCTRL2_OFFSET);
 346 +       devstsctr2 = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
 347 +       if (devstsctr2 & PCIE2_CAP_DEVSTSCTRL2_LTRENAB) {
 348 +               /* force the right LTR values */
 349 +               bcma_core_pcie2_set_ltr_vals(pcie2);
 350 +
 351 +               /* TODO:
 352 +               si_core_wrapperreg(pcie2, 3, 0x60, 0x8080, 0); */
 353 +
 354 +               /* enable the LTR */
 355 +               devstsctr2 |= PCIE2_CAP_DEVSTSCTRL2_LTRENAB;
 356 +               pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
 357 +                             PCIE2_CAP_DEVSTSCTRL2_OFFSET);
 358 +               pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, devstsctr2);
 359 +
 360 +               /* set the LTR state to be active */
 361 +               pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
 362 +                             PCIE2_LTR_ACTIVE);
 363 +               usleep_range(1000, 2000);
 364 +
 365 +               /* set the LTR state to be sleep */
 366 +               pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
 367 +                             PCIE2_LTR_SLEEP);
 368 +               usleep_range(1000, 2000);
 369 +       }
 370 +}
 371 +
 372 +static void pciedev_crwlpciegen2(struct bcma_drv_pcie2 *pcie2)
 373 +{
 374 +       u8 core_rev = pcie2->core->id.rev;
 375 +       bool pciewar160, pciewar162;
 376 +
 377 +       pciewar160 = core_rev == 7 || core_rev == 9 || core_rev == 11;
 378 +       pciewar162 = core_rev == 5 || core_rev == 7 || core_rev == 8 ||
 379 +                    core_rev == 9 || core_rev == 11;
 380 +
 381 +       if (!pciewar160 && !pciewar162)
 382 +               return;
 383 +
 384 +/* TODO */
 385 +#if 0
 386 +       pcie2_set32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL,
 387 +                   PCIE_DISABLE_L1CLK_GATING);
 388 +#if 0
 389 +       pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
 390 +                     PCIEGEN2_COE_PVT_TL_CTRL_0);
 391 +       pcie2_mask32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA,
 392 +                    ~(1 << COE_PVT_TL_CTRL_0_PM_DIS_L1_REENTRY_BIT));
 393 +#endif
 394 +#endif
 395 +}
 396 +
 397 +static void pciedev_crwlpciegen2_180(struct bcma_drv_pcie2 *pcie2)
 398 +{
 399 +       pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_PMCR_REFUP);
 400 +       pcie2_set32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x1f);
 401 +}
 402 +
 403 +static void pciedev_crwlpciegen2_182(struct bcma_drv_pcie2 *pcie2)
 404 +{
 405 +       pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_SBMBX);
 406 +       pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 1 << 0);
 407 +}
 408 +
 409 +static void pciedev_reg_pm_clk_period(struct bcma_drv_pcie2 *pcie2)
 410 +{
 411 +       struct bcma_drv_cc *drv_cc = &pcie2->core->bus->drv_cc;
 412 +       u8 core_rev = pcie2->core->id.rev;
 413 +       u32 alp_khz, pm_value;
 414 +
 415 +       if (core_rev <= 13) {
 416 +               alp_khz = bcma_pmu_get_alp_clock(drv_cc) / 1000;
 417 +               pm_value = (1000000 * 2) / alp_khz;
 418 +               pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
 419 +                             PCIE2_PVT_REG_PM_CLK_PERIOD);
 420 +               pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, pm_value);
 421 +       }
 422 +}
 423 +
 424 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2)
 425 +{
 426 +       struct bcma_chipinfo *ci = &pcie2->core->bus->chipinfo;
 427 +       u32 tmp;
 428 +
 429 +       tmp = pcie2_read32(pcie2, BCMA_CORE_PCIE2_SPROM(54));
 430 +       if ((tmp & 0xe) >> 1 == 2)
 431 +               bcma_core_pcie2_cfg_write(pcie2, 0x4e0, 0x17);
 432 +
 433 +       /* TODO: Do we need pcie_reqsize? */
 434 +
 435 +       if (ci->id == BCMA_CHIP_ID_BCM4360 && ci->rev > 3)
 436 +               bcma_core_pcie2_war_delay_perst_enab(pcie2, true);
 437 +       bcma_core_pcie2_hw_ltr_war(pcie2);
 438 +       pciedev_crwlpciegen2(pcie2);
 439 +       pciedev_reg_pm_clk_period(pcie2);
 440 +       pciedev_crwlpciegen2_180(pcie2);
 441 +       pciedev_crwlpciegen2_182(pcie2);
 442 +}
 443 --- a/drivers/bcma/host_pci.c
 444 +++ b/drivers/bcma/host_pci.c
 445 @@ -238,7 +238,6 @@ static void bcma_host_pci_remove(struct
 446         pci_release_regions(dev);
 447         pci_disable_device(dev);
 448         kfree(bus);
 449 -       pci_set_drvdata(dev, NULL);
 450  }
 451
 452  #ifdef CONFIG_PM_SLEEP
 453 @@ -270,7 +269,7 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
 454
 455  #endif /* CONFIG_PM_SLEEP */
 456
 457 -static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
 458 +static const struct pci_device_id bcma_pci_bridge_tbl[] = {
 459         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
 460         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4313) },
 461         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) },
 462 @@ -280,6 +279,8 @@ static DEFINE_PCI_DEVICE_TABLE(bcma_pci_
 463         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
 464         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
 465         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
 466 +       { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) },
 467 +       { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43aa) },
 468         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
 469         { 0, },
 470  };
 471 --- a/drivers/bcma/main.c
 472 +++ b/drivers/bcma/main.c
 473 @@ -78,18 +78,6 @@ static u16 bcma_cc_core_id(struct bcma_b
 474         return BCMA_CORE_CHIPCOMMON;
 475  }
 476
 477 -struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
 478 -{
 479 -       struct bcma_device *core;
 480 -
 481 -       list_for_each_entry(core, &bus->cores, list) {
 482 -               if (core->id.id == coreid)
 483 -                       return core;
 484 -       }
 485 -       return NULL;
 486 -}
 487 -EXPORT_SYMBOL_GPL(bcma_find_core);
 488 -
 489  struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
 490                                         u8 unit)
 491  {
 492 @@ -101,6 +89,7 @@ struct bcma_device *bcma_find_core_unit(
 493         }
 494         return NULL;
 495  }
 496 +EXPORT_SYMBOL_GPL(bcma_find_core_unit);
 497
 498  bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
 499                      int timeout)
 500 @@ -143,6 +132,7 @@ static int bcma_register_cores(struct bc
 501                 case BCMA_CORE_CHIPCOMMON:
 502                 case BCMA_CORE_PCI:
 503                 case BCMA_CORE_PCIE:
 504 +               case BCMA_CORE_PCIE2:
 505                 case BCMA_CORE_MIPS_74K:
 506                 case BCMA_CORE_4706_MAC_GBIT_COMMON:
 507                         continue;
 508 @@ -176,6 +166,7 @@ static int bcma_register_cores(struct bc
 509                         bcma_err(bus,
 510                                  "Could not register dev for core 0x%03X\n",
 511                                  core->id.id);
 512 +                       put_device(&core->dev);
 513                         continue;
 514                 }
 515                 core->dev_registered = true;
 516 @@ -291,6 +282,13 @@ int bcma_bus_register(struct bcma_bus *b
 517                 bcma_core_pci_init(&bus->drv_pci[1]);
 518         }
 519
 520 +       /* Init PCIe Gen 2 core */
 521 +       core = bcma_find_core_unit(bus, BCMA_CORE_PCIE2, 0);
 522 +       if (core) {
 523 +               bus->drv_pcie2.core = core;
 524 +               bcma_core_pcie2_init(&bus->drv_pcie2);
 525 +       }
 526 +
 527         /* Init GBIT MAC COMMON core */
 528         core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
 529         if (core) {
 530 --- a/drivers/bcma/sprom.c
 531 +++ b/drivers/bcma/sprom.c
 532 @@ -201,6 +201,23 @@ static int bcma_sprom_valid(struct bcma_
 533                 SPEX(_field[7], _offset + 14, _mask, _shift);   \
 534         } while (0)
 535
 536 +static s8 sprom_extract_antgain(const u16 *in, u16 offset, u16 mask, u16 shift)
 537 +{
 538 +       u16 v;
 539 +       u8 gain;
 540 +
 541 +       v = in[SPOFF(offset)];
 542 +       gain = (v & mask) >> shift;
 543 +       if (gain == 0xFF) {
 544 +               gain = 8; /* If unset use 2dBm */
 545 +       } else {
 546 +               /* Q5.2 Fractional part is stored in 0xC0 */
 547 +               gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
 548 +       }
 549 +
 550 +       return (s8)gain;
 551 +}
 552 +
 553  static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
 554  {
 555         u16 v, o;
 556 @@ -381,14 +398,22 @@ static void bcma_sprom_extract_r8(struct
 557         SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, ~0, 0);
 558
 559         /* Extract the antenna gain values. */
 560 -       SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
 561 -            SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
 562 -       SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
 563 -            SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
 564 -       SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
 565 -            SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
 566 -       SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
 567 -            SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
 568 +       bus->sprom.antenna_gain.a0 = sprom_extract_antgain(sprom,
 569 +                                                          SSB_SPROM8_AGAIN01,
 570 +                                                          SSB_SPROM8_AGAIN0,
 571 +                                                          SSB_SPROM8_AGAIN0_SHIFT);
 572 +       bus->sprom.antenna_gain.a1 = sprom_extract_antgain(sprom,
 573 +                                                          SSB_SPROM8_AGAIN01,
 574 +                                                          SSB_SPROM8_AGAIN1,
 575 +                                                          SSB_SPROM8_AGAIN1_SHIFT);
 576 +       bus->sprom.antenna_gain.a2 = sprom_extract_antgain(sprom,
 577 +                                                          SSB_SPROM8_AGAIN23,
 578 +                                                          SSB_SPROM8_AGAIN2,
 579 +                                                          SSB_SPROM8_AGAIN2_SHIFT);
 580 +       bus->sprom.antenna_gain.a3 = sprom_extract_antgain(sprom,
 581 +                                                          SSB_SPROM8_AGAIN23,
 582 +                                                          SSB_SPROM8_AGAIN3,
 583 +                                                          SSB_SPROM8_AGAIN3_SHIFT);
 584
 585         SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
 586              SSB_SPROM8_LEDDC_ON_SHIFT);
 587 @@ -509,6 +534,8 @@ static bool bcma_sprom_onchip_available(
 588                 /* for these chips OTP is always available */
 589                 present = true;
 590                 break;
 591 +       case BCMA_CHIP_ID_BCM43131:
 592 +       case BCMA_CHIP_ID_BCM43217:
 593         case BCMA_CHIP_ID_BCM43227:
 594         case BCMA_CHIP_ID_BCM43228:
 595         case BCMA_CHIP_ID_BCM43428:
 596 --- a/include/linux/bcma/bcma.h
 597 +++ b/include/linux/bcma/bcma.h
 598 @@ -6,6 +6,7 @@
 599
 600  #include <linux/bcma/bcma_driver_chipcommon.h>
 601  #include <linux/bcma/bcma_driver_pci.h>
 602 +#include <linux/bcma/bcma_driver_pcie2.h>
 603  #include <linux/bcma/bcma_driver_mips.h>
 604  #include <linux/bcma/bcma_driver_gmac_cmn.h>
 605  #include <linux/ssb/ssb.h> /* SPROM sharing */
 606 @@ -157,6 +158,9 @@ struct bcma_host_ops {
 607  /* Chip IDs of PCIe devices */
 608  #define BCMA_CHIP_ID_BCM4313   0x4313
 609  #define BCMA_CHIP_ID_BCM43142  43142
 610 +#define BCMA_CHIP_ID_BCM43131  43131
 611 +#define BCMA_CHIP_ID_BCM43217  43217
 612 +#define BCMA_CHIP_ID_BCM43222  43222
 613  #define BCMA_CHIP_ID_BCM43224  43224
 614  #define  BCMA_PKG_ID_BCM43224_FAB_CSM  0x8
 615  #define  BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
 616 @@ -333,6 +337,7 @@ struct bcma_bus {
 617
 618         struct bcma_drv_cc drv_cc;
 619         struct bcma_drv_pci drv_pci[2];
 620 +       struct bcma_drv_pcie2 drv_pcie2;
 621         struct bcma_drv_mips drv_mips;
 622         struct bcma_drv_gmac_cmn drv_gmac_cmn;
 623
 624 @@ -418,7 +423,14 @@ static inline void bcma_maskset16(struct
 625         bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
 626  }
 627
 628 -extern struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid);
 629 +extern struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
 630 +                                              u8 unit);
 631 +static inline struct bcma_device *bcma_find_core(struct bcma_bus *bus,
 632 +                                                u16 coreid)
 633 +{
 634 +       return bcma_find_core_unit(bus, coreid, 0);
 635 +}
 636 +
 637  extern bool bcma_core_is_enabled(struct bcma_device *core);
 638  extern void bcma_core_disable(struct bcma_device *core, u32 flags);
 639  extern int bcma_core_enable(struct bcma_device *core, u32 flags);
 640 --- a/include/linux/bcma/bcma_driver_chipcommon.h
 641 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
 642 @@ -640,6 +640,7 @@ struct bcma_drv_cc {
 643         spinlock_t gpio_lock;
 644  #ifdef CONFIG_BCMA_DRIVER_GPIO
 645         struct gpio_chip gpio;
 646 +       struct irq_domain *irq_domain;
 647  #endif
 648  };
 649
 650 --- /dev/null
 651 +++ b/include/linux/bcma/bcma_driver_pcie2.h
 652 @@ -0,0 +1,158 @@
 653 +#ifndef LINUX_BCMA_DRIVER_PCIE2_H_
 654 +#define LINUX_BCMA_DRIVER_PCIE2_H_
 655 +
 656 +#define BCMA_CORE_PCIE2_CLK_CONTROL            0x0000
 657 +#define  PCIE2_CLKC_RST_OE                     0x0001 /* When set, drives PCI_RESET out to pin */
 658 +#define  PCIE2_CLKC_RST                                0x0002 /* Value driven out to pin */
 659 +#define  PCIE2_CLKC_SPERST                     0x0004 /* SurvivePeRst */
 660 +#define  PCIE2_CLKC_DISABLE_L1CLK_GATING       0x0010
 661 +#define  PCIE2_CLKC_DLYPERST                   0x0100 /* Delay PeRst to CoE Core */
 662 +#define  PCIE2_CLKC_DISSPROMLD                 0x0200 /* DisableSpromLoadOnPerst */
 663 +#define  PCIE2_CLKC_WAKE_MODE_L2               0x1000 /* Wake on L2 */
 664 +#define BCMA_CORE_PCIE2_RC_PM_CONTROL          0x0004
 665 +#define BCMA_CORE_PCIE2_RC_PM_STATUS           0x0008
 666 +#define BCMA_CORE_PCIE2_EP_PM_CONTROL          0x000C
 667 +#define BCMA_CORE_PCIE2_EP_PM_STATUS           0x0010
 668 +#define BCMA_CORE_PCIE2_EP_LTR_CONTROL         0x0014
 669 +#define BCMA_CORE_PCIE2_EP_LTR_STATUS          0x0018
 670 +#define BCMA_CORE_PCIE2_EP_OBFF_STATUS         0x001C
 671 +#define BCMA_CORE_PCIE2_PCIE_ERR_STATUS                0x0020
 672 +#define BCMA_CORE_PCIE2_RC_AXI_CONFIG          0x0100
 673 +#define BCMA_CORE_PCIE2_EP_AXI_CONFIG          0x0104
 674 +#define BCMA_CORE_PCIE2_RXDEBUG_STATUS0                0x0108
 675 +#define BCMA_CORE_PCIE2_RXDEBUG_CONTROL0       0x010C
 676 +#define BCMA_CORE_PCIE2_CONFIGINDADDR          0x0120
 677 +#define BCMA_CORE_PCIE2_CONFIGINDDATA          0x0124
 678 +#define BCMA_CORE_PCIE2_MDIOCONTROL            0x0128
 679 +#define BCMA_CORE_PCIE2_MDIOWRDATA             0x012C
 680 +#define BCMA_CORE_PCIE2_MDIORDDATA             0x0130
 681 +#define BCMA_CORE_PCIE2_DATAINTF               0x0180
 682 +#define BCMA_CORE_PCIE2_D2H_INTRLAZY_0         0x0188
 683 +#define BCMA_CORE_PCIE2_H2D_INTRLAZY_0         0x018c
 684 +#define BCMA_CORE_PCIE2_H2D_INTSTAT_0          0x0190
 685 +#define BCMA_CORE_PCIE2_H2D_INTMASK_0          0x0194
 686 +#define BCMA_CORE_PCIE2_D2H_INTSTAT_0          0x0198
 687 +#define BCMA_CORE_PCIE2_D2H_INTMASK_0          0x019c
 688 +#define BCMA_CORE_PCIE2_LTR_STATE              0x01A0 /* Latency Tolerance Reporting */
 689 +#define  PCIE2_LTR_ACTIVE                      2
 690 +#define  PCIE2_LTR_ACTIVE_IDLE                 1
 691 +#define  PCIE2_LTR_SLEEP                       0
 692 +#define  PCIE2_LTR_FINAL_MASK                  0x300
 693 +#define  PCIE2_LTR_FINAL_SHIFT                 8
 694 +#define BCMA_CORE_PCIE2_PWR_INT_STATUS         0x01A4
 695 +#define BCMA_CORE_PCIE2_PWR_INT_MASK           0x01A8
 696 +#define BCMA_CORE_PCIE2_CFG_ADDR               0x01F8
 697 +#define BCMA_CORE_PCIE2_CFG_DATA               0x01FC
 698 +#define BCMA_CORE_PCIE2_SYS_EQ_PAGE            0x0200
 699 +#define BCMA_CORE_PCIE2_SYS_MSI_PAGE           0x0204
 700 +#define BCMA_CORE_PCIE2_SYS_MSI_INTREN         0x0208
 701 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL0          0x0210
 702 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL1          0x0214
 703 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL2          0x0218
 704 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL3          0x021C
 705 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL4          0x0220
 706 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL5          0x0224
 707 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD0           0x0250
 708 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL0           0x0254
 709 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD1           0x0258
 710 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL1           0x025C
 711 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD2           0x0260
 712 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL2           0x0264
 713 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD3           0x0268
 714 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL3           0x026C
 715 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD4           0x0270
 716 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL4           0x0274
 717 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD5           0x0278
 718 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL5           0x027C
 719 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_EN         0x0330
 720 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_CSR                0x0334
 721 +#define BCMA_CORE_PCIE2_SYS_MSI_REQ            0x0340
 722 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_EN       0x0344
 723 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_CSR      0x0348
 724 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR0         0x0350
 725 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR1         0x0354
 726 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR2         0x0358
 727 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR3         0x035C
 728 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN0         0x0360
 729 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN1         0x0364
 730 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR0                0x0370
 731 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR1                0x0374
 732 +#define BCMA_CORE_PCIE2_SPROM(wordoffset)      (0x0800 + ((wordoffset) * 2))
 733 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_0          0x0C00
 734 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_1          0x0C04
 735 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_2          0x0C08
 736 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_3          0x0C0C
 737 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_4          0x0C10
 738 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_5          0x0C14
 739 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_6          0x0C18
 740 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_7          0x0C1C
 741 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_0          0x0C20
 742 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_1          0x0C24
 743 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_2          0x0C28
 744 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_3          0x0C2C
 745 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_4          0x0C30
 746 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_5          0x0C34
 747 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_6          0x0C38
 748 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_7          0x0C3C
 749 +#define BCMA_CORE_PCIE2_FUNC0_IMAP1            0x0C80
 750 +#define BCMA_CORE_PCIE2_FUNC1_IMAP1            0x0C88
 751 +#define BCMA_CORE_PCIE2_FUNC0_IMAP2            0x0CC0
 752 +#define BCMA_CORE_PCIE2_FUNC1_IMAP2            0x0CC8
 753 +#define BCMA_CORE_PCIE2_IARR0_LOWER            0x0D00
 754 +#define BCMA_CORE_PCIE2_IARR0_UPPER            0x0D04
 755 +#define BCMA_CORE_PCIE2_IARR1_LOWER            0x0D08
 756 +#define BCMA_CORE_PCIE2_IARR1_UPPER            0x0D0C
 757 +#define BCMA_CORE_PCIE2_IARR2_LOWER            0x0D10
 758 +#define BCMA_CORE_PCIE2_IARR2_UPPER            0x0D14
 759 +#define BCMA_CORE_PCIE2_OARR0                  0x0D20
 760 +#define BCMA_CORE_PCIE2_OARR1                  0x0D28
 761 +#define BCMA_CORE_PCIE2_OARR2                  0x0D30
 762 +#define BCMA_CORE_PCIE2_OMAP0_LOWER            0x0D40
 763 +#define BCMA_CORE_PCIE2_OMAP0_UPPER            0x0D44
 764 +#define BCMA_CORE_PCIE2_OMAP1_LOWER            0x0D48
 765 +#define BCMA_CORE_PCIE2_OMAP1_UPPER            0x0D4C
 766 +#define BCMA_CORE_PCIE2_OMAP2_LOWER            0x0D50
 767 +#define BCMA_CORE_PCIE2_OMAP2_UPPER            0x0D54
 768 +#define BCMA_CORE_PCIE2_FUNC1_IARR1_SIZE       0x0D58
 769 +#define BCMA_CORE_PCIE2_FUNC1_IARR2_SIZE       0x0D5C
 770 +#define BCMA_CORE_PCIE2_MEM_CONTROL            0x0F00
 771 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG0                0x0F04
 772 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG1                0x0F08
 773 +#define BCMA_CORE_PCIE2_LINK_STATUS            0x0F0C
 774 +#define BCMA_CORE_PCIE2_STRAP_STATUS           0x0F10
 775 +#define BCMA_CORE_PCIE2_RESET_STATUS           0x0F14
 776 +#define BCMA_CORE_PCIE2_RESETEN_IN_LINKDOWN    0x0F18
 777 +#define BCMA_CORE_PCIE2_MISC_INTR_EN           0x0F1C
 778 +#define BCMA_CORE_PCIE2_TX_DEBUG_CFG           0x0F20
 779 +#define BCMA_CORE_PCIE2_MISC_CONFIG            0x0F24
 780 +#define BCMA_CORE_PCIE2_MISC_STATUS            0x0F28
 781 +#define BCMA_CORE_PCIE2_INTR_EN                        0x0F30
 782 +#define BCMA_CORE_PCIE2_INTR_CLEAR             0x0F34
 783 +#define BCMA_CORE_PCIE2_INTR_STATUS            0x0F38
 784 +
 785 +/* PCIE gen2 config regs */
 786 +#define PCIE2_INTSTATUS                                0x090
 787 +#define PCIE2_INTMASK                          0x094
 788 +#define PCIE2_SBMBX                            0x098
 789 +
 790 +#define PCIE2_PMCR_REFUP                       0x1814 /* Trefup time */
 791 +
 792 +#define PCIE2_CAP_DEVSTSCTRL2_OFFSET           0xD4
 793 +#define PCIE2_CAP_DEVSTSCTRL2_LTRENAB          0x400
 794 +#define PCIE2_PVT_REG_PM_CLK_PERIOD            0x184c
 795 +
 796 +struct bcma_drv_pcie2 {
 797 +       struct bcma_device *core;
 798 +};
 799 +
 800 +#define pcie2_read16(pcie2, offset)            bcma_read16((pcie2)->core, offset)
 801 +#define pcie2_read32(pcie2, offset)            bcma_read32((pcie2)->core, offset)
 802 +#define pcie2_write16(pcie2, offset, val)      bcma_write16((pcie2)->core, offset, val)
 803 +#define pcie2_write32(pcie2, offset, val)      bcma_write32((pcie2)->core, offset, val)
 804 +
 805 +#define pcie2_set32(pcie2, offset, set)                bcma_set32((pcie2)->core, offset, set)
 806 +#define pcie2_mask32(pcie2, offset, mask)      bcma_mask32((pcie2)->core, offset, mask)
 807 +
 808 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2);
 809 +
 810 +#endif /* LINUX_BCMA_DRIVER_PCIE2_H_ */