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kernel: update bcma to the tag master-2014-09-26 (wireless-next)
[openwrt/openwrt.git] / target / linux / generic / patches-3.14 / 025-bcma_backport.patch
1 --- a/drivers/bcma/Makefile
2 +++ b/drivers/bcma/Makefile
3 @@ -1,8 +1,10 @@
4 bcma-y += main.o scan.o core.o sprom.o
5 bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o
6 +bcma-y += driver_chipcommon_b.o
7 bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o
8 bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o
9 bcma-y += driver_pci.o
10 +bcma-y += driver_pcie2.o
11 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
12 bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
13 bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
14 --- a/drivers/bcma/driver_chipcommon_pmu.c
15 +++ b/drivers/bcma/driver_chipcommon_pmu.c
16 @@ -603,6 +603,8 @@ void bcma_pmu_spuravoid_pllupdate(struct
17 tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
18 break;
19
20 + case BCMA_CHIP_ID_BCM43131:
21 + case BCMA_CHIP_ID_BCM43217:
22 case BCMA_CHIP_ID_BCM43227:
23 case BCMA_CHIP_ID_BCM43228:
24 case BCMA_CHIP_ID_BCM43428:
25 --- a/drivers/bcma/driver_gpio.c
26 +++ b/drivers/bcma/driver_gpio.c
27 @@ -76,7 +76,7 @@ static void bcma_gpio_free(struct gpio_c
28 bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
29 }
30
31 -#if IS_BUILTIN(CONFIG_BCMA_HOST_SOC)
32 +#if IS_BUILTIN(CONFIG_BCM47XX)
33 static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
34 {
35 struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
36 @@ -215,10 +215,18 @@ int bcma_gpio_init(struct bcma_drv_cc *c
37 chip->set = bcma_gpio_set_value;
38 chip->direction_input = bcma_gpio_direction_input;
39 chip->direction_output = bcma_gpio_direction_output;
40 -#if IS_BUILTIN(CONFIG_BCMA_HOST_SOC)
41 +#if IS_BUILTIN(CONFIG_BCM47XX)
42 chip->to_irq = bcma_gpio_to_irq;
43 #endif
44 - chip->ngpio = 16;
45 + switch (cc->core->bus->chipinfo.id) {
46 + case BCMA_CHIP_ID_BCM5357:
47 + case BCMA_CHIP_ID_BCM53572:
48 + chip->ngpio = 32;
49 + break;
50 + default:
51 + chip->ngpio = 16;
52 + }
53 +
54 /* There is just one SoC in one device and its GPIO addresses should be
55 * deterministic to address them more easily. The other buses could get
56 * a random base number. */
57 --- /dev/null
58 +++ b/drivers/bcma/driver_pcie2.c
59 @@ -0,0 +1,175 @@
60 +/*
61 + * Broadcom specific AMBA
62 + * PCIe Gen 2 Core
63 + *
64 + * Copyright 2014, Broadcom Corporation
65 + * Copyright 2014, Rafał Miłecki <zajec5@gmail.com>
66 + *
67 + * Licensed under the GNU/GPL. See COPYING for details.
68 + */
69 +
70 +#include "bcma_private.h"
71 +#include <linux/bcma/bcma.h>
72 +
73 +/**************************************************
74 + * R/W ops.
75 + **************************************************/
76 +
77 +#if 0
78 +static u32 bcma_core_pcie2_cfg_read(struct bcma_drv_pcie2 *pcie2, u32 addr)
79 +{
80 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
81 + pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR);
82 + return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
83 +}
84 +#endif
85 +
86 +static void bcma_core_pcie2_cfg_write(struct bcma_drv_pcie2 *pcie2, u32 addr,
87 + u32 val)
88 +{
89 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
90 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, val);
91 +}
92 +
93 +/**************************************************
94 + * Init.
95 + **************************************************/
96 +
97 +static u32 bcma_core_pcie2_war_delay_perst_enab(struct bcma_drv_pcie2 *pcie2,
98 + bool enable)
99 +{
100 + u32 val;
101 +
102 + /* restore back to default */
103 + val = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
104 + val |= PCIE2_CLKC_DLYPERST;
105 + val &= ~PCIE2_CLKC_DISSPROMLD;
106 + if (enable) {
107 + val &= ~PCIE2_CLKC_DLYPERST;
108 + val |= PCIE2_CLKC_DISSPROMLD;
109 + }
110 + pcie2_write32(pcie2, (BCMA_CORE_PCIE2_CLK_CONTROL), val);
111 + /* flush */
112 + return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
113 +}
114 +
115 +static void bcma_core_pcie2_set_ltr_vals(struct bcma_drv_pcie2 *pcie2)
116 +{
117 + /* LTR0 */
118 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x844);
119 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x883c883c);
120 + /* LTR1 */
121 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x848);
122 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x88648864);
123 + /* LTR2 */
124 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x84C);
125 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x90039003);
126 +}
127 +
128 +static void bcma_core_pcie2_hw_ltr_war(struct bcma_drv_pcie2 *pcie2)
129 +{
130 + u8 core_rev = pcie2->core->id.rev;
131 + u32 devstsctr2;
132 +
133 + if (core_rev < 2 || core_rev == 10 || core_rev > 13)
134 + return;
135 +
136 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
137 + PCIE2_CAP_DEVSTSCTRL2_OFFSET);
138 + devstsctr2 = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
139 + if (devstsctr2 & PCIE2_CAP_DEVSTSCTRL2_LTRENAB) {
140 + /* force the right LTR values */
141 + bcma_core_pcie2_set_ltr_vals(pcie2);
142 +
143 + /* TODO:
144 + si_core_wrapperreg(pcie2, 3, 0x60, 0x8080, 0); */
145 +
146 + /* enable the LTR */
147 + devstsctr2 |= PCIE2_CAP_DEVSTSCTRL2_LTRENAB;
148 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
149 + PCIE2_CAP_DEVSTSCTRL2_OFFSET);
150 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, devstsctr2);
151 +
152 + /* set the LTR state to be active */
153 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
154 + PCIE2_LTR_ACTIVE);
155 + usleep_range(1000, 2000);
156 +
157 + /* set the LTR state to be sleep */
158 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
159 + PCIE2_LTR_SLEEP);
160 + usleep_range(1000, 2000);
161 + }
162 +}
163 +
164 +static void pciedev_crwlpciegen2(struct bcma_drv_pcie2 *pcie2)
165 +{
166 + u8 core_rev = pcie2->core->id.rev;
167 + bool pciewar160, pciewar162;
168 +
169 + pciewar160 = core_rev == 7 || core_rev == 9 || core_rev == 11;
170 + pciewar162 = core_rev == 5 || core_rev == 7 || core_rev == 8 ||
171 + core_rev == 9 || core_rev == 11;
172 +
173 + if (!pciewar160 && !pciewar162)
174 + return;
175 +
176 +/* TODO */
177 +#if 0
178 + pcie2_set32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL,
179 + PCIE_DISABLE_L1CLK_GATING);
180 +#if 0
181 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
182 + PCIEGEN2_COE_PVT_TL_CTRL_0);
183 + pcie2_mask32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA,
184 + ~(1 << COE_PVT_TL_CTRL_0_PM_DIS_L1_REENTRY_BIT));
185 +#endif
186 +#endif
187 +}
188 +
189 +static void pciedev_crwlpciegen2_180(struct bcma_drv_pcie2 *pcie2)
190 +{
191 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_PMCR_REFUP);
192 + pcie2_set32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x1f);
193 +}
194 +
195 +static void pciedev_crwlpciegen2_182(struct bcma_drv_pcie2 *pcie2)
196 +{
197 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_SBMBX);
198 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 1 << 0);
199 +}
200 +
201 +static void pciedev_reg_pm_clk_period(struct bcma_drv_pcie2 *pcie2)
202 +{
203 + struct bcma_drv_cc *drv_cc = &pcie2->core->bus->drv_cc;
204 + u8 core_rev = pcie2->core->id.rev;
205 + u32 alp_khz, pm_value;
206 +
207 + if (core_rev <= 13) {
208 + alp_khz = bcma_pmu_get_alp_clock(drv_cc) / 1000;
209 + pm_value = (1000000 * 2) / alp_khz;
210 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
211 + PCIE2_PVT_REG_PM_CLK_PERIOD);
212 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, pm_value);
213 + }
214 +}
215 +
216 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2)
217 +{
218 + struct bcma_chipinfo *ci = &pcie2->core->bus->chipinfo;
219 + u32 tmp;
220 +
221 + tmp = pcie2_read32(pcie2, BCMA_CORE_PCIE2_SPROM(54));
222 + if ((tmp & 0xe) >> 1 == 2)
223 + bcma_core_pcie2_cfg_write(pcie2, 0x4e0, 0x17);
224 +
225 + /* TODO: Do we need pcie_reqsize? */
226 +
227 + if (ci->id == BCMA_CHIP_ID_BCM4360 && ci->rev > 3)
228 + bcma_core_pcie2_war_delay_perst_enab(pcie2, true);
229 + bcma_core_pcie2_hw_ltr_war(pcie2);
230 + pciedev_crwlpciegen2(pcie2);
231 + pciedev_reg_pm_clk_period(pcie2);
232 + pciedev_crwlpciegen2_180(pcie2);
233 + pciedev_crwlpciegen2_182(pcie2);
234 +}
235 --- a/drivers/bcma/host_pci.c
236 +++ b/drivers/bcma/host_pci.c
237 @@ -208,6 +208,9 @@ static int bcma_host_pci_probe(struct pc
238 bus->boardinfo.vendor = bus->host_pci->subsystem_vendor;
239 bus->boardinfo.type = bus->host_pci->subsystem_device;
240
241 + /* Initialize struct, detect chip */
242 + bcma_init_bus(bus);
243 +
244 /* Register */
245 err = bcma_bus_register(bus);
246 if (err)
247 @@ -279,7 +282,10 @@ static const struct pci_device_id bcma_p
248 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
249 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
250 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
251 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) },
252 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43aa) },
253 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
254 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43227) }, /* 0xA8DB */
255 { 0, },
256 };
257 MODULE_DEVICE_TABLE(pci, bcma_pci_bridge_tbl);
258 --- a/drivers/bcma/main.c
259 +++ b/drivers/bcma/main.c
260 @@ -120,56 +120,78 @@ static void bcma_release_core_dev(struct
261 kfree(core);
262 }
263
264 -static int bcma_register_cores(struct bcma_bus *bus)
265 +static bool bcma_is_core_needed_early(u16 core_id)
266 +{
267 + switch (core_id) {
268 + case BCMA_CORE_NS_NAND:
269 + case BCMA_CORE_NS_QSPI:
270 + return true;
271 + }
272 +
273 + return false;
274 +}
275 +
276 +static void bcma_register_core(struct bcma_bus *bus, struct bcma_device *core)
277 +{
278 + int err;
279 +
280 + core->dev.release = bcma_release_core_dev;
281 + core->dev.bus = &bcma_bus_type;
282 + dev_set_name(&core->dev, "bcma%d:%d", bus->num, core->core_index);
283 +
284 + switch (bus->hosttype) {
285 + case BCMA_HOSTTYPE_PCI:
286 + core->dev.parent = &bus->host_pci->dev;
287 + core->dma_dev = &bus->host_pci->dev;
288 + core->irq = bus->host_pci->irq;
289 + break;
290 + case BCMA_HOSTTYPE_SOC:
291 + core->dev.dma_mask = &core->dev.coherent_dma_mask;
292 + core->dma_dev = &core->dev;
293 + break;
294 + case BCMA_HOSTTYPE_SDIO:
295 + break;
296 + }
297 +
298 + err = device_register(&core->dev);
299 + if (err) {
300 + bcma_err(bus, "Could not register dev for core 0x%03X\n",
301 + core->id.id);
302 + put_device(&core->dev);
303 + return;
304 + }
305 + core->dev_registered = true;
306 +}
307 +
308 +static int bcma_register_devices(struct bcma_bus *bus)
309 {
310 struct bcma_device *core;
311 - int err, dev_id = 0;
312 + int err;
313
314 list_for_each_entry(core, &bus->cores, list) {
315 /* We support that cores ourself */
316 switch (core->id.id) {
317 case BCMA_CORE_4706_CHIPCOMMON:
318 case BCMA_CORE_CHIPCOMMON:
319 + case BCMA_CORE_NS_CHIPCOMMON_B:
320 case BCMA_CORE_PCI:
321 case BCMA_CORE_PCIE:
322 + case BCMA_CORE_PCIE2:
323 case BCMA_CORE_MIPS_74K:
324 case BCMA_CORE_4706_MAC_GBIT_COMMON:
325 continue;
326 }
327
328 + /* Early cores were already registered */
329 + if (bcma_is_core_needed_early(core->id.id))
330 + continue;
331 +
332 /* Only first GMAC core on BCM4706 is connected and working */
333 if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
334 core->core_unit > 0)
335 continue;
336
337 - core->dev.release = bcma_release_core_dev;
338 - core->dev.bus = &bcma_bus_type;
339 - dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
340 -
341 - switch (bus->hosttype) {
342 - case BCMA_HOSTTYPE_PCI:
343 - core->dev.parent = &bus->host_pci->dev;
344 - core->dma_dev = &bus->host_pci->dev;
345 - core->irq = bus->host_pci->irq;
346 - break;
347 - case BCMA_HOSTTYPE_SOC:
348 - core->dev.dma_mask = &core->dev.coherent_dma_mask;
349 - core->dma_dev = &core->dev;
350 - break;
351 - case BCMA_HOSTTYPE_SDIO:
352 - break;
353 - }
354 -
355 - err = device_register(&core->dev);
356 - if (err) {
357 - bcma_err(bus,
358 - "Could not register dev for core 0x%03X\n",
359 - core->id.id);
360 - put_device(&core->dev);
361 - continue;
362 - }
363 - core->dev_registered = true;
364 - dev_id++;
365 + bcma_register_core(bus, core);
366 }
367
368 #ifdef CONFIG_BCMA_DRIVER_MIPS
369 @@ -246,6 +268,12 @@ int bcma_bus_register(struct bcma_bus *b
370 bcma_core_chipcommon_early_init(&bus->drv_cc);
371 }
372
373 + /* Cores providing flash access go before SPROM init */
374 + list_for_each_entry(core, &bus->cores, list) {
375 + if (bcma_is_core_needed_early(core->id.id))
376 + bcma_register_core(bus, core);
377 + }
378 +
379 /* Try to get SPROM */
380 err = bcma_sprom_get(bus);
381 if (err == -ENOENT) {
382 @@ -260,6 +288,13 @@ int bcma_bus_register(struct bcma_bus *b
383 bcma_core_chipcommon_init(&bus->drv_cc);
384 }
385
386 + /* Init CC core */
387 + core = bcma_find_core(bus, BCMA_CORE_NS_CHIPCOMMON_B);
388 + if (core) {
389 + bus->drv_cc_b.core = core;
390 + bcma_core_chipcommon_b_init(&bus->drv_cc_b);
391 + }
392 +
393 /* Init MIPS core */
394 core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
395 if (core) {
396 @@ -281,6 +316,13 @@ int bcma_bus_register(struct bcma_bus *b
397 bcma_core_pci_init(&bus->drv_pci[1]);
398 }
399
400 + /* Init PCIe Gen 2 core */
401 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE2, 0);
402 + if (core) {
403 + bus->drv_pcie2.core = core;
404 + bcma_core_pcie2_init(&bus->drv_pcie2);
405 + }
406 +
407 /* Init GBIT MAC COMMON core */
408 core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
409 if (core) {
410 @@ -289,7 +331,7 @@ int bcma_bus_register(struct bcma_bus *b
411 }
412
413 /* Register found cores */
414 - bcma_register_cores(bus);
415 + bcma_register_devices(bus);
416
417 bcma_info(bus, "Bus registered\n");
418
419 @@ -307,6 +349,8 @@ void bcma_bus_unregister(struct bcma_bus
420 else if (err)
421 bcma_err(bus, "Can not unregister GPIO driver: %i\n", err);
422
423 + bcma_core_chipcommon_b_free(&bus->drv_cc_b);
424 +
425 cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
426 cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE);
427 cores[2] = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
428 @@ -326,8 +370,6 @@ int __init bcma_bus_early_register(struc
429 struct bcma_device *core;
430 struct bcma_device_id match;
431
432 - bcma_init_bus(bus);
433 -
434 match.manuf = BCMA_MANUF_BCM;
435 match.id = bcma_cc_core_id(bus);
436 match.class = BCMA_CL_SIM;
437 --- a/drivers/bcma/sprom.c
438 +++ b/drivers/bcma/sprom.c
439 @@ -201,6 +201,23 @@ static int bcma_sprom_valid(struct bcma_
440 SPEX(_field[7], _offset + 14, _mask, _shift); \
441 } while (0)
442
443 +static s8 sprom_extract_antgain(const u16 *in, u16 offset, u16 mask, u16 shift)
444 +{
445 + u16 v;
446 + u8 gain;
447 +
448 + v = in[SPOFF(offset)];
449 + gain = (v & mask) >> shift;
450 + if (gain == 0xFF) {
451 + gain = 8; /* If unset use 2dBm */
452 + } else {
453 + /* Q5.2 Fractional part is stored in 0xC0 */
454 + gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
455 + }
456 +
457 + return (s8)gain;
458 +}
459 +
460 static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
461 {
462 u16 v, o;
463 @@ -381,14 +398,22 @@ static void bcma_sprom_extract_r8(struct
464 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, ~0, 0);
465
466 /* Extract the antenna gain values. */
467 - SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
468 - SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
469 - SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
470 - SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
471 - SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
472 - SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
473 - SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
474 - SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
475 + bus->sprom.antenna_gain.a0 = sprom_extract_antgain(sprom,
476 + SSB_SPROM8_AGAIN01,
477 + SSB_SPROM8_AGAIN0,
478 + SSB_SPROM8_AGAIN0_SHIFT);
479 + bus->sprom.antenna_gain.a1 = sprom_extract_antgain(sprom,
480 + SSB_SPROM8_AGAIN01,
481 + SSB_SPROM8_AGAIN1,
482 + SSB_SPROM8_AGAIN1_SHIFT);
483 + bus->sprom.antenna_gain.a2 = sprom_extract_antgain(sprom,
484 + SSB_SPROM8_AGAIN23,
485 + SSB_SPROM8_AGAIN2,
486 + SSB_SPROM8_AGAIN2_SHIFT);
487 + bus->sprom.antenna_gain.a3 = sprom_extract_antgain(sprom,
488 + SSB_SPROM8_AGAIN23,
489 + SSB_SPROM8_AGAIN3,
490 + SSB_SPROM8_AGAIN3_SHIFT);
491
492 SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
493 SSB_SPROM8_LEDDC_ON_SHIFT);
494 @@ -509,6 +534,8 @@ static bool bcma_sprom_onchip_available(
495 /* for these chips OTP is always available */
496 present = true;
497 break;
498 + case BCMA_CHIP_ID_BCM43131:
499 + case BCMA_CHIP_ID_BCM43217:
500 case BCMA_CHIP_ID_BCM43227:
501 case BCMA_CHIP_ID_BCM43228:
502 case BCMA_CHIP_ID_BCM43428:
503 --- a/include/linux/bcma/bcma.h
504 +++ b/include/linux/bcma/bcma.h
505 @@ -6,6 +6,7 @@
506
507 #include <linux/bcma/bcma_driver_chipcommon.h>
508 #include <linux/bcma/bcma_driver_pci.h>
509 +#include <linux/bcma/bcma_driver_pcie2.h>
510 #include <linux/bcma/bcma_driver_mips.h>
511 #include <linux/bcma/bcma_driver_gmac_cmn.h>
512 #include <linux/ssb/ssb.h> /* SPROM sharing */
513 @@ -72,17 +73,17 @@ struct bcma_host_ops {
514 /* Core-ID values. */
515 #define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
516 #define BCMA_CORE_4706_CHIPCOMMON 0x500
517 -#define BCMA_CORE_PCIEG2 0x501
518 -#define BCMA_CORE_DMA 0x502
519 -#define BCMA_CORE_SDIO3 0x503
520 -#define BCMA_CORE_USB20 0x504
521 -#define BCMA_CORE_USB30 0x505
522 -#define BCMA_CORE_A9JTAG 0x506
523 -#define BCMA_CORE_DDR23 0x507
524 -#define BCMA_CORE_ROM 0x508
525 -#define BCMA_CORE_NAND 0x509
526 -#define BCMA_CORE_QSPI 0x50A
527 -#define BCMA_CORE_CHIPCOMMON_B 0x50B
528 +#define BCMA_CORE_NS_PCIEG2 0x501
529 +#define BCMA_CORE_NS_DMA 0x502
530 +#define BCMA_CORE_NS_SDIO3 0x503
531 +#define BCMA_CORE_NS_USB20 0x504
532 +#define BCMA_CORE_NS_USB30 0x505
533 +#define BCMA_CORE_NS_A9JTAG 0x506
534 +#define BCMA_CORE_NS_DDR23 0x507
535 +#define BCMA_CORE_NS_ROM 0x508
536 +#define BCMA_CORE_NS_NAND 0x509
537 +#define BCMA_CORE_NS_QSPI 0x50A
538 +#define BCMA_CORE_NS_CHIPCOMMON_B 0x50B
539 #define BCMA_CORE_4706_SOC_RAM 0x50E
540 #define BCMA_CORE_ARMCA9 0x510
541 #define BCMA_CORE_4706_MAC_GBIT 0x52D
542 @@ -157,6 +158,9 @@ struct bcma_host_ops {
543 /* Chip IDs of PCIe devices */
544 #define BCMA_CHIP_ID_BCM4313 0x4313
545 #define BCMA_CHIP_ID_BCM43142 43142
546 +#define BCMA_CHIP_ID_BCM43131 43131
547 +#define BCMA_CHIP_ID_BCM43217 43217
548 +#define BCMA_CHIP_ID_BCM43222 43222
549 #define BCMA_CHIP_ID_BCM43224 43224
550 #define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
551 #define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
552 @@ -263,7 +267,7 @@ struct bcma_device {
553 u8 core_unit;
554
555 u32 addr;
556 - u32 addr1;
557 + u32 addr_s[8];
558 u32 wrap;
559
560 void __iomem *io_addr;
561 @@ -328,11 +332,12 @@ struct bcma_bus {
562 struct bcma_device *mapped_core;
563 struct list_head cores;
564 u8 nr_cores;
565 - u8 init_done:1;
566 u8 num;
567
568 struct bcma_drv_cc drv_cc;
569 + struct bcma_drv_cc_b drv_cc_b;
570 struct bcma_drv_pci drv_pci[2];
571 + struct bcma_drv_pcie2 drv_pcie2;
572 struct bcma_drv_mips drv_mips;
573 struct bcma_drv_gmac_cmn drv_gmac_cmn;
574
575 --- /dev/null
576 +++ b/include/linux/bcma/bcma_driver_pcie2.h
577 @@ -0,0 +1,158 @@
578 +#ifndef LINUX_BCMA_DRIVER_PCIE2_H_
579 +#define LINUX_BCMA_DRIVER_PCIE2_H_
580 +
581 +#define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000
582 +#define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */
583 +#define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */
584 +#define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */
585 +#define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010
586 +#define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */
587 +#define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */
588 +#define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */
589 +#define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004
590 +#define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008
591 +#define BCMA_CORE_PCIE2_EP_PM_CONTROL 0x000C
592 +#define BCMA_CORE_PCIE2_EP_PM_STATUS 0x0010
593 +#define BCMA_CORE_PCIE2_EP_LTR_CONTROL 0x0014
594 +#define BCMA_CORE_PCIE2_EP_LTR_STATUS 0x0018
595 +#define BCMA_CORE_PCIE2_EP_OBFF_STATUS 0x001C
596 +#define BCMA_CORE_PCIE2_PCIE_ERR_STATUS 0x0020
597 +#define BCMA_CORE_PCIE2_RC_AXI_CONFIG 0x0100
598 +#define BCMA_CORE_PCIE2_EP_AXI_CONFIG 0x0104
599 +#define BCMA_CORE_PCIE2_RXDEBUG_STATUS0 0x0108
600 +#define BCMA_CORE_PCIE2_RXDEBUG_CONTROL0 0x010C
601 +#define BCMA_CORE_PCIE2_CONFIGINDADDR 0x0120
602 +#define BCMA_CORE_PCIE2_CONFIGINDDATA 0x0124
603 +#define BCMA_CORE_PCIE2_MDIOCONTROL 0x0128
604 +#define BCMA_CORE_PCIE2_MDIOWRDATA 0x012C
605 +#define BCMA_CORE_PCIE2_MDIORDDATA 0x0130
606 +#define BCMA_CORE_PCIE2_DATAINTF 0x0180
607 +#define BCMA_CORE_PCIE2_D2H_INTRLAZY_0 0x0188
608 +#define BCMA_CORE_PCIE2_H2D_INTRLAZY_0 0x018c
609 +#define BCMA_CORE_PCIE2_H2D_INTSTAT_0 0x0190
610 +#define BCMA_CORE_PCIE2_H2D_INTMASK_0 0x0194
611 +#define BCMA_CORE_PCIE2_D2H_INTSTAT_0 0x0198
612 +#define BCMA_CORE_PCIE2_D2H_INTMASK_0 0x019c
613 +#define BCMA_CORE_PCIE2_LTR_STATE 0x01A0 /* Latency Tolerance Reporting */
614 +#define PCIE2_LTR_ACTIVE 2
615 +#define PCIE2_LTR_ACTIVE_IDLE 1
616 +#define PCIE2_LTR_SLEEP 0
617 +#define PCIE2_LTR_FINAL_MASK 0x300
618 +#define PCIE2_LTR_FINAL_SHIFT 8
619 +#define BCMA_CORE_PCIE2_PWR_INT_STATUS 0x01A4
620 +#define BCMA_CORE_PCIE2_PWR_INT_MASK 0x01A8
621 +#define BCMA_CORE_PCIE2_CFG_ADDR 0x01F8
622 +#define BCMA_CORE_PCIE2_CFG_DATA 0x01FC
623 +#define BCMA_CORE_PCIE2_SYS_EQ_PAGE 0x0200
624 +#define BCMA_CORE_PCIE2_SYS_MSI_PAGE 0x0204
625 +#define BCMA_CORE_PCIE2_SYS_MSI_INTREN 0x0208
626 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL0 0x0210
627 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL1 0x0214
628 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL2 0x0218
629 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL3 0x021C
630 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL4 0x0220
631 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL5 0x0224
632 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD0 0x0250
633 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL0 0x0254
634 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD1 0x0258
635 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL1 0x025C
636 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD2 0x0260
637 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL2 0x0264
638 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD3 0x0268
639 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL3 0x026C
640 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD4 0x0270
641 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL4 0x0274
642 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD5 0x0278
643 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL5 0x027C
644 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_EN 0x0330
645 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_CSR 0x0334
646 +#define BCMA_CORE_PCIE2_SYS_MSI_REQ 0x0340
647 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_EN 0x0344
648 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_CSR 0x0348
649 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR0 0x0350
650 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR1 0x0354
651 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR2 0x0358
652 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR3 0x035C
653 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN0 0x0360
654 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN1 0x0364
655 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR0 0x0370
656 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR1 0x0374
657 +#define BCMA_CORE_PCIE2_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2))
658 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_0 0x0C00
659 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_1 0x0C04
660 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_2 0x0C08
661 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_3 0x0C0C
662 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_4 0x0C10
663 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_5 0x0C14
664 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_6 0x0C18
665 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_7 0x0C1C
666 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_0 0x0C20
667 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_1 0x0C24
668 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_2 0x0C28
669 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_3 0x0C2C
670 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_4 0x0C30
671 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_5 0x0C34
672 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_6 0x0C38
673 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_7 0x0C3C
674 +#define BCMA_CORE_PCIE2_FUNC0_IMAP1 0x0C80
675 +#define BCMA_CORE_PCIE2_FUNC1_IMAP1 0x0C88
676 +#define BCMA_CORE_PCIE2_FUNC0_IMAP2 0x0CC0
677 +#define BCMA_CORE_PCIE2_FUNC1_IMAP2 0x0CC8
678 +#define BCMA_CORE_PCIE2_IARR0_LOWER 0x0D00
679 +#define BCMA_CORE_PCIE2_IARR0_UPPER 0x0D04
680 +#define BCMA_CORE_PCIE2_IARR1_LOWER 0x0D08
681 +#define BCMA_CORE_PCIE2_IARR1_UPPER 0x0D0C
682 +#define BCMA_CORE_PCIE2_IARR2_LOWER 0x0D10
683 +#define BCMA_CORE_PCIE2_IARR2_UPPER 0x0D14
684 +#define BCMA_CORE_PCIE2_OARR0 0x0D20
685 +#define BCMA_CORE_PCIE2_OARR1 0x0D28
686 +#define BCMA_CORE_PCIE2_OARR2 0x0D30
687 +#define BCMA_CORE_PCIE2_OMAP0_LOWER 0x0D40
688 +#define BCMA_CORE_PCIE2_OMAP0_UPPER 0x0D44
689 +#define BCMA_CORE_PCIE2_OMAP1_LOWER 0x0D48
690 +#define BCMA_CORE_PCIE2_OMAP1_UPPER 0x0D4C
691 +#define BCMA_CORE_PCIE2_OMAP2_LOWER 0x0D50
692 +#define BCMA_CORE_PCIE2_OMAP2_UPPER 0x0D54
693 +#define BCMA_CORE_PCIE2_FUNC1_IARR1_SIZE 0x0D58
694 +#define BCMA_CORE_PCIE2_FUNC1_IARR2_SIZE 0x0D5C
695 +#define BCMA_CORE_PCIE2_MEM_CONTROL 0x0F00
696 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG0 0x0F04
697 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG1 0x0F08
698 +#define BCMA_CORE_PCIE2_LINK_STATUS 0x0F0C
699 +#define BCMA_CORE_PCIE2_STRAP_STATUS 0x0F10
700 +#define BCMA_CORE_PCIE2_RESET_STATUS 0x0F14
701 +#define BCMA_CORE_PCIE2_RESETEN_IN_LINKDOWN 0x0F18
702 +#define BCMA_CORE_PCIE2_MISC_INTR_EN 0x0F1C
703 +#define BCMA_CORE_PCIE2_TX_DEBUG_CFG 0x0F20
704 +#define BCMA_CORE_PCIE2_MISC_CONFIG 0x0F24
705 +#define BCMA_CORE_PCIE2_MISC_STATUS 0x0F28
706 +#define BCMA_CORE_PCIE2_INTR_EN 0x0F30
707 +#define BCMA_CORE_PCIE2_INTR_CLEAR 0x0F34
708 +#define BCMA_CORE_PCIE2_INTR_STATUS 0x0F38
709 +
710 +/* PCIE gen2 config regs */
711 +#define PCIE2_INTSTATUS 0x090
712 +#define PCIE2_INTMASK 0x094
713 +#define PCIE2_SBMBX 0x098
714 +
715 +#define PCIE2_PMCR_REFUP 0x1814 /* Trefup time */
716 +
717 +#define PCIE2_CAP_DEVSTSCTRL2_OFFSET 0xD4
718 +#define PCIE2_CAP_DEVSTSCTRL2_LTRENAB 0x400
719 +#define PCIE2_PVT_REG_PM_CLK_PERIOD 0x184c
720 +
721 +struct bcma_drv_pcie2 {
722 + struct bcma_device *core;
723 +};
724 +
725 +#define pcie2_read16(pcie2, offset) bcma_read16((pcie2)->core, offset)
726 +#define pcie2_read32(pcie2, offset) bcma_read32((pcie2)->core, offset)
727 +#define pcie2_write16(pcie2, offset, val) bcma_write16((pcie2)->core, offset, val)
728 +#define pcie2_write32(pcie2, offset, val) bcma_write32((pcie2)->core, offset, val)
729 +
730 +#define pcie2_set32(pcie2, offset, set) bcma_set32((pcie2)->core, offset, set)
731 +#define pcie2_mask32(pcie2, offset, mask) bcma_mask32((pcie2)->core, offset, mask)
732 +
733 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2);
734 +
735 +#endif /* LINUX_BCMA_DRIVER_PCIE2_H_ */
736 --- a/drivers/bcma/scan.c
737 +++ b/drivers/bcma/scan.c
738 @@ -32,17 +32,17 @@ static const struct bcma_device_id_name
739 { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
740 { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
741 { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
742 - { BCMA_CORE_PCIEG2, "PCIe Gen 2" },
743 - { BCMA_CORE_DMA, "DMA" },
744 - { BCMA_CORE_SDIO3, "SDIO3" },
745 - { BCMA_CORE_USB20, "USB 2.0" },
746 - { BCMA_CORE_USB30, "USB 3.0" },
747 - { BCMA_CORE_A9JTAG, "ARM Cortex A9 JTAG" },
748 - { BCMA_CORE_DDR23, "Denali DDR2/DDR3 memory controller" },
749 - { BCMA_CORE_ROM, "ROM" },
750 - { BCMA_CORE_NAND, "NAND flash controller" },
751 - { BCMA_CORE_QSPI, "SPI flash controller" },
752 - { BCMA_CORE_CHIPCOMMON_B, "Chipcommon B" },
753 + { BCMA_CORE_NS_PCIEG2, "PCIe Gen 2" },
754 + { BCMA_CORE_NS_DMA, "DMA" },
755 + { BCMA_CORE_NS_SDIO3, "SDIO3" },
756 + { BCMA_CORE_NS_USB20, "USB 2.0" },
757 + { BCMA_CORE_NS_USB30, "USB 3.0" },
758 + { BCMA_CORE_NS_A9JTAG, "ARM Cortex A9 JTAG" },
759 + { BCMA_CORE_NS_DDR23, "Denali DDR2/DDR3 memory controller" },
760 + { BCMA_CORE_NS_ROM, "ROM" },
761 + { BCMA_CORE_NS_NAND, "NAND flash controller" },
762 + { BCMA_CORE_NS_QSPI, "SPI flash controller" },
763 + { BCMA_CORE_NS_CHIPCOMMON_B, "Chipcommon B" },
764 { BCMA_CORE_ARMCA9, "ARM Cortex A9 core (ihost)" },
765 { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
766 { BCMA_CORE_ALTA, "ALTA (I2S)" },
767 @@ -276,7 +276,7 @@ static int bcma_get_next_core(struct bcm
768 struct bcma_device *core)
769 {
770 u32 tmp;
771 - u8 i, j;
772 + u8 i, j, k;
773 s32 cia, cib;
774 u8 ports[2], wrappers[2];
775
776 @@ -314,6 +314,7 @@ static int bcma_get_next_core(struct bcm
777 /* Some specific cores don't need wrappers */
778 switch (core->id.id) {
779 case BCMA_CORE_4706_MAC_GBIT_COMMON:
780 + case BCMA_CORE_NS_CHIPCOMMON_B:
781 /* Not used yet: case BCMA_CORE_OOB_ROUTER: */
782 break;
783 default:
784 @@ -367,6 +368,7 @@ static int bcma_get_next_core(struct bcm
785 core->addr = tmp;
786
787 /* get & parse slave ports */
788 + k = 0;
789 for (i = 0; i < ports[1]; i++) {
790 for (j = 0; ; j++) {
791 tmp = bcma_erom_get_addr_desc(bus, eromptr,
792 @@ -376,9 +378,9 @@ static int bcma_get_next_core(struct bcm
793 /* pr_debug("erom: slave port %d "
794 * "has %d descriptors\n", i, j); */
795 break;
796 - } else {
797 - if (i == 0 && j == 0)
798 - core->addr1 = tmp;
799 + } else if (k < ARRAY_SIZE(core->addr_s)) {
800 + core->addr_s[k] = tmp;
801 + k++;
802 }
803 }
804 }
805 @@ -421,10 +423,13 @@ static int bcma_get_next_core(struct bcm
806 core->io_addr = ioremap_nocache(core->addr, BCMA_CORE_SIZE);
807 if (!core->io_addr)
808 return -ENOMEM;
809 - core->io_wrap = ioremap_nocache(core->wrap, BCMA_CORE_SIZE);
810 - if (!core->io_wrap) {
811 - iounmap(core->io_addr);
812 - return -ENOMEM;
813 + if (core->wrap) {
814 + core->io_wrap = ioremap_nocache(core->wrap,
815 + BCMA_CORE_SIZE);
816 + if (!core->io_wrap) {
817 + iounmap(core->io_addr);
818 + return -ENOMEM;
819 + }
820 }
821 }
822 return 0;
823 @@ -434,9 +439,7 @@ void bcma_init_bus(struct bcma_bus *bus)
824 {
825 s32 tmp;
826 struct bcma_chipinfo *chipinfo = &(bus->chipinfo);
827 -
828 - if (bus->init_done)
829 - return;
830 + char chip_id[8];
831
832 INIT_LIST_HEAD(&bus->cores);
833 bus->nr_cores = 0;
834 @@ -447,10 +450,11 @@ void bcma_init_bus(struct bcma_bus *bus)
835 chipinfo->id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
836 chipinfo->rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
837 chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
838 - bcma_info(bus, "Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
839 - chipinfo->id, chipinfo->rev, chipinfo->pkg);
840
841 - bus->init_done = true;
842 + snprintf(chip_id, ARRAY_SIZE(chip_id),
843 + (chipinfo->id > 0x9999) ? "%d" : "0x%04X", chipinfo->id);
844 + bcma_info(bus, "Found chip with id %s, rev 0x%02X and package 0x%02X\n",
845 + chip_id, chipinfo->rev, chipinfo->pkg);
846 }
847
848 int bcma_bus_scan(struct bcma_bus *bus)
849 @@ -460,8 +464,6 @@ int bcma_bus_scan(struct bcma_bus *bus)
850
851 int err, core_num = 0;
852
853 - bcma_init_bus(bus);
854 -
855 erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM);
856 if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
857 eromptr = ioremap_nocache(erombase, BCMA_CORE_SIZE);
858 --- a/drivers/bcma/host_soc.c
859 +++ b/drivers/bcma/host_soc.c
860 @@ -134,12 +134,16 @@ static void bcma_host_soc_block_write(st
861
862 static u32 bcma_host_soc_aread32(struct bcma_device *core, u16 offset)
863 {
864 + if (WARN_ONCE(!core->io_wrap, "Accessed core has no wrapper/agent\n"))
865 + return ~0;
866 return readl(core->io_wrap + offset);
867 }
868
869 static void bcma_host_soc_awrite32(struct bcma_device *core, u16 offset,
870 u32 value)
871 {
872 + if (WARN_ONCE(!core->io_wrap, "Accessed core has no wrapper/agent\n"))
873 + return;
874 writel(value, core->io_wrap + offset);
875 }
876
877 @@ -161,7 +165,6 @@ static const struct bcma_host_ops bcma_h
878 int __init bcma_host_soc_register(struct bcma_soc *soc)
879 {
880 struct bcma_bus *bus = &soc->bus;
881 - int err;
882
883 /* iomap only first core. We have to read some register on this core
884 * to scan the bus.
885 @@ -174,7 +177,18 @@ int __init bcma_host_soc_register(struct
886 bus->hosttype = BCMA_HOSTTYPE_SOC;
887 bus->ops = &bcma_host_soc_ops;
888
889 - /* Register */
890 + /* Initialize struct, detect chip */
891 + bcma_init_bus(bus);
892 +
893 + return 0;
894 +}
895 +
896 +int __init bcma_host_soc_init(struct bcma_soc *soc)
897 +{
898 + struct bcma_bus *bus = &soc->bus;
899 + int err;
900 +
901 + /* Scan bus and initialize it */
902 err = bcma_bus_early_register(bus, &soc->core_cc, &soc->core_mips);
903 if (err)
904 iounmap(bus->mmio);
905 --- a/drivers/bcma/driver_mips.c
906 +++ b/drivers/bcma/driver_mips.c
907 @@ -21,6 +21,14 @@
908 #include <linux/serial_reg.h>
909 #include <linux/time.h>
910
911 +enum bcma_boot_dev {
912 + BCMA_BOOT_DEV_UNK = 0,
913 + BCMA_BOOT_DEV_ROM,
914 + BCMA_BOOT_DEV_PARALLEL,
915 + BCMA_BOOT_DEV_SERIAL,
916 + BCMA_BOOT_DEV_NAND,
917 +};
918 +
919 static const char * const part_probes[] = { "bcm47xxpart", NULL };
920
921 static struct physmap_flash_data bcma_pflash_data = {
922 @@ -229,11 +237,51 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
923 }
924 EXPORT_SYMBOL(bcma_cpu_clock);
925
926 +static enum bcma_boot_dev bcma_boot_dev(struct bcma_bus *bus)
927 +{
928 + struct bcma_drv_cc *cc = &bus->drv_cc;
929 + u8 cc_rev = cc->core->id.rev;
930 +
931 + if (cc_rev == 42) {
932 + struct bcma_device *core;
933 +
934 + core = bcma_find_core(bus, BCMA_CORE_NS_ROM);
935 + if (core) {
936 + switch (bcma_aread32(core, BCMA_IOST) &
937 + BCMA_NS_ROM_IOST_BOOT_DEV_MASK) {
938 + case BCMA_NS_ROM_IOST_BOOT_DEV_NOR:
939 + return BCMA_BOOT_DEV_SERIAL;
940 + case BCMA_NS_ROM_IOST_BOOT_DEV_NAND:
941 + return BCMA_BOOT_DEV_NAND;
942 + case BCMA_NS_ROM_IOST_BOOT_DEV_ROM:
943 + default:
944 + return BCMA_BOOT_DEV_ROM;
945 + }
946 + }
947 + } else {
948 + if (cc_rev == 38) {
949 + if (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)
950 + return BCMA_BOOT_DEV_NAND;
951 + else if (cc->status & BIT(5))
952 + return BCMA_BOOT_DEV_ROM;
953 + }
954 +
955 + if ((cc->capabilities & BCMA_CC_CAP_FLASHT) ==
956 + BCMA_CC_FLASHT_PARA)
957 + return BCMA_BOOT_DEV_PARALLEL;
958 + else
959 + return BCMA_BOOT_DEV_SERIAL;
960 + }
961 +
962 + return BCMA_BOOT_DEV_SERIAL;
963 +}
964 +
965 static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
966 {
967 struct bcma_bus *bus = mcore->core->bus;
968 struct bcma_drv_cc *cc = &bus->drv_cc;
969 struct bcma_pflash *pflash = &cc->pflash;
970 + enum bcma_boot_dev boot_dev;
971
972 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
973 case BCMA_CC_FLASHT_STSER:
974 @@ -269,6 +317,20 @@ static void bcma_core_mips_flash_detect(
975 bcma_nflash_init(cc);
976 }
977 }
978 +
979 + /* Determine flash type this SoC boots from */
980 + boot_dev = bcma_boot_dev(bus);
981 + switch (boot_dev) {
982 + case BCMA_BOOT_DEV_PARALLEL:
983 + case BCMA_BOOT_DEV_SERIAL:
984 + /* TODO: Init NVRAM using BCMA_SOC_FLASH2 window */
985 + break;
986 + case BCMA_BOOT_DEV_NAND:
987 + /* TODO: Init NVRAM using BCMA_SOC_FLASH1 window */
988 + break;
989 + default:
990 + break;
991 + }
992 }
993
994 void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
995 --- a/include/linux/bcma/bcma_regs.h
996 +++ b/include/linux/bcma/bcma_regs.h
997 @@ -39,6 +39,11 @@
998 #define BCMA_RESET_CTL_RESET 0x0001
999 #define BCMA_RESET_ST 0x0804
1000
1001 +#define BCMA_NS_ROM_IOST_BOOT_DEV_MASK 0x0003
1002 +#define BCMA_NS_ROM_IOST_BOOT_DEV_NOR 0x0000
1003 +#define BCMA_NS_ROM_IOST_BOOT_DEV_NAND 0x0001
1004 +#define BCMA_NS_ROM_IOST_BOOT_DEV_ROM 0x0002
1005 +
1006 /* BCMA PCI config space registers. */
1007 #define BCMA_PCI_PMCSR 0x44
1008 #define BCMA_PCI_PE 0x100
1009 --- a/drivers/usb/host/bcma-hcd.c
1010 +++ b/drivers/usb/host/bcma-hcd.c
1011 @@ -237,7 +237,7 @@ static int bcma_hcd_probe(struct bcma_de
1012 bcma_hcd_init_chip(dev);
1013
1014 /* In AI chips EHCI is addrspace 0, OHCI is 1 */
1015 - ohci_addr = dev->addr1;
1016 + ohci_addr = dev->addr_s[0];
1017 if ((chipinfo->id == 0x5357 || chipinfo->id == 0x4749)
1018 && chipinfo->rev == 0)
1019 ohci_addr = 0x18009000;
1020 --- a/drivers/bcma/bcma_private.h
1021 +++ b/drivers/bcma/bcma_private.h
1022 @@ -50,6 +50,10 @@ void bcma_chipco_serial_init(struct bcma
1023 extern struct platform_device bcma_pflash_dev;
1024 #endif /* CONFIG_BCMA_DRIVER_MIPS */
1025
1026 +/* driver_chipcommon_b.c */
1027 +int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb);
1028 +void bcma_core_chipcommon_b_free(struct bcma_drv_cc_b *ccb);
1029 +
1030 /* driver_chipcommon_pmu.c */
1031 u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
1032 u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
1033 --- /dev/null
1034 +++ b/drivers/bcma/driver_chipcommon_b.c
1035 @@ -0,0 +1,61 @@
1036 +/*
1037 + * Broadcom specific AMBA
1038 + * ChipCommon B Unit driver
1039 + *
1040 + * Copyright 2014, Hauke Mehrtens <hauke@hauke-m.de>
1041 + *
1042 + * Licensed under the GNU/GPL. See COPYING for details.
1043 + */
1044 +
1045 +#include "bcma_private.h"
1046 +#include <linux/export.h>
1047 +#include <linux/bcma/bcma.h>
1048 +
1049 +static bool bcma_wait_reg(struct bcma_bus *bus, void __iomem *addr, u32 mask,
1050 + u32 value, int timeout)
1051 +{
1052 + unsigned long deadline = jiffies + timeout;
1053 + u32 val;
1054 +
1055 + do {
1056 + val = readl(addr);
1057 + if ((val & mask) == value)
1058 + return true;
1059 + cpu_relax();
1060 + udelay(10);
1061 + } while (!time_after_eq(jiffies, deadline));
1062 +
1063 + bcma_err(bus, "Timeout waiting for register %p\n", addr);
1064 +
1065 + return false;
1066 +}
1067 +
1068 +void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value)
1069 +{
1070 + struct bcma_bus *bus = ccb->core->bus;
1071 +
1072 + writel(offset, ccb->mii + 0x00);
1073 + bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100);
1074 + writel(value, ccb->mii + 0x04);
1075 + bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100);
1076 +}
1077 +EXPORT_SYMBOL_GPL(bcma_chipco_b_mii_write);
1078 +
1079 +int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb)
1080 +{
1081 + if (ccb->setup_done)
1082 + return 0;
1083 +
1084 + ccb->setup_done = 1;
1085 + ccb->mii = ioremap_nocache(ccb->core->addr_s[1], BCMA_CORE_SIZE);
1086 + if (!ccb->mii)
1087 + return -ENOMEM;
1088 +
1089 + return 0;
1090 +}
1091 +
1092 +void bcma_core_chipcommon_b_free(struct bcma_drv_cc_b *ccb)
1093 +{
1094 + if (ccb->mii)
1095 + iounmap(ccb->mii);
1096 +}
1097 --- a/include/linux/bcma/bcma_driver_chipcommon.h
1098 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
1099 @@ -644,6 +644,12 @@ struct bcma_drv_cc {
1100 #endif
1101 };
1102
1103 +struct bcma_drv_cc_b {
1104 + struct bcma_device *core;
1105 + u8 setup_done:1;
1106 + void __iomem *mii;
1107 +};
1108 +
1109 /* Register access */
1110 #define bcma_cc_read32(cc, offset) \
1111 bcma_read32((cc)->core, offset)
1112 @@ -699,4 +705,6 @@ extern void bcma_pmu_spuravoid_pllupdate
1113
1114 extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc);
1115
1116 +void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value);
1117 +
1118 #endif /* LINUX_BCMA_DRIVER_CC_H_ */
1119 --- a/arch/mips/bcm47xx/setup.c
1120 +++ b/arch/mips/bcm47xx/setup.c
1121 @@ -202,6 +202,10 @@ static void __init bcm47xx_register_bcma
1122
1123 err = bcma_host_soc_register(&bcm47xx_bus.bcma);
1124 if (err)
1125 + panic("Failed to register BCMA bus (err %d)", err);
1126 +
1127 + err = bcma_host_soc_init(&bcm47xx_bus.bcma);
1128 + if (err)
1129 panic("Failed to initialize BCMA bus (err %d)", err);
1130
1131 bcm47xx_fill_bcma_boardinfo(&bcm47xx_bus.bcma.bus.boardinfo, NULL);
1132 --- a/include/linux/bcma/bcma_soc.h
1133 +++ b/include/linux/bcma/bcma_soc.h
1134 @@ -10,6 +10,7 @@ struct bcma_soc {
1135 };
1136
1137 int __init bcma_host_soc_register(struct bcma_soc *soc);
1138 +int __init bcma_host_soc_init(struct bcma_soc *soc);
1139
1140 int bcma_bus_register(struct bcma_bus *bus);
1141
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