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kernel: update 3.10 to 3.10.34
[openwrt/openwrt.git] / target / linux / generic / patches-3.6 / 020-ssb_update.patch
1 --- a/arch/mips/bcm47xx/nvram.c
2 +++ b/arch/mips/bcm47xx/nvram.c
3 @@ -43,8 +43,8 @@ static void early_nvram_init(void)
4 #ifdef CONFIG_BCM47XX_SSB
5 case BCM47XX_BUS_TYPE_SSB:
6 mcore_ssb = &bcm47xx_bus.ssb.mipscore;
7 - base = mcore_ssb->flash_window;
8 - lim = mcore_ssb->flash_window_size;
9 + base = mcore_ssb->pflash.window;
10 + lim = mcore_ssb->pflash.window_size;
11 break;
12 #endif
13 #ifdef CONFIG_BCM47XX_BCMA
14 --- a/arch/mips/bcm47xx/wgt634u.c
15 +++ b/arch/mips/bcm47xx/wgt634u.c
16 @@ -156,10 +156,10 @@ static int __init wgt634u_init(void)
17 SSB_CHIPCO_IRQ_GPIO);
18 }
19
20 - wgt634u_flash_data.width = mcore->flash_buswidth;
21 - wgt634u_flash_resource.start = mcore->flash_window;
22 - wgt634u_flash_resource.end = mcore->flash_window
23 - + mcore->flash_window_size
24 + wgt634u_flash_data.width = mcore->pflash.buswidth;
25 + wgt634u_flash_resource.start = mcore->pflash.window;
26 + wgt634u_flash_resource.end = mcore->pflash.window
27 + + mcore->pflash.window_size
28 - 1;
29 return platform_add_devices(wgt634u_devices,
30 ARRAY_SIZE(wgt634u_devices));
31 --- a/drivers/ssb/Kconfig
32 +++ b/drivers/ssb/Kconfig
33 @@ -136,10 +136,15 @@ config SSB_DRIVER_MIPS
34
35 If unsure, say N
36
37 +config SSB_SFLASH
38 + bool "SSB serial flash support"
39 + depends on SSB_DRIVER_MIPS
40 + default y
41 +
42 # Assumption: We are on embedded, if we compile the MIPS core.
43 config SSB_EMBEDDED
44 bool
45 - depends on SSB_DRIVER_MIPS
46 + depends on SSB_DRIVER_MIPS && SSB_PCICORE_HOSTMODE
47 default y
48
49 config SSB_DRIVER_EXTIF
50 @@ -160,4 +165,12 @@ config SSB_DRIVER_GIGE
51
52 If unsure, say N
53
54 +config SSB_DRIVER_GPIO
55 + bool "SSB GPIO driver"
56 + depends on SSB && GPIOLIB
57 + help
58 + Driver to provide access to the GPIO pins on the bus.
59 +
60 + If unsure, say N
61 +
62 endmenu
63 --- a/drivers/ssb/Makefile
64 +++ b/drivers/ssb/Makefile
65 @@ -11,10 +11,12 @@ ssb-$(CONFIG_SSB_SDIOHOST) += sdio.o
66 # built-in drivers
67 ssb-y += driver_chipcommon.o
68 ssb-y += driver_chipcommon_pmu.o
69 +ssb-$(CONFIG_SSB_SFLASH) += driver_chipcommon_sflash.o
70 ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o
71 ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o
72 ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o
73 ssb-$(CONFIG_SSB_DRIVER_GIGE) += driver_gige.o
74 +ssb-$(CONFIG_SSB_DRIVER_GPIO) += driver_gpio.o
75
76 # b43 pci-ssb-bridge driver
77 # Not strictly a part of SSB, but kept here for convenience
78 --- a/drivers/ssb/b43_pci_bridge.c
79 +++ b/drivers/ssb/b43_pci_bridge.c
80 @@ -37,6 +37,7 @@ static const struct pci_device_id b43_pc
81 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
82 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
83 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
84 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4350) },
85 { 0, },
86 };
87 MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
88 --- a/drivers/ssb/driver_chipcommon.c
89 +++ b/drivers/ssb/driver_chipcommon.c
90 @@ -4,6 +4,7 @@
91 *
92 * Copyright 2005, Broadcom Corporation
93 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
94 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
95 *
96 * Licensed under the GNU/GPL. See COPYING for details.
97 */
98 @@ -12,6 +13,7 @@
99 #include <linux/ssb/ssb_regs.h>
100 #include <linux/export.h>
101 #include <linux/pci.h>
102 +#include <linux/bcm47xx_wdt.h>
103
104 #include "ssb_private.h"
105
106 @@ -280,13 +282,79 @@ static void calc_fast_powerup_delay(stru
107 cc->fast_pwrup_delay = tmp;
108 }
109
110 +static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc)
111 +{
112 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
113 + return ssb_pmu_get_alp_clock(cc);
114 +
115 + return 20000000;
116 +}
117 +
118 +static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc)
119 +{
120 + u32 nb;
121 +
122 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
123 + if (cc->dev->id.revision < 26)
124 + nb = 16;
125 + else
126 + nb = (cc->dev->id.revision >= 37) ? 32 : 24;
127 + } else {
128 + nb = 28;
129 + }
130 + if (nb == 32)
131 + return 0xffffffff;
132 + else
133 + return (1 << nb) - 1;
134 +}
135 +
136 +u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
137 +{
138 + struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
139 +
140 + if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
141 + return 0;
142 +
143 + return ssb_chipco_watchdog_timer_set(cc, ticks);
144 +}
145 +
146 +u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
147 +{
148 + struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
149 + u32 ticks;
150 +
151 + if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
152 + return 0;
153 +
154 + ticks = ssb_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
155 + return ticks / cc->ticks_per_ms;
156 +}
157 +
158 +static int ssb_chipco_watchdog_ticks_per_ms(struct ssb_chipcommon *cc)
159 +{
160 + struct ssb_bus *bus = cc->dev->bus;
161 +
162 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
163 + /* based on 32KHz ILP clock */
164 + return 32;
165 + } else {
166 + if (cc->dev->id.revision < 18)
167 + return ssb_clockspeed(bus) / 1000;
168 + else
169 + return ssb_chipco_alp_clock(cc) / 1000;
170 + }
171 +}
172 +
173 void ssb_chipcommon_init(struct ssb_chipcommon *cc)
174 {
175 if (!cc->dev)
176 return; /* We don't have a ChipCommon */
177 +
178 + spin_lock_init(&cc->gpio_lock);
179 +
180 if (cc->dev->id.revision >= 11)
181 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
182 - ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
183 + ssb_dbg("chipcommon status is 0x%x\n", cc->status);
184
185 if (cc->dev->id.revision >= 20) {
186 chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
187 @@ -297,6 +365,11 @@ void ssb_chipcommon_init(struct ssb_chip
188 chipco_powercontrol_init(cc);
189 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
190 calc_fast_powerup_delay(cc);
191 +
192 + if (cc->dev->bus->bustype == SSB_BUSTYPE_SSB) {
193 + cc->ticks_per_ms = ssb_chipco_watchdog_ticks_per_ms(cc);
194 + cc->max_timer_ms = ssb_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
195 + }
196 }
197
198 void ssb_chipco_suspend(struct ssb_chipcommon *cc)
199 @@ -395,10 +468,27 @@ void ssb_chipco_timing_init(struct ssb_c
200 }
201
202 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
203 -void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
204 +u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
205 {
206 - /* instant NMI */
207 - chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
208 + u32 maxt;
209 + enum ssb_clkmode clkmode;
210 +
211 + maxt = ssb_chipco_watchdog_get_max_timer(cc);
212 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
213 + if (ticks == 1)
214 + ticks = 2;
215 + else if (ticks > maxt)
216 + ticks = maxt;
217 + chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks);
218 + } else {
219 + clkmode = ticks ? SSB_CLKMODE_FAST : SSB_CLKMODE_DYNAMIC;
220 + ssb_chipco_set_clockmode(cc, clkmode);
221 + if (ticks > maxt)
222 + ticks = maxt;
223 + /* instant NMI */
224 + chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
225 + }
226 + return ticks;
227 }
228
229 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
230 @@ -418,28 +508,93 @@ u32 ssb_chipco_gpio_in(struct ssb_chipco
231
232 u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
233 {
234 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
235 + unsigned long flags;
236 + u32 res = 0;
237 +
238 + spin_lock_irqsave(&cc->gpio_lock, flags);
239 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
240 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
241 +
242 + return res;
243 }
244
245 u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
246 {
247 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
248 + unsigned long flags;
249 + u32 res = 0;
250 +
251 + spin_lock_irqsave(&cc->gpio_lock, flags);
252 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
253 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
254 +
255 + return res;
256 }
257
258 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
259 {
260 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
261 + unsigned long flags;
262 + u32 res = 0;
263 +
264 + spin_lock_irqsave(&cc->gpio_lock, flags);
265 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
266 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
267 +
268 + return res;
269 }
270 EXPORT_SYMBOL(ssb_chipco_gpio_control);
271
272 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
273 {
274 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
275 + unsigned long flags;
276 + u32 res = 0;
277 +
278 + spin_lock_irqsave(&cc->gpio_lock, flags);
279 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
280 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
281 +
282 + return res;
283 }
284
285 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
286 {
287 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
288 + unsigned long flags;
289 + u32 res = 0;
290 +
291 + spin_lock_irqsave(&cc->gpio_lock, flags);
292 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
293 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
294 +
295 + return res;
296 +}
297 +
298 +u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value)
299 +{
300 + unsigned long flags;
301 + u32 res = 0;
302 +
303 + if (cc->dev->id.revision < 20)
304 + return 0xffffffff;
305 +
306 + spin_lock_irqsave(&cc->gpio_lock, flags);
307 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLUP, mask, value);
308 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
309 +
310 + return res;
311 +}
312 +
313 +u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value)
314 +{
315 + unsigned long flags;
316 + u32 res = 0;
317 +
318 + if (cc->dev->id.revision < 20)
319 + return 0xffffffff;
320 +
321 + spin_lock_irqsave(&cc->gpio_lock, flags);
322 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLDOWN, mask, value);
323 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
324 +
325 + return res;
326 }
327
328 #ifdef CONFIG_SSB_SERIAL
329 @@ -473,12 +628,7 @@ int ssb_chipco_serial_init(struct ssb_ch
330 chipco_read32(cc, SSB_CHIPCO_CORECTL)
331 | SSB_CHIPCO_CORECTL_UARTCLK0);
332 } else if ((ccrev >= 11) && (ccrev != 15)) {
333 - /* Fixed ALP clock */
334 - baud_base = 20000000;
335 - if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
336 - /* FIXME: baud_base is different for devices with a PMU */
337 - SSB_WARN_ON(1);
338 - }
339 + baud_base = ssb_chipco_alp_clock(cc);
340 div = 1;
341 if (ccrev >= 21) {
342 /* Turn off UART clock before switching clocksource. */
343 --- a/drivers/ssb/driver_chipcommon_pmu.c
344 +++ b/drivers/ssb/driver_chipcommon_pmu.c
345 @@ -110,8 +110,8 @@ static void ssb_pmu0_pllinit_r0(struct s
346 return;
347 }
348
349 - ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
350 - (crystalfreq / 1000), (crystalfreq % 1000));
351 + ssb_info("Programming PLL to %u.%03u MHz\n",
352 + crystalfreq / 1000, crystalfreq % 1000);
353
354 /* First turn the PLL off. */
355 switch (bus->chip_id) {
356 @@ -138,7 +138,7 @@ static void ssb_pmu0_pllinit_r0(struct s
357 }
358 tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
359 if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
360 - ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n");
361 + ssb_emerg("Failed to turn the PLL off!\n");
362
363 /* Set PDIV in PLL control 0. */
364 pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL0);
365 @@ -249,8 +249,8 @@ static void ssb_pmu1_pllinit_r0(struct s
366 return;
367 }
368
369 - ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
370 - (crystalfreq / 1000), (crystalfreq % 1000));
371 + ssb_info("Programming PLL to %u.%03u MHz\n",
372 + crystalfreq / 1000, crystalfreq % 1000);
373
374 /* First turn the PLL off. */
375 switch (bus->chip_id) {
376 @@ -275,7 +275,7 @@ static void ssb_pmu1_pllinit_r0(struct s
377 }
378 tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
379 if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
380 - ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n");
381 + ssb_emerg("Failed to turn the PLL off!\n");
382
383 /* Set p1div and p2div. */
384 pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL0);
385 @@ -346,10 +346,11 @@ static void ssb_pmu_pll_init(struct ssb_
386 chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
387 }
388 break;
389 + case 43222:
390 + break;
391 default:
392 - ssb_printk(KERN_ERR PFX
393 - "ERROR: PLL init unknown for device %04X\n",
394 - bus->chip_id);
395 + ssb_err("ERROR: PLL init unknown for device %04X\n",
396 + bus->chip_id);
397 }
398 }
399
400 @@ -434,6 +435,7 @@ static void ssb_pmu_resources_init(struc
401 min_msk = 0xCBB;
402 break;
403 case 0x4322:
404 + case 43222:
405 /* We keep the default settings:
406 * min_msk = 0xCBB
407 * max_msk = 0x7FFFF
408 @@ -469,9 +471,8 @@ static void ssb_pmu_resources_init(struc
409 max_msk = 0xFFFFF;
410 break;
411 default:
412 - ssb_printk(KERN_ERR PFX
413 - "ERROR: PMU resource config unknown for device %04X\n",
414 - bus->chip_id);
415 + ssb_err("ERROR: PMU resource config unknown for device %04X\n",
416 + bus->chip_id);
417 }
418
419 if (updown_tab) {
420 @@ -523,8 +524,8 @@ void ssb_pmu_init(struct ssb_chipcommon
421 pmucap = chipco_read32(cc, SSB_CHIPCO_PMU_CAP);
422 cc->pmu.rev = (pmucap & SSB_CHIPCO_PMU_CAP_REVISION);
423
424 - ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n",
425 - cc->pmu.rev, pmucap);
426 + ssb_dbg("Found rev %u PMU (capabilities 0x%08X)\n",
427 + cc->pmu.rev, pmucap);
428
429 if (cc->pmu.rev == 1)
430 chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
431 @@ -615,6 +616,32 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
432 EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
433 EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
434
435 +static u32 ssb_pmu_get_alp_clock_clk0(struct ssb_chipcommon *cc)
436 +{
437 + u32 crystalfreq;
438 + const struct pmu0_plltab_entry *e = NULL;
439 +
440 + crystalfreq = chipco_read32(cc, SSB_CHIPCO_PMU_CTL) &
441 + SSB_CHIPCO_PMU_CTL_XTALFREQ >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT;
442 + e = pmu0_plltab_find_entry(crystalfreq);
443 + BUG_ON(!e);
444 + return e->freq * 1000;
445 +}
446 +
447 +u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc)
448 +{
449 + struct ssb_bus *bus = cc->dev->bus;
450 +
451 + switch (bus->chip_id) {
452 + case 0x5354:
453 + ssb_pmu_get_alp_clock_clk0(cc);
454 + default:
455 + ssb_err("ERROR: PMU alp clock unknown for device %04X\n",
456 + bus->chip_id);
457 + return 0;
458 + }
459 +}
460 +
461 u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
462 {
463 struct ssb_bus *bus = cc->dev->bus;
464 @@ -624,9 +651,8 @@ u32 ssb_pmu_get_cpu_clock(struct ssb_chi
465 /* 5354 chip uses a non programmable PLL of frequency 240MHz */
466 return 240000000;
467 default:
468 - ssb_printk(KERN_ERR PFX
469 - "ERROR: PMU cpu clock unknown for device %04X\n",
470 - bus->chip_id);
471 + ssb_err("ERROR: PMU cpu clock unknown for device %04X\n",
472 + bus->chip_id);
473 return 0;
474 }
475 }
476 @@ -639,9 +665,52 @@ u32 ssb_pmu_get_controlclock(struct ssb_
477 case 0x5354:
478 return 120000000;
479 default:
480 - ssb_printk(KERN_ERR PFX
481 - "ERROR: PMU controlclock unknown for device %04X\n",
482 - bus->chip_id);
483 + ssb_err("ERROR: PMU controlclock unknown for device %04X\n",
484 + bus->chip_id);
485 return 0;
486 }
487 }
488 +
489 +void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid)
490 +{
491 + u32 pmu_ctl = 0;
492 +
493 + switch (cc->dev->bus->chip_id) {
494 + case 0x4322:
495 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100070);
496 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x1014140a);
497 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888854);
498 + if (spuravoid == 1)
499 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05201828);
500 + else
501 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05001828);
502 + pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD;
503 + break;
504 + case 43222:
505 + if (spuravoid == 1) {
506 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11500008);
507 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0C000C06);
508 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x0F600a08);
509 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000);
510 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x2001E920);
511 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888815);
512 + } else {
513 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100008);
514 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0c000c06);
515 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x03000a08);
516 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000);
517 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x200005c0);
518 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888855);
519 + }
520 + pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD;
521 + break;
522 + default:
523 + ssb_printk(KERN_ERR PFX
524 + "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
525 + cc->dev->bus->chip_id);
526 + return;
527 + }
528 +
529 + chipco_set32(cc, SSB_CHIPCO_PMU_CTL, pmu_ctl);
530 +}
531 +EXPORT_SYMBOL_GPL(ssb_pmu_spuravoid_pllupdate);
532 --- /dev/null
533 +++ b/drivers/ssb/driver_chipcommon_sflash.c
534 @@ -0,0 +1,164 @@
535 +/*
536 + * Sonics Silicon Backplane
537 + * ChipCommon serial flash interface
538 + *
539 + * Licensed under the GNU/GPL. See COPYING for details.
540 + */
541 +
542 +#include <linux/ssb/ssb.h>
543 +
544 +#include "ssb_private.h"
545 +
546 +static struct resource ssb_sflash_resource = {
547 + .name = "ssb_sflash",
548 + .start = SSB_FLASH2,
549 + .end = 0,
550 + .flags = IORESOURCE_MEM | IORESOURCE_READONLY,
551 +};
552 +
553 +struct platform_device ssb_sflash_dev = {
554 + .name = "ssb_sflash",
555 + .resource = &ssb_sflash_resource,
556 + .num_resources = 1,
557 +};
558 +
559 +struct ssb_sflash_tbl_e {
560 + char *name;
561 + u32 id;
562 + u32 blocksize;
563 + u16 numblocks;
564 +};
565 +
566 +static const struct ssb_sflash_tbl_e ssb_sflash_st_tbl[] = {
567 + { "M25P20", 0x11, 0x10000, 4, },
568 + { "M25P40", 0x12, 0x10000, 8, },
569 +
570 + { "M25P16", 0x14, 0x10000, 32, },
571 + { "M25P32", 0x15, 0x10000, 64, },
572 + { "M25P64", 0x16, 0x10000, 128, },
573 + { "M25FL128", 0x17, 0x10000, 256, },
574 + { 0 },
575 +};
576 +
577 +static const struct ssb_sflash_tbl_e ssb_sflash_sst_tbl[] = {
578 + { "SST25WF512", 1, 0x1000, 16, },
579 + { "SST25VF512", 0x48, 0x1000, 16, },
580 + { "SST25WF010", 2, 0x1000, 32, },
581 + { "SST25VF010", 0x49, 0x1000, 32, },
582 + { "SST25WF020", 3, 0x1000, 64, },
583 + { "SST25VF020", 0x43, 0x1000, 64, },
584 + { "SST25WF040", 4, 0x1000, 128, },
585 + { "SST25VF040", 0x44, 0x1000, 128, },
586 + { "SST25VF040B", 0x8d, 0x1000, 128, },
587 + { "SST25WF080", 5, 0x1000, 256, },
588 + { "SST25VF080B", 0x8e, 0x1000, 256, },
589 + { "SST25VF016", 0x41, 0x1000, 512, },
590 + { "SST25VF032", 0x4a, 0x1000, 1024, },
591 + { "SST25VF064", 0x4b, 0x1000, 2048, },
592 + { 0 },
593 +};
594 +
595 +static const struct ssb_sflash_tbl_e ssb_sflash_at_tbl[] = {
596 + { "AT45DB011", 0xc, 256, 512, },
597 + { "AT45DB021", 0x14, 256, 1024, },
598 + { "AT45DB041", 0x1c, 256, 2048, },
599 + { "AT45DB081", 0x24, 256, 4096, },
600 + { "AT45DB161", 0x2c, 512, 4096, },
601 + { "AT45DB321", 0x34, 512, 8192, },
602 + { "AT45DB642", 0x3c, 1024, 8192, },
603 + { 0 },
604 +};
605 +
606 +static void ssb_sflash_cmd(struct ssb_chipcommon *cc, u32 opcode)
607 +{
608 + int i;
609 + chipco_write32(cc, SSB_CHIPCO_FLASHCTL,
610 + SSB_CHIPCO_FLASHCTL_START | opcode);
611 + for (i = 0; i < 1000; i++) {
612 + if (!(chipco_read32(cc, SSB_CHIPCO_FLASHCTL) &
613 + SSB_CHIPCO_FLASHCTL_BUSY))
614 + return;
615 + cpu_relax();
616 + }
617 + pr_err("SFLASH control command failed (timeout)!\n");
618 +}
619 +
620 +/* Initialize serial flash access */
621 +int ssb_sflash_init(struct ssb_chipcommon *cc)
622 +{
623 + struct ssb_sflash *sflash = &cc->dev->bus->mipscore.sflash;
624 + const struct ssb_sflash_tbl_e *e;
625 + u32 id, id2;
626 +
627 + switch (cc->capabilities & SSB_CHIPCO_CAP_FLASHT) {
628 + case SSB_CHIPCO_FLASHT_STSER:
629 + ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_DP);
630 +
631 + chipco_write32(cc, SSB_CHIPCO_FLASHADDR, 0);
632 + ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_RES);
633 + id = chipco_read32(cc, SSB_CHIPCO_FLASHDATA);
634 +
635 + chipco_write32(cc, SSB_CHIPCO_FLASHADDR, 1);
636 + ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_RES);
637 + id2 = chipco_read32(cc, SSB_CHIPCO_FLASHDATA);
638 +
639 + switch (id) {
640 + case 0xbf:
641 + for (e = ssb_sflash_sst_tbl; e->name; e++) {
642 + if (e->id == id2)
643 + break;
644 + }
645 + break;
646 + case 0x13:
647 + return -ENOTSUPP;
648 + default:
649 + for (e = ssb_sflash_st_tbl; e->name; e++) {
650 + if (e->id == id)
651 + break;
652 + }
653 + break;
654 + }
655 + if (!e->name) {
656 + pr_err("Unsupported ST serial flash (id: 0x%X, id2: 0x%X)\n",
657 + id, id2);
658 + return -ENOTSUPP;
659 + }
660 +
661 + break;
662 + case SSB_CHIPCO_FLASHT_ATSER:
663 + ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_AT_STATUS);
664 + id = chipco_read32(cc, SSB_CHIPCO_FLASHDATA) & 0x3c;
665 +
666 + for (e = ssb_sflash_at_tbl; e->name; e++) {
667 + if (e->id == id)
668 + break;
669 + }
670 + if (!e->name) {
671 + pr_err("Unsupported Atmel serial flash (id: 0x%X)\n",
672 + id);
673 + return -ENOTSUPP;
674 + }
675 +
676 + break;
677 + default:
678 + pr_err("Unsupported flash type\n");
679 + return -ENOTSUPP;
680 + }
681 +
682 + sflash->window = SSB_FLASH2;
683 + sflash->blocksize = e->blocksize;
684 + sflash->numblocks = e->numblocks;
685 + sflash->size = sflash->blocksize * sflash->numblocks;
686 + sflash->present = true;
687 +
688 + pr_info("Found %s serial flash (size: %dKiB, blocksize: 0x%X, blocks: %d)\n",
689 + e->name, sflash->size / 1024, e->blocksize, e->numblocks);
690 +
691 + /* Prepare platform device, but don't register it yet. It's too early,
692 + * malloc (required by device_private_init) is not available yet. */
693 + ssb_sflash_dev.resource[0].end = ssb_sflash_dev.resource[0].start +
694 + sflash->size;
695 + ssb_sflash_dev.dev.platform_data = sflash;
696 +
697 + return 0;
698 +}
699 --- a/drivers/ssb/driver_extif.c
700 +++ b/drivers/ssb/driver_extif.c
701 @@ -112,10 +112,37 @@ void ssb_extif_get_clockcontrol(struct s
702 *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
703 }
704
705 -void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
706 - u32 ticks)
707 +u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
708 {
709 + struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
710 +
711 + return ssb_extif_watchdog_timer_set(extif, ticks);
712 +}
713 +
714 +u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
715 +{
716 + struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
717 + u32 ticks = (SSB_EXTIF_WATCHDOG_CLK / 1000) * ms;
718 +
719 + ticks = ssb_extif_watchdog_timer_set(extif, ticks);
720 +
721 + return (ticks * 1000) / SSB_EXTIF_WATCHDOG_CLK;
722 +}
723 +
724 +u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
725 +{
726 + if (ticks > SSB_EXTIF_WATCHDOG_MAX_TIMER)
727 + ticks = SSB_EXTIF_WATCHDOG_MAX_TIMER;
728 extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks);
729 +
730 + return ticks;
731 +}
732 +
733 +void ssb_extif_init(struct ssb_extif *extif)
734 +{
735 + if (!extif->dev)
736 + return; /* We don't have a Extif core */
737 + spin_lock_init(&extif->gpio_lock);
738 }
739
740 u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
741 @@ -125,22 +152,50 @@ u32 ssb_extif_gpio_in(struct ssb_extif *
742
743 u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value)
744 {
745 - return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
746 + unsigned long flags;
747 + u32 res = 0;
748 +
749 + spin_lock_irqsave(&extif->gpio_lock, flags);
750 + res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
751 mask, value);
752 + spin_unlock_irqrestore(&extif->gpio_lock, flags);
753 +
754 + return res;
755 }
756
757 u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value)
758 {
759 - return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
760 + unsigned long flags;
761 + u32 res = 0;
762 +
763 + spin_lock_irqsave(&extif->gpio_lock, flags);
764 + res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
765 mask, value);
766 + spin_unlock_irqrestore(&extif->gpio_lock, flags);
767 +
768 + return res;
769 }
770
771 u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value)
772 {
773 - return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
774 + unsigned long flags;
775 + u32 res = 0;
776 +
777 + spin_lock_irqsave(&extif->gpio_lock, flags);
778 + res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
779 + spin_unlock_irqrestore(&extif->gpio_lock, flags);
780 +
781 + return res;
782 }
783
784 u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value)
785 {
786 - return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
787 + unsigned long flags;
788 + u32 res = 0;
789 +
790 + spin_lock_irqsave(&extif->gpio_lock, flags);
791 + res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
792 + spin_unlock_irqrestore(&extif->gpio_lock, flags);
793 +
794 + return res;
795 }
796 --- /dev/null
797 +++ b/drivers/ssb/driver_gpio.c
798 @@ -0,0 +1,210 @@
799 +/*
800 + * Sonics Silicon Backplane
801 + * GPIO driver
802 + *
803 + * Copyright 2011, Broadcom Corporation
804 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
805 + *
806 + * Licensed under the GNU/GPL. See COPYING for details.
807 + */
808 +
809 +#include <linux/gpio.h>
810 +#include <linux/export.h>
811 +#include <linux/ssb/ssb.h>
812 +
813 +#include "ssb_private.h"
814 +
815 +static struct ssb_bus *ssb_gpio_get_bus(struct gpio_chip *chip)
816 +{
817 + return container_of(chip, struct ssb_bus, gpio);
818 +}
819 +
820 +static int ssb_gpio_chipco_get_value(struct gpio_chip *chip, unsigned gpio)
821 +{
822 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
823 +
824 + return !!ssb_chipco_gpio_in(&bus->chipco, 1 << gpio);
825 +}
826 +
827 +static void ssb_gpio_chipco_set_value(struct gpio_chip *chip, unsigned gpio,
828 + int value)
829 +{
830 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
831 +
832 + ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0);
833 +}
834 +
835 +static int ssb_gpio_chipco_direction_input(struct gpio_chip *chip,
836 + unsigned gpio)
837 +{
838 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
839 +
840 + ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 0);
841 + return 0;
842 +}
843 +
844 +static int ssb_gpio_chipco_direction_output(struct gpio_chip *chip,
845 + unsigned gpio, int value)
846 +{
847 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
848 +
849 + ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 1 << gpio);
850 + ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0);
851 + return 0;
852 +}
853 +
854 +static int ssb_gpio_chipco_request(struct gpio_chip *chip, unsigned gpio)
855 +{
856 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
857 +
858 + ssb_chipco_gpio_control(&bus->chipco, 1 << gpio, 0);
859 + /* clear pulldown */
860 + ssb_chipco_gpio_pulldown(&bus->chipco, 1 << gpio, 0);
861 + /* Set pullup */
862 + ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 1 << gpio);
863 +
864 + return 0;
865 +}
866 +
867 +static void ssb_gpio_chipco_free(struct gpio_chip *chip, unsigned gpio)
868 +{
869 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
870 +
871 + /* clear pullup */
872 + ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 0);
873 +}
874 +
875 +static int ssb_gpio_chipco_to_irq(struct gpio_chip *chip, unsigned gpio)
876 +{
877 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
878 +
879 + if (bus->bustype == SSB_BUSTYPE_SSB)
880 + return ssb_mips_irq(bus->chipco.dev) + 2;
881 + else
882 + return -EINVAL;
883 +}
884 +
885 +static int ssb_gpio_chipco_init(struct ssb_bus *bus)
886 +{
887 + struct gpio_chip *chip = &bus->gpio;
888 +
889 + chip->label = "ssb_chipco_gpio";
890 + chip->owner = THIS_MODULE;
891 + chip->request = ssb_gpio_chipco_request;
892 + chip->free = ssb_gpio_chipco_free;
893 + chip->get = ssb_gpio_chipco_get_value;
894 + chip->set = ssb_gpio_chipco_set_value;
895 + chip->direction_input = ssb_gpio_chipco_direction_input;
896 + chip->direction_output = ssb_gpio_chipco_direction_output;
897 + chip->to_irq = ssb_gpio_chipco_to_irq;
898 + chip->ngpio = 16;
899 + /* There is just one SoC in one device and its GPIO addresses should be
900 + * deterministic to address them more easily. The other buses could get
901 + * a random base number. */
902 + if (bus->bustype == SSB_BUSTYPE_SSB)
903 + chip->base = 0;
904 + else
905 + chip->base = -1;
906 +
907 + return gpiochip_add(chip);
908 +}
909 +
910 +#ifdef CONFIG_SSB_DRIVER_EXTIF
911 +
912 +static int ssb_gpio_extif_get_value(struct gpio_chip *chip, unsigned gpio)
913 +{
914 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
915 +
916 + return !!ssb_extif_gpio_in(&bus->extif, 1 << gpio);
917 +}
918 +
919 +static void ssb_gpio_extif_set_value(struct gpio_chip *chip, unsigned gpio,
920 + int value)
921 +{
922 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
923 +
924 + ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0);
925 +}
926 +
927 +static int ssb_gpio_extif_direction_input(struct gpio_chip *chip,
928 + unsigned gpio)
929 +{
930 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
931 +
932 + ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 0);
933 + return 0;
934 +}
935 +
936 +static int ssb_gpio_extif_direction_output(struct gpio_chip *chip,
937 + unsigned gpio, int value)
938 +{
939 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
940 +
941 + ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 1 << gpio);
942 + ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0);
943 + return 0;
944 +}
945 +
946 +static int ssb_gpio_extif_to_irq(struct gpio_chip *chip, unsigned gpio)
947 +{
948 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
949 +
950 + if (bus->bustype == SSB_BUSTYPE_SSB)
951 + return ssb_mips_irq(bus->extif.dev) + 2;
952 + else
953 + return -EINVAL;
954 +}
955 +
956 +static int ssb_gpio_extif_init(struct ssb_bus *bus)
957 +{
958 + struct gpio_chip *chip = &bus->gpio;
959 +
960 + chip->label = "ssb_extif_gpio";
961 + chip->owner = THIS_MODULE;
962 + chip->get = ssb_gpio_extif_get_value;
963 + chip->set = ssb_gpio_extif_set_value;
964 + chip->direction_input = ssb_gpio_extif_direction_input;
965 + chip->direction_output = ssb_gpio_extif_direction_output;
966 + chip->to_irq = ssb_gpio_extif_to_irq;
967 + chip->ngpio = 5;
968 + /* There is just one SoC in one device and its GPIO addresses should be
969 + * deterministic to address them more easily. The other buses could get
970 + * a random base number. */
971 + if (bus->bustype == SSB_BUSTYPE_SSB)
972 + chip->base = 0;
973 + else
974 + chip->base = -1;
975 +
976 + return gpiochip_add(chip);
977 +}
978 +
979 +#else
980 +static int ssb_gpio_extif_init(struct ssb_bus *bus)
981 +{
982 + return -ENOTSUPP;
983 +}
984 +#endif
985 +
986 +int ssb_gpio_init(struct ssb_bus *bus)
987 +{
988 + if (ssb_chipco_available(&bus->chipco))
989 + return ssb_gpio_chipco_init(bus);
990 + else if (ssb_extif_available(&bus->extif))
991 + return ssb_gpio_extif_init(bus);
992 + else
993 + SSB_WARN_ON(1);
994 +
995 + return -1;
996 +}
997 +
998 +int ssb_gpio_unregister(struct ssb_bus *bus)
999 +{
1000 + if (ssb_chipco_available(&bus->chipco) ||
1001 + ssb_extif_available(&bus->extif)) {
1002 + return gpiochip_remove(&bus->gpio);
1003 + } else {
1004 + SSB_WARN_ON(1);
1005 + }
1006 +
1007 + return -1;
1008 +}
1009 --- a/drivers/ssb/driver_mipscore.c
1010 +++ b/drivers/ssb/driver_mipscore.c
1011 @@ -10,6 +10,7 @@
1012
1013 #include <linux/ssb/ssb.h>
1014
1015 +#include <linux/mtd/physmap.h>
1016 #include <linux/serial.h>
1017 #include <linux/serial_core.h>
1018 #include <linux/serial_reg.h>
1019 @@ -17,6 +18,25 @@
1020
1021 #include "ssb_private.h"
1022
1023 +static const char * const part_probes[] = { "bcm47xxpart", NULL };
1024 +
1025 +static struct physmap_flash_data ssb_pflash_data = {
1026 + .part_probe_types = part_probes,
1027 +};
1028 +
1029 +static struct resource ssb_pflash_resource = {
1030 + .name = "ssb_pflash",
1031 + .flags = IORESOURCE_MEM,
1032 +};
1033 +
1034 +struct platform_device ssb_pflash_dev = {
1035 + .name = "physmap-flash",
1036 + .dev = {
1037 + .platform_data = &ssb_pflash_data,
1038 + },
1039 + .resource = &ssb_pflash_resource,
1040 + .num_resources = 1,
1041 +};
1042
1043 static inline u32 mips_read32(struct ssb_mipscore *mcore,
1044 u16 offset)
1045 @@ -147,21 +167,22 @@ static void set_irq(struct ssb_device *d
1046 irqflag |= (ipsflag & ~ipsflag_irq_mask[irq]);
1047 ssb_write32(mdev, SSB_IPSFLAG, irqflag);
1048 }
1049 - ssb_dprintk(KERN_INFO PFX
1050 - "set_irq: core 0x%04x, irq %d => %d\n",
1051 - dev->id.coreid, oldirq+2, irq+2);
1052 + ssb_dbg("set_irq: core 0x%04x, irq %d => %d\n",
1053 + dev->id.coreid, oldirq+2, irq+2);
1054 }
1055
1056 static void print_irq(struct ssb_device *dev, unsigned int irq)
1057 {
1058 - int i;
1059 static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
1060 - ssb_dprintk(KERN_INFO PFX
1061 - "core 0x%04x, irq :", dev->id.coreid);
1062 - for (i = 0; i <= 6; i++) {
1063 - ssb_dprintk(" %s%s", irq_name[i], i==irq?"*":" ");
1064 - }
1065 - ssb_dprintk("\n");
1066 + ssb_dbg("core 0x%04x, irq : %s%s %s%s %s%s %s%s %s%s %s%s %s%s\n",
1067 + dev->id.coreid,
1068 + irq_name[0], irq == 0 ? "*" : " ",
1069 + irq_name[1], irq == 1 ? "*" : " ",
1070 + irq_name[2], irq == 2 ? "*" : " ",
1071 + irq_name[3], irq == 3 ? "*" : " ",
1072 + irq_name[4], irq == 4 ? "*" : " ",
1073 + irq_name[5], irq == 5 ? "*" : " ",
1074 + irq_name[6], irq == 6 ? "*" : " ");
1075 }
1076
1077 static void dump_irq(struct ssb_bus *bus)
1078 @@ -178,9 +199,9 @@ static void ssb_mips_serial_init(struct
1079 {
1080 struct ssb_bus *bus = mcore->dev->bus;
1081
1082 - if (bus->extif.dev)
1083 + if (ssb_extif_available(&bus->extif))
1084 mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
1085 - else if (bus->chipco.dev)
1086 + else if (ssb_chipco_available(&bus->chipco))
1087 mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
1088 else
1089 mcore->nr_serial_ports = 0;
1090 @@ -189,17 +210,42 @@ static void ssb_mips_serial_init(struct
1091 static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
1092 {
1093 struct ssb_bus *bus = mcore->dev->bus;
1094 + struct ssb_pflash *pflash = &mcore->pflash;
1095
1096 - mcore->flash_buswidth = 2;
1097 - if (bus->chipco.dev) {
1098 - mcore->flash_window = 0x1c000000;
1099 - mcore->flash_window_size = 0x02000000;
1100 + /* When there is no chipcommon on the bus there is 4MB flash */
1101 + if (!ssb_chipco_available(&bus->chipco)) {
1102 + pflash->present = true;
1103 + pflash->buswidth = 2;
1104 + pflash->window = SSB_FLASH1;
1105 + pflash->window_size = SSB_FLASH1_SZ;
1106 + goto ssb_pflash;
1107 + }
1108 +
1109 + /* There is ChipCommon, so use it to read info about flash */
1110 + switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
1111 + case SSB_CHIPCO_FLASHT_STSER:
1112 + case SSB_CHIPCO_FLASHT_ATSER:
1113 + pr_debug("Found serial flash\n");
1114 + ssb_sflash_init(&bus->chipco);
1115 + break;
1116 + case SSB_CHIPCO_FLASHT_PARA:
1117 + pr_debug("Found parallel flash\n");
1118 + pflash->present = true;
1119 + pflash->window = SSB_FLASH2;
1120 + pflash->window_size = SSB_FLASH2_SZ;
1121 if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
1122 & SSB_CHIPCO_CFG_DS16) == 0)
1123 - mcore->flash_buswidth = 1;
1124 - } else {
1125 - mcore->flash_window = 0x1fc00000;
1126 - mcore->flash_window_size = 0x00400000;
1127 + pflash->buswidth = 1;
1128 + else
1129 + pflash->buswidth = 2;
1130 + break;
1131 + }
1132 +
1133 +ssb_pflash:
1134 + if (pflash->present) {
1135 + ssb_pflash_data.width = pflash->buswidth;
1136 + ssb_pflash_resource.start = pflash->window;
1137 + ssb_pflash_resource.end = pflash->window + pflash->window_size;
1138 }
1139 }
1140
1141 @@ -211,9 +257,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
1142 if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
1143 return ssb_pmu_get_cpu_clock(&bus->chipco);
1144
1145 - if (bus->extif.dev) {
1146 + if (ssb_extif_available(&bus->extif)) {
1147 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
1148 - } else if (bus->chipco.dev) {
1149 + } else if (ssb_chipco_available(&bus->chipco)) {
1150 ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
1151 } else
1152 return 0;
1153 @@ -241,7 +287,7 @@ void ssb_mipscore_init(struct ssb_mipsco
1154 if (!mcore->dev)
1155 return; /* We don't have a MIPS core */
1156
1157 - ssb_dprintk(KERN_INFO PFX "Initializing MIPS core...\n");
1158 + ssb_dbg("Initializing MIPS core...\n");
1159
1160 bus = mcore->dev->bus;
1161 hz = ssb_clockspeed(bus);
1162 @@ -249,9 +295,9 @@ void ssb_mipscore_init(struct ssb_mipsco
1163 hz = 100000000;
1164 ns = 1000000000 / hz;
1165
1166 - if (bus->extif.dev)
1167 + if (ssb_extif_available(&bus->extif))
1168 ssb_extif_timing_init(&bus->extif, ns);
1169 - else if (bus->chipco.dev)
1170 + else if (ssb_chipco_available(&bus->chipco))
1171 ssb_chipco_timing_init(&bus->chipco, ns);
1172
1173 /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
1174 @@ -289,7 +335,7 @@ void ssb_mipscore_init(struct ssb_mipsco
1175 break;
1176 }
1177 }
1178 - ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
1179 + ssb_dbg("after irq reconfiguration\n");
1180 dump_irq(bus);
1181
1182 ssb_mips_serial_init(mcore);
1183 --- a/drivers/ssb/driver_pcicore.c
1184 +++ b/drivers/ssb/driver_pcicore.c
1185 @@ -263,8 +263,7 @@ int ssb_pcicore_plat_dev_init(struct pci
1186 return -ENODEV;
1187 }
1188
1189 - ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
1190 - pci_name(d));
1191 + ssb_info("PCI: Fixing up device %s\n", pci_name(d));
1192
1193 /* Fix up interrupt lines */
1194 d->irq = ssb_mips_irq(extpci_core->dev) + 2;
1195 @@ -285,12 +284,12 @@ static void ssb_pcicore_fixup_pcibridge(
1196 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
1197 return;
1198
1199 - ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
1200 + ssb_info("PCI: Fixing up bridge %s\n", pci_name(dev));
1201
1202 /* Enable PCI bridge bus mastering and memory space */
1203 pci_set_master(dev);
1204 if (pcibios_enable_device(dev, ~0) < 0) {
1205 - ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
1206 + ssb_err("PCI: SSB bridge enable failed\n");
1207 return;
1208 }
1209
1210 @@ -299,8 +298,8 @@ static void ssb_pcicore_fixup_pcibridge(
1211
1212 /* Make sure our latency is high enough to handle the devices behind us */
1213 lat = 168;
1214 - ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
1215 - pci_name(dev), lat);
1216 + ssb_info("PCI: Fixing latency timer of device %s to %u\n",
1217 + pci_name(dev), lat);
1218 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
1219 }
1220 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge);
1221 @@ -323,7 +322,7 @@ static void __devinit ssb_pcicore_init_h
1222 return;
1223 extpci_core = pc;
1224
1225 - ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n");
1226 + ssb_dbg("PCIcore in host mode found\n");
1227 /* Reset devices on the external PCI bus */
1228 val = SSB_PCICORE_CTL_RST_OE;
1229 val |= SSB_PCICORE_CTL_CLK_OE;
1230 @@ -338,7 +337,7 @@ static void __devinit ssb_pcicore_init_h
1231 udelay(1); /* Assertion time demanded by the PCI standard */
1232
1233 if (pc->dev->bus->has_cardbus_slot) {
1234 - ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n");
1235 + ssb_dbg("CardBus slot detected\n");
1236 pc->cardbusmode = 1;
1237 /* GPIO 1 resets the bridge */
1238 ssb_gpio_out(pc->dev->bus, 1, 1);
1239 --- a/drivers/ssb/embedded.c
1240 +++ b/drivers/ssb/embedded.c
1241 @@ -4,11 +4,13 @@
1242 *
1243 * Copyright 2005-2008, Broadcom Corporation
1244 * Copyright 2006-2008, Michael Buesch <m@bues.ch>
1245 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
1246 *
1247 * Licensed under the GNU/GPL. See COPYING for details.
1248 */
1249
1250 #include <linux/export.h>
1251 +#include <linux/platform_device.h>
1252 #include <linux/ssb/ssb.h>
1253 #include <linux/ssb/ssb_embedded.h>
1254 #include <linux/ssb/ssb_driver_pci.h>
1255 @@ -32,6 +34,38 @@ int ssb_watchdog_timer_set(struct ssb_bu
1256 }
1257 EXPORT_SYMBOL(ssb_watchdog_timer_set);
1258
1259 +int ssb_watchdog_register(struct ssb_bus *bus)
1260 +{
1261 + struct bcm47xx_wdt wdt = {};
1262 + struct platform_device *pdev;
1263 +
1264 + if (ssb_chipco_available(&bus->chipco)) {
1265 + wdt.driver_data = &bus->chipco;
1266 + wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt;
1267 + wdt.timer_set_ms = ssb_chipco_watchdog_timer_set_ms;
1268 + wdt.max_timer_ms = bus->chipco.max_timer_ms;
1269 + } else if (ssb_extif_available(&bus->extif)) {
1270 + wdt.driver_data = &bus->extif;
1271 + wdt.timer_set = ssb_extif_watchdog_timer_set_wdt;
1272 + wdt.timer_set_ms = ssb_extif_watchdog_timer_set_ms;
1273 + wdt.max_timer_ms = SSB_EXTIF_WATCHDOG_MAX_TIMER_MS;
1274 + } else {
1275 + return -ENODEV;
1276 + }
1277 +
1278 + pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
1279 + bus->busnumber, &wdt,
1280 + sizeof(wdt));
1281 + if (IS_ERR(pdev)) {
1282 + ssb_dbg("can not register watchdog device, err: %li\n",
1283 + PTR_ERR(pdev));
1284 + return PTR_ERR(pdev);
1285 + }
1286 +
1287 + bus->watchdog = pdev;
1288 + return 0;
1289 +}
1290 +
1291 u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask)
1292 {
1293 unsigned long flags;
1294 --- a/drivers/ssb/main.c
1295 +++ b/drivers/ssb/main.c
1296 @@ -13,6 +13,7 @@
1297 #include <linux/delay.h>
1298 #include <linux/io.h>
1299 #include <linux/module.h>
1300 +#include <linux/platform_device.h>
1301 #include <linux/ssb/ssb.h>
1302 #include <linux/ssb/ssb_regs.h>
1303 #include <linux/ssb/ssb_driver_gige.h>
1304 @@ -274,8 +275,8 @@ int ssb_devices_thaw(struct ssb_freeze_c
1305
1306 err = sdrv->probe(sdev, &sdev->id);
1307 if (err) {
1308 - ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
1309 - dev_name(sdev->dev));
1310 + ssb_err("Failed to thaw device %s\n",
1311 + dev_name(sdev->dev));
1312 result = err;
1313 }
1314 ssb_device_put(sdev);
1315 @@ -433,10 +434,23 @@ static void ssb_devices_unregister(struc
1316 if (sdev->dev)
1317 device_unregister(sdev->dev);
1318 }
1319 +
1320 +#ifdef CONFIG_SSB_EMBEDDED
1321 + if (bus->bustype == SSB_BUSTYPE_SSB)
1322 + platform_device_unregister(bus->watchdog);
1323 +#endif
1324 }
1325
1326 void ssb_bus_unregister(struct ssb_bus *bus)
1327 {
1328 + int err;
1329 +
1330 + err = ssb_gpio_unregister(bus);
1331 + if (err == -EBUSY)
1332 + ssb_dbg("Some GPIOs are still in use\n");
1333 + else if (err)
1334 + ssb_dbg("Can not unregister GPIO driver: %i\n", err);
1335 +
1336 ssb_buses_lock();
1337 ssb_devices_unregister(bus);
1338 list_del(&bus->list);
1339 @@ -482,8 +496,7 @@ static int ssb_devices_register(struct s
1340
1341 devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
1342 if (!devwrap) {
1343 - ssb_printk(KERN_ERR PFX
1344 - "Could not allocate device\n");
1345 + ssb_err("Could not allocate device\n");
1346 err = -ENOMEM;
1347 goto error;
1348 }
1349 @@ -522,9 +535,7 @@ static int ssb_devices_register(struct s
1350 sdev->dev = dev;
1351 err = device_register(dev);
1352 if (err) {
1353 - ssb_printk(KERN_ERR PFX
1354 - "Could not register %s\n",
1355 - dev_name(dev));
1356 + ssb_err("Could not register %s\n", dev_name(dev));
1357 /* Set dev to NULL to not unregister
1358 * dev on error unwinding. */
1359 sdev->dev = NULL;
1360 @@ -534,6 +545,22 @@ static int ssb_devices_register(struct s
1361 dev_idx++;
1362 }
1363
1364 +#ifdef CONFIG_SSB_DRIVER_MIPS
1365 + if (bus->mipscore.pflash.present) {
1366 + err = platform_device_register(&ssb_pflash_dev);
1367 + if (err)
1368 + pr_err("Error registering parallel flash\n");
1369 + }
1370 +#endif
1371 +
1372 +#ifdef CONFIG_SSB_SFLASH
1373 + if (bus->mipscore.sflash.present) {
1374 + err = platform_device_register(&ssb_sflash_dev);
1375 + if (err)
1376 + pr_err("Error registering serial flash\n");
1377 + }
1378 +#endif
1379 +
1380 return 0;
1381 error:
1382 /* Unwind the already registered devices. */
1383 @@ -561,6 +588,8 @@ static int __devinit ssb_attach_queued_b
1384 if (err)
1385 goto error;
1386 ssb_pcicore_init(&bus->pcicore);
1387 + if (bus->bustype == SSB_BUSTYPE_SSB)
1388 + ssb_watchdog_register(bus);
1389 ssb_bus_may_powerdown(bus);
1390
1391 err = ssb_devices_register(bus);
1392 @@ -796,7 +825,13 @@ static int __devinit ssb_bus_register(st
1393 if (err)
1394 goto err_pcmcia_exit;
1395 ssb_chipcommon_init(&bus->chipco);
1396 + ssb_extif_init(&bus->extif);
1397 ssb_mipscore_init(&bus->mipscore);
1398 + err = ssb_gpio_init(bus);
1399 + if (err == -ENOTSUPP)
1400 + ssb_dbg("GPIO driver not activated\n");
1401 + else if (err)
1402 + ssb_dbg("Error registering GPIO driver: %i\n", err);
1403 err = ssb_fetch_invariants(bus, get_invariants);
1404 if (err) {
1405 ssb_bus_may_powerdown(bus);
1406 @@ -847,11 +882,11 @@ int __devinit ssb_bus_pcibus_register(st
1407
1408 err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
1409 if (!err) {
1410 - ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
1411 - "PCI device %s\n", dev_name(&host_pci->dev));
1412 + ssb_info("Sonics Silicon Backplane found on PCI device %s\n",
1413 + dev_name(&host_pci->dev));
1414 } else {
1415 - ssb_printk(KERN_ERR PFX "Failed to register PCI version"
1416 - " of SSB with error %d\n", err);
1417 + ssb_err("Failed to register PCI version of SSB with error %d\n",
1418 + err);
1419 }
1420
1421 return err;
1422 @@ -872,8 +907,8 @@ int __devinit ssb_bus_pcmciabus_register
1423
1424 err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
1425 if (!err) {
1426 - ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
1427 - "PCMCIA device %s\n", pcmcia_dev->devname);
1428 + ssb_info("Sonics Silicon Backplane found on PCMCIA device %s\n",
1429 + pcmcia_dev->devname);
1430 }
1431
1432 return err;
1433 @@ -895,8 +930,8 @@ int __devinit ssb_bus_sdiobus_register(s
1434
1435 err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
1436 if (!err) {
1437 - ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
1438 - "SDIO device %s\n", sdio_func_id(func));
1439 + ssb_info("Sonics Silicon Backplane found on SDIO device %s\n",
1440 + sdio_func_id(func));
1441 }
1442
1443 return err;
1444 @@ -915,8 +950,8 @@ int __devinit ssb_bus_ssbbus_register(st
1445
1446 err = ssb_bus_register(bus, get_invariants, baseaddr);
1447 if (!err) {
1448 - ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at "
1449 - "address 0x%08lX\n", baseaddr);
1450 + ssb_info("Sonics Silicon Backplane found at address 0x%08lX\n",
1451 + baseaddr);
1452 }
1453
1454 return err;
1455 @@ -1118,8 +1153,7 @@ static u32 ssb_tmslow_reject_bitmask(str
1456 case SSB_IDLOW_SSBREV_27: /* same here */
1457 return SSB_TMSLOW_REJECT; /* this is a guess */
1458 default:
1459 - printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
1460 - WARN_ON(1);
1461 + WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
1462 }
1463 return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
1464 }
1465 @@ -1311,7 +1345,7 @@ out:
1466 #endif
1467 return err;
1468 error:
1469 - ssb_printk(KERN_ERR PFX "Bus powerdown failed\n");
1470 + ssb_err("Bus powerdown failed\n");
1471 goto out;
1472 }
1473 EXPORT_SYMBOL(ssb_bus_may_powerdown);
1474 @@ -1334,7 +1368,7 @@ int ssb_bus_powerup(struct ssb_bus *bus,
1475
1476 return 0;
1477 error:
1478 - ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
1479 + ssb_err("Bus powerup failed\n");
1480 return err;
1481 }
1482 EXPORT_SYMBOL(ssb_bus_powerup);
1483 @@ -1442,15 +1476,13 @@ static int __init ssb_modinit(void)
1484
1485 err = b43_pci_ssb_bridge_init();
1486 if (err) {
1487 - ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
1488 - "initialization failed\n");
1489 + ssb_err("Broadcom 43xx PCI-SSB-bridge initialization failed\n");
1490 /* don't fail SSB init because of this */
1491 err = 0;
1492 }
1493 err = ssb_gige_init();
1494 if (err) {
1495 - ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
1496 - "driver initialization failed\n");
1497 + ssb_err("SSB Broadcom Gigabit Ethernet driver initialization failed\n");
1498 /* don't fail SSB init because of this */
1499 err = 0;
1500 }
1501 --- a/drivers/ssb/pci.c
1502 +++ b/drivers/ssb/pci.c
1503 @@ -56,7 +56,7 @@ int ssb_pci_switch_coreidx(struct ssb_bu
1504 }
1505 return 0;
1506 error:
1507 - ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx);
1508 + ssb_err("Failed to switch to core %u\n", coreidx);
1509 return -ENODEV;
1510 }
1511
1512 @@ -67,10 +67,9 @@ int ssb_pci_switch_core(struct ssb_bus *
1513 unsigned long flags;
1514
1515 #if SSB_VERBOSE_PCICORESWITCH_DEBUG
1516 - ssb_printk(KERN_INFO PFX
1517 - "Switching to %s core, index %d\n",
1518 - ssb_core_name(dev->id.coreid),
1519 - dev->core_index);
1520 + ssb_info("Switching to %s core, index %d\n",
1521 + ssb_core_name(dev->id.coreid),
1522 + dev->core_index);
1523 #endif
1524
1525 spin_lock_irqsave(&bus->bar_lock, flags);
1526 @@ -231,6 +230,15 @@ static inline u8 ssb_crc8(u8 crc, u8 dat
1527 return t[crc ^ data];
1528 }
1529
1530 +static void sprom_get_mac(char *mac, const u16 *in)
1531 +{
1532 + int i;
1533 + for (i = 0; i < 3; i++) {
1534 + *mac++ = in[i] >> 8;
1535 + *mac++ = in[i];
1536 + }
1537 +}
1538 +
1539 static u8 ssb_sprom_crc(const u16 *sprom, u16 size)
1540 {
1541 int word;
1542 @@ -278,7 +286,7 @@ static int sprom_do_write(struct ssb_bus
1543 u32 spromctl;
1544 u16 size = bus->sprom_size;
1545
1546 - ssb_printk(KERN_NOTICE PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n");
1547 + ssb_notice("Writing SPROM. Do NOT turn off the power! Please stand by...\n");
1548 err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl);
1549 if (err)
1550 goto err_ctlreg;
1551 @@ -286,17 +294,17 @@ static int sprom_do_write(struct ssb_bus
1552 err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl);
1553 if (err)
1554 goto err_ctlreg;
1555 - ssb_printk(KERN_NOTICE PFX "[ 0%%");
1556 + ssb_notice("[ 0%%");
1557 msleep(500);
1558 for (i = 0; i < size; i++) {
1559 if (i == size / 4)
1560 - ssb_printk("25%%");
1561 + ssb_cont("25%%");
1562 else if (i == size / 2)
1563 - ssb_printk("50%%");
1564 + ssb_cont("50%%");
1565 else if (i == (size * 3) / 4)
1566 - ssb_printk("75%%");
1567 + ssb_cont("75%%");
1568 else if (i % 2)
1569 - ssb_printk(".");
1570 + ssb_cont(".");
1571 writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
1572 mmiowb();
1573 msleep(20);
1574 @@ -309,12 +317,12 @@ static int sprom_do_write(struct ssb_bus
1575 if (err)
1576 goto err_ctlreg;
1577 msleep(500);
1578 - ssb_printk("100%% ]\n");
1579 - ssb_printk(KERN_NOTICE PFX "SPROM written.\n");
1580 + ssb_cont("100%% ]\n");
1581 + ssb_notice("SPROM written\n");
1582
1583 return 0;
1584 err_ctlreg:
1585 - ssb_printk(KERN_ERR PFX "Could not access SPROM control register.\n");
1586 + ssb_err("Could not access SPROM control register.\n");
1587 return err;
1588 }
1589
1590 @@ -339,10 +347,23 @@ static s8 r123_extract_antgain(u8 sprom_
1591 return (s8)gain;
1592 }
1593
1594 +static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in)
1595 +{
1596 + SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
1597 + SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);
1598 + SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);
1599 + SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);
1600 + SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);
1601 + SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);
1602 + SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);
1603 + SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);
1604 + SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);
1605 + SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,
1606 + SSB_SPROM2_MAXP_A_LO_SHIFT);
1607 +}
1608 +
1609 static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)
1610 {
1611 - int i;
1612 - u16 v;
1613 u16 loc[3];
1614
1615 if (out->revision == 3) /* rev 3 moved MAC */
1616 @@ -352,19 +373,10 @@ static void sprom_extract_r123(struct ss
1617 loc[1] = SSB_SPROM1_ET0MAC;
1618 loc[2] = SSB_SPROM1_ET1MAC;
1619 }
1620 - for (i = 0; i < 3; i++) {
1621 - v = in[SPOFF(loc[0]) + i];
1622 - *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
1623 - }
1624 + sprom_get_mac(out->il0mac, &in[SPOFF(loc[0])]);
1625 if (out->revision < 3) { /* only rev 1-2 have et0, et1 */
1626 - for (i = 0; i < 3; i++) {
1627 - v = in[SPOFF(loc[1]) + i];
1628 - *(((__be16 *)out->et0mac) + i) = cpu_to_be16(v);
1629 - }
1630 - for (i = 0; i < 3; i++) {
1631 - v = in[SPOFF(loc[2]) + i];
1632 - *(((__be16 *)out->et1mac) + i) = cpu_to_be16(v);
1633 - }
1634 + sprom_get_mac(out->et0mac, &in[SPOFF(loc[1])]);
1635 + sprom_get_mac(out->et1mac, &in[SPOFF(loc[2])]);
1636 }
1637 SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0);
1638 SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A,
1639 @@ -372,6 +384,7 @@ static void sprom_extract_r123(struct ss
1640 SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
1641 SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
1642 SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
1643 + SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
1644 if (out->revision == 1)
1645 SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
1646 SSB_SPROM1_BINF_CCODE_SHIFT);
1647 @@ -398,8 +411,7 @@ static void sprom_extract_r123(struct ss
1648 SSB_SPROM1_ITSSI_A_SHIFT);
1649 SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);
1650 SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
1651 - if (out->revision >= 2)
1652 - SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
1653 +
1654 SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
1655 SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
1656
1657 @@ -410,6 +422,8 @@ static void sprom_extract_r123(struct ss
1658 out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
1659 SSB_SPROM1_AGAIN_A,
1660 SSB_SPROM1_AGAIN_A_SHIFT);
1661 + if (out->revision >= 2)
1662 + sprom_extract_r23(out, in);
1663 }
1664
1665 /* Revs 4 5 and 8 have partially shared layout */
1666 @@ -454,23 +468,20 @@ static void sprom_extract_r458(struct ss
1667
1668 static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
1669 {
1670 - int i;
1671 - u16 v;
1672 u16 il0mac_offset;
1673
1674 if (out->revision == 4)
1675 il0mac_offset = SSB_SPROM4_IL0MAC;
1676 else
1677 il0mac_offset = SSB_SPROM5_IL0MAC;
1678 - /* extract the MAC address */
1679 - for (i = 0; i < 3; i++) {
1680 - v = in[SPOFF(il0mac_offset) + i];
1681 - *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
1682 - }
1683 +
1684 + sprom_get_mac(out->il0mac, &in[SPOFF(il0mac_offset)]);
1685 +
1686 SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
1687 SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
1688 SSB_SPROM4_ETHPHY_ET1A_SHIFT);
1689 SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0);
1690 + SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
1691 if (out->revision == 4) {
1692 SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8);
1693 SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0);
1694 @@ -530,7 +541,7 @@ static void sprom_extract_r45(struct ssb
1695 static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
1696 {
1697 int i;
1698 - u16 v, o;
1699 + u16 o;
1700 u16 pwr_info_offset[] = {
1701 SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
1702 SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
1703 @@ -539,11 +550,10 @@ static void sprom_extract_r8(struct ssb_
1704 ARRAY_SIZE(out->core_pwr_info));
1705
1706 /* extract the MAC address */
1707 - for (i = 0; i < 3; i++) {
1708 - v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
1709 - *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
1710 - }
1711 + sprom_get_mac(out->il0mac, &in[SPOFF(SSB_SPROM8_IL0MAC)]);
1712 +
1713 SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0);
1714 + SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
1715 SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
1716 SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
1717 SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
1718 @@ -743,7 +753,7 @@ static int sprom_extract(struct ssb_bus
1719 memset(out, 0, sizeof(*out));
1720
1721 out->revision = in[size - 1] & 0x00FF;
1722 - ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
1723 + ssb_dbg("SPROM revision %d detected\n", out->revision);
1724 memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */
1725 memset(out->et1mac, 0xFF, 6);
1726
1727 @@ -752,7 +762,7 @@ static int sprom_extract(struct ssb_bus
1728 * number stored in the SPROM.
1729 * Always extract r1. */
1730 out->revision = 1;
1731 - ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision);
1732 + ssb_dbg("SPROM treated as revision %d\n", out->revision);
1733 }
1734
1735 switch (out->revision) {
1736 @@ -769,9 +779,8 @@ static int sprom_extract(struct ssb_bus
1737 sprom_extract_r8(out, in);
1738 break;
1739 default:
1740 - ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
1741 - " revision %d detected. Will extract"
1742 - " v1\n", out->revision);
1743 + ssb_warn("Unsupported SPROM revision %d detected. Will extract v1\n",
1744 + out->revision);
1745 out->revision = 1;
1746 sprom_extract_r123(out, in);
1747 }
1748 @@ -791,7 +800,7 @@ static int ssb_pci_sprom_get(struct ssb_
1749 u16 *buf;
1750
1751 if (!ssb_is_sprom_available(bus)) {
1752 - ssb_printk(KERN_ERR PFX "No SPROM available!\n");
1753 + ssb_err("No SPROM available!\n");
1754 return -ENODEV;
1755 }
1756 if (bus->chipco.dev) { /* can be unavailable! */
1757 @@ -810,7 +819,7 @@ static int ssb_pci_sprom_get(struct ssb_
1758 } else {
1759 bus->sprom_offset = SSB_SPROM_BASE1;
1760 }
1761 - ssb_dprintk(KERN_INFO PFX "SPROM offset is 0x%x\n", bus->sprom_offset);
1762 + ssb_dbg("SPROM offset is 0x%x\n", bus->sprom_offset);
1763
1764 buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
1765 if (!buf)
1766 @@ -835,18 +844,15 @@ static int ssb_pci_sprom_get(struct ssb_
1767 * available for this device in some other storage */
1768 err = ssb_fill_sprom_with_fallback(bus, sprom);
1769 if (err) {
1770 - ssb_printk(KERN_WARNING PFX "WARNING: Using"
1771 - " fallback SPROM failed (err %d)\n",
1772 - err);
1773 + ssb_warn("WARNING: Using fallback SPROM failed (err %d)\n",
1774 + err);
1775 } else {
1776 - ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
1777 - " revision %d provided by"
1778 - " platform.\n", sprom->revision);
1779 + ssb_dbg("Using SPROM revision %d provided by platform\n",
1780 + sprom->revision);
1781 err = 0;
1782 goto out_free;
1783 }
1784 - ssb_printk(KERN_WARNING PFX "WARNING: Invalid"
1785 - " SPROM CRC (corrupt SPROM)\n");
1786 + ssb_warn("WARNING: Invalid SPROM CRC (corrupt SPROM)\n");
1787 }
1788 }
1789 err = sprom_extract(bus, sprom, buf, bus->sprom_size);
1790 --- a/drivers/ssb/pcihost_wrapper.c
1791 +++ b/drivers/ssb/pcihost_wrapper.c
1792 @@ -38,7 +38,7 @@ static int ssb_pcihost_resume(struct pci
1793 struct ssb_bus *ssb = pci_get_drvdata(dev);
1794 int err;
1795
1796 - pci_set_power_state(dev, 0);
1797 + pci_set_power_state(dev, PCI_D0);
1798 err = pci_enable_device(dev);
1799 if (err)
1800 return err;
1801 --- a/drivers/ssb/pcmcia.c
1802 +++ b/drivers/ssb/pcmcia.c
1803 @@ -143,7 +143,7 @@ int ssb_pcmcia_switch_coreidx(struct ssb
1804
1805 return 0;
1806 error:
1807 - ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx);
1808 + ssb_err("Failed to switch to core %u\n", coreidx);
1809 return err;
1810 }
1811
1812 @@ -153,10 +153,9 @@ int ssb_pcmcia_switch_core(struct ssb_bu
1813 int err;
1814
1815 #if SSB_VERBOSE_PCMCIACORESWITCH_DEBUG
1816 - ssb_printk(KERN_INFO PFX
1817 - "Switching to %s core, index %d\n",
1818 - ssb_core_name(dev->id.coreid),
1819 - dev->core_index);
1820 + ssb_info("Switching to %s core, index %d\n",
1821 + ssb_core_name(dev->id.coreid),
1822 + dev->core_index);
1823 #endif
1824
1825 err = ssb_pcmcia_switch_coreidx(bus, dev->core_index);
1826 @@ -192,7 +191,7 @@ int ssb_pcmcia_switch_segment(struct ssb
1827
1828 return 0;
1829 error:
1830 - ssb_printk(KERN_ERR PFX "Failed to switch pcmcia segment\n");
1831 + ssb_err("Failed to switch pcmcia segment\n");
1832 return err;
1833 }
1834
1835 @@ -549,44 +548,39 @@ static int ssb_pcmcia_sprom_write_all(st
1836 bool failed = 0;
1837 size_t size = SSB_PCMCIA_SPROM_SIZE;
1838
1839 - ssb_printk(KERN_NOTICE PFX
1840 - "Writing SPROM. Do NOT turn off the power! "
1841 - "Please stand by...\n");
1842 + ssb_notice("Writing SPROM. Do NOT turn off the power! Please stand by...\n");
1843 err = ssb_pcmcia_sprom_command(bus, SSB_PCMCIA_SPROMCTL_WRITEEN);
1844 if (err) {
1845 - ssb_printk(KERN_NOTICE PFX
1846 - "Could not enable SPROM write access.\n");
1847 + ssb_notice("Could not enable SPROM write access\n");
1848 return -EBUSY;
1849 }
1850 - ssb_printk(KERN_NOTICE PFX "[ 0%%");
1851 + ssb_notice("[ 0%%");
1852 msleep(500);
1853 for (i = 0; i < size; i++) {
1854 if (i == size / 4)
1855 - ssb_printk("25%%");
1856 + ssb_cont("25%%");
1857 else if (i == size / 2)
1858 - ssb_printk("50%%");
1859 + ssb_cont("50%%");
1860 else if (i == (size * 3) / 4)
1861 - ssb_printk("75%%");
1862 + ssb_cont("75%%");
1863 else if (i % 2)
1864 - ssb_printk(".");
1865 + ssb_cont(".");
1866 err = ssb_pcmcia_sprom_write(bus, i, sprom[i]);
1867 if (err) {
1868 - ssb_printk(KERN_NOTICE PFX
1869 - "Failed to write to SPROM.\n");
1870 + ssb_notice("Failed to write to SPROM\n");
1871 failed = 1;
1872 break;
1873 }
1874 }
1875 err = ssb_pcmcia_sprom_command(bus, SSB_PCMCIA_SPROMCTL_WRITEDIS);
1876 if (err) {
1877 - ssb_printk(KERN_NOTICE PFX
1878 - "Could not disable SPROM write access.\n");
1879 + ssb_notice("Could not disable SPROM write access\n");
1880 failed = 1;
1881 }
1882 msleep(500);
1883 if (!failed) {
1884 - ssb_printk("100%% ]\n");
1885 - ssb_printk(KERN_NOTICE PFX "SPROM written.\n");
1886 + ssb_cont("100%% ]\n");
1887 + ssb_notice("SPROM written\n");
1888 }
1889
1890 return failed ? -EBUSY : 0;
1891 @@ -700,7 +694,7 @@ static int ssb_pcmcia_do_get_invariants(
1892 return -ENOSPC; /* continue with next entry */
1893
1894 error:
1895 - ssb_printk(KERN_ERR PFX
1896 + ssb_err(
1897 "PCMCIA: Failed to fetch device invariants: %s\n",
1898 error_description);
1899 return -ENODEV;
1900 @@ -722,7 +716,7 @@ int ssb_pcmcia_get_invariants(struct ssb
1901 res = pcmcia_loop_tuple(bus->host_pcmcia, CISTPL_FUNCE,
1902 ssb_pcmcia_get_mac, sprom);
1903 if (res != 0) {
1904 - ssb_printk(KERN_ERR PFX
1905 + ssb_err(
1906 "PCMCIA: Failed to fetch MAC address\n");
1907 return -ENODEV;
1908 }
1909 @@ -733,7 +727,7 @@ int ssb_pcmcia_get_invariants(struct ssb
1910 if ((res == 0) || (res == -ENOSPC))
1911 return 0;
1912
1913 - ssb_printk(KERN_ERR PFX
1914 + ssb_err(
1915 "PCMCIA: Failed to fetch device invariants\n");
1916 return -ENODEV;
1917 }
1918 @@ -843,6 +837,6 @@ int ssb_pcmcia_init(struct ssb_bus *bus)
1919
1920 return 0;
1921 error:
1922 - ssb_printk(KERN_ERR PFX "Failed to initialize PCMCIA host device\n");
1923 + ssb_err("Failed to initialize PCMCIA host device\n");
1924 return err;
1925 }
1926 --- a/drivers/ssb/scan.c
1927 +++ b/drivers/ssb/scan.c
1928 @@ -125,8 +125,7 @@ static u16 pcidev_to_chipid(struct pci_d
1929 chipid_fallback = 0x4401;
1930 break;
1931 default:
1932 - ssb_printk(KERN_ERR PFX
1933 - "PCI-ID not in fallback list\n");
1934 + ssb_err("PCI-ID not in fallback list\n");
1935 }
1936
1937 return chipid_fallback;
1938 @@ -152,8 +151,7 @@ static u8 chipid_to_nrcores(u16 chipid)
1939 case 0x4704:
1940 return 9;
1941 default:
1942 - ssb_printk(KERN_ERR PFX
1943 - "CHIPID not in nrcores fallback list\n");
1944 + ssb_err("CHIPID not in nrcores fallback list\n");
1945 }
1946
1947 return 1;
1948 @@ -320,15 +318,13 @@ int ssb_bus_scan(struct ssb_bus *bus,
1949 bus->chip_package = 0;
1950 }
1951 }
1952 - ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
1953 - "package 0x%02X\n", bus->chip_id, bus->chip_rev,
1954 - bus->chip_package);
1955 + ssb_info("Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
1956 + bus->chip_id, bus->chip_rev, bus->chip_package);
1957 if (!bus->nr_devices)
1958 bus->nr_devices = chipid_to_nrcores(bus->chip_id);
1959 if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
1960 - ssb_printk(KERN_ERR PFX
1961 - "More than %d ssb cores found (%d)\n",
1962 - SSB_MAX_NR_CORES, bus->nr_devices);
1963 + ssb_err("More than %d ssb cores found (%d)\n",
1964 + SSB_MAX_NR_CORES, bus->nr_devices);
1965 goto err_unmap;
1966 }
1967 if (bus->bustype == SSB_BUSTYPE_SSB) {
1968 @@ -370,8 +366,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
1969 nr_80211_cores++;
1970 if (nr_80211_cores > 1) {
1971 if (!we_support_multiple_80211_cores(bus)) {
1972 - ssb_dprintk(KERN_INFO PFX "Ignoring additional "
1973 - "802.11 core\n");
1974 + ssb_dbg("Ignoring additional 802.11 core\n");
1975 continue;
1976 }
1977 }
1978 @@ -379,8 +374,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
1979 case SSB_DEV_EXTIF:
1980 #ifdef CONFIG_SSB_DRIVER_EXTIF
1981 if (bus->extif.dev) {
1982 - ssb_printk(KERN_WARNING PFX
1983 - "WARNING: Multiple EXTIFs found\n");
1984 + ssb_warn("WARNING: Multiple EXTIFs found\n");
1985 break;
1986 }
1987 bus->extif.dev = dev;
1988 @@ -388,8 +382,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
1989 break;
1990 case SSB_DEV_CHIPCOMMON:
1991 if (bus->chipco.dev) {
1992 - ssb_printk(KERN_WARNING PFX
1993 - "WARNING: Multiple ChipCommon found\n");
1994 + ssb_warn("WARNING: Multiple ChipCommon found\n");
1995 break;
1996 }
1997 bus->chipco.dev = dev;
1998 @@ -398,8 +391,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
1999 case SSB_DEV_MIPS_3302:
2000 #ifdef CONFIG_SSB_DRIVER_MIPS
2001 if (bus->mipscore.dev) {
2002 - ssb_printk(KERN_WARNING PFX
2003 - "WARNING: Multiple MIPS cores found\n");
2004 + ssb_warn("WARNING: Multiple MIPS cores found\n");
2005 break;
2006 }
2007 bus->mipscore.dev = dev;
2008 @@ -420,8 +412,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
2009 }
2010 }
2011 if (bus->pcicore.dev) {
2012 - ssb_printk(KERN_WARNING PFX
2013 - "WARNING: Multiple PCI(E) cores found\n");
2014 + ssb_warn("WARNING: Multiple PCI(E) cores found\n");
2015 break;
2016 }
2017 bus->pcicore.dev = dev;
2018 --- a/drivers/ssb/sprom.c
2019 +++ b/drivers/ssb/sprom.c
2020 @@ -54,7 +54,7 @@ static int hex2sprom(u16 *sprom, const c
2021 while (cnt < sprom_size_words) {
2022 memcpy(tmp, dump, 4);
2023 dump += 4;
2024 - err = strict_strtoul(tmp, 16, &parsed);
2025 + err = kstrtoul(tmp, 16, &parsed);
2026 if (err)
2027 return err;
2028 sprom[cnt++] = swab16((u16)parsed);
2029 @@ -127,13 +127,13 @@ ssize_t ssb_attr_sprom_store(struct ssb_
2030 goto out_kfree;
2031 err = ssb_devices_freeze(bus, &freeze);
2032 if (err) {
2033 - ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n");
2034 + ssb_err("SPROM write: Could not freeze all devices\n");
2035 goto out_unlock;
2036 }
2037 res = sprom_write(bus, sprom);
2038 err = ssb_devices_thaw(&freeze);
2039 if (err)
2040 - ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n");
2041 + ssb_err("SPROM write: Could not thaw all devices\n");
2042 out_unlock:
2043 mutex_unlock(&bus->sprom_mutex);
2044 out_kfree:
2045 --- a/drivers/ssb/ssb_private.h
2046 +++ b/drivers/ssb/ssb_private.h
2047 @@ -3,21 +3,33 @@
2048
2049 #include <linux/ssb/ssb.h>
2050 #include <linux/types.h>
2051 +#include <linux/bcm47xx_wdt.h>
2052
2053
2054 #define PFX "ssb: "
2055
2056 #ifdef CONFIG_SSB_SILENT
2057 -# define ssb_printk(fmt, x...) do { /* nothing */ } while (0)
2058 +# define ssb_printk(fmt, ...) \
2059 + do { if (0) printk(fmt, ##__VA_ARGS__); } while (0)
2060 #else
2061 -# define ssb_printk printk
2062 +# define ssb_printk(fmt, ...) \
2063 + printk(fmt, ##__VA_ARGS__)
2064 #endif /* CONFIG_SSB_SILENT */
2065
2066 +#define ssb_emerg(fmt, ...) ssb_printk(KERN_EMERG PFX fmt, ##__VA_ARGS__)
2067 +#define ssb_err(fmt, ...) ssb_printk(KERN_ERR PFX fmt, ##__VA_ARGS__)
2068 +#define ssb_warn(fmt, ...) ssb_printk(KERN_WARNING PFX fmt, ##__VA_ARGS__)
2069 +#define ssb_notice(fmt, ...) ssb_printk(KERN_NOTICE PFX fmt, ##__VA_ARGS__)
2070 +#define ssb_info(fmt, ...) ssb_printk(KERN_INFO PFX fmt, ##__VA_ARGS__)
2071 +#define ssb_cont(fmt, ...) ssb_printk(KERN_CONT fmt, ##__VA_ARGS__)
2072 +
2073 /* dprintk: Debugging printk; vanishes for non-debug compilation */
2074 #ifdef CONFIG_SSB_DEBUG
2075 -# define ssb_dprintk(fmt, x...) ssb_printk(fmt , ##x)
2076 +# define ssb_dbg(fmt, ...) \
2077 + ssb_printk(KERN_DEBUG PFX fmt, ##__VA_ARGS__)
2078 #else
2079 -# define ssb_dprintk(fmt, x...) do { /* nothing */ } while (0)
2080 +# define ssb_dbg(fmt, ...) \
2081 + do { if (0) printk(KERN_DEBUG PFX fmt, ##__VA_ARGS__); } while (0)
2082 #endif
2083
2084 #ifdef CONFIG_SSB_DEBUG
2085 @@ -210,5 +222,76 @@ static inline void b43_pci_ssb_bridge_ex
2086 /* driver_chipcommon_pmu.c */
2087 extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
2088 extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
2089 +extern u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc);
2090 +
2091 +extern u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
2092 + u32 ticks);
2093 +extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
2094 +
2095 +/* driver_chipcommon_sflash.c */
2096 +#ifdef CONFIG_SSB_SFLASH
2097 +int ssb_sflash_init(struct ssb_chipcommon *cc);
2098 +#else
2099 +static inline int ssb_sflash_init(struct ssb_chipcommon *cc)
2100 +{
2101 + pr_err("Serial flash not supported\n");
2102 + return 0;
2103 +}
2104 +#endif /* CONFIG_SSB_SFLASH */
2105 +
2106 +#ifdef CONFIG_SSB_DRIVER_MIPS
2107 +extern struct platform_device ssb_pflash_dev;
2108 +#endif
2109 +
2110 +#ifdef CONFIG_SSB_SFLASH
2111 +extern struct platform_device ssb_sflash_dev;
2112 +#endif
2113 +
2114 +#ifdef CONFIG_SSB_DRIVER_EXTIF
2115 +extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
2116 +extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
2117 +#else
2118 +static inline u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
2119 + u32 ticks)
2120 +{
2121 + return 0;
2122 +}
2123 +static inline u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt,
2124 + u32 ms)
2125 +{
2126 + return 0;
2127 +}
2128 +#endif
2129 +
2130 +#ifdef CONFIG_SSB_EMBEDDED
2131 +extern int ssb_watchdog_register(struct ssb_bus *bus);
2132 +#else /* CONFIG_SSB_EMBEDDED */
2133 +static inline int ssb_watchdog_register(struct ssb_bus *bus)
2134 +{
2135 + return 0;
2136 +}
2137 +#endif /* CONFIG_SSB_EMBEDDED */
2138 +
2139 +#ifdef CONFIG_SSB_DRIVER_EXTIF
2140 +extern void ssb_extif_init(struct ssb_extif *extif);
2141 +#else
2142 +static inline void ssb_extif_init(struct ssb_extif *extif)
2143 +{
2144 +}
2145 +#endif
2146 +
2147 +#ifdef CONFIG_SSB_DRIVER_GPIO
2148 +extern int ssb_gpio_init(struct ssb_bus *bus);
2149 +extern int ssb_gpio_unregister(struct ssb_bus *bus);
2150 +#else /* CONFIG_SSB_DRIVER_GPIO */
2151 +static inline int ssb_gpio_init(struct ssb_bus *bus)
2152 +{
2153 + return -ENOTSUPP;
2154 +}
2155 +static inline int ssb_gpio_unregister(struct ssb_bus *bus)
2156 +{
2157 + return 0;
2158 +}
2159 +#endif /* CONFIG_SSB_DRIVER_GPIO */
2160
2161 #endif /* LINUX_SSB_PRIVATE_H_ */
2162 --- a/include/linux/ssb/ssb.h
2163 +++ b/include/linux/ssb/ssb.h
2164 @@ -6,8 +6,10 @@
2165 #include <linux/types.h>
2166 #include <linux/spinlock.h>
2167 #include <linux/pci.h>
2168 +#include <linux/gpio.h>
2169 #include <linux/mod_devicetable.h>
2170 #include <linux/dma-mapping.h>
2171 +#include <linux/platform_device.h>
2172
2173 #include <linux/ssb/ssb_regs.h>
2174
2175 @@ -24,9 +26,9 @@ struct ssb_sprom_core_pwr_info {
2176
2177 struct ssb_sprom {
2178 u8 revision;
2179 - u8 il0mac[6]; /* MAC address for 802.11b/g */
2180 - u8 et0mac[6]; /* MAC address for Ethernet */
2181 - u8 et1mac[6]; /* MAC address for 802.11a */
2182 + u8 il0mac[6] __aligned(sizeof(u16)); /* MAC address for 802.11b/g */
2183 + u8 et0mac[6] __aligned(sizeof(u16)); /* MAC address for Ethernet */
2184 + u8 et1mac[6] __aligned(sizeof(u16)); /* MAC address for 802.11a */
2185 u8 et0phyaddr; /* MII address for enet0 */
2186 u8 et1phyaddr; /* MII address for enet1 */
2187 u8 et0mdcport; /* MDIO for enet0 */
2188 @@ -338,13 +340,61 @@ enum ssb_bustype {
2189 #define SSB_BOARDVENDOR_DELL 0x1028 /* Dell */
2190 #define SSB_BOARDVENDOR_HP 0x0E11 /* HP */
2191 /* board_type */
2192 +#define SSB_BOARD_BCM94301CB 0x0406
2193 +#define SSB_BOARD_BCM94301MP 0x0407
2194 +#define SSB_BOARD_BU4309 0x040A
2195 +#define SSB_BOARD_BCM94309CB 0x040B
2196 +#define SSB_BOARD_BCM4309MP 0x040C
2197 +#define SSB_BOARD_BU4306 0x0416
2198 #define SSB_BOARD_BCM94306MP 0x0418
2199 #define SSB_BOARD_BCM4309G 0x0421
2200 #define SSB_BOARD_BCM4306CB 0x0417
2201 -#define SSB_BOARD_BCM4309MP 0x040C
2202 +#define SSB_BOARD_BCM94306PC 0x0425 /* pcmcia 3.3v 4306 card */
2203 +#define SSB_BOARD_BCM94306CBSG 0x042B /* with SiGe PA */
2204 +#define SSB_BOARD_PCSG94306 0x042D /* with SiGe PA */
2205 +#define SSB_BOARD_BU4704SD 0x042E /* with sdram */
2206 +#define SSB_BOARD_BCM94704AGR 0x042F /* dual 11a/11g Router */
2207 +#define SSB_BOARD_BCM94308MP 0x0430 /* 11a-only minipci */
2208 +#define SSB_BOARD_BU4318 0x0447
2209 +#define SSB_BOARD_CB4318 0x0448
2210 +#define SSB_BOARD_MPG4318 0x0449
2211 #define SSB_BOARD_MP4318 0x044A
2212 -#define SSB_BOARD_BU4306 0x0416
2213 -#define SSB_BOARD_BU4309 0x040A
2214 +#define SSB_BOARD_SD4318 0x044B
2215 +#define SSB_BOARD_BCM94306P 0x044C /* with SiGe */
2216 +#define SSB_BOARD_BCM94303MP 0x044E
2217 +#define SSB_BOARD_BCM94306MPM 0x0450
2218 +#define SSB_BOARD_BCM94306MPL 0x0453
2219 +#define SSB_BOARD_PC4303 0x0454 /* pcmcia */
2220 +#define SSB_BOARD_BCM94306MPLNA 0x0457
2221 +#define SSB_BOARD_BCM94306MPH 0x045B
2222 +#define SSB_BOARD_BCM94306PCIV 0x045C
2223 +#define SSB_BOARD_BCM94318MPGH 0x0463
2224 +#define SSB_BOARD_BU4311 0x0464
2225 +#define SSB_BOARD_BCM94311MC 0x0465
2226 +#define SSB_BOARD_BCM94311MCAG 0x0466
2227 +/* 4321 boards */
2228 +#define SSB_BOARD_BU4321 0x046B
2229 +#define SSB_BOARD_BU4321E 0x047C
2230 +#define SSB_BOARD_MP4321 0x046C
2231 +#define SSB_BOARD_CB2_4321 0x046D
2232 +#define SSB_BOARD_CB2_4321_AG 0x0066
2233 +#define SSB_BOARD_MC4321 0x046E
2234 +/* 4325 boards */
2235 +#define SSB_BOARD_BCM94325DEVBU 0x0490
2236 +#define SSB_BOARD_BCM94325BGABU 0x0491
2237 +#define SSB_BOARD_BCM94325SDGWB 0x0492
2238 +#define SSB_BOARD_BCM94325SDGMDL 0x04AA
2239 +#define SSB_BOARD_BCM94325SDGMDL2 0x04C6
2240 +#define SSB_BOARD_BCM94325SDGMDL3 0x04C9
2241 +#define SSB_BOARD_BCM94325SDABGWBA 0x04E1
2242 +/* 4322 boards */
2243 +#define SSB_BOARD_BCM94322MC 0x04A4
2244 +#define SSB_BOARD_BCM94322USB 0x04A8 /* dualband */
2245 +#define SSB_BOARD_BCM94322HM 0x04B0
2246 +#define SSB_BOARD_BCM94322USB2D 0x04Bf /* single band discrete front end */
2247 +/* 4312 boards */
2248 +#define SSB_BOARD_BU4312 0x048A
2249 +#define SSB_BOARD_BCM4312MCGSG 0x04B5
2250 /* chip_package */
2251 #define SSB_CHIPPACK_BCM4712S 1 /* Small 200pin 4712 */
2252 #define SSB_CHIPPACK_BCM4712M 2 /* Medium 225pin 4712 */
2253 @@ -432,7 +482,11 @@ struct ssb_bus {
2254 #ifdef CONFIG_SSB_EMBEDDED
2255 /* Lock for GPIO register access. */
2256 spinlock_t gpio_lock;
2257 + struct platform_device *watchdog;
2258 #endif /* EMBEDDED */
2259 +#ifdef CONFIG_SSB_DRIVER_GPIO
2260 + struct gpio_chip gpio;
2261 +#endif /* DRIVER_GPIO */
2262
2263 /* Internal-only stuff follows. Do not touch. */
2264 struct list_head list;
2265 --- a/include/linux/ssb/ssb_driver_chipcommon.h
2266 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
2267 @@ -219,6 +219,7 @@
2268 #define SSB_CHIPCO_PMU_CTL 0x0600 /* PMU control */
2269 #define SSB_CHIPCO_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
2270 #define SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT 16
2271 +#define SSB_CHIPCO_PMU_CTL_PLL_UPD 0x00000400
2272 #define SSB_CHIPCO_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
2273 #define SSB_CHIPCO_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
2274 #define SSB_CHIPCO_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
2275 @@ -504,7 +505,9 @@
2276 #define SSB_CHIPCO_FLASHCTL_ST_SE 0x02D8 /* Sector Erase */
2277 #define SSB_CHIPCO_FLASHCTL_ST_BE 0x00C7 /* Bulk Erase */
2278 #define SSB_CHIPCO_FLASHCTL_ST_DP 0x00B9 /* Deep Power-down */
2279 -#define SSB_CHIPCO_FLASHCTL_ST_RSIG 0x03AB /* Read Electronic Signature */
2280 +#define SSB_CHIPCO_FLASHCTL_ST_RES 0x03AB /* Read Electronic Signature */
2281 +#define SSB_CHIPCO_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
2282 +#define SSB_CHIPCO_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
2283
2284 /* Status register bits for ST flashes */
2285 #define SSB_CHIPCO_FLASHSTA_ST_WIP 0x01 /* Write In Progress */
2286 @@ -588,7 +591,10 @@ struct ssb_chipcommon {
2287 u32 status;
2288 /* Fast Powerup Delay constant */
2289 u16 fast_pwrup_delay;
2290 + spinlock_t gpio_lock;
2291 struct ssb_chipcommon_pmu pmu;
2292 + u32 ticks_per_ms;
2293 + u32 max_timer_ms;
2294 };
2295
2296 static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
2297 @@ -628,8 +634,7 @@ enum ssb_clkmode {
2298 extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
2299 enum ssb_clkmode mode);
2300
2301 -extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc,
2302 - u32 ticks);
2303 +extern u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks);
2304
2305 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value);
2306
2307 @@ -642,6 +647,8 @@ u32 ssb_chipco_gpio_outen(struct ssb_chi
2308 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value);
2309 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value);
2310 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value);
2311 +u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value);
2312 +u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value);
2313
2314 #ifdef CONFIG_SSB_SERIAL
2315 extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
2316 @@ -661,5 +668,6 @@ enum ssb_pmu_ldo_volt_id {
2317 void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
2318 enum ssb_pmu_ldo_volt_id id, u32 voltage);
2319 void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on);
2320 +void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid);
2321
2322 #endif /* LINUX_SSB_CHIPCO_H_ */
2323 --- a/include/linux/ssb/ssb_driver_extif.h
2324 +++ b/include/linux/ssb/ssb_driver_extif.h
2325 @@ -152,12 +152,16 @@
2326 /* watchdog */
2327 #define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */
2328
2329 +#define SSB_EXTIF_WATCHDOG_MAX_TIMER ((1 << 28) - 1)
2330 +#define SSB_EXTIF_WATCHDOG_MAX_TIMER_MS (SSB_EXTIF_WATCHDOG_MAX_TIMER \
2331 + / (SSB_EXTIF_WATCHDOG_CLK / 1000))
2332
2333
2334 #ifdef CONFIG_SSB_DRIVER_EXTIF
2335
2336 struct ssb_extif {
2337 struct ssb_device *dev;
2338 + spinlock_t gpio_lock;
2339 };
2340
2341 static inline bool ssb_extif_available(struct ssb_extif *extif)
2342 @@ -171,8 +175,7 @@ extern void ssb_extif_get_clockcontrol(s
2343 extern void ssb_extif_timing_init(struct ssb_extif *extif,
2344 unsigned long ns);
2345
2346 -extern void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
2347 - u32 ticks);
2348 +extern u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks);
2349
2350 /* Extif GPIO pin access */
2351 u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask);
2352 @@ -205,10 +208,52 @@ void ssb_extif_get_clockcontrol(struct s
2353 }
2354
2355 static inline
2356 -void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
2357 - u32 ticks)
2358 +void ssb_extif_timing_init(struct ssb_extif *extif, unsigned long ns)
2359 {
2360 }
2361
2362 +static inline
2363 +u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
2364 +{
2365 + return 0;
2366 +}
2367 +
2368 +static inline u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
2369 +{
2370 + return 0;
2371 +}
2372 +
2373 +static inline u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask,
2374 + u32 value)
2375 +{
2376 + return 0;
2377 +}
2378 +
2379 +static inline u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask,
2380 + u32 value)
2381 +{
2382 + return 0;
2383 +}
2384 +
2385 +static inline u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask,
2386 + u32 value)
2387 +{
2388 + return 0;
2389 +}
2390 +
2391 +static inline u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask,
2392 + u32 value)
2393 +{
2394 + return 0;
2395 +}
2396 +
2397 +#ifdef CONFIG_SSB_SERIAL
2398 +static inline int ssb_extif_serial_init(struct ssb_extif *extif,
2399 + struct ssb_serial_port *ports)
2400 +{
2401 + return 0;
2402 +}
2403 +#endif /* CONFIG_SSB_SERIAL */
2404 +
2405 #endif /* CONFIG_SSB_DRIVER_EXTIF */
2406 #endif /* LINUX_SSB_EXTIFCORE_H_ */
2407 --- a/include/linux/ssb/ssb_driver_gige.h
2408 +++ b/include/linux/ssb/ssb_driver_gige.h
2409 @@ -97,21 +97,16 @@ static inline bool ssb_gige_must_flush_p
2410 return 0;
2411 }
2412
2413 -#ifdef CONFIG_BCM47XX
2414 -#include <asm/mach-bcm47xx/nvram.h>
2415 /* Get the device MAC address */
2416 -static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
2417 -{
2418 - char buf[20];
2419 - if (nvram_getenv("et0macaddr", buf, sizeof(buf)) < 0)
2420 - return;
2421 - nvram_parse_macaddr(buf, macaddr);
2422 -}
2423 -#else
2424 -static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
2425 +static inline int ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
2426 {
2427 + struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
2428 + if (!dev)
2429 + return -ENODEV;
2430 +
2431 + memcpy(macaddr, dev->dev->bus->sprom.et0mac, 6);
2432 + return 0;
2433 }
2434 -#endif
2435
2436 extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
2437 struct pci_dev *pdev);
2438 @@ -175,6 +170,10 @@ static inline bool ssb_gige_must_flush_p
2439 {
2440 return 0;
2441 }
2442 +static inline int ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
2443 +{
2444 + return -ENODEV;
2445 +}
2446
2447 #endif /* CONFIG_SSB_DRIVER_GIGE */
2448 #endif /* LINUX_SSB_DRIVER_GIGE_H_ */
2449 --- a/include/linux/ssb/ssb_driver_mips.h
2450 +++ b/include/linux/ssb/ssb_driver_mips.h
2451 @@ -13,6 +13,24 @@ struct ssb_serial_port {
2452 unsigned int reg_shift;
2453 };
2454
2455 +struct ssb_pflash {
2456 + bool present;
2457 + u8 buswidth;
2458 + u32 window;
2459 + u32 window_size;
2460 +};
2461 +
2462 +#ifdef CONFIG_SSB_SFLASH
2463 +struct ssb_sflash {
2464 + bool present;
2465 + u32 window;
2466 + u32 blocksize;
2467 + u16 numblocks;
2468 + u32 size;
2469 +
2470 + void *priv;
2471 +};
2472 +#endif
2473
2474 struct ssb_mipscore {
2475 struct ssb_device *dev;
2476 @@ -20,9 +38,10 @@ struct ssb_mipscore {
2477 int nr_serial_ports;
2478 struct ssb_serial_port serial_ports[4];
2479
2480 - u8 flash_buswidth;
2481 - u32 flash_window;
2482 - u32 flash_window_size;
2483 + struct ssb_pflash pflash;
2484 +#ifdef CONFIG_SSB_SFLASH
2485 + struct ssb_sflash sflash;
2486 +#endif
2487 };
2488
2489 extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
2490 @@ -41,6 +60,11 @@ void ssb_mipscore_init(struct ssb_mipsco
2491 {
2492 }
2493
2494 +static inline unsigned int ssb_mips_irq(struct ssb_device *dev)
2495 +{
2496 + return 0;
2497 +}
2498 +
2499 #endif /* CONFIG_SSB_DRIVER_MIPS */
2500
2501 #endif /* LINUX_SSB_MIPSCORE_H_ */
2502 --- a/include/linux/ssb/ssb_regs.h
2503 +++ b/include/linux/ssb/ssb_regs.h
2504 @@ -172,6 +172,7 @@
2505 #define SSB_SPROMSIZE_WORDS_R4 220
2506 #define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
2507 #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
2508 +#define SSB_SPROMSIZE_WORDS_R10 230
2509 #define SSB_SPROM_BASE1 0x1000
2510 #define SSB_SPROM_BASE31 0x0800
2511 #define SSB_SPROM_REVISION 0x007E
2512 @@ -289,11 +290,11 @@
2513 #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
2514 #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
2515 #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
2516 -#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
2517 -#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
2518 -#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
2519 -#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
2520 -#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
2521 +#define SSB_SPROM4_ANTAVAIL 0x005C /* Antenna available bitfields */
2522 +#define SSB_SPROM4_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
2523 +#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 0
2524 +#define SSB_SPROM4_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
2525 +#define SSB_SPROM4_ANTAVAIL_A_SHIFT 8
2526 #define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
2527 #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
2528 #define SSB_SPROM4_AGAIN0_SHIFT 0
2529 @@ -485,7 +486,7 @@
2530 #define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
2531 #define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL 0x0020
2532 #define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT 5
2533 -#define SSB_SPROM8_TEMPDELTA 0x00BA
2534 +#define SSB_SPROM8_TEMPDELTA 0x00BC
2535 #define SSB_SPROM8_TEMPDELTA_PHYCAL 0x00ff
2536 #define SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT 0
2537 #define SSB_SPROM8_TEMPDELTA_PERIOD 0x0f00
2538 --- /dev/null
2539 +++ b/include/linux/bcm47xx_wdt.h
2540 @@ -0,0 +1,19 @@
2541 +#ifndef LINUX_BCM47XX_WDT_H_
2542 +#define LINUX_BCM47XX_WDT_H_
2543 +
2544 +#include <linux/types.h>
2545 +
2546 +
2547 +struct bcm47xx_wdt {
2548 + u32 (*timer_set)(struct bcm47xx_wdt *, u32);
2549 + u32 (*timer_set_ms)(struct bcm47xx_wdt *, u32);
2550 + u32 max_timer_ms;
2551 +
2552 + void *driver_data;
2553 +};
2554 +
2555 +static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt)
2556 +{
2557 + return wdt->driver_data;
2558 +}
2559 +#endif /* LINUX_BCM47XX_WDT_H_ */
2560 --- a/drivers/net/wireless/b43/phy_n.c
2561 +++ b/drivers/net/wireless/b43/phy_n.c
2562 @@ -4583,7 +4583,8 @@ static void b43_nphy_pmu_spur_avoid(stru
2563 #endif
2564 #ifdef CONFIG_B43_SSB
2565 case B43_BUS_SSB:
2566 - /* FIXME */
2567 + ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco,
2568 + avoid);
2569 break;
2570 #endif
2571 }
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