target/linux/generic/patches-3.7/020-ssb_update.patch

   1 --- a/drivers/ssb/b43_pci_bridge.c
   2 +++ b/drivers/ssb/b43_pci_bridge.c
   3 @@ -37,6 +37,7 @@ static const struct pci_device_id b43_pc
   4         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
   5         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
   6         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
   7 +       { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4350) },
   8         { 0, },
   9  };
  10  MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
  11 --- a/drivers/ssb/driver_chipcommon.c
  12 +++ b/drivers/ssb/driver_chipcommon.c
  13 @@ -4,6 +4,7 @@
  14   *
  15   * Copyright 2005, Broadcom Corporation
  16   * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
  17 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
  18   *
  19   * Licensed under the GNU/GPL. See COPYING for details.
  20   */
  21 @@ -12,6 +13,7 @@
  22  #include <linux/ssb/ssb_regs.h>
  23  #include <linux/export.h>
  24  #include <linux/pci.h>
  25 +#include <linux/bcm47xx_wdt.h>
  26
  27  #include "ssb_private.h"
  28
  29 @@ -280,6 +282,69 @@ static void calc_fast_powerup_delay(stru
  30         cc->fast_pwrup_delay = tmp;
  31  }
  32
  33 +static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc)
  34 +{
  35 +       if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
  36 +               return ssb_pmu_get_alp_clock(cc);
  37 +
  38 +       return 20000000;
  39 +}
  40 +
  41 +static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc)
  42 +{
  43 +       u32 nb;
  44 +
  45 +       if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
  46 +               if (cc->dev->id.revision < 26)
  47 +                       nb = 16;
  48 +               else
  49 +                       nb = (cc->dev->id.revision >= 37) ? 32 : 24;
  50 +       } else {
  51 +               nb = 28;
  52 +       }
  53 +       if (nb == 32)
  54 +               return 0xffffffff;
  55 +       else
  56 +               return (1 << nb) - 1;
  57 +}
  58 +
  59 +u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
  60 +{
  61 +       struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
  62 +
  63 +       if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
  64 +               return 0;
  65 +
  66 +       return ssb_chipco_watchdog_timer_set(cc, ticks);
  67 +}
  68 +
  69 +u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
  70 +{
  71 +       struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
  72 +       u32 ticks;
  73 +
  74 +       if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
  75 +               return 0;
  76 +
  77 +       ticks = ssb_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
  78 +       return ticks / cc->ticks_per_ms;
  79 +}
  80 +
  81 +static int ssb_chipco_watchdog_ticks_per_ms(struct ssb_chipcommon *cc)
  82 +{
  83 +       struct ssb_bus *bus = cc->dev->bus;
  84 +
  85 +       if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
  86 +                       /* based on 32KHz ILP clock */
  87 +                       return 32;
  88 +       } else {
  89 +               if (cc->dev->id.revision < 18)
  90 +                       return ssb_clockspeed(bus) / 1000;
  91 +               else
  92 +                       return ssb_chipco_alp_clock(cc) / 1000;
  93 +       }
  94 +}
  95 +
  96  void ssb_chipcommon_init(struct ssb_chipcommon *cc)
  97  {
  98         if (!cc->dev)
  99 @@ -297,6 +362,11 @@ void ssb_chipcommon_init(struct ssb_chip
 100         chipco_powercontrol_init(cc);
 101         ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
 102         calc_fast_powerup_delay(cc);
 103 +
 104 +       if (cc->dev->bus->bustype == SSB_BUSTYPE_SSB) {
 105 +               cc->ticks_per_ms = ssb_chipco_watchdog_ticks_per_ms(cc);
 106 +               cc->max_timer_ms = ssb_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
 107 +       }
 108  }
 109
 110  void ssb_chipco_suspend(struct ssb_chipcommon *cc)
 111 @@ -395,10 +465,27 @@ void ssb_chipco_timing_init(struct ssb_c
 112  }
 113
 114  /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
 115 -void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
 116 +u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
 117  {
 118 -       /* instant NMI */
 119 -       chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
 120 +       u32 maxt;
 121 +       enum ssb_clkmode clkmode;
 122 +
 123 +       maxt = ssb_chipco_watchdog_get_max_timer(cc);
 124 +       if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
 125 +               if (ticks == 1)
 126 +                       ticks = 2;
 127 +               else if (ticks > maxt)
 128 +                       ticks = maxt;
 129 +               chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks);
 130 +       } else {
 131 +               clkmode = ticks ? SSB_CLKMODE_FAST : SSB_CLKMODE_DYNAMIC;
 132 +               ssb_chipco_set_clockmode(cc, clkmode);
 133 +               if (ticks > maxt)
 134 +                       ticks = maxt;
 135 +               /* instant NMI */
 136 +               chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
 137 +       }
 138 +       return ticks;
 139  }
 140
 141  void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
 142 @@ -473,12 +560,7 @@ int ssb_chipco_serial_init(struct ssb_ch
 143                                        chipco_read32(cc, SSB_CHIPCO_CORECTL)
 144                                        | SSB_CHIPCO_CORECTL_UARTCLK0);
 145                 } else if ((ccrev >= 11) && (ccrev != 15)) {
 146 -                       /* Fixed ALP clock */
 147 -                       baud_base = 20000000;
 148 -                       if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
 149 -                               /* FIXME: baud_base is different for devices with a PMU */
 150 -                               SSB_WARN_ON(1);
 151 -                       }
 152 +                       baud_base = ssb_chipco_alp_clock(cc);
 153                         div = 1;
 154                         if (ccrev >= 21) {
 155                                 /* Turn off UART clock before switching clocksource. */
 156 --- a/drivers/ssb/driver_chipcommon_pmu.c
 157 +++ b/drivers/ssb/driver_chipcommon_pmu.c
 158 @@ -346,6 +346,8 @@ static void ssb_pmu_pll_init(struct ssb_
 159                         chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
 160                 }
 161                 break;
 162 +       case 43222:
 163 +               break;
 164         default:
 165                 ssb_printk(KERN_ERR PFX
 166                            "ERROR: PLL init unknown for device %04X\n",
 167 @@ -434,6 +436,7 @@ static void ssb_pmu_resources_init(struc
 168                  min_msk = 0xCBB;
 169                  break;
 170         case 0x4322:
 171 +       case 43222:
 172                 /* We keep the default settings:
 173                  * min_msk = 0xCBB
 174                  * max_msk = 0x7FFFF
 175 @@ -615,6 +618,33 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
 176  EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
 177  EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
 178
 179 +static u32 ssb_pmu_get_alp_clock_clk0(struct ssb_chipcommon *cc)
 180 +{
 181 +       u32 crystalfreq;
 182 +       const struct pmu0_plltab_entry *e = NULL;
 183 +
 184 +       crystalfreq = chipco_read32(cc, SSB_CHIPCO_PMU_CTL) &
 185 +                     SSB_CHIPCO_PMU_CTL_XTALFREQ >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT;
 186 +       e = pmu0_plltab_find_entry(crystalfreq);
 187 +       BUG_ON(!e);
 188 +       return e->freq * 1000;
 189 +}
 190 +
 191 +u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc)
 192 +{
 193 +       struct ssb_bus *bus = cc->dev->bus;
 194 +
 195 +       switch (bus->chip_id) {
 196 +       case 0x5354:
 197 +               ssb_pmu_get_alp_clock_clk0(cc);
 198 +       default:
 199 +               ssb_printk(KERN_ERR PFX
 200 +                          "ERROR: PMU alp clock unknown for device %04X\n",
 201 +                          bus->chip_id);
 202 +               return 0;
 203 +       }
 204 +}
 205 +
 206  u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
 207  {
 208         struct ssb_bus *bus = cc->dev->bus;
 209 --- a/drivers/ssb/driver_extif.c
 210 +++ b/drivers/ssb/driver_extif.c
 211 @@ -112,10 +112,30 @@ void ssb_extif_get_clockcontrol(struct s
 212         *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
 213  }
 214
 215 -void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
 216 -                                 u32 ticks)
 217 +u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
 218  {
 219 +       struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
 220 +
 221 +       return ssb_extif_watchdog_timer_set(extif, ticks);
 222 +}
 223 +
 224 +u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
 225 +{
 226 +       struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
 227 +       u32 ticks = (SSB_EXTIF_WATCHDOG_CLK / 1000) * ms;
 228 +
 229 +       ticks = ssb_extif_watchdog_timer_set(extif, ticks);
 230 +
 231 +       return (ticks * 1000) / SSB_EXTIF_WATCHDOG_CLK;
 232 +}
 233 +
 234 +u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
 235 +{
 236 +       if (ticks > SSB_EXTIF_WATCHDOG_MAX_TIMER)
 237 +               ticks = SSB_EXTIF_WATCHDOG_MAX_TIMER;
 238         extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks);
 239 +
 240 +       return ticks;
 241  }
 242
 243  u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
 244 --- a/drivers/ssb/driver_mipscore.c
 245 +++ b/drivers/ssb/driver_mipscore.c
 246 @@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct
 247  {
 248         struct ssb_bus *bus = mcore->dev->bus;
 249
 250 -       if (bus->extif.dev)
 251 +       if (ssb_extif_available(&bus->extif))
 252                 mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
 253 -       else if (bus->chipco.dev)
 254 +       else if (ssb_chipco_available(&bus->chipco))
 255                 mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
 256         else
 257                 mcore->nr_serial_ports = 0;
 258 @@ -191,10 +191,11 @@ static void ssb_mips_flash_detect(struct
 259         struct ssb_bus *bus = mcore->dev->bus;
 260
 261         /* When there is no chipcommon on the bus there is 4MB flash */
 262 -       if (!bus->chipco.dev) {
 263 -               mcore->flash_buswidth = 2;
 264 -               mcore->flash_window = SSB_FLASH1;
 265 -               mcore->flash_window_size = SSB_FLASH1_SZ;
 266 +       if (!ssb_chipco_available(&bus->chipco)) {
 267 +               mcore->pflash.present = true;
 268 +               mcore->pflash.buswidth = 2;
 269 +               mcore->pflash.window = SSB_FLASH1;
 270 +               mcore->pflash.window_size = SSB_FLASH1_SZ;
 271                 return;
 272         }
 273
 274 @@ -206,13 +207,14 @@ static void ssb_mips_flash_detect(struct
 275                 break;
 276         case SSB_CHIPCO_FLASHT_PARA:
 277                 pr_debug("Found parallel flash\n");
 278 -               mcore->flash_window = SSB_FLASH2;
 279 -               mcore->flash_window_size = SSB_FLASH2_SZ;
 280 +               mcore->pflash.present = true;
 281 +               mcore->pflash.window = SSB_FLASH2;
 282 +               mcore->pflash.window_size = SSB_FLASH2_SZ;
 283                 if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
 284                                & SSB_CHIPCO_CFG_DS16) == 0)
 285 -                       mcore->flash_buswidth = 1;
 286 +                       mcore->pflash.buswidth = 1;
 287                 else
 288 -                       mcore->flash_buswidth = 2;
 289 +                       mcore->pflash.buswidth = 2;
 290                 break;
 291         }
 292  }
 293 @@ -225,9 +227,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
 294         if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
 295                 return ssb_pmu_get_cpu_clock(&bus->chipco);
 296
 297 -       if (bus->extif.dev) {
 298 +       if (ssb_extif_available(&bus->extif)) {
 299                 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
 300 -       } else if (bus->chipco.dev) {
 301 +       } else if (ssb_chipco_available(&bus->chipco)) {
 302                 ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
 303         } else
 304                 return 0;
 305 @@ -263,9 +265,9 @@ void ssb_mipscore_init(struct ssb_mipsco
 306                 hz = 100000000;
 307         ns = 1000000000 / hz;
 308
 309 -       if (bus->extif.dev)
 310 +       if (ssb_extif_available(&bus->extif))
 311                 ssb_extif_timing_init(&bus->extif, ns);
 312 -       else if (bus->chipco.dev)
 313 +       else if (ssb_chipco_available(&bus->chipco))
 314                 ssb_chipco_timing_init(&bus->chipco, ns);
 315
 316         /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
 317 --- a/drivers/ssb/embedded.c
 318 +++ b/drivers/ssb/embedded.c
 319 @@ -4,11 +4,13 @@
 320   *
 321   * Copyright 2005-2008, Broadcom Corporation
 322   * Copyright 2006-2008, Michael Buesch <m@bues.ch>
 323 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
 324   *
 325   * Licensed under the GNU/GPL. See COPYING for details.
 326   */
 327
 328  #include <linux/export.h>
 329 +#include <linux/platform_device.h>
 330  #include <linux/ssb/ssb.h>
 331  #include <linux/ssb/ssb_embedded.h>
 332  #include <linux/ssb/ssb_driver_pci.h>
 333 @@ -32,6 +34,39 @@ int ssb_watchdog_timer_set(struct ssb_bu
 334  }
 335  EXPORT_SYMBOL(ssb_watchdog_timer_set);
 336
 337 +int ssb_watchdog_register(struct ssb_bus *bus)
 338 +{
 339 +       struct bcm47xx_wdt wdt = {};
 340 +       struct platform_device *pdev;
 341 +
 342 +       if (ssb_chipco_available(&bus->chipco)) {
 343 +               wdt.driver_data = &bus->chipco;
 344 +               wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt;
 345 +               wdt.timer_set_ms = ssb_chipco_watchdog_timer_set_ms;
 346 +               wdt.max_timer_ms = bus->chipco.max_timer_ms;
 347 +       } else if (ssb_extif_available(&bus->extif)) {
 348 +               wdt.driver_data = &bus->extif;
 349 +               wdt.timer_set = ssb_extif_watchdog_timer_set_wdt;
 350 +               wdt.timer_set_ms = ssb_extif_watchdog_timer_set_ms;
 351 +               wdt.max_timer_ms = SSB_EXTIF_WATCHDOG_MAX_TIMER_MS;
 352 +       } else {
 353 +               return -ENODEV;
 354 +       }
 355 +
 356 +       pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
 357 +                                            bus->busnumber, &wdt,
 358 +                                            sizeof(wdt));
 359 +       if (IS_ERR(pdev)) {
 360 +               ssb_dprintk(KERN_INFO PFX
 361 +                           "can not register watchdog device, err: %li\n",
 362 +                           PTR_ERR(pdev));
 363 +               return PTR_ERR(pdev);
 364 +       }
 365 +
 366 +       bus->watchdog = pdev;
 367 +       return 0;
 368 +}
 369 +
 370  u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask)
 371  {
 372         unsigned long flags;
 373 --- a/drivers/ssb/main.c
 374 +++ b/drivers/ssb/main.c
 375 @@ -13,6 +13,7 @@
 376  #include <linux/delay.h>
 377  #include <linux/io.h>
 378  #include <linux/module.h>
 379 +#include <linux/platform_device.h>
 380  #include <linux/ssb/ssb.h>
 381  #include <linux/ssb/ssb_regs.h>
 382  #include <linux/ssb/ssb_driver_gige.h>
 383 @@ -433,6 +434,11 @@ static void ssb_devices_unregister(struc
 384                 if (sdev->dev)
 385                         device_unregister(sdev->dev);
 386         }
 387 +
 388 +#ifdef CONFIG_SSB_EMBEDDED
 389 +       if (bus->bustype == SSB_BUSTYPE_SSB)
 390 +               platform_device_unregister(bus->watchdog);
 391 +#endif
 392  }
 393
 394  void ssb_bus_unregister(struct ssb_bus *bus)
 395 @@ -561,6 +567,8 @@ static int __devinit ssb_attach_queued_b
 396                 if (err)
 397                         goto error;
 398                 ssb_pcicore_init(&bus->pcicore);
 399 +               if (bus->bustype == SSB_BUSTYPE_SSB)
 400 +                       ssb_watchdog_register(bus);
 401                 ssb_bus_may_powerdown(bus);
 402
 403                 err = ssb_devices_register(bus);
 404 @@ -1118,8 +1126,7 @@ static u32 ssb_tmslow_reject_bitmask(str
 405         case SSB_IDLOW_SSBREV_27:     /* same here */
 406                 return SSB_TMSLOW_REJECT;       /* this is a guess */
 407         default:
 408 -               printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
 409 -               WARN_ON(1);
 410 +               WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
 411         }
 412         return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
 413  }
 414 --- a/drivers/ssb/ssb_private.h
 415 +++ b/drivers/ssb/ssb_private.h
 416 @@ -3,6 +3,7 @@
 417
 418  #include <linux/ssb/ssb.h>
 419  #include <linux/types.h>
 420 +#include <linux/bcm47xx_wdt.h>
 421
 422
 423  #define PFX    "ssb: "
 424 @@ -210,5 +211,35 @@ static inline void b43_pci_ssb_bridge_ex
 425  /* driver_chipcommon_pmu.c */
 426  extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
 427  extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
 428 +extern u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc);
 429 +
 430 +extern u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
 431 +                                            u32 ticks);
 432 +extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
 433 +
 434 +#ifdef CONFIG_SSB_DRIVER_EXTIF
 435 +extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
 436 +extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
 437 +#else
 438 +static inline u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
 439 +                                                  u32 ticks)
 440 +{
 441 +       return 0;
 442 +}
 443 +static inline u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt,
 444 +                                                 u32 ms)
 445 +{
 446 +       return 0;
 447 +}
 448 +#endif
 449 +
 450 +#ifdef CONFIG_SSB_EMBEDDED
 451 +extern int ssb_watchdog_register(struct ssb_bus *bus);
 452 +#else /* CONFIG_SSB_EMBEDDED */
 453 +static inline int ssb_watchdog_register(struct ssb_bus *bus)
 454 +{
 455 +       return 0;
 456 +}
 457 +#endif /* CONFIG_SSB_EMBEDDED */
 458
 459  #endif /* LINUX_SSB_PRIVATE_H_ */
 460 --- a/include/linux/ssb/ssb.h
 461 +++ b/include/linux/ssb/ssb.h
 462 @@ -8,6 +8,7 @@
 463  #include <linux/pci.h>
 464  #include <linux/mod_devicetable.h>
 465  #include <linux/dma-mapping.h>
 466 +#include <linux/platform_device.h>
 467
 468  #include <linux/ssb/ssb_regs.h>
 469
 470 @@ -432,6 +433,7 @@ struct ssb_bus {
 471  #ifdef CONFIG_SSB_EMBEDDED
 472         /* Lock for GPIO register access. */
 473         spinlock_t gpio_lock;
 474 +       struct platform_device *watchdog;
 475  #endif /* EMBEDDED */
 476
 477         /* Internal-only stuff follows. Do not touch. */
 478 --- a/include/linux/ssb/ssb_driver_chipcommon.h
 479 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
 480 @@ -591,6 +591,8 @@ struct ssb_chipcommon {
 481         /* Fast Powerup Delay constant */
 482         u16 fast_pwrup_delay;
 483         struct ssb_chipcommon_pmu pmu;
 484 +       u32 ticks_per_ms;
 485 +       u32 max_timer_ms;
 486  };
 487
 488  static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
 489 @@ -630,8 +632,7 @@ enum ssb_clkmode {
 490  extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
 491                                      enum ssb_clkmode mode);
 492
 493 -extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc,
 494 -                                         u32 ticks);
 495 +extern u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks);
 496
 497  void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value);
 498
 499 --- a/include/linux/ssb/ssb_driver_extif.h
 500 +++ b/include/linux/ssb/ssb_driver_extif.h
 501 @@ -152,6 +152,9 @@
 502  /* watchdog */
 503  #define SSB_EXTIF_WATCHDOG_CLK         48000000        /* Hz */
 504
 505 +#define SSB_EXTIF_WATCHDOG_MAX_TIMER   ((1 << 28) - 1)
 506 +#define SSB_EXTIF_WATCHDOG_MAX_TIMER_MS        (SSB_EXTIF_WATCHDOG_MAX_TIMER \
 507 +                                        / (SSB_EXTIF_WATCHDOG_CLK / 1000))
 508
 509
 510  #ifdef CONFIG_SSB_DRIVER_EXTIF
 511 @@ -171,8 +174,7 @@ extern void ssb_extif_get_clockcontrol(s
 512  extern void ssb_extif_timing_init(struct ssb_extif *extif,
 513                                   unsigned long ns);
 514
 515 -extern void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
 516 -                                        u32 ticks);
 517 +extern u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks);
 518
 519  /* Extif GPIO pin access */
 520  u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask);
 521 @@ -205,10 +207,52 @@ void ssb_extif_get_clockcontrol(struct s
 522  }
 523
 524  static inline
 525 -void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
 526 -                                 u32 ticks)
 527 +void ssb_extif_timing_init(struct ssb_extif *extif, unsigned long ns)
 528  {
 529  }
 530
 531 +static inline
 532 +u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
 533 +{
 534 +       return 0;
 535 +}
 536 +
 537 +static inline u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
 538 +{
 539 +       return 0;
 540 +}
 541 +
 542 +static inline u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask,
 543 +                                    u32 value)
 544 +{
 545 +       return 0;
 546 +}
 547 +
 548 +static inline u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask,
 549 +                                      u32 value)
 550 +{
 551 +       return 0;
 552 +}
 553 +
 554 +static inline u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask,
 555 +                                         u32 value)
 556 +{
 557 +       return 0;
 558 +}
 559 +
 560 +static inline u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask,
 561 +                                        u32 value)
 562 +{
 563 +       return 0;
 564 +}
 565 +
 566 +#ifdef CONFIG_SSB_SERIAL
 567 +static inline int ssb_extif_serial_init(struct ssb_extif *extif,
 568 +                                       struct ssb_serial_port *ports)
 569 +{
 570 +       return 0;
 571 +}
 572 +#endif /* CONFIG_SSB_SERIAL */
 573 +
 574  #endif /* CONFIG_SSB_DRIVER_EXTIF */
 575  #endif /* LINUX_SSB_EXTIFCORE_H_ */
 576 --- a/include/linux/ssb/ssb_driver_mips.h
 577 +++ b/include/linux/ssb/ssb_driver_mips.h
 578 @@ -13,6 +13,12 @@ struct ssb_serial_port {
 579         unsigned int reg_shift;
 580  };
 581
 582 +struct ssb_pflash {
 583 +       bool present;
 584 +       u8 buswidth;
 585 +       u32 window;
 586 +       u32 window_size;
 587 +};
 588
 589  struct ssb_mipscore {
 590         struct ssb_device *dev;
 591 @@ -20,9 +26,7 @@ struct ssb_mipscore {
 592         int nr_serial_ports;
 593         struct ssb_serial_port serial_ports[4];
 594
 595 -       u8 flash_buswidth;
 596 -       u32 flash_window;
 597 -       u32 flash_window_size;
 598 +       struct ssb_pflash pflash;
 599  };
 600
 601  extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
 602 --- a/include/linux/ssb/ssb_regs.h
 603 +++ b/include/linux/ssb/ssb_regs.h
 604 @@ -485,7 +485,7 @@
 605  #define  SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
 606  #define  SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL        0x0020
 607  #define  SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT  5
 608 -#define SSB_SPROM8_TEMPDELTA           0x00BA
 609 +#define SSB_SPROM8_TEMPDELTA           0x00BC
 610  #define  SSB_SPROM8_TEMPDELTA_PHYCAL   0x00ff
 611  #define  SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT     0
 612  #define  SSB_SPROM8_TEMPDELTA_PERIOD   0x0f00