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kernel: update bcma and ssb to version from wireless-testing/master tag master-2013...
[openwrt/openwrt.git] / target / linux / generic / patches-3.7 / 020-ssb_update.patch
1 --- a/arch/mips/bcm47xx/nvram.c
2 +++ b/arch/mips/bcm47xx/nvram.c
3 @@ -43,8 +43,8 @@ static void early_nvram_init(void)
4 #ifdef CONFIG_BCM47XX_SSB
5 case BCM47XX_BUS_TYPE_SSB:
6 mcore_ssb = &bcm47xx_bus.ssb.mipscore;
7 - base = mcore_ssb->flash_window;
8 - lim = mcore_ssb->flash_window_size;
9 + base = mcore_ssb->pflash.window;
10 + lim = mcore_ssb->pflash.window_size;
11 break;
12 #endif
13 #ifdef CONFIG_BCM47XX_BCMA
14 --- a/arch/mips/bcm47xx/wgt634u.c
15 +++ b/arch/mips/bcm47xx/wgt634u.c
16 @@ -156,10 +156,10 @@ static int __init wgt634u_init(void)
17 SSB_CHIPCO_IRQ_GPIO);
18 }
19
20 - wgt634u_flash_data.width = mcore->flash_buswidth;
21 - wgt634u_flash_resource.start = mcore->flash_window;
22 - wgt634u_flash_resource.end = mcore->flash_window
23 - + mcore->flash_window_size
24 + wgt634u_flash_data.width = mcore->pflash.buswidth;
25 + wgt634u_flash_resource.start = mcore->pflash.window;
26 + wgt634u_flash_resource.end = mcore->pflash.window
27 + + mcore->pflash.window_size
28 - 1;
29 return platform_add_devices(wgt634u_devices,
30 ARRAY_SIZE(wgt634u_devices));
31 --- a/drivers/ssb/Kconfig
32 +++ b/drivers/ssb/Kconfig
33 @@ -136,10 +136,15 @@ config SSB_DRIVER_MIPS
34
35 If unsure, say N
36
37 +config SSB_SFLASH
38 + bool "SSB serial flash support"
39 + depends on SSB_DRIVER_MIPS && BROKEN
40 + default y
41 +
42 # Assumption: We are on embedded, if we compile the MIPS core.
43 config SSB_EMBEDDED
44 bool
45 - depends on SSB_DRIVER_MIPS
46 + depends on SSB_DRIVER_MIPS && SSB_PCICORE_HOSTMODE
47 default y
48
49 config SSB_DRIVER_EXTIF
50 @@ -160,4 +165,12 @@ config SSB_DRIVER_GIGE
51
52 If unsure, say N
53
54 +config SSB_DRIVER_GPIO
55 + bool "SSB GPIO driver"
56 + depends on SSB && GPIOLIB
57 + help
58 + Driver to provide access to the GPIO pins on the bus.
59 +
60 + If unsure, say N
61 +
62 endmenu
63 --- a/drivers/ssb/Makefile
64 +++ b/drivers/ssb/Makefile
65 @@ -11,10 +11,12 @@ ssb-$(CONFIG_SSB_SDIOHOST) += sdio.o
66 # built-in drivers
67 ssb-y += driver_chipcommon.o
68 ssb-y += driver_chipcommon_pmu.o
69 +ssb-$(CONFIG_SSB_SFLASH) += driver_chipcommon_sflash.o
70 ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o
71 ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o
72 ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o
73 ssb-$(CONFIG_SSB_DRIVER_GIGE) += driver_gige.o
74 +ssb-$(CONFIG_SSB_DRIVER_GPIO) += driver_gpio.o
75
76 # b43 pci-ssb-bridge driver
77 # Not strictly a part of SSB, but kept here for convenience
78 --- a/drivers/ssb/b43_pci_bridge.c
79 +++ b/drivers/ssb/b43_pci_bridge.c
80 @@ -37,6 +37,7 @@ static const struct pci_device_id b43_pc
81 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
82 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
83 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
84 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4350) },
85 { 0, },
86 };
87 MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
88 --- a/drivers/ssb/driver_chipcommon.c
89 +++ b/drivers/ssb/driver_chipcommon.c
90 @@ -4,6 +4,7 @@
91 *
92 * Copyright 2005, Broadcom Corporation
93 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
94 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
95 *
96 * Licensed under the GNU/GPL. See COPYING for details.
97 */
98 @@ -12,6 +13,7 @@
99 #include <linux/ssb/ssb_regs.h>
100 #include <linux/export.h>
101 #include <linux/pci.h>
102 +#include <linux/bcm47xx_wdt.h>
103
104 #include "ssb_private.h"
105
106 @@ -280,13 +282,79 @@ static void calc_fast_powerup_delay(stru
107 cc->fast_pwrup_delay = tmp;
108 }
109
110 +static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc)
111 +{
112 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
113 + return ssb_pmu_get_alp_clock(cc);
114 +
115 + return 20000000;
116 +}
117 +
118 +static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc)
119 +{
120 + u32 nb;
121 +
122 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
123 + if (cc->dev->id.revision < 26)
124 + nb = 16;
125 + else
126 + nb = (cc->dev->id.revision >= 37) ? 32 : 24;
127 + } else {
128 + nb = 28;
129 + }
130 + if (nb == 32)
131 + return 0xffffffff;
132 + else
133 + return (1 << nb) - 1;
134 +}
135 +
136 +u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
137 +{
138 + struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
139 +
140 + if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
141 + return 0;
142 +
143 + return ssb_chipco_watchdog_timer_set(cc, ticks);
144 +}
145 +
146 +u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
147 +{
148 + struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
149 + u32 ticks;
150 +
151 + if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
152 + return 0;
153 +
154 + ticks = ssb_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
155 + return ticks / cc->ticks_per_ms;
156 +}
157 +
158 +static int ssb_chipco_watchdog_ticks_per_ms(struct ssb_chipcommon *cc)
159 +{
160 + struct ssb_bus *bus = cc->dev->bus;
161 +
162 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
163 + /* based on 32KHz ILP clock */
164 + return 32;
165 + } else {
166 + if (cc->dev->id.revision < 18)
167 + return ssb_clockspeed(bus) / 1000;
168 + else
169 + return ssb_chipco_alp_clock(cc) / 1000;
170 + }
171 +}
172 +
173 void ssb_chipcommon_init(struct ssb_chipcommon *cc)
174 {
175 if (!cc->dev)
176 return; /* We don't have a ChipCommon */
177 +
178 + spin_lock_init(&cc->gpio_lock);
179 +
180 if (cc->dev->id.revision >= 11)
181 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
182 - ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
183 + ssb_dbg("chipcommon status is 0x%x\n", cc->status);
184
185 if (cc->dev->id.revision >= 20) {
186 chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
187 @@ -297,6 +365,11 @@ void ssb_chipcommon_init(struct ssb_chip
188 chipco_powercontrol_init(cc);
189 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
190 calc_fast_powerup_delay(cc);
191 +
192 + if (cc->dev->bus->bustype == SSB_BUSTYPE_SSB) {
193 + cc->ticks_per_ms = ssb_chipco_watchdog_ticks_per_ms(cc);
194 + cc->max_timer_ms = ssb_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
195 + }
196 }
197
198 void ssb_chipco_suspend(struct ssb_chipcommon *cc)
199 @@ -395,10 +468,27 @@ void ssb_chipco_timing_init(struct ssb_c
200 }
201
202 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
203 -void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
204 +u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
205 {
206 - /* instant NMI */
207 - chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
208 + u32 maxt;
209 + enum ssb_clkmode clkmode;
210 +
211 + maxt = ssb_chipco_watchdog_get_max_timer(cc);
212 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
213 + if (ticks == 1)
214 + ticks = 2;
215 + else if (ticks > maxt)
216 + ticks = maxt;
217 + chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks);
218 + } else {
219 + clkmode = ticks ? SSB_CLKMODE_FAST : SSB_CLKMODE_DYNAMIC;
220 + ssb_chipco_set_clockmode(cc, clkmode);
221 + if (ticks > maxt)
222 + ticks = maxt;
223 + /* instant NMI */
224 + chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
225 + }
226 + return ticks;
227 }
228
229 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
230 @@ -418,28 +508,93 @@ u32 ssb_chipco_gpio_in(struct ssb_chipco
231
232 u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
233 {
234 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
235 + unsigned long flags;
236 + u32 res = 0;
237 +
238 + spin_lock_irqsave(&cc->gpio_lock, flags);
239 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
240 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
241 +
242 + return res;
243 }
244
245 u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
246 {
247 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
248 + unsigned long flags;
249 + u32 res = 0;
250 +
251 + spin_lock_irqsave(&cc->gpio_lock, flags);
252 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
253 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
254 +
255 + return res;
256 }
257
258 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
259 {
260 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
261 + unsigned long flags;
262 + u32 res = 0;
263 +
264 + spin_lock_irqsave(&cc->gpio_lock, flags);
265 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
266 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
267 +
268 + return res;
269 }
270 EXPORT_SYMBOL(ssb_chipco_gpio_control);
271
272 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
273 {
274 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
275 + unsigned long flags;
276 + u32 res = 0;
277 +
278 + spin_lock_irqsave(&cc->gpio_lock, flags);
279 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
280 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
281 +
282 + return res;
283 }
284
285 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
286 {
287 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
288 + unsigned long flags;
289 + u32 res = 0;
290 +
291 + spin_lock_irqsave(&cc->gpio_lock, flags);
292 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
293 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
294 +
295 + return res;
296 +}
297 +
298 +u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value)
299 +{
300 + unsigned long flags;
301 + u32 res = 0;
302 +
303 + if (cc->dev->id.revision < 20)
304 + return 0xffffffff;
305 +
306 + spin_lock_irqsave(&cc->gpio_lock, flags);
307 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLUP, mask, value);
308 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
309 +
310 + return res;
311 +}
312 +
313 +u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value)
314 +{
315 + unsigned long flags;
316 + u32 res = 0;
317 +
318 + if (cc->dev->id.revision < 20)
319 + return 0xffffffff;
320 +
321 + spin_lock_irqsave(&cc->gpio_lock, flags);
322 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLDOWN, mask, value);
323 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
324 +
325 + return res;
326 }
327
328 #ifdef CONFIG_SSB_SERIAL
329 @@ -473,12 +628,7 @@ int ssb_chipco_serial_init(struct ssb_ch
330 chipco_read32(cc, SSB_CHIPCO_CORECTL)
331 | SSB_CHIPCO_CORECTL_UARTCLK0);
332 } else if ((ccrev >= 11) && (ccrev != 15)) {
333 - /* Fixed ALP clock */
334 - baud_base = 20000000;
335 - if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
336 - /* FIXME: baud_base is different for devices with a PMU */
337 - SSB_WARN_ON(1);
338 - }
339 + baud_base = ssb_chipco_alp_clock(cc);
340 div = 1;
341 if (ccrev >= 21) {
342 /* Turn off UART clock before switching clocksource. */
343 --- a/drivers/ssb/driver_chipcommon_pmu.c
344 +++ b/drivers/ssb/driver_chipcommon_pmu.c
345 @@ -110,8 +110,8 @@ static void ssb_pmu0_pllinit_r0(struct s
346 return;
347 }
348
349 - ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
350 - (crystalfreq / 1000), (crystalfreq % 1000));
351 + ssb_info("Programming PLL to %u.%03u MHz\n",
352 + crystalfreq / 1000, crystalfreq % 1000);
353
354 /* First turn the PLL off. */
355 switch (bus->chip_id) {
356 @@ -138,7 +138,7 @@ static void ssb_pmu0_pllinit_r0(struct s
357 }
358 tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
359 if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
360 - ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n");
361 + ssb_emerg("Failed to turn the PLL off!\n");
362
363 /* Set PDIV in PLL control 0. */
364 pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL0);
365 @@ -249,8 +249,8 @@ static void ssb_pmu1_pllinit_r0(struct s
366 return;
367 }
368
369 - ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
370 - (crystalfreq / 1000), (crystalfreq % 1000));
371 + ssb_info("Programming PLL to %u.%03u MHz\n",
372 + crystalfreq / 1000, crystalfreq % 1000);
373
374 /* First turn the PLL off. */
375 switch (bus->chip_id) {
376 @@ -275,7 +275,7 @@ static void ssb_pmu1_pllinit_r0(struct s
377 }
378 tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
379 if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
380 - ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n");
381 + ssb_emerg("Failed to turn the PLL off!\n");
382
383 /* Set p1div and p2div. */
384 pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL0);
385 @@ -346,10 +346,11 @@ static void ssb_pmu_pll_init(struct ssb_
386 chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
387 }
388 break;
389 + case 43222:
390 + break;
391 default:
392 - ssb_printk(KERN_ERR PFX
393 - "ERROR: PLL init unknown for device %04X\n",
394 - bus->chip_id);
395 + ssb_err("ERROR: PLL init unknown for device %04X\n",
396 + bus->chip_id);
397 }
398 }
399
400 @@ -434,6 +435,7 @@ static void ssb_pmu_resources_init(struc
401 min_msk = 0xCBB;
402 break;
403 case 0x4322:
404 + case 43222:
405 /* We keep the default settings:
406 * min_msk = 0xCBB
407 * max_msk = 0x7FFFF
408 @@ -469,9 +471,8 @@ static void ssb_pmu_resources_init(struc
409 max_msk = 0xFFFFF;
410 break;
411 default:
412 - ssb_printk(KERN_ERR PFX
413 - "ERROR: PMU resource config unknown for device %04X\n",
414 - bus->chip_id);
415 + ssb_err("ERROR: PMU resource config unknown for device %04X\n",
416 + bus->chip_id);
417 }
418
419 if (updown_tab) {
420 @@ -523,8 +524,8 @@ void ssb_pmu_init(struct ssb_chipcommon
421 pmucap = chipco_read32(cc, SSB_CHIPCO_PMU_CAP);
422 cc->pmu.rev = (pmucap & SSB_CHIPCO_PMU_CAP_REVISION);
423
424 - ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n",
425 - cc->pmu.rev, pmucap);
426 + ssb_dbg("Found rev %u PMU (capabilities 0x%08X)\n",
427 + cc->pmu.rev, pmucap);
428
429 if (cc->pmu.rev == 1)
430 chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
431 @@ -615,6 +616,32 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
432 EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
433 EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
434
435 +static u32 ssb_pmu_get_alp_clock_clk0(struct ssb_chipcommon *cc)
436 +{
437 + u32 crystalfreq;
438 + const struct pmu0_plltab_entry *e = NULL;
439 +
440 + crystalfreq = chipco_read32(cc, SSB_CHIPCO_PMU_CTL) &
441 + SSB_CHIPCO_PMU_CTL_XTALFREQ >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT;
442 + e = pmu0_plltab_find_entry(crystalfreq);
443 + BUG_ON(!e);
444 + return e->freq * 1000;
445 +}
446 +
447 +u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc)
448 +{
449 + struct ssb_bus *bus = cc->dev->bus;
450 +
451 + switch (bus->chip_id) {
452 + case 0x5354:
453 + ssb_pmu_get_alp_clock_clk0(cc);
454 + default:
455 + ssb_err("ERROR: PMU alp clock unknown for device %04X\n",
456 + bus->chip_id);
457 + return 0;
458 + }
459 +}
460 +
461 u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
462 {
463 struct ssb_bus *bus = cc->dev->bus;
464 @@ -624,9 +651,8 @@ u32 ssb_pmu_get_cpu_clock(struct ssb_chi
465 /* 5354 chip uses a non programmable PLL of frequency 240MHz */
466 return 240000000;
467 default:
468 - ssb_printk(KERN_ERR PFX
469 - "ERROR: PMU cpu clock unknown for device %04X\n",
470 - bus->chip_id);
471 + ssb_err("ERROR: PMU cpu clock unknown for device %04X\n",
472 + bus->chip_id);
473 return 0;
474 }
475 }
476 @@ -639,9 +665,52 @@ u32 ssb_pmu_get_controlclock(struct ssb_
477 case 0x5354:
478 return 120000000;
479 default:
480 - ssb_printk(KERN_ERR PFX
481 - "ERROR: PMU controlclock unknown for device %04X\n",
482 - bus->chip_id);
483 + ssb_err("ERROR: PMU controlclock unknown for device %04X\n",
484 + bus->chip_id);
485 return 0;
486 }
487 }
488 +
489 +void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid)
490 +{
491 + u32 pmu_ctl = 0;
492 +
493 + switch (cc->dev->bus->chip_id) {
494 + case 0x4322:
495 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100070);
496 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x1014140a);
497 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888854);
498 + if (spuravoid == 1)
499 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05201828);
500 + else
501 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05001828);
502 + pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD;
503 + break;
504 + case 43222:
505 + if (spuravoid == 1) {
506 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11500008);
507 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0C000C06);
508 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x0F600a08);
509 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000);
510 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x2001E920);
511 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888815);
512 + } else {
513 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100008);
514 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0c000c06);
515 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x03000a08);
516 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000);
517 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x200005c0);
518 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888855);
519 + }
520 + pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD;
521 + break;
522 + default:
523 + ssb_printk(KERN_ERR PFX
524 + "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
525 + cc->dev->bus->chip_id);
526 + return;
527 + }
528 +
529 + chipco_set32(cc, SSB_CHIPCO_PMU_CTL, pmu_ctl);
530 +}
531 +EXPORT_SYMBOL_GPL(ssb_pmu_spuravoid_pllupdate);
532 --- /dev/null
533 +++ b/drivers/ssb/driver_chipcommon_sflash.c
534 @@ -0,0 +1,166 @@
535 +/*
536 + * Sonics Silicon Backplane
537 + * ChipCommon serial flash interface
538 + *
539 + * Licensed under the GNU/GPL. See COPYING for details.
540 + */
541 +
542 +#include <linux/ssb/ssb.h>
543 +
544 +#include "ssb_private.h"
545 +
546 +static struct resource ssb_sflash_resource = {
547 + .name = "ssb_sflash",
548 + .start = SSB_FLASH2,
549 + .end = 0,
550 + .flags = IORESOURCE_MEM | IORESOURCE_READONLY,
551 +};
552 +
553 +struct platform_device ssb_sflash_dev = {
554 + .name = "ssb_sflash",
555 + .resource = &ssb_sflash_resource,
556 + .num_resources = 1,
557 +};
558 +
559 +struct ssb_sflash_tbl_e {
560 + char *name;
561 + u32 id;
562 + u32 blocksize;
563 + u16 numblocks;
564 +};
565 +
566 +static const struct ssb_sflash_tbl_e ssb_sflash_st_tbl[] = {
567 + { "M25P20", 0x11, 0x10000, 4, },
568 + { "M25P40", 0x12, 0x10000, 8, },
569 +
570 + { "M25P16", 0x14, 0x10000, 32, },
571 + { "M25P32", 0x15, 0x10000, 64, },
572 + { "M25P64", 0x16, 0x10000, 128, },
573 + { "M25FL128", 0x17, 0x10000, 256, },
574 + { 0 },
575 +};
576 +
577 +static const struct ssb_sflash_tbl_e ssb_sflash_sst_tbl[] = {
578 + { "SST25WF512", 1, 0x1000, 16, },
579 + { "SST25VF512", 0x48, 0x1000, 16, },
580 + { "SST25WF010", 2, 0x1000, 32, },
581 + { "SST25VF010", 0x49, 0x1000, 32, },
582 + { "SST25WF020", 3, 0x1000, 64, },
583 + { "SST25VF020", 0x43, 0x1000, 64, },
584 + { "SST25WF040", 4, 0x1000, 128, },
585 + { "SST25VF040", 0x44, 0x1000, 128, },
586 + { "SST25VF040B", 0x8d, 0x1000, 128, },
587 + { "SST25WF080", 5, 0x1000, 256, },
588 + { "SST25VF080B", 0x8e, 0x1000, 256, },
589 + { "SST25VF016", 0x41, 0x1000, 512, },
590 + { "SST25VF032", 0x4a, 0x1000, 1024, },
591 + { "SST25VF064", 0x4b, 0x1000, 2048, },
592 + { 0 },
593 +};
594 +
595 +static const struct ssb_sflash_tbl_e ssb_sflash_at_tbl[] = {
596 + { "AT45DB011", 0xc, 256, 512, },
597 + { "AT45DB021", 0x14, 256, 1024, },
598 + { "AT45DB041", 0x1c, 256, 2048, },
599 + { "AT45DB081", 0x24, 256, 4096, },
600 + { "AT45DB161", 0x2c, 512, 4096, },
601 + { "AT45DB321", 0x34, 512, 8192, },
602 + { "AT45DB642", 0x3c, 1024, 8192, },
603 + { 0 },
604 +};
605 +
606 +static void ssb_sflash_cmd(struct ssb_chipcommon *cc, u32 opcode)
607 +{
608 + int i;
609 + chipco_write32(cc, SSB_CHIPCO_FLASHCTL,
610 + SSB_CHIPCO_FLASHCTL_START | opcode);
611 + for (i = 0; i < 1000; i++) {
612 + if (!(chipco_read32(cc, SSB_CHIPCO_FLASHCTL) &
613 + SSB_CHIPCO_FLASHCTL_BUSY))
614 + return;
615 + cpu_relax();
616 + }
617 + pr_err("SFLASH control command failed (timeout)!\n");
618 +}
619 +
620 +/* Initialize serial flash access */
621 +int ssb_sflash_init(struct ssb_chipcommon *cc)
622 +{
623 + struct ssb_sflash *sflash = &cc->dev->bus->mipscore.sflash;
624 + const struct ssb_sflash_tbl_e *e;
625 + u32 id, id2;
626 +
627 + switch (cc->capabilities & SSB_CHIPCO_CAP_FLASHT) {
628 + case SSB_CHIPCO_FLASHT_STSER:
629 + ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_DP);
630 +
631 + chipco_write32(cc, SSB_CHIPCO_FLASHADDR, 0);
632 + ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_RES);
633 + id = chipco_read32(cc, SSB_CHIPCO_FLASHDATA);
634 +
635 + chipco_write32(cc, SSB_CHIPCO_FLASHADDR, 1);
636 + ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_RES);
637 + id2 = chipco_read32(cc, SSB_CHIPCO_FLASHDATA);
638 +
639 + switch (id) {
640 + case 0xbf:
641 + for (e = ssb_sflash_sst_tbl; e->name; e++) {
642 + if (e->id == id2)
643 + break;
644 + }
645 + break;
646 + case 0x13:
647 + return -ENOTSUPP;
648 + default:
649 + for (e = ssb_sflash_st_tbl; e->name; e++) {
650 + if (e->id == id)
651 + break;
652 + }
653 + break;
654 + }
655 + if (!e->name) {
656 + pr_err("Unsupported ST serial flash (id: 0x%X, id2: 0x%X)\n",
657 + id, id2);
658 + return -ENOTSUPP;
659 + }
660 +
661 + break;
662 + case SSB_CHIPCO_FLASHT_ATSER:
663 + ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_AT_STATUS);
664 + id = chipco_read32(cc, SSB_CHIPCO_FLASHDATA) & 0x3c;
665 +
666 + for (e = ssb_sflash_at_tbl; e->name; e++) {
667 + if (e->id == id)
668 + break;
669 + }
670 + if (!e->name) {
671 + pr_err("Unsupported Atmel serial flash (id: 0x%X)\n",
672 + id);
673 + return -ENOTSUPP;
674 + }
675 +
676 + break;
677 + default:
678 + pr_err("Unsupported flash type\n");
679 + return -ENOTSUPP;
680 + }
681 +
682 + sflash->window = SSB_FLASH2;
683 + sflash->blocksize = e->blocksize;
684 + sflash->numblocks = e->numblocks;
685 + sflash->size = sflash->blocksize * sflash->numblocks;
686 + sflash->present = true;
687 +
688 + pr_info("Found %s serial flash (blocksize: 0x%X, blocks: %d)\n",
689 + e->name, e->blocksize, e->numblocks);
690 +
691 + /* Prepare platform device, but don't register it yet. It's too early,
692 + * malloc (required by device_private_init) is not available yet. */
693 + ssb_sflash_dev.resource[0].end = ssb_sflash_dev.resource[0].start +
694 + sflash->size;
695 + ssb_sflash_dev.dev.platform_data = sflash;
696 +
697 + pr_err("Serial flash support is not implemented yet!\n");
698 +
699 + return -ENOTSUPP;
700 +}
701 --- a/drivers/ssb/driver_extif.c
702 +++ b/drivers/ssb/driver_extif.c
703 @@ -112,10 +112,37 @@ void ssb_extif_get_clockcontrol(struct s
704 *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
705 }
706
707 -void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
708 - u32 ticks)
709 +u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
710 {
711 + struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
712 +
713 + return ssb_extif_watchdog_timer_set(extif, ticks);
714 +}
715 +
716 +u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
717 +{
718 + struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
719 + u32 ticks = (SSB_EXTIF_WATCHDOG_CLK / 1000) * ms;
720 +
721 + ticks = ssb_extif_watchdog_timer_set(extif, ticks);
722 +
723 + return (ticks * 1000) / SSB_EXTIF_WATCHDOG_CLK;
724 +}
725 +
726 +u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
727 +{
728 + if (ticks > SSB_EXTIF_WATCHDOG_MAX_TIMER)
729 + ticks = SSB_EXTIF_WATCHDOG_MAX_TIMER;
730 extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks);
731 +
732 + return ticks;
733 +}
734 +
735 +void ssb_extif_init(struct ssb_extif *extif)
736 +{
737 + if (!extif->dev)
738 + return; /* We don't have a Extif core */
739 + spin_lock_init(&extif->gpio_lock);
740 }
741
742 u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
743 @@ -125,22 +152,50 @@ u32 ssb_extif_gpio_in(struct ssb_extif *
744
745 u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value)
746 {
747 - return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
748 + unsigned long flags;
749 + u32 res = 0;
750 +
751 + spin_lock_irqsave(&extif->gpio_lock, flags);
752 + res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
753 mask, value);
754 + spin_unlock_irqrestore(&extif->gpio_lock, flags);
755 +
756 + return res;
757 }
758
759 u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value)
760 {
761 - return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
762 + unsigned long flags;
763 + u32 res = 0;
764 +
765 + spin_lock_irqsave(&extif->gpio_lock, flags);
766 + res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
767 mask, value);
768 + spin_unlock_irqrestore(&extif->gpio_lock, flags);
769 +
770 + return res;
771 }
772
773 u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value)
774 {
775 - return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
776 + unsigned long flags;
777 + u32 res = 0;
778 +
779 + spin_lock_irqsave(&extif->gpio_lock, flags);
780 + res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
781 + spin_unlock_irqrestore(&extif->gpio_lock, flags);
782 +
783 + return res;
784 }
785
786 u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value)
787 {
788 - return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
789 + unsigned long flags;
790 + u32 res = 0;
791 +
792 + spin_lock_irqsave(&extif->gpio_lock, flags);
793 + res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
794 + spin_unlock_irqrestore(&extif->gpio_lock, flags);
795 +
796 + return res;
797 }
798 --- /dev/null
799 +++ b/drivers/ssb/driver_gpio.c
800 @@ -0,0 +1,210 @@
801 +/*
802 + * Sonics Silicon Backplane
803 + * GPIO driver
804 + *
805 + * Copyright 2011, Broadcom Corporation
806 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
807 + *
808 + * Licensed under the GNU/GPL. See COPYING for details.
809 + */
810 +
811 +#include <linux/gpio.h>
812 +#include <linux/export.h>
813 +#include <linux/ssb/ssb.h>
814 +
815 +#include "ssb_private.h"
816 +
817 +static struct ssb_bus *ssb_gpio_get_bus(struct gpio_chip *chip)
818 +{
819 + return container_of(chip, struct ssb_bus, gpio);
820 +}
821 +
822 +static int ssb_gpio_chipco_get_value(struct gpio_chip *chip, unsigned gpio)
823 +{
824 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
825 +
826 + return !!ssb_chipco_gpio_in(&bus->chipco, 1 << gpio);
827 +}
828 +
829 +static void ssb_gpio_chipco_set_value(struct gpio_chip *chip, unsigned gpio,
830 + int value)
831 +{
832 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
833 +
834 + ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0);
835 +}
836 +
837 +static int ssb_gpio_chipco_direction_input(struct gpio_chip *chip,
838 + unsigned gpio)
839 +{
840 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
841 +
842 + ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 0);
843 + return 0;
844 +}
845 +
846 +static int ssb_gpio_chipco_direction_output(struct gpio_chip *chip,
847 + unsigned gpio, int value)
848 +{
849 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
850 +
851 + ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 1 << gpio);
852 + ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0);
853 + return 0;
854 +}
855 +
856 +static int ssb_gpio_chipco_request(struct gpio_chip *chip, unsigned gpio)
857 +{
858 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
859 +
860 + ssb_chipco_gpio_control(&bus->chipco, 1 << gpio, 0);
861 + /* clear pulldown */
862 + ssb_chipco_gpio_pulldown(&bus->chipco, 1 << gpio, 0);
863 + /* Set pullup */
864 + ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 1 << gpio);
865 +
866 + return 0;
867 +}
868 +
869 +static void ssb_gpio_chipco_free(struct gpio_chip *chip, unsigned gpio)
870 +{
871 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
872 +
873 + /* clear pullup */
874 + ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 0);
875 +}
876 +
877 +static int ssb_gpio_chipco_to_irq(struct gpio_chip *chip, unsigned gpio)
878 +{
879 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
880 +
881 + if (bus->bustype == SSB_BUSTYPE_SSB)
882 + return ssb_mips_irq(bus->chipco.dev) + 2;
883 + else
884 + return -EINVAL;
885 +}
886 +
887 +static int ssb_gpio_chipco_init(struct ssb_bus *bus)
888 +{
889 + struct gpio_chip *chip = &bus->gpio;
890 +
891 + chip->label = "ssb_chipco_gpio";
892 + chip->owner = THIS_MODULE;
893 + chip->request = ssb_gpio_chipco_request;
894 + chip->free = ssb_gpio_chipco_free;
895 + chip->get = ssb_gpio_chipco_get_value;
896 + chip->set = ssb_gpio_chipco_set_value;
897 + chip->direction_input = ssb_gpio_chipco_direction_input;
898 + chip->direction_output = ssb_gpio_chipco_direction_output;
899 + chip->to_irq = ssb_gpio_chipco_to_irq;
900 + chip->ngpio = 16;
901 + /* There is just one SoC in one device and its GPIO addresses should be
902 + * deterministic to address them more easily. The other buses could get
903 + * a random base number. */
904 + if (bus->bustype == SSB_BUSTYPE_SSB)
905 + chip->base = 0;
906 + else
907 + chip->base = -1;
908 +
909 + return gpiochip_add(chip);
910 +}
911 +
912 +#ifdef CONFIG_SSB_DRIVER_EXTIF
913 +
914 +static int ssb_gpio_extif_get_value(struct gpio_chip *chip, unsigned gpio)
915 +{
916 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
917 +
918 + return !!ssb_extif_gpio_in(&bus->extif, 1 << gpio);
919 +}
920 +
921 +static void ssb_gpio_extif_set_value(struct gpio_chip *chip, unsigned gpio,
922 + int value)
923 +{
924 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
925 +
926 + ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0);
927 +}
928 +
929 +static int ssb_gpio_extif_direction_input(struct gpio_chip *chip,
930 + unsigned gpio)
931 +{
932 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
933 +
934 + ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 0);
935 + return 0;
936 +}
937 +
938 +static int ssb_gpio_extif_direction_output(struct gpio_chip *chip,
939 + unsigned gpio, int value)
940 +{
941 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
942 +
943 + ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 1 << gpio);
944 + ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0);
945 + return 0;
946 +}
947 +
948 +static int ssb_gpio_extif_to_irq(struct gpio_chip *chip, unsigned gpio)
949 +{
950 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
951 +
952 + if (bus->bustype == SSB_BUSTYPE_SSB)
953 + return ssb_mips_irq(bus->extif.dev) + 2;
954 + else
955 + return -EINVAL;
956 +}
957 +
958 +static int ssb_gpio_extif_init(struct ssb_bus *bus)
959 +{
960 + struct gpio_chip *chip = &bus->gpio;
961 +
962 + chip->label = "ssb_extif_gpio";
963 + chip->owner = THIS_MODULE;
964 + chip->get = ssb_gpio_extif_get_value;
965 + chip->set = ssb_gpio_extif_set_value;
966 + chip->direction_input = ssb_gpio_extif_direction_input;
967 + chip->direction_output = ssb_gpio_extif_direction_output;
968 + chip->to_irq = ssb_gpio_extif_to_irq;
969 + chip->ngpio = 5;
970 + /* There is just one SoC in one device and its GPIO addresses should be
971 + * deterministic to address them more easily. The other buses could get
972 + * a random base number. */
973 + if (bus->bustype == SSB_BUSTYPE_SSB)
974 + chip->base = 0;
975 + else
976 + chip->base = -1;
977 +
978 + return gpiochip_add(chip);
979 +}
980 +
981 +#else
982 +static int ssb_gpio_extif_init(struct ssb_bus *bus)
983 +{
984 + return -ENOTSUPP;
985 +}
986 +#endif
987 +
988 +int ssb_gpio_init(struct ssb_bus *bus)
989 +{
990 + if (ssb_chipco_available(&bus->chipco))
991 + return ssb_gpio_chipco_init(bus);
992 + else if (ssb_extif_available(&bus->extif))
993 + return ssb_gpio_extif_init(bus);
994 + else
995 + SSB_WARN_ON(1);
996 +
997 + return -1;
998 +}
999 +
1000 +int ssb_gpio_unregister(struct ssb_bus *bus)
1001 +{
1002 + if (ssb_chipco_available(&bus->chipco) ||
1003 + ssb_extif_available(&bus->extif)) {
1004 + return gpiochip_remove(&bus->gpio);
1005 + } else {
1006 + SSB_WARN_ON(1);
1007 + }
1008 +
1009 + return -1;
1010 +}
1011 --- a/drivers/ssb/driver_mipscore.c
1012 +++ b/drivers/ssb/driver_mipscore.c
1013 @@ -10,6 +10,7 @@
1014
1015 #include <linux/ssb/ssb.h>
1016
1017 +#include <linux/mtd/physmap.h>
1018 #include <linux/serial.h>
1019 #include <linux/serial_core.h>
1020 #include <linux/serial_reg.h>
1021 @@ -17,6 +18,25 @@
1022
1023 #include "ssb_private.h"
1024
1025 +static const char * const part_probes[] = { "bcm47xxpart", NULL };
1026 +
1027 +static struct physmap_flash_data ssb_pflash_data = {
1028 + .part_probe_types = part_probes,
1029 +};
1030 +
1031 +static struct resource ssb_pflash_resource = {
1032 + .name = "ssb_pflash",
1033 + .flags = IORESOURCE_MEM,
1034 +};
1035 +
1036 +struct platform_device ssb_pflash_dev = {
1037 + .name = "physmap-flash",
1038 + .dev = {
1039 + .platform_data = &ssb_pflash_data,
1040 + },
1041 + .resource = &ssb_pflash_resource,
1042 + .num_resources = 1,
1043 +};
1044
1045 static inline u32 mips_read32(struct ssb_mipscore *mcore,
1046 u16 offset)
1047 @@ -147,21 +167,22 @@ static void set_irq(struct ssb_device *d
1048 irqflag |= (ipsflag & ~ipsflag_irq_mask[irq]);
1049 ssb_write32(mdev, SSB_IPSFLAG, irqflag);
1050 }
1051 - ssb_dprintk(KERN_INFO PFX
1052 - "set_irq: core 0x%04x, irq %d => %d\n",
1053 - dev->id.coreid, oldirq+2, irq+2);
1054 + ssb_dbg("set_irq: core 0x%04x, irq %d => %d\n",
1055 + dev->id.coreid, oldirq+2, irq+2);
1056 }
1057
1058 static void print_irq(struct ssb_device *dev, unsigned int irq)
1059 {
1060 - int i;
1061 static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
1062 - ssb_dprintk(KERN_INFO PFX
1063 - "core 0x%04x, irq :", dev->id.coreid);
1064 - for (i = 0; i <= 6; i++) {
1065 - ssb_dprintk(" %s%s", irq_name[i], i==irq?"*":" ");
1066 - }
1067 - ssb_dprintk("\n");
1068 + ssb_dbg("core 0x%04x, irq : %s%s %s%s %s%s %s%s %s%s %s%s %s%s\n",
1069 + dev->id.coreid,
1070 + irq_name[0], irq == 0 ? "*" : " ",
1071 + irq_name[1], irq == 1 ? "*" : " ",
1072 + irq_name[2], irq == 2 ? "*" : " ",
1073 + irq_name[3], irq == 3 ? "*" : " ",
1074 + irq_name[4], irq == 4 ? "*" : " ",
1075 + irq_name[5], irq == 5 ? "*" : " ",
1076 + irq_name[6], irq == 6 ? "*" : " ");
1077 }
1078
1079 static void dump_irq(struct ssb_bus *bus)
1080 @@ -178,9 +199,9 @@ static void ssb_mips_serial_init(struct
1081 {
1082 struct ssb_bus *bus = mcore->dev->bus;
1083
1084 - if (bus->extif.dev)
1085 + if (ssb_extif_available(&bus->extif))
1086 mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
1087 - else if (bus->chipco.dev)
1088 + else if (ssb_chipco_available(&bus->chipco))
1089 mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
1090 else
1091 mcore->nr_serial_ports = 0;
1092 @@ -189,32 +210,43 @@ static void ssb_mips_serial_init(struct
1093 static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
1094 {
1095 struct ssb_bus *bus = mcore->dev->bus;
1096 + struct ssb_pflash *pflash = &mcore->pflash;
1097
1098 /* When there is no chipcommon on the bus there is 4MB flash */
1099 - if (!bus->chipco.dev) {
1100 - mcore->flash_buswidth = 2;
1101 - mcore->flash_window = SSB_FLASH1;
1102 - mcore->flash_window_size = SSB_FLASH1_SZ;
1103 - return;
1104 + if (!ssb_chipco_available(&bus->chipco)) {
1105 + pflash->present = true;
1106 + pflash->buswidth = 2;
1107 + pflash->window = SSB_FLASH1;
1108 + pflash->window_size = SSB_FLASH1_SZ;
1109 + goto ssb_pflash;
1110 }
1111
1112 /* There is ChipCommon, so use it to read info about flash */
1113 switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
1114 case SSB_CHIPCO_FLASHT_STSER:
1115 case SSB_CHIPCO_FLASHT_ATSER:
1116 - pr_err("Serial flash not supported\n");
1117 + pr_debug("Found serial flash\n");
1118 + ssb_sflash_init(&bus->chipco);
1119 break;
1120 case SSB_CHIPCO_FLASHT_PARA:
1121 pr_debug("Found parallel flash\n");
1122 - mcore->flash_window = SSB_FLASH2;
1123 - mcore->flash_window_size = SSB_FLASH2_SZ;
1124 + pflash->present = true;
1125 + pflash->window = SSB_FLASH2;
1126 + pflash->window_size = SSB_FLASH2_SZ;
1127 if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
1128 & SSB_CHIPCO_CFG_DS16) == 0)
1129 - mcore->flash_buswidth = 1;
1130 + pflash->buswidth = 1;
1131 else
1132 - mcore->flash_buswidth = 2;
1133 + pflash->buswidth = 2;
1134 break;
1135 }
1136 +
1137 +ssb_pflash:
1138 + if (pflash->present) {
1139 + ssb_pflash_data.width = pflash->buswidth;
1140 + ssb_pflash_resource.start = pflash->window;
1141 + ssb_pflash_resource.end = pflash->window + pflash->window_size;
1142 + }
1143 }
1144
1145 u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
1146 @@ -225,9 +257,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
1147 if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
1148 return ssb_pmu_get_cpu_clock(&bus->chipco);
1149
1150 - if (bus->extif.dev) {
1151 + if (ssb_extif_available(&bus->extif)) {
1152 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
1153 - } else if (bus->chipco.dev) {
1154 + } else if (ssb_chipco_available(&bus->chipco)) {
1155 ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
1156 } else
1157 return 0;
1158 @@ -255,7 +287,7 @@ void ssb_mipscore_init(struct ssb_mipsco
1159 if (!mcore->dev)
1160 return; /* We don't have a MIPS core */
1161
1162 - ssb_dprintk(KERN_INFO PFX "Initializing MIPS core...\n");
1163 + ssb_dbg("Initializing MIPS core...\n");
1164
1165 bus = mcore->dev->bus;
1166 hz = ssb_clockspeed(bus);
1167 @@ -263,9 +295,9 @@ void ssb_mipscore_init(struct ssb_mipsco
1168 hz = 100000000;
1169 ns = 1000000000 / hz;
1170
1171 - if (bus->extif.dev)
1172 + if (ssb_extif_available(&bus->extif))
1173 ssb_extif_timing_init(&bus->extif, ns);
1174 - else if (bus->chipco.dev)
1175 + else if (ssb_chipco_available(&bus->chipco))
1176 ssb_chipco_timing_init(&bus->chipco, ns);
1177
1178 /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
1179 @@ -303,7 +335,7 @@ void ssb_mipscore_init(struct ssb_mipsco
1180 break;
1181 }
1182 }
1183 - ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
1184 + ssb_dbg("after irq reconfiguration\n");
1185 dump_irq(bus);
1186
1187 ssb_mips_serial_init(mcore);
1188 --- a/drivers/ssb/driver_pcicore.c
1189 +++ b/drivers/ssb/driver_pcicore.c
1190 @@ -263,8 +263,7 @@ int ssb_pcicore_plat_dev_init(struct pci
1191 return -ENODEV;
1192 }
1193
1194 - ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
1195 - pci_name(d));
1196 + ssb_info("PCI: Fixing up device %s\n", pci_name(d));
1197
1198 /* Fix up interrupt lines */
1199 d->irq = ssb_mips_irq(extpci_core->dev) + 2;
1200 @@ -285,12 +284,12 @@ static void ssb_pcicore_fixup_pcibridge(
1201 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
1202 return;
1203
1204 - ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
1205 + ssb_info("PCI: Fixing up bridge %s\n", pci_name(dev));
1206
1207 /* Enable PCI bridge bus mastering and memory space */
1208 pci_set_master(dev);
1209 if (pcibios_enable_device(dev, ~0) < 0) {
1210 - ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
1211 + ssb_err("PCI: SSB bridge enable failed\n");
1212 return;
1213 }
1214
1215 @@ -299,8 +298,8 @@ static void ssb_pcicore_fixup_pcibridge(
1216
1217 /* Make sure our latency is high enough to handle the devices behind us */
1218 lat = 168;
1219 - ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
1220 - pci_name(dev), lat);
1221 + ssb_info("PCI: Fixing latency timer of device %s to %u\n",
1222 + pci_name(dev), lat);
1223 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
1224 }
1225 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge);
1226 @@ -323,7 +322,7 @@ static void __devinit ssb_pcicore_init_h
1227 return;
1228 extpci_core = pc;
1229
1230 - ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n");
1231 + ssb_dbg("PCIcore in host mode found\n");
1232 /* Reset devices on the external PCI bus */
1233 val = SSB_PCICORE_CTL_RST_OE;
1234 val |= SSB_PCICORE_CTL_CLK_OE;
1235 @@ -338,7 +337,7 @@ static void __devinit ssb_pcicore_init_h
1236 udelay(1); /* Assertion time demanded by the PCI standard */
1237
1238 if (pc->dev->bus->has_cardbus_slot) {
1239 - ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n");
1240 + ssb_dbg("CardBus slot detected\n");
1241 pc->cardbusmode = 1;
1242 /* GPIO 1 resets the bridge */
1243 ssb_gpio_out(pc->dev->bus, 1, 1);
1244 --- a/drivers/ssb/embedded.c
1245 +++ b/drivers/ssb/embedded.c
1246 @@ -4,11 +4,13 @@
1247 *
1248 * Copyright 2005-2008, Broadcom Corporation
1249 * Copyright 2006-2008, Michael Buesch <m@bues.ch>
1250 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
1251 *
1252 * Licensed under the GNU/GPL. See COPYING for details.
1253 */
1254
1255 #include <linux/export.h>
1256 +#include <linux/platform_device.h>
1257 #include <linux/ssb/ssb.h>
1258 #include <linux/ssb/ssb_embedded.h>
1259 #include <linux/ssb/ssb_driver_pci.h>
1260 @@ -32,6 +34,38 @@ int ssb_watchdog_timer_set(struct ssb_bu
1261 }
1262 EXPORT_SYMBOL(ssb_watchdog_timer_set);
1263
1264 +int ssb_watchdog_register(struct ssb_bus *bus)
1265 +{
1266 + struct bcm47xx_wdt wdt = {};
1267 + struct platform_device *pdev;
1268 +
1269 + if (ssb_chipco_available(&bus->chipco)) {
1270 + wdt.driver_data = &bus->chipco;
1271 + wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt;
1272 + wdt.timer_set_ms = ssb_chipco_watchdog_timer_set_ms;
1273 + wdt.max_timer_ms = bus->chipco.max_timer_ms;
1274 + } else if (ssb_extif_available(&bus->extif)) {
1275 + wdt.driver_data = &bus->extif;
1276 + wdt.timer_set = ssb_extif_watchdog_timer_set_wdt;
1277 + wdt.timer_set_ms = ssb_extif_watchdog_timer_set_ms;
1278 + wdt.max_timer_ms = SSB_EXTIF_WATCHDOG_MAX_TIMER_MS;
1279 + } else {
1280 + return -ENODEV;
1281 + }
1282 +
1283 + pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
1284 + bus->busnumber, &wdt,
1285 + sizeof(wdt));
1286 + if (IS_ERR(pdev)) {
1287 + ssb_dbg("can not register watchdog device, err: %li\n",
1288 + PTR_ERR(pdev));
1289 + return PTR_ERR(pdev);
1290 + }
1291 +
1292 + bus->watchdog = pdev;
1293 + return 0;
1294 +}
1295 +
1296 u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask)
1297 {
1298 unsigned long flags;
1299 --- a/drivers/ssb/main.c
1300 +++ b/drivers/ssb/main.c
1301 @@ -13,6 +13,7 @@
1302 #include <linux/delay.h>
1303 #include <linux/io.h>
1304 #include <linux/module.h>
1305 +#include <linux/platform_device.h>
1306 #include <linux/ssb/ssb.h>
1307 #include <linux/ssb/ssb_regs.h>
1308 #include <linux/ssb/ssb_driver_gige.h>
1309 @@ -274,8 +275,8 @@ int ssb_devices_thaw(struct ssb_freeze_c
1310
1311 err = sdrv->probe(sdev, &sdev->id);
1312 if (err) {
1313 - ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
1314 - dev_name(sdev->dev));
1315 + ssb_err("Failed to thaw device %s\n",
1316 + dev_name(sdev->dev));
1317 result = err;
1318 }
1319 ssb_device_put(sdev);
1320 @@ -433,10 +434,23 @@ static void ssb_devices_unregister(struc
1321 if (sdev->dev)
1322 device_unregister(sdev->dev);
1323 }
1324 +
1325 +#ifdef CONFIG_SSB_EMBEDDED
1326 + if (bus->bustype == SSB_BUSTYPE_SSB)
1327 + platform_device_unregister(bus->watchdog);
1328 +#endif
1329 }
1330
1331 void ssb_bus_unregister(struct ssb_bus *bus)
1332 {
1333 + int err;
1334 +
1335 + err = ssb_gpio_unregister(bus);
1336 + if (err == -EBUSY)
1337 + ssb_dbg("Some GPIOs are still in use\n");
1338 + else if (err)
1339 + ssb_dbg("Can not unregister GPIO driver: %i\n", err);
1340 +
1341 ssb_buses_lock();
1342 ssb_devices_unregister(bus);
1343 list_del(&bus->list);
1344 @@ -482,8 +496,7 @@ static int ssb_devices_register(struct s
1345
1346 devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
1347 if (!devwrap) {
1348 - ssb_printk(KERN_ERR PFX
1349 - "Could not allocate device\n");
1350 + ssb_err("Could not allocate device\n");
1351 err = -ENOMEM;
1352 goto error;
1353 }
1354 @@ -522,9 +535,7 @@ static int ssb_devices_register(struct s
1355 sdev->dev = dev;
1356 err = device_register(dev);
1357 if (err) {
1358 - ssb_printk(KERN_ERR PFX
1359 - "Could not register %s\n",
1360 - dev_name(dev));
1361 + ssb_err("Could not register %s\n", dev_name(dev));
1362 /* Set dev to NULL to not unregister
1363 * dev on error unwinding. */
1364 sdev->dev = NULL;
1365 @@ -534,6 +545,22 @@ static int ssb_devices_register(struct s
1366 dev_idx++;
1367 }
1368
1369 +#ifdef CONFIG_SSB_DRIVER_MIPS
1370 + if (bus->mipscore.pflash.present) {
1371 + err = platform_device_register(&ssb_pflash_dev);
1372 + if (err)
1373 + pr_err("Error registering parallel flash\n");
1374 + }
1375 +#endif
1376 +
1377 +#ifdef CONFIG_SSB_SFLASH
1378 + if (bus->mipscore.sflash.present) {
1379 + err = platform_device_register(&ssb_sflash_dev);
1380 + if (err)
1381 + pr_err("Error registering serial flash\n");
1382 + }
1383 +#endif
1384 +
1385 return 0;
1386 error:
1387 /* Unwind the already registered devices. */
1388 @@ -561,6 +588,8 @@ static int __devinit ssb_attach_queued_b
1389 if (err)
1390 goto error;
1391 ssb_pcicore_init(&bus->pcicore);
1392 + if (bus->bustype == SSB_BUSTYPE_SSB)
1393 + ssb_watchdog_register(bus);
1394 ssb_bus_may_powerdown(bus);
1395
1396 err = ssb_devices_register(bus);
1397 @@ -796,7 +825,13 @@ static int __devinit ssb_bus_register(st
1398 if (err)
1399 goto err_pcmcia_exit;
1400 ssb_chipcommon_init(&bus->chipco);
1401 + ssb_extif_init(&bus->extif);
1402 ssb_mipscore_init(&bus->mipscore);
1403 + err = ssb_gpio_init(bus);
1404 + if (err == -ENOTSUPP)
1405 + ssb_dbg("GPIO driver not activated\n");
1406 + else if (err)
1407 + ssb_dbg("Error registering GPIO driver: %i\n", err);
1408 err = ssb_fetch_invariants(bus, get_invariants);
1409 if (err) {
1410 ssb_bus_may_powerdown(bus);
1411 @@ -847,11 +882,11 @@ int __devinit ssb_bus_pcibus_register(st
1412
1413 err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
1414 if (!err) {
1415 - ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
1416 - "PCI device %s\n", dev_name(&host_pci->dev));
1417 + ssb_info("Sonics Silicon Backplane found on PCI device %s\n",
1418 + dev_name(&host_pci->dev));
1419 } else {
1420 - ssb_printk(KERN_ERR PFX "Failed to register PCI version"
1421 - " of SSB with error %d\n", err);
1422 + ssb_err("Failed to register PCI version of SSB with error %d\n",
1423 + err);
1424 }
1425
1426 return err;
1427 @@ -872,8 +907,8 @@ int __devinit ssb_bus_pcmciabus_register
1428
1429 err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
1430 if (!err) {
1431 - ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
1432 - "PCMCIA device %s\n", pcmcia_dev->devname);
1433 + ssb_info("Sonics Silicon Backplane found on PCMCIA device %s\n",
1434 + pcmcia_dev->devname);
1435 }
1436
1437 return err;
1438 @@ -895,8 +930,8 @@ int __devinit ssb_bus_sdiobus_register(s
1439
1440 err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
1441 if (!err) {
1442 - ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
1443 - "SDIO device %s\n", sdio_func_id(func));
1444 + ssb_info("Sonics Silicon Backplane found on SDIO device %s\n",
1445 + sdio_func_id(func));
1446 }
1447
1448 return err;
1449 @@ -915,8 +950,8 @@ int __devinit ssb_bus_ssbbus_register(st
1450
1451 err = ssb_bus_register(bus, get_invariants, baseaddr);
1452 if (!err) {
1453 - ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at "
1454 - "address 0x%08lX\n", baseaddr);
1455 + ssb_info("Sonics Silicon Backplane found at address 0x%08lX\n",
1456 + baseaddr);
1457 }
1458
1459 return err;
1460 @@ -1118,8 +1153,7 @@ static u32 ssb_tmslow_reject_bitmask(str
1461 case SSB_IDLOW_SSBREV_27: /* same here */
1462 return SSB_TMSLOW_REJECT; /* this is a guess */
1463 default:
1464 - printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
1465 - WARN_ON(1);
1466 + WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
1467 }
1468 return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
1469 }
1470 @@ -1311,7 +1345,7 @@ out:
1471 #endif
1472 return err;
1473 error:
1474 - ssb_printk(KERN_ERR PFX "Bus powerdown failed\n");
1475 + ssb_err("Bus powerdown failed\n");
1476 goto out;
1477 }
1478 EXPORT_SYMBOL(ssb_bus_may_powerdown);
1479 @@ -1334,7 +1368,7 @@ int ssb_bus_powerup(struct ssb_bus *bus,
1480
1481 return 0;
1482 error:
1483 - ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
1484 + ssb_err("Bus powerup failed\n");
1485 return err;
1486 }
1487 EXPORT_SYMBOL(ssb_bus_powerup);
1488 @@ -1442,15 +1476,13 @@ static int __init ssb_modinit(void)
1489
1490 err = b43_pci_ssb_bridge_init();
1491 if (err) {
1492 - ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
1493 - "initialization failed\n");
1494 + ssb_err("Broadcom 43xx PCI-SSB-bridge initialization failed\n");
1495 /* don't fail SSB init because of this */
1496 err = 0;
1497 }
1498 err = ssb_gige_init();
1499 if (err) {
1500 - ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
1501 - "driver initialization failed\n");
1502 + ssb_err("SSB Broadcom Gigabit Ethernet driver initialization failed\n");
1503 /* don't fail SSB init because of this */
1504 err = 0;
1505 }
1506 --- a/drivers/ssb/pci.c
1507 +++ b/drivers/ssb/pci.c
1508 @@ -56,7 +56,7 @@ int ssb_pci_switch_coreidx(struct ssb_bu
1509 }
1510 return 0;
1511 error:
1512 - ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx);
1513 + ssb_err("Failed to switch to core %u\n", coreidx);
1514 return -ENODEV;
1515 }
1516
1517 @@ -67,10 +67,9 @@ int ssb_pci_switch_core(struct ssb_bus *
1518 unsigned long flags;
1519
1520 #if SSB_VERBOSE_PCICORESWITCH_DEBUG
1521 - ssb_printk(KERN_INFO PFX
1522 - "Switching to %s core, index %d\n",
1523 - ssb_core_name(dev->id.coreid),
1524 - dev->core_index);
1525 + ssb_info("Switching to %s core, index %d\n",
1526 + ssb_core_name(dev->id.coreid),
1527 + dev->core_index);
1528 #endif
1529
1530 spin_lock_irqsave(&bus->bar_lock, flags);
1531 @@ -231,6 +230,15 @@ static inline u8 ssb_crc8(u8 crc, u8 dat
1532 return t[crc ^ data];
1533 }
1534
1535 +static void sprom_get_mac(char *mac, const u16 *in)
1536 +{
1537 + int i;
1538 + for (i = 0; i < 3; i++) {
1539 + *mac++ = in[i] >> 8;
1540 + *mac++ = in[i];
1541 + }
1542 +}
1543 +
1544 static u8 ssb_sprom_crc(const u16 *sprom, u16 size)
1545 {
1546 int word;
1547 @@ -278,7 +286,7 @@ static int sprom_do_write(struct ssb_bus
1548 u32 spromctl;
1549 u16 size = bus->sprom_size;
1550
1551 - ssb_printk(KERN_NOTICE PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n");
1552 + ssb_notice("Writing SPROM. Do NOT turn off the power! Please stand by...\n");
1553 err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl);
1554 if (err)
1555 goto err_ctlreg;
1556 @@ -286,17 +294,17 @@ static int sprom_do_write(struct ssb_bus
1557 err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl);
1558 if (err)
1559 goto err_ctlreg;
1560 - ssb_printk(KERN_NOTICE PFX "[ 0%%");
1561 + ssb_notice("[ 0%%");
1562 msleep(500);
1563 for (i = 0; i < size; i++) {
1564 if (i == size / 4)
1565 - ssb_printk("25%%");
1566 + ssb_cont("25%%");
1567 else if (i == size / 2)
1568 - ssb_printk("50%%");
1569 + ssb_cont("50%%");
1570 else if (i == (size * 3) / 4)
1571 - ssb_printk("75%%");
1572 + ssb_cont("75%%");
1573 else if (i % 2)
1574 - ssb_printk(".");
1575 + ssb_cont(".");
1576 writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
1577 mmiowb();
1578 msleep(20);
1579 @@ -309,12 +317,12 @@ static int sprom_do_write(struct ssb_bus
1580 if (err)
1581 goto err_ctlreg;
1582 msleep(500);
1583 - ssb_printk("100%% ]\n");
1584 - ssb_printk(KERN_NOTICE PFX "SPROM written.\n");
1585 + ssb_cont("100%% ]\n");
1586 + ssb_notice("SPROM written\n");
1587
1588 return 0;
1589 err_ctlreg:
1590 - ssb_printk(KERN_ERR PFX "Could not access SPROM control register.\n");
1591 + ssb_err("Could not access SPROM control register.\n");
1592 return err;
1593 }
1594
1595 @@ -339,10 +347,23 @@ static s8 r123_extract_antgain(u8 sprom_
1596 return (s8)gain;
1597 }
1598
1599 +static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in)
1600 +{
1601 + SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
1602 + SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);
1603 + SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);
1604 + SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);
1605 + SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);
1606 + SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);
1607 + SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);
1608 + SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);
1609 + SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);
1610 + SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,
1611 + SSB_SPROM2_MAXP_A_LO_SHIFT);
1612 +}
1613 +
1614 static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)
1615 {
1616 - int i;
1617 - u16 v;
1618 u16 loc[3];
1619
1620 if (out->revision == 3) /* rev 3 moved MAC */
1621 @@ -352,19 +373,10 @@ static void sprom_extract_r123(struct ss
1622 loc[1] = SSB_SPROM1_ET0MAC;
1623 loc[2] = SSB_SPROM1_ET1MAC;
1624 }
1625 - for (i = 0; i < 3; i++) {
1626 - v = in[SPOFF(loc[0]) + i];
1627 - *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
1628 - }
1629 + sprom_get_mac(out->il0mac, &in[SPOFF(loc[0])]);
1630 if (out->revision < 3) { /* only rev 1-2 have et0, et1 */
1631 - for (i = 0; i < 3; i++) {
1632 - v = in[SPOFF(loc[1]) + i];
1633 - *(((__be16 *)out->et0mac) + i) = cpu_to_be16(v);
1634 - }
1635 - for (i = 0; i < 3; i++) {
1636 - v = in[SPOFF(loc[2]) + i];
1637 - *(((__be16 *)out->et1mac) + i) = cpu_to_be16(v);
1638 - }
1639 + sprom_get_mac(out->et0mac, &in[SPOFF(loc[1])]);
1640 + sprom_get_mac(out->et1mac, &in[SPOFF(loc[2])]);
1641 }
1642 SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0);
1643 SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A,
1644 @@ -372,6 +384,7 @@ static void sprom_extract_r123(struct ss
1645 SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
1646 SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
1647 SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
1648 + SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
1649 if (out->revision == 1)
1650 SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
1651 SSB_SPROM1_BINF_CCODE_SHIFT);
1652 @@ -398,8 +411,7 @@ static void sprom_extract_r123(struct ss
1653 SSB_SPROM1_ITSSI_A_SHIFT);
1654 SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);
1655 SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
1656 - if (out->revision >= 2)
1657 - SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
1658 +
1659 SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
1660 SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
1661
1662 @@ -410,6 +422,8 @@ static void sprom_extract_r123(struct ss
1663 out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
1664 SSB_SPROM1_AGAIN_A,
1665 SSB_SPROM1_AGAIN_A_SHIFT);
1666 + if (out->revision >= 2)
1667 + sprom_extract_r23(out, in);
1668 }
1669
1670 /* Revs 4 5 and 8 have partially shared layout */
1671 @@ -454,23 +468,20 @@ static void sprom_extract_r458(struct ss
1672
1673 static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
1674 {
1675 - int i;
1676 - u16 v;
1677 u16 il0mac_offset;
1678
1679 if (out->revision == 4)
1680 il0mac_offset = SSB_SPROM4_IL0MAC;
1681 else
1682 il0mac_offset = SSB_SPROM5_IL0MAC;
1683 - /* extract the MAC address */
1684 - for (i = 0; i < 3; i++) {
1685 - v = in[SPOFF(il0mac_offset) + i];
1686 - *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
1687 - }
1688 +
1689 + sprom_get_mac(out->il0mac, &in[SPOFF(il0mac_offset)]);
1690 +
1691 SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
1692 SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
1693 SSB_SPROM4_ETHPHY_ET1A_SHIFT);
1694 SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0);
1695 + SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
1696 if (out->revision == 4) {
1697 SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8);
1698 SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0);
1699 @@ -530,7 +541,7 @@ static void sprom_extract_r45(struct ssb
1700 static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
1701 {
1702 int i;
1703 - u16 v, o;
1704 + u16 o;
1705 u16 pwr_info_offset[] = {
1706 SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
1707 SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
1708 @@ -539,11 +550,10 @@ static void sprom_extract_r8(struct ssb_
1709 ARRAY_SIZE(out->core_pwr_info));
1710
1711 /* extract the MAC address */
1712 - for (i = 0; i < 3; i++) {
1713 - v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
1714 - *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
1715 - }
1716 + sprom_get_mac(out->il0mac, &in[SPOFF(SSB_SPROM8_IL0MAC)]);
1717 +
1718 SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0);
1719 + SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
1720 SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
1721 SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
1722 SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
1723 @@ -743,7 +753,7 @@ static int sprom_extract(struct ssb_bus
1724 memset(out, 0, sizeof(*out));
1725
1726 out->revision = in[size - 1] & 0x00FF;
1727 - ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
1728 + ssb_dbg("SPROM revision %d detected\n", out->revision);
1729 memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */
1730 memset(out->et1mac, 0xFF, 6);
1731
1732 @@ -752,7 +762,7 @@ static int sprom_extract(struct ssb_bus
1733 * number stored in the SPROM.
1734 * Always extract r1. */
1735 out->revision = 1;
1736 - ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision);
1737 + ssb_dbg("SPROM treated as revision %d\n", out->revision);
1738 }
1739
1740 switch (out->revision) {
1741 @@ -769,9 +779,8 @@ static int sprom_extract(struct ssb_bus
1742 sprom_extract_r8(out, in);
1743 break;
1744 default:
1745 - ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
1746 - " revision %d detected. Will extract"
1747 - " v1\n", out->revision);
1748 + ssb_warn("Unsupported SPROM revision %d detected. Will extract v1\n",
1749 + out->revision);
1750 out->revision = 1;
1751 sprom_extract_r123(out, in);
1752 }
1753 @@ -791,7 +800,7 @@ static int ssb_pci_sprom_get(struct ssb_
1754 u16 *buf;
1755
1756 if (!ssb_is_sprom_available(bus)) {
1757 - ssb_printk(KERN_ERR PFX "No SPROM available!\n");
1758 + ssb_err("No SPROM available!\n");
1759 return -ENODEV;
1760 }
1761 if (bus->chipco.dev) { /* can be unavailable! */
1762 @@ -810,7 +819,7 @@ static int ssb_pci_sprom_get(struct ssb_
1763 } else {
1764 bus->sprom_offset = SSB_SPROM_BASE1;
1765 }
1766 - ssb_dprintk(KERN_INFO PFX "SPROM offset is 0x%x\n", bus->sprom_offset);
1767 + ssb_dbg("SPROM offset is 0x%x\n", bus->sprom_offset);
1768
1769 buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
1770 if (!buf)
1771 @@ -835,18 +844,15 @@ static int ssb_pci_sprom_get(struct ssb_
1772 * available for this device in some other storage */
1773 err = ssb_fill_sprom_with_fallback(bus, sprom);
1774 if (err) {
1775 - ssb_printk(KERN_WARNING PFX "WARNING: Using"
1776 - " fallback SPROM failed (err %d)\n",
1777 - err);
1778 + ssb_warn("WARNING: Using fallback SPROM failed (err %d)\n",
1779 + err);
1780 } else {
1781 - ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
1782 - " revision %d provided by"
1783 - " platform.\n", sprom->revision);
1784 + ssb_dbg("Using SPROM revision %d provided by platform\n",
1785 + sprom->revision);
1786 err = 0;
1787 goto out_free;
1788 }
1789 - ssb_printk(KERN_WARNING PFX "WARNING: Invalid"
1790 - " SPROM CRC (corrupt SPROM)\n");
1791 + ssb_warn("WARNING: Invalid SPROM CRC (corrupt SPROM)\n");
1792 }
1793 }
1794 err = sprom_extract(bus, sprom, buf, bus->sprom_size);
1795 --- a/drivers/ssb/pcihost_wrapper.c
1796 +++ b/drivers/ssb/pcihost_wrapper.c
1797 @@ -38,7 +38,7 @@ static int ssb_pcihost_resume(struct pci
1798 struct ssb_bus *ssb = pci_get_drvdata(dev);
1799 int err;
1800
1801 - pci_set_power_state(dev, 0);
1802 + pci_set_power_state(dev, PCI_D0);
1803 err = pci_enable_device(dev);
1804 if (err)
1805 return err;
1806 --- a/drivers/ssb/pcmcia.c
1807 +++ b/drivers/ssb/pcmcia.c
1808 @@ -143,7 +143,7 @@ int ssb_pcmcia_switch_coreidx(struct ssb
1809
1810 return 0;
1811 error:
1812 - ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx);
1813 + ssb_err("Failed to switch to core %u\n", coreidx);
1814 return err;
1815 }
1816
1817 @@ -153,10 +153,9 @@ int ssb_pcmcia_switch_core(struct ssb_bu
1818 int err;
1819
1820 #if SSB_VERBOSE_PCMCIACORESWITCH_DEBUG
1821 - ssb_printk(KERN_INFO PFX
1822 - "Switching to %s core, index %d\n",
1823 - ssb_core_name(dev->id.coreid),
1824 - dev->core_index);
1825 + ssb_info("Switching to %s core, index %d\n",
1826 + ssb_core_name(dev->id.coreid),
1827 + dev->core_index);
1828 #endif
1829
1830 err = ssb_pcmcia_switch_coreidx(bus, dev->core_index);
1831 @@ -192,7 +191,7 @@ int ssb_pcmcia_switch_segment(struct ssb
1832
1833 return 0;
1834 error:
1835 - ssb_printk(KERN_ERR PFX "Failed to switch pcmcia segment\n");
1836 + ssb_err("Failed to switch pcmcia segment\n");
1837 return err;
1838 }
1839
1840 @@ -549,44 +548,39 @@ static int ssb_pcmcia_sprom_write_all(st
1841 bool failed = 0;
1842 size_t size = SSB_PCMCIA_SPROM_SIZE;
1843
1844 - ssb_printk(KERN_NOTICE PFX
1845 - "Writing SPROM. Do NOT turn off the power! "
1846 - "Please stand by...\n");
1847 + ssb_notice("Writing SPROM. Do NOT turn off the power! Please stand by...\n");
1848 err = ssb_pcmcia_sprom_command(bus, SSB_PCMCIA_SPROMCTL_WRITEEN);
1849 if (err) {
1850 - ssb_printk(KERN_NOTICE PFX
1851 - "Could not enable SPROM write access.\n");
1852 + ssb_notice("Could not enable SPROM write access\n");
1853 return -EBUSY;
1854 }
1855 - ssb_printk(KERN_NOTICE PFX "[ 0%%");
1856 + ssb_notice("[ 0%%");
1857 msleep(500);
1858 for (i = 0; i < size; i++) {
1859 if (i == size / 4)
1860 - ssb_printk("25%%");
1861 + ssb_cont("25%%");
1862 else if (i == size / 2)
1863 - ssb_printk("50%%");
1864 + ssb_cont("50%%");
1865 else if (i == (size * 3) / 4)
1866 - ssb_printk("75%%");
1867 + ssb_cont("75%%");
1868 else if (i % 2)
1869 - ssb_printk(".");
1870 + ssb_cont(".");
1871 err = ssb_pcmcia_sprom_write(bus, i, sprom[i]);
1872 if (err) {
1873 - ssb_printk(KERN_NOTICE PFX
1874 - "Failed to write to SPROM.\n");
1875 + ssb_notice("Failed to write to SPROM\n");
1876 failed = 1;
1877 break;
1878 }
1879 }
1880 err = ssb_pcmcia_sprom_command(bus, SSB_PCMCIA_SPROMCTL_WRITEDIS);
1881 if (err) {
1882 - ssb_printk(KERN_NOTICE PFX
1883 - "Could not disable SPROM write access.\n");
1884 + ssb_notice("Could not disable SPROM write access\n");
1885 failed = 1;
1886 }
1887 msleep(500);
1888 if (!failed) {
1889 - ssb_printk("100%% ]\n");
1890 - ssb_printk(KERN_NOTICE PFX "SPROM written.\n");
1891 + ssb_cont("100%% ]\n");
1892 + ssb_notice("SPROM written\n");
1893 }
1894
1895 return failed ? -EBUSY : 0;
1896 @@ -700,7 +694,7 @@ static int ssb_pcmcia_do_get_invariants(
1897 return -ENOSPC; /* continue with next entry */
1898
1899 error:
1900 - ssb_printk(KERN_ERR PFX
1901 + ssb_err(
1902 "PCMCIA: Failed to fetch device invariants: %s\n",
1903 error_description);
1904 return -ENODEV;
1905 @@ -722,7 +716,7 @@ int ssb_pcmcia_get_invariants(struct ssb
1906 res = pcmcia_loop_tuple(bus->host_pcmcia, CISTPL_FUNCE,
1907 ssb_pcmcia_get_mac, sprom);
1908 if (res != 0) {
1909 - ssb_printk(KERN_ERR PFX
1910 + ssb_err(
1911 "PCMCIA: Failed to fetch MAC address\n");
1912 return -ENODEV;
1913 }
1914 @@ -733,7 +727,7 @@ int ssb_pcmcia_get_invariants(struct ssb
1915 if ((res == 0) || (res == -ENOSPC))
1916 return 0;
1917
1918 - ssb_printk(KERN_ERR PFX
1919 + ssb_err(
1920 "PCMCIA: Failed to fetch device invariants\n");
1921 return -ENODEV;
1922 }
1923 @@ -843,6 +837,6 @@ int ssb_pcmcia_init(struct ssb_bus *bus)
1924
1925 return 0;
1926 error:
1927 - ssb_printk(KERN_ERR PFX "Failed to initialize PCMCIA host device\n");
1928 + ssb_err("Failed to initialize PCMCIA host device\n");
1929 return err;
1930 }
1931 --- a/drivers/ssb/scan.c
1932 +++ b/drivers/ssb/scan.c
1933 @@ -125,8 +125,7 @@ static u16 pcidev_to_chipid(struct pci_d
1934 chipid_fallback = 0x4401;
1935 break;
1936 default:
1937 - ssb_printk(KERN_ERR PFX
1938 - "PCI-ID not in fallback list\n");
1939 + ssb_err("PCI-ID not in fallback list\n");
1940 }
1941
1942 return chipid_fallback;
1943 @@ -152,8 +151,7 @@ static u8 chipid_to_nrcores(u16 chipid)
1944 case 0x4704:
1945 return 9;
1946 default:
1947 - ssb_printk(KERN_ERR PFX
1948 - "CHIPID not in nrcores fallback list\n");
1949 + ssb_err("CHIPID not in nrcores fallback list\n");
1950 }
1951
1952 return 1;
1953 @@ -320,15 +318,13 @@ int ssb_bus_scan(struct ssb_bus *bus,
1954 bus->chip_package = 0;
1955 }
1956 }
1957 - ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
1958 - "package 0x%02X\n", bus->chip_id, bus->chip_rev,
1959 - bus->chip_package);
1960 + ssb_info("Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
1961 + bus->chip_id, bus->chip_rev, bus->chip_package);
1962 if (!bus->nr_devices)
1963 bus->nr_devices = chipid_to_nrcores(bus->chip_id);
1964 if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
1965 - ssb_printk(KERN_ERR PFX
1966 - "More than %d ssb cores found (%d)\n",
1967 - SSB_MAX_NR_CORES, bus->nr_devices);
1968 + ssb_err("More than %d ssb cores found (%d)\n",
1969 + SSB_MAX_NR_CORES, bus->nr_devices);
1970 goto err_unmap;
1971 }
1972 if (bus->bustype == SSB_BUSTYPE_SSB) {
1973 @@ -370,8 +366,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
1974 nr_80211_cores++;
1975 if (nr_80211_cores > 1) {
1976 if (!we_support_multiple_80211_cores(bus)) {
1977 - ssb_dprintk(KERN_INFO PFX "Ignoring additional "
1978 - "802.11 core\n");
1979 + ssb_dbg("Ignoring additional 802.11 core\n");
1980 continue;
1981 }
1982 }
1983 @@ -379,8 +374,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
1984 case SSB_DEV_EXTIF:
1985 #ifdef CONFIG_SSB_DRIVER_EXTIF
1986 if (bus->extif.dev) {
1987 - ssb_printk(KERN_WARNING PFX
1988 - "WARNING: Multiple EXTIFs found\n");
1989 + ssb_warn("WARNING: Multiple EXTIFs found\n");
1990 break;
1991 }
1992 bus->extif.dev = dev;
1993 @@ -388,8 +382,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
1994 break;
1995 case SSB_DEV_CHIPCOMMON:
1996 if (bus->chipco.dev) {
1997 - ssb_printk(KERN_WARNING PFX
1998 - "WARNING: Multiple ChipCommon found\n");
1999 + ssb_warn("WARNING: Multiple ChipCommon found\n");
2000 break;
2001 }
2002 bus->chipco.dev = dev;
2003 @@ -398,8 +391,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
2004 case SSB_DEV_MIPS_3302:
2005 #ifdef CONFIG_SSB_DRIVER_MIPS
2006 if (bus->mipscore.dev) {
2007 - ssb_printk(KERN_WARNING PFX
2008 - "WARNING: Multiple MIPS cores found\n");
2009 + ssb_warn("WARNING: Multiple MIPS cores found\n");
2010 break;
2011 }
2012 bus->mipscore.dev = dev;
2013 @@ -420,8 +412,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
2014 }
2015 }
2016 if (bus->pcicore.dev) {
2017 - ssb_printk(KERN_WARNING PFX
2018 - "WARNING: Multiple PCI(E) cores found\n");
2019 + ssb_warn("WARNING: Multiple PCI(E) cores found\n");
2020 break;
2021 }
2022 bus->pcicore.dev = dev;
2023 --- a/drivers/ssb/sprom.c
2024 +++ b/drivers/ssb/sprom.c
2025 @@ -54,7 +54,7 @@ static int hex2sprom(u16 *sprom, const c
2026 while (cnt < sprom_size_words) {
2027 memcpy(tmp, dump, 4);
2028 dump += 4;
2029 - err = strict_strtoul(tmp, 16, &parsed);
2030 + err = kstrtoul(tmp, 16, &parsed);
2031 if (err)
2032 return err;
2033 sprom[cnt++] = swab16((u16)parsed);
2034 @@ -127,13 +127,13 @@ ssize_t ssb_attr_sprom_store(struct ssb_
2035 goto out_kfree;
2036 err = ssb_devices_freeze(bus, &freeze);
2037 if (err) {
2038 - ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n");
2039 + ssb_err("SPROM write: Could not freeze all devices\n");
2040 goto out_unlock;
2041 }
2042 res = sprom_write(bus, sprom);
2043 err = ssb_devices_thaw(&freeze);
2044 if (err)
2045 - ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n");
2046 + ssb_err("SPROM write: Could not thaw all devices\n");
2047 out_unlock:
2048 mutex_unlock(&bus->sprom_mutex);
2049 out_kfree:
2050 --- a/drivers/ssb/ssb_private.h
2051 +++ b/drivers/ssb/ssb_private.h
2052 @@ -3,21 +3,33 @@
2053
2054 #include <linux/ssb/ssb.h>
2055 #include <linux/types.h>
2056 +#include <linux/bcm47xx_wdt.h>
2057
2058
2059 #define PFX "ssb: "
2060
2061 #ifdef CONFIG_SSB_SILENT
2062 -# define ssb_printk(fmt, x...) do { /* nothing */ } while (0)
2063 +# define ssb_printk(fmt, ...) \
2064 + do { if (0) printk(fmt, ##__VA_ARGS__); } while (0)
2065 #else
2066 -# define ssb_printk printk
2067 +# define ssb_printk(fmt, ...) \
2068 + printk(fmt, ##__VA_ARGS__)
2069 #endif /* CONFIG_SSB_SILENT */
2070
2071 +#define ssb_emerg(fmt, ...) ssb_printk(KERN_EMERG PFX fmt, ##__VA_ARGS__)
2072 +#define ssb_err(fmt, ...) ssb_printk(KERN_ERR PFX fmt, ##__VA_ARGS__)
2073 +#define ssb_warn(fmt, ...) ssb_printk(KERN_WARNING PFX fmt, ##__VA_ARGS__)
2074 +#define ssb_notice(fmt, ...) ssb_printk(KERN_NOTICE PFX fmt, ##__VA_ARGS__)
2075 +#define ssb_info(fmt, ...) ssb_printk(KERN_INFO PFX fmt, ##__VA_ARGS__)
2076 +#define ssb_cont(fmt, ...) ssb_printk(KERN_CONT fmt, ##__VA_ARGS__)
2077 +
2078 /* dprintk: Debugging printk; vanishes for non-debug compilation */
2079 #ifdef CONFIG_SSB_DEBUG
2080 -# define ssb_dprintk(fmt, x...) ssb_printk(fmt , ##x)
2081 +# define ssb_dbg(fmt, ...) \
2082 + ssb_printk(KERN_DEBUG PFX fmt, ##__VA_ARGS__)
2083 #else
2084 -# define ssb_dprintk(fmt, x...) do { /* nothing */ } while (0)
2085 +# define ssb_dbg(fmt, ...) \
2086 + do { if (0) printk(KERN_DEBUG PFX fmt, ##__VA_ARGS__); } while (0)
2087 #endif
2088
2089 #ifdef CONFIG_SSB_DEBUG
2090 @@ -210,5 +222,76 @@ static inline void b43_pci_ssb_bridge_ex
2091 /* driver_chipcommon_pmu.c */
2092 extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
2093 extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
2094 +extern u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc);
2095 +
2096 +extern u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
2097 + u32 ticks);
2098 +extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
2099 +
2100 +/* driver_chipcommon_sflash.c */
2101 +#ifdef CONFIG_SSB_SFLASH
2102 +int ssb_sflash_init(struct ssb_chipcommon *cc);
2103 +#else
2104 +static inline int ssb_sflash_init(struct ssb_chipcommon *cc)
2105 +{
2106 + pr_err("Serial flash not supported\n");
2107 + return 0;
2108 +}
2109 +#endif /* CONFIG_SSB_SFLASH */
2110 +
2111 +#ifdef CONFIG_SSB_DRIVER_MIPS
2112 +extern struct platform_device ssb_pflash_dev;
2113 +#endif
2114 +
2115 +#ifdef CONFIG_SSB_SFLASH
2116 +extern struct platform_device ssb_sflash_dev;
2117 +#endif
2118 +
2119 +#ifdef CONFIG_SSB_DRIVER_EXTIF
2120 +extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
2121 +extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
2122 +#else
2123 +static inline u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
2124 + u32 ticks)
2125 +{
2126 + return 0;
2127 +}
2128 +static inline u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt,
2129 + u32 ms)
2130 +{
2131 + return 0;
2132 +}
2133 +#endif
2134 +
2135 +#ifdef CONFIG_SSB_EMBEDDED
2136 +extern int ssb_watchdog_register(struct ssb_bus *bus);
2137 +#else /* CONFIG_SSB_EMBEDDED */
2138 +static inline int ssb_watchdog_register(struct ssb_bus *bus)
2139 +{
2140 + return 0;
2141 +}
2142 +#endif /* CONFIG_SSB_EMBEDDED */
2143 +
2144 +#ifdef CONFIG_SSB_DRIVER_EXTIF
2145 +extern void ssb_extif_init(struct ssb_extif *extif);
2146 +#else
2147 +static inline void ssb_extif_init(struct ssb_extif *extif)
2148 +{
2149 +}
2150 +#endif
2151 +
2152 +#ifdef CONFIG_SSB_DRIVER_GPIO
2153 +extern int ssb_gpio_init(struct ssb_bus *bus);
2154 +extern int ssb_gpio_unregister(struct ssb_bus *bus);
2155 +#else /* CONFIG_SSB_DRIVER_GPIO */
2156 +static inline int ssb_gpio_init(struct ssb_bus *bus)
2157 +{
2158 + return -ENOTSUPP;
2159 +}
2160 +static inline int ssb_gpio_unregister(struct ssb_bus *bus)
2161 +{
2162 + return 0;
2163 +}
2164 +#endif /* CONFIG_SSB_DRIVER_GPIO */
2165
2166 #endif /* LINUX_SSB_PRIVATE_H_ */
2167 --- a/include/linux/ssb/ssb.h
2168 +++ b/include/linux/ssb/ssb.h
2169 @@ -6,8 +6,10 @@
2170 #include <linux/types.h>
2171 #include <linux/spinlock.h>
2172 #include <linux/pci.h>
2173 +#include <linux/gpio.h>
2174 #include <linux/mod_devicetable.h>
2175 #include <linux/dma-mapping.h>
2176 +#include <linux/platform_device.h>
2177
2178 #include <linux/ssb/ssb_regs.h>
2179
2180 @@ -24,9 +26,9 @@ struct ssb_sprom_core_pwr_info {
2181
2182 struct ssb_sprom {
2183 u8 revision;
2184 - u8 il0mac[6]; /* MAC address for 802.11b/g */
2185 - u8 et0mac[6]; /* MAC address for Ethernet */
2186 - u8 et1mac[6]; /* MAC address for 802.11a */
2187 + u8 il0mac[6] __aligned(sizeof(u16)); /* MAC address for 802.11b/g */
2188 + u8 et0mac[6] __aligned(sizeof(u16)); /* MAC address for Ethernet */
2189 + u8 et1mac[6] __aligned(sizeof(u16)); /* MAC address for 802.11a */
2190 u8 et0phyaddr; /* MII address for enet0 */
2191 u8 et1phyaddr; /* MII address for enet1 */
2192 u8 et0mdcport; /* MDIO for enet0 */
2193 @@ -338,13 +340,61 @@ enum ssb_bustype {
2194 #define SSB_BOARDVENDOR_DELL 0x1028 /* Dell */
2195 #define SSB_BOARDVENDOR_HP 0x0E11 /* HP */
2196 /* board_type */
2197 +#define SSB_BOARD_BCM94301CB 0x0406
2198 +#define SSB_BOARD_BCM94301MP 0x0407
2199 +#define SSB_BOARD_BU4309 0x040A
2200 +#define SSB_BOARD_BCM94309CB 0x040B
2201 +#define SSB_BOARD_BCM4309MP 0x040C
2202 +#define SSB_BOARD_BU4306 0x0416
2203 #define SSB_BOARD_BCM94306MP 0x0418
2204 #define SSB_BOARD_BCM4309G 0x0421
2205 #define SSB_BOARD_BCM4306CB 0x0417
2206 -#define SSB_BOARD_BCM4309MP 0x040C
2207 +#define SSB_BOARD_BCM94306PC 0x0425 /* pcmcia 3.3v 4306 card */
2208 +#define SSB_BOARD_BCM94306CBSG 0x042B /* with SiGe PA */
2209 +#define SSB_BOARD_PCSG94306 0x042D /* with SiGe PA */
2210 +#define SSB_BOARD_BU4704SD 0x042E /* with sdram */
2211 +#define SSB_BOARD_BCM94704AGR 0x042F /* dual 11a/11g Router */
2212 +#define SSB_BOARD_BCM94308MP 0x0430 /* 11a-only minipci */
2213 +#define SSB_BOARD_BU4318 0x0447
2214 +#define SSB_BOARD_CB4318 0x0448
2215 +#define SSB_BOARD_MPG4318 0x0449
2216 #define SSB_BOARD_MP4318 0x044A
2217 -#define SSB_BOARD_BU4306 0x0416
2218 -#define SSB_BOARD_BU4309 0x040A
2219 +#define SSB_BOARD_SD4318 0x044B
2220 +#define SSB_BOARD_BCM94306P 0x044C /* with SiGe */
2221 +#define SSB_BOARD_BCM94303MP 0x044E
2222 +#define SSB_BOARD_BCM94306MPM 0x0450
2223 +#define SSB_BOARD_BCM94306MPL 0x0453
2224 +#define SSB_BOARD_PC4303 0x0454 /* pcmcia */
2225 +#define SSB_BOARD_BCM94306MPLNA 0x0457
2226 +#define SSB_BOARD_BCM94306MPH 0x045B
2227 +#define SSB_BOARD_BCM94306PCIV 0x045C
2228 +#define SSB_BOARD_BCM94318MPGH 0x0463
2229 +#define SSB_BOARD_BU4311 0x0464
2230 +#define SSB_BOARD_BCM94311MC 0x0465
2231 +#define SSB_BOARD_BCM94311MCAG 0x0466
2232 +/* 4321 boards */
2233 +#define SSB_BOARD_BU4321 0x046B
2234 +#define SSB_BOARD_BU4321E 0x047C
2235 +#define SSB_BOARD_MP4321 0x046C
2236 +#define SSB_BOARD_CB2_4321 0x046D
2237 +#define SSB_BOARD_CB2_4321_AG 0x0066
2238 +#define SSB_BOARD_MC4321 0x046E
2239 +/* 4325 boards */
2240 +#define SSB_BOARD_BCM94325DEVBU 0x0490
2241 +#define SSB_BOARD_BCM94325BGABU 0x0491
2242 +#define SSB_BOARD_BCM94325SDGWB 0x0492
2243 +#define SSB_BOARD_BCM94325SDGMDL 0x04AA
2244 +#define SSB_BOARD_BCM94325SDGMDL2 0x04C6
2245 +#define SSB_BOARD_BCM94325SDGMDL3 0x04C9
2246 +#define SSB_BOARD_BCM94325SDABGWBA 0x04E1
2247 +/* 4322 boards */
2248 +#define SSB_BOARD_BCM94322MC 0x04A4
2249 +#define SSB_BOARD_BCM94322USB 0x04A8 /* dualband */
2250 +#define SSB_BOARD_BCM94322HM 0x04B0
2251 +#define SSB_BOARD_BCM94322USB2D 0x04Bf /* single band discrete front end */
2252 +/* 4312 boards */
2253 +#define SSB_BOARD_BU4312 0x048A
2254 +#define SSB_BOARD_BCM4312MCGSG 0x04B5
2255 /* chip_package */
2256 #define SSB_CHIPPACK_BCM4712S 1 /* Small 200pin 4712 */
2257 #define SSB_CHIPPACK_BCM4712M 2 /* Medium 225pin 4712 */
2258 @@ -432,7 +482,11 @@ struct ssb_bus {
2259 #ifdef CONFIG_SSB_EMBEDDED
2260 /* Lock for GPIO register access. */
2261 spinlock_t gpio_lock;
2262 + struct platform_device *watchdog;
2263 #endif /* EMBEDDED */
2264 +#ifdef CONFIG_SSB_DRIVER_GPIO
2265 + struct gpio_chip gpio;
2266 +#endif /* DRIVER_GPIO */
2267
2268 /* Internal-only stuff follows. Do not touch. */
2269 struct list_head list;
2270 --- a/include/linux/ssb/ssb_driver_chipcommon.h
2271 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
2272 @@ -219,6 +219,7 @@
2273 #define SSB_CHIPCO_PMU_CTL 0x0600 /* PMU control */
2274 #define SSB_CHIPCO_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
2275 #define SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT 16
2276 +#define SSB_CHIPCO_PMU_CTL_PLL_UPD 0x00000400
2277 #define SSB_CHIPCO_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
2278 #define SSB_CHIPCO_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
2279 #define SSB_CHIPCO_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
2280 @@ -590,7 +591,10 @@ struct ssb_chipcommon {
2281 u32 status;
2282 /* Fast Powerup Delay constant */
2283 u16 fast_pwrup_delay;
2284 + spinlock_t gpio_lock;
2285 struct ssb_chipcommon_pmu pmu;
2286 + u32 ticks_per_ms;
2287 + u32 max_timer_ms;
2288 };
2289
2290 static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
2291 @@ -630,8 +634,7 @@ enum ssb_clkmode {
2292 extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
2293 enum ssb_clkmode mode);
2294
2295 -extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc,
2296 - u32 ticks);
2297 +extern u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks);
2298
2299 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value);
2300
2301 @@ -644,6 +647,8 @@ u32 ssb_chipco_gpio_outen(struct ssb_chi
2302 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value);
2303 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value);
2304 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value);
2305 +u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value);
2306 +u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value);
2307
2308 #ifdef CONFIG_SSB_SERIAL
2309 extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
2310 @@ -663,5 +668,6 @@ enum ssb_pmu_ldo_volt_id {
2311 void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
2312 enum ssb_pmu_ldo_volt_id id, u32 voltage);
2313 void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on);
2314 +void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid);
2315
2316 #endif /* LINUX_SSB_CHIPCO_H_ */
2317 --- a/include/linux/ssb/ssb_driver_extif.h
2318 +++ b/include/linux/ssb/ssb_driver_extif.h
2319 @@ -152,12 +152,16 @@
2320 /* watchdog */
2321 #define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */
2322
2323 +#define SSB_EXTIF_WATCHDOG_MAX_TIMER ((1 << 28) - 1)
2324 +#define SSB_EXTIF_WATCHDOG_MAX_TIMER_MS (SSB_EXTIF_WATCHDOG_MAX_TIMER \
2325 + / (SSB_EXTIF_WATCHDOG_CLK / 1000))
2326
2327
2328 #ifdef CONFIG_SSB_DRIVER_EXTIF
2329
2330 struct ssb_extif {
2331 struct ssb_device *dev;
2332 + spinlock_t gpio_lock;
2333 };
2334
2335 static inline bool ssb_extif_available(struct ssb_extif *extif)
2336 @@ -171,8 +175,7 @@ extern void ssb_extif_get_clockcontrol(s
2337 extern void ssb_extif_timing_init(struct ssb_extif *extif,
2338 unsigned long ns);
2339
2340 -extern void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
2341 - u32 ticks);
2342 +extern u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks);
2343
2344 /* Extif GPIO pin access */
2345 u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask);
2346 @@ -205,10 +208,52 @@ void ssb_extif_get_clockcontrol(struct s
2347 }
2348
2349 static inline
2350 -void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
2351 - u32 ticks)
2352 +void ssb_extif_timing_init(struct ssb_extif *extif, unsigned long ns)
2353 {
2354 }
2355
2356 +static inline
2357 +u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
2358 +{
2359 + return 0;
2360 +}
2361 +
2362 +static inline u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
2363 +{
2364 + return 0;
2365 +}
2366 +
2367 +static inline u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask,
2368 + u32 value)
2369 +{
2370 + return 0;
2371 +}
2372 +
2373 +static inline u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask,
2374 + u32 value)
2375 +{
2376 + return 0;
2377 +}
2378 +
2379 +static inline u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask,
2380 + u32 value)
2381 +{
2382 + return 0;
2383 +}
2384 +
2385 +static inline u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask,
2386 + u32 value)
2387 +{
2388 + return 0;
2389 +}
2390 +
2391 +#ifdef CONFIG_SSB_SERIAL
2392 +static inline int ssb_extif_serial_init(struct ssb_extif *extif,
2393 + struct ssb_serial_port *ports)
2394 +{
2395 + return 0;
2396 +}
2397 +#endif /* CONFIG_SSB_SERIAL */
2398 +
2399 #endif /* CONFIG_SSB_DRIVER_EXTIF */
2400 #endif /* LINUX_SSB_EXTIFCORE_H_ */
2401 --- a/include/linux/ssb/ssb_driver_gige.h
2402 +++ b/include/linux/ssb/ssb_driver_gige.h
2403 @@ -97,21 +97,16 @@ static inline bool ssb_gige_must_flush_p
2404 return 0;
2405 }
2406
2407 -#ifdef CONFIG_BCM47XX
2408 -#include <asm/mach-bcm47xx/nvram.h>
2409 /* Get the device MAC address */
2410 -static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
2411 -{
2412 - char buf[20];
2413 - if (nvram_getenv("et0macaddr", buf, sizeof(buf)) < 0)
2414 - return;
2415 - nvram_parse_macaddr(buf, macaddr);
2416 -}
2417 -#else
2418 -static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
2419 +static inline int ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
2420 {
2421 + struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
2422 + if (!dev)
2423 + return -ENODEV;
2424 +
2425 + memcpy(macaddr, dev->dev->bus->sprom.et0mac, 6);
2426 + return 0;
2427 }
2428 -#endif
2429
2430 extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
2431 struct pci_dev *pdev);
2432 @@ -175,6 +170,10 @@ static inline bool ssb_gige_must_flush_p
2433 {
2434 return 0;
2435 }
2436 +static inline int ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
2437 +{
2438 + return -ENODEV;
2439 +}
2440
2441 #endif /* CONFIG_SSB_DRIVER_GIGE */
2442 #endif /* LINUX_SSB_DRIVER_GIGE_H_ */
2443 --- a/include/linux/ssb/ssb_driver_mips.h
2444 +++ b/include/linux/ssb/ssb_driver_mips.h
2445 @@ -13,6 +13,24 @@ struct ssb_serial_port {
2446 unsigned int reg_shift;
2447 };
2448
2449 +struct ssb_pflash {
2450 + bool present;
2451 + u8 buswidth;
2452 + u32 window;
2453 + u32 window_size;
2454 +};
2455 +
2456 +#ifdef CONFIG_SSB_SFLASH
2457 +struct ssb_sflash {
2458 + bool present;
2459 + u32 window;
2460 + u32 blocksize;
2461 + u16 numblocks;
2462 + u32 size;
2463 +
2464 + void *priv;
2465 +};
2466 +#endif
2467
2468 struct ssb_mipscore {
2469 struct ssb_device *dev;
2470 @@ -20,9 +38,10 @@ struct ssb_mipscore {
2471 int nr_serial_ports;
2472 struct ssb_serial_port serial_ports[4];
2473
2474 - u8 flash_buswidth;
2475 - u32 flash_window;
2476 - u32 flash_window_size;
2477 + struct ssb_pflash pflash;
2478 +#ifdef CONFIG_SSB_SFLASH
2479 + struct ssb_sflash sflash;
2480 +#endif
2481 };
2482
2483 extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
2484 @@ -41,6 +60,11 @@ void ssb_mipscore_init(struct ssb_mipsco
2485 {
2486 }
2487
2488 +static inline unsigned int ssb_mips_irq(struct ssb_device *dev)
2489 +{
2490 + return 0;
2491 +}
2492 +
2493 #endif /* CONFIG_SSB_DRIVER_MIPS */
2494
2495 #endif /* LINUX_SSB_MIPSCORE_H_ */
2496 --- a/include/linux/ssb/ssb_regs.h
2497 +++ b/include/linux/ssb/ssb_regs.h
2498 @@ -172,6 +172,7 @@
2499 #define SSB_SPROMSIZE_WORDS_R4 220
2500 #define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
2501 #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
2502 +#define SSB_SPROMSIZE_WORDS_R10 230
2503 #define SSB_SPROM_BASE1 0x1000
2504 #define SSB_SPROM_BASE31 0x0800
2505 #define SSB_SPROM_REVISION 0x007E
2506 @@ -289,11 +290,11 @@
2507 #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
2508 #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
2509 #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
2510 -#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
2511 -#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
2512 -#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
2513 -#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
2514 -#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
2515 +#define SSB_SPROM4_ANTAVAIL 0x005C /* Antenna available bitfields */
2516 +#define SSB_SPROM4_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
2517 +#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 0
2518 +#define SSB_SPROM4_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
2519 +#define SSB_SPROM4_ANTAVAIL_A_SHIFT 8
2520 #define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
2521 #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
2522 #define SSB_SPROM4_AGAIN0_SHIFT 0
2523 @@ -485,7 +486,7 @@
2524 #define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
2525 #define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL 0x0020
2526 #define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT 5
2527 -#define SSB_SPROM8_TEMPDELTA 0x00BA
2528 +#define SSB_SPROM8_TEMPDELTA 0x00BC
2529 #define SSB_SPROM8_TEMPDELTA_PHYCAL 0x00ff
2530 #define SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT 0
2531 #define SSB_SPROM8_TEMPDELTA_PERIOD 0x0f00
2532 --- /dev/null
2533 +++ b/include/linux/bcm47xx_wdt.h
2534 @@ -0,0 +1,19 @@
2535 +#ifndef LINUX_BCM47XX_WDT_H_
2536 +#define LINUX_BCM47XX_WDT_H_
2537 +
2538 +#include <linux/types.h>
2539 +
2540 +
2541 +struct bcm47xx_wdt {
2542 + u32 (*timer_set)(struct bcm47xx_wdt *, u32);
2543 + u32 (*timer_set_ms)(struct bcm47xx_wdt *, u32);
2544 + u32 max_timer_ms;
2545 +
2546 + void *driver_data;
2547 +};
2548 +
2549 +static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt)
2550 +{
2551 + return wdt->driver_data;
2552 +}
2553 +#endif /* LINUX_BCM47XX_WDT_H_ */
2554 --- a/drivers/net/wireless/b43/phy_n.c
2555 +++ b/drivers/net/wireless/b43/phy_n.c
2556 @@ -5165,7 +5165,8 @@ static void b43_nphy_pmu_spur_avoid(stru
2557 #endif
2558 #ifdef CONFIG_B43_SSB
2559 case B43_BUS_SSB:
2560 - /* FIXME */
2561 + ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco,
2562 + avoid);
2563 break;
2564 #endif
2565 }
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