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3228ff134d4072b603a5fd9662cdfc2eb18eeb13
[openwrt/openwrt.git] / target / linux / generic / patches-3.7 / 025-bcma_backport.patch
1 --- a/arch/mips/bcm47xx/nvram.c
2 +++ b/arch/mips/bcm47xx/nvram.c
3 @@ -43,8 +43,8 @@ static void early_nvram_init(void)
4 #ifdef CONFIG_BCM47XX_SSB
5 case BCM47XX_BUS_TYPE_SSB:
6 mcore_ssb = &bcm47xx_bus.ssb.mipscore;
7 - base = mcore_ssb->flash_window;
8 - lim = mcore_ssb->flash_window_size;
9 + base = mcore_ssb->pflash.window;
10 + lim = mcore_ssb->pflash.window_size;
11 break;
12 #endif
13 #ifdef CONFIG_BCM47XX_BCMA
14 --- a/arch/mips/bcm47xx/wgt634u.c
15 +++ b/arch/mips/bcm47xx/wgt634u.c
16 @@ -156,10 +156,10 @@ static int __init wgt634u_init(void)
17 SSB_CHIPCO_IRQ_GPIO);
18 }
19
20 - wgt634u_flash_data.width = mcore->flash_buswidth;
21 - wgt634u_flash_resource.start = mcore->flash_window;
22 - wgt634u_flash_resource.end = mcore->flash_window
23 - + mcore->flash_window_size
24 + wgt634u_flash_data.width = mcore->pflash.buswidth;
25 + wgt634u_flash_resource.start = mcore->pflash.window;
26 + wgt634u_flash_resource.end = mcore->pflash.window
27 + + mcore->pflash.window_size
28 - 1;
29 return platform_add_devices(wgt634u_devices,
30 ARRAY_SIZE(wgt634u_devices));
31 --- a/drivers/bcma/bcma_private.h
32 +++ b/drivers/bcma/bcma_private.h
33 @@ -48,8 +48,8 @@ void bcma_chipco_serial_init(struct bcma
34 #endif /* CONFIG_BCMA_DRIVER_MIPS */
35
36 /* driver_chipcommon_pmu.c */
37 -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
38 -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
39 +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
40 +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
41
42 #ifdef CONFIG_BCMA_SFLASH
43 /* driver_chipcommon_sflash.c */
44 @@ -84,6 +84,8 @@ extern void __exit bcma_host_pci_exit(vo
45 /* driver_pci.c */
46 u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
47
48 +extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc);
49 +
50 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
51 bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
52 void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
53 --- a/drivers/bcma/driver_chipcommon.c
54 +++ b/drivers/bcma/driver_chipcommon.c
55 @@ -4,12 +4,15 @@
56 *
57 * Copyright 2005, Broadcom Corporation
58 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
59 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
60 *
61 * Licensed under the GNU/GPL. See COPYING for details.
62 */
63
64 #include "bcma_private.h"
65 +#include <linux/bcm47xx_wdt.h>
66 #include <linux/export.h>
67 +#include <linux/platform_device.h>
68 #include <linux/bcma/bcma.h>
69
70 static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
71 @@ -22,12 +25,93 @@ static inline u32 bcma_cc_write32_masked
72 return value;
73 }
74
75 -void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
76 +static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
77 {
78 - u32 leddc_on = 10;
79 - u32 leddc_off = 90;
80 + if (cc->capabilities & BCMA_CC_CAP_PMU)
81 + return bcma_pmu_get_alp_clock(cc);
82
83 - if (cc->setup_done)
84 + return 20000000;
85 +}
86 +
87 +static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
88 +{
89 + struct bcma_bus *bus = cc->core->bus;
90 + u32 nb;
91 +
92 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
93 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
94 + nb = 32;
95 + else if (cc->core->id.rev < 26)
96 + nb = 16;
97 + else
98 + nb = (cc->core->id.rev >= 37) ? 32 : 24;
99 + } else {
100 + nb = 28;
101 + }
102 + if (nb == 32)
103 + return 0xffffffff;
104 + else
105 + return (1 << nb) - 1;
106 +}
107 +
108 +static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
109 + u32 ticks)
110 +{
111 + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
112 +
113 + return bcma_chipco_watchdog_timer_set(cc, ticks);
114 +}
115 +
116 +static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
117 + u32 ms)
118 +{
119 + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
120 + u32 ticks;
121 +
122 + ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
123 + return ticks / cc->ticks_per_ms;
124 +}
125 +
126 +static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
127 +{
128 + struct bcma_bus *bus = cc->core->bus;
129 +
130 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
131 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
132 + /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */
133 + return bcma_chipco_get_alp_clock(cc) / 4000;
134 + else
135 + /* based on 32KHz ILP clock */
136 + return 32;
137 + } else {
138 + return bcma_chipco_get_alp_clock(cc) / 1000;
139 + }
140 +}
141 +
142 +int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
143 +{
144 + struct bcm47xx_wdt wdt = {};
145 + struct platform_device *pdev;
146 +
147 + wdt.driver_data = cc;
148 + wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
149 + wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
150 + wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
151 +
152 + pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
153 + cc->core->bus->num, &wdt,
154 + sizeof(wdt));
155 + if (IS_ERR(pdev))
156 + return PTR_ERR(pdev);
157 +
158 + cc->watchdog = pdev;
159 +
160 + return 0;
161 +}
162 +
163 +void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
164 +{
165 + if (cc->early_setup_done)
166 return;
167
168 if (cc->core->id.rev >= 11)
169 @@ -36,6 +120,22 @@ void bcma_core_chipcommon_init(struct bc
170 if (cc->core->id.rev >= 35)
171 cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
172
173 + if (cc->capabilities & BCMA_CC_CAP_PMU)
174 + bcma_pmu_early_init(cc);
175 +
176 + cc->early_setup_done = true;
177 +}
178 +
179 +void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
180 +{
181 + u32 leddc_on = 10;
182 + u32 leddc_off = 90;
183 +
184 + if (cc->setup_done)
185 + return;
186 +
187 + bcma_core_chipcommon_early_init(cc);
188 +
189 if (cc->core->id.rev >= 20) {
190 bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
191 bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
192 @@ -56,15 +156,33 @@ void bcma_core_chipcommon_init(struct bc
193 ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
194 (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
195 }
196 + cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
197
198 cc->setup_done = true;
199 }
200
201 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
202 -void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
203 +u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
204 {
205 - /* instant NMI */
206 - bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
207 + u32 maxt;
208 + enum bcma_clkmode clkmode;
209 +
210 + maxt = bcma_chipco_watchdog_get_max_timer(cc);
211 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
212 + if (ticks == 1)
213 + ticks = 2;
214 + else if (ticks > maxt)
215 + ticks = maxt;
216 + bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
217 + } else {
218 + clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC;
219 + bcma_core_set_clockmode(cc->core, clkmode);
220 + if (ticks > maxt)
221 + ticks = maxt;
222 + /* instant NMI */
223 + bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
224 + }
225 + return ticks;
226 }
227
228 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
229 @@ -118,8 +236,7 @@ void bcma_chipco_serial_init(struct bcma
230 struct bcma_serial_port *ports = cc->serial_ports;
231
232 if (ccrev >= 11 && ccrev != 15) {
233 - /* Fixed ALP clock */
234 - baud_base = bcma_pmu_alp_clock(cc);
235 + baud_base = bcma_chipco_get_alp_clock(cc);
236 if (ccrev >= 21) {
237 /* Turn off UART clock before switching clocksource. */
238 bcma_cc_write32(cc, BCMA_CC_CORECTL,
239 --- a/drivers/bcma/driver_chipcommon_nflash.c
240 +++ b/drivers/bcma/driver_chipcommon_nflash.c
241 @@ -32,6 +32,9 @@ int bcma_nflash_init(struct bcma_drv_cc
242 }
243
244 cc->nflash.present = true;
245 + if (cc->core->id.rev == 38 &&
246 + (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT))
247 + cc->nflash.boot = true;
248
249 /* Prepare platform device, but don't register it yet. It's too early,
250 * malloc (required by device_private_init) is not available yet. */
251 --- a/drivers/bcma/driver_chipcommon_pmu.c
252 +++ b/drivers/bcma/driver_chipcommon_pmu.c
253 @@ -144,7 +144,7 @@ static void bcma_pmu_workarounds(struct
254 }
255 }
256
257 -void bcma_pmu_init(struct bcma_drv_cc *cc)
258 +void bcma_pmu_early_init(struct bcma_drv_cc *cc)
259 {
260 u32 pmucap;
261
262 @@ -153,7 +153,10 @@ void bcma_pmu_init(struct bcma_drv_cc *c
263
264 bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
265 cc->pmu.rev, pmucap);
266 +}
267
268 +void bcma_pmu_init(struct bcma_drv_cc *cc)
269 +{
270 if (cc->pmu.rev == 1)
271 bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
272 ~BCMA_CC_PMU_CTL_NOILPONW);
273 @@ -165,7 +168,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c
274 bcma_pmu_workarounds(cc);
275 }
276
277 -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
278 +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
279 {
280 struct bcma_bus *bus = cc->core->bus;
281
282 @@ -193,7 +196,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
283 /* Find the output of the "m" pll divider given pll controls that start with
284 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
285 */
286 -static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
287 +static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
288 {
289 u32 tmp, div, ndiv, p1, p2, fc;
290 struct bcma_bus *bus = cc->core->bus;
291 @@ -222,14 +225,14 @@ static u32 bcma_pmu_clock(struct bcma_dr
292 ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
293
294 /* Do calculation in Mhz */
295 - fc = bcma_pmu_alp_clock(cc) / 1000000;
296 + fc = bcma_pmu_get_alp_clock(cc) / 1000000;
297 fc = (p1 * ndiv * fc) / p2;
298
299 /* Return clock in Hertz */
300 return (fc / div) * 1000000;
301 }
302
303 -static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
304 +static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
305 {
306 u32 tmp, ndiv, p1div, p2div;
307 u32 clock;
308 @@ -260,7 +263,7 @@ static u32 bcma_pmu_clock_bcm4706(struct
309 }
310
311 /* query bus clock frequency for PMU-enabled chipcommon */
312 -static u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
313 +static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
314 {
315 struct bcma_bus *bus = cc->core->bus;
316
317 @@ -268,40 +271,42 @@ static u32 bcma_pmu_get_clockcontrol(str
318 case BCMA_CHIP_ID_BCM4716:
319 case BCMA_CHIP_ID_BCM4748:
320 case BCMA_CHIP_ID_BCM47162:
321 - return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
322 - BCMA_CC_PMU5_MAINPLL_SSB);
323 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
324 + BCMA_CC_PMU5_MAINPLL_SSB);
325 case BCMA_CHIP_ID_BCM5356:
326 - return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
327 - BCMA_CC_PMU5_MAINPLL_SSB);
328 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
329 + BCMA_CC_PMU5_MAINPLL_SSB);
330 case BCMA_CHIP_ID_BCM5357:
331 case BCMA_CHIP_ID_BCM4749:
332 - return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
333 - BCMA_CC_PMU5_MAINPLL_SSB);
334 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
335 + BCMA_CC_PMU5_MAINPLL_SSB);
336 case BCMA_CHIP_ID_BCM4706:
337 - return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
338 - BCMA_CC_PMU5_MAINPLL_SSB);
339 + return bcma_pmu_pll_clock_bcm4706(cc,
340 + BCMA_CC_PMU4706_MAINPLL_PLL0,
341 + BCMA_CC_PMU5_MAINPLL_SSB);
342 case BCMA_CHIP_ID_BCM53572:
343 return 75000000;
344 default:
345 - bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
346 + bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
347 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
348 }
349 return BCMA_CC_PMU_HT_CLOCK;
350 }
351
352 /* query cpu clock frequency for PMU-enabled chipcommon */
353 -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
354 +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
355 {
356 struct bcma_bus *bus = cc->core->bus;
357
358 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
359 return 300000000;
360
361 + /* New PMUs can have different clock for bus and CPU */
362 if (cc->pmu.rev >= 5) {
363 u32 pll;
364 switch (bus->chipinfo.id) {
365 case BCMA_CHIP_ID_BCM4706:
366 - return bcma_pmu_clock_bcm4706(cc,
367 + return bcma_pmu_pll_clock_bcm4706(cc,
368 BCMA_CC_PMU4706_MAINPLL_PLL0,
369 BCMA_CC_PMU5_MAINPLL_CPU);
370 case BCMA_CHIP_ID_BCM5356:
371 @@ -316,10 +321,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
372 break;
373 }
374
375 - return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
376 + return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
377 }
378
379 - return bcma_pmu_get_clockcontrol(cc);
380 + /* On old PMUs CPU has the same clock as the bus */
381 + return bcma_pmu_get_bus_clock(cc);
382 }
383
384 static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
385 --- a/drivers/bcma/driver_chipcommon_sflash.c
386 +++ b/drivers/bcma/driver_chipcommon_sflash.c
387 @@ -12,7 +12,7 @@
388
389 static struct resource bcma_sflash_resource = {
390 .name = "bcma_sflash",
391 - .start = BCMA_SFLASH,
392 + .start = BCMA_SOC_FLASH2,
393 .end = 0,
394 .flags = IORESOURCE_MEM | IORESOURCE_READONLY,
395 };
396 @@ -31,15 +31,42 @@ struct bcma_sflash_tbl_e {
397 };
398
399 static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
400 - { "", 0x14, 0x10000, 32, },
401 + { "M25P20", 0x11, 0x10000, 4, },
402 + { "M25P40", 0x12, 0x10000, 8, },
403 +
404 + { "M25P16", 0x14, 0x10000, 32, },
405 + { "M25P32", 0x14, 0x10000, 64, },
406 + { "M25P64", 0x16, 0x10000, 128, },
407 + { "M25FL128", 0x17, 0x10000, 256, },
408 { 0 },
409 };
410
411 static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
412 + { "SST25WF512", 1, 0x1000, 16, },
413 + { "SST25VF512", 0x48, 0x1000, 16, },
414 + { "SST25WF010", 2, 0x1000, 32, },
415 + { "SST25VF010", 0x49, 0x1000, 32, },
416 + { "SST25WF020", 3, 0x1000, 64, },
417 + { "SST25VF020", 0x43, 0x1000, 64, },
418 + { "SST25WF040", 4, 0x1000, 128, },
419 + { "SST25VF040", 0x44, 0x1000, 128, },
420 + { "SST25VF040B", 0x8d, 0x1000, 128, },
421 + { "SST25WF080", 5, 0x1000, 256, },
422 + { "SST25VF080B", 0x8e, 0x1000, 256, },
423 + { "SST25VF016", 0x41, 0x1000, 512, },
424 + { "SST25VF032", 0x4a, 0x1000, 1024, },
425 + { "SST25VF064", 0x4b, 0x1000, 2048, },
426 { 0 },
427 };
428
429 static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
430 + { "AT45DB011", 0xc, 256, 512, },
431 + { "AT45DB021", 0x14, 256, 1024, },
432 + { "AT45DB041", 0x1c, 256, 2048, },
433 + { "AT45DB081", 0x24, 256, 4096, },
434 + { "AT45DB161", 0x2c, 512, 4096, },
435 + { "AT45DB321", 0x34, 512, 8192, },
436 + { "AT45DB642", 0x3c, 1024, 8192, },
437 { 0 },
438 };
439
440 @@ -84,6 +111,8 @@ int bcma_sflash_init(struct bcma_drv_cc
441 break;
442 }
443 break;
444 + case 0x13:
445 + return -ENOTSUPP;
446 default:
447 for (e = bcma_sflash_st_tbl; e->name; e++) {
448 if (e->id == id)
449 @@ -116,7 +145,7 @@ int bcma_sflash_init(struct bcma_drv_cc
450 return -ENOTSUPP;
451 }
452
453 - sflash->window = BCMA_SFLASH;
454 + sflash->window = BCMA_SOC_FLASH2;
455 sflash->blocksize = e->blocksize;
456 sflash->numblocks = e->numblocks;
457 sflash->size = sflash->blocksize * sflash->numblocks;
458 --- a/drivers/bcma/driver_mips.c
459 +++ b/drivers/bcma/driver_mips.c
460 @@ -115,7 +115,7 @@ static void bcma_core_mips_set_irq(struc
461 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
462 ~(1 << irqflag));
463 else
464 - bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 0);
465 + bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
466
467 /* assign the new one */
468 if (irq == 0) {
469 @@ -171,7 +171,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
470 struct bcma_bus *bus = mcore->core->bus;
471
472 if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
473 - return bcma_pmu_get_clockcpu(&bus->drv_cc);
474 + return bcma_pmu_get_cpu_clock(&bus->drv_cc);
475
476 bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
477 return 0;
478 @@ -181,47 +181,66 @@ EXPORT_SYMBOL(bcma_cpu_clock);
479 static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
480 {
481 struct bcma_bus *bus = mcore->core->bus;
482 + struct bcma_drv_cc *cc = &bus->drv_cc;
483
484 - switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
485 + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
486 case BCMA_CC_FLASHT_STSER:
487 case BCMA_CC_FLASHT_ATSER:
488 bcma_debug(bus, "Found serial flash\n");
489 - bcma_sflash_init(&bus->drv_cc);
490 + bcma_sflash_init(cc);
491 break;
492 case BCMA_CC_FLASHT_PARA:
493 bcma_debug(bus, "Found parallel flash\n");
494 - bus->drv_cc.pflash.window = 0x1c000000;
495 - bus->drv_cc.pflash.window_size = 0x02000000;
496 + cc->pflash.present = true;
497 + cc->pflash.window = BCMA_SOC_FLASH2;
498 + cc->pflash.window_size = BCMA_SOC_FLASH2_SZ;
499
500 - if ((bcma_read32(bus->drv_cc.core, BCMA_CC_FLASH_CFG) &
501 + if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
502 BCMA_CC_FLASH_CFG_DS) == 0)
503 - bus->drv_cc.pflash.buswidth = 1;
504 + cc->pflash.buswidth = 1;
505 else
506 - bus->drv_cc.pflash.buswidth = 2;
507 + cc->pflash.buswidth = 2;
508 break;
509 default:
510 bcma_err(bus, "Flash type not supported\n");
511 }
512
513 - if (bus->drv_cc.core->id.rev == 38 ||
514 + if (cc->core->id.rev == 38 ||
515 bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
516 - if (bus->drv_cc.capabilities & BCMA_CC_CAP_NFLASH) {
517 + if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
518 bcma_debug(bus, "Found NAND flash\n");
519 - bcma_nflash_init(&bus->drv_cc);
520 + bcma_nflash_init(cc);
521 }
522 }
523 }
524
525 +void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
526 +{
527 + struct bcma_bus *bus = mcore->core->bus;
528 +
529 + if (mcore->early_setup_done)
530 + return;
531 +
532 + bcma_chipco_serial_init(&bus->drv_cc);
533 + bcma_core_mips_flash_detect(mcore);
534 +
535 + mcore->early_setup_done = true;
536 +}
537 +
538 void bcma_core_mips_init(struct bcma_drv_mips *mcore)
539 {
540 struct bcma_bus *bus;
541 struct bcma_device *core;
542 bus = mcore->core->bus;
543
544 + if (mcore->setup_done)
545 + return;
546 +
547 bcma_info(bus, "Initializing MIPS core...\n");
548
549 - if (!mcore->setup_done)
550 - mcore->assigned_irqs = 1;
551 + bcma_core_mips_early_init(mcore);
552 +
553 + mcore->assigned_irqs = 1;
554
555 /* Assign IRQs to all cores on the bus */
556 list_for_each_entry(core, &bus->cores, list) {
557 @@ -256,10 +275,5 @@ void bcma_core_mips_init(struct bcma_drv
558 bcma_info(bus, "IRQ reconfiguration done\n");
559 bcma_core_mips_dump_irq(bus);
560
561 - if (mcore->setup_done)
562 - return;
563 -
564 - bcma_chipco_serial_init(&bus->drv_cc);
565 - bcma_core_mips_flash_detect(mcore);
566 mcore->setup_done = true;
567 }
568 --- a/drivers/bcma/driver_pci_host.c
569 +++ b/drivers/bcma/driver_pci_host.c
570 @@ -35,11 +35,6 @@ bool __devinit bcma_core_pci_is_in_hostm
571 chipid_top != 0x5300)
572 return false;
573
574 - if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
575 - bcma_info(bus, "This PCI core is disabled and not working\n");
576 - return false;
577 - }
578 -
579 bcma_core_enable(pc->core, 0);
580
581 return !mips_busprobe32(tmp, pc->core->io_addr);
582 @@ -396,6 +391,11 @@ void __devinit bcma_core_pci_hostmode_in
583
584 bcma_info(bus, "PCIEcore in host mode found\n");
585
586 + if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
587 + bcma_info(bus, "This PCIE core is disabled and not working\n");
588 + return;
589 + }
590 +
591 pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
592 if (!pc_host) {
593 bcma_err(bus, "can not allocate memory");
594 @@ -452,6 +452,8 @@ void __devinit bcma_core_pci_hostmode_in
595 pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
596 pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
597 BCMA_SOC_PCI_MEM_SZ - 1;
598 + pc_host->io_resource.start = 0x100;
599 + pc_host->io_resource.end = 0x47F;
600 pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
601 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
602 tmp | BCMA_SOC_PCI_MEM);
603 @@ -459,6 +461,8 @@ void __devinit bcma_core_pci_hostmode_in
604 pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
605 pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
606 BCMA_SOC_PCI_MEM_SZ - 1;
607 + pc_host->io_resource.start = 0x480;
608 + pc_host->io_resource.end = 0x7FF;
609 pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
610 pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
611 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
612 @@ -534,7 +538,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_
613 static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
614 {
615 struct resource *res;
616 - int pos;
617 + int pos, err;
618
619 if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
620 /* This is not a device on the PCI-core bridge. */
621 @@ -547,8 +551,12 @@ static void bcma_core_pci_fixup_addresse
622
623 for (pos = 0; pos < 6; pos++) {
624 res = &dev->resource[pos];
625 - if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM))
626 - pci_assign_resource(dev, pos);
627 + if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) {
628 + err = pci_assign_resource(dev, pos);
629 + if (err)
630 + pr_err("PCI: Problem fixing up the addresses on %s\n",
631 + pci_name(dev));
632 + }
633 }
634 }
635 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
636 --- a/drivers/bcma/host_pci.c
637 +++ b/drivers/bcma/host_pci.c
638 @@ -238,7 +238,7 @@ static void __devexit bcma_host_pci_remo
639 pci_set_drvdata(dev, NULL);
640 }
641
642 -#ifdef CONFIG_PM
643 +#ifdef CONFIG_PM_SLEEP
644 static int bcma_host_pci_suspend(struct device *dev)
645 {
646 struct pci_dev *pdev = to_pci_dev(dev);
647 @@ -261,11 +261,11 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
648 bcma_host_pci_resume);
649 #define BCMA_PM_OPS (&bcma_pm_ops)
650
651 -#else /* CONFIG_PM */
652 +#else /* CONFIG_PM_SLEEP */
653
654 #define BCMA_PM_OPS NULL
655
656 -#endif /* CONFIG_PM */
657 +#endif /* CONFIG_PM_SLEEP */
658
659 static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
660 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
661 --- a/drivers/bcma/main.c
662 +++ b/drivers/bcma/main.c
663 @@ -81,6 +81,18 @@ struct bcma_device *bcma_find_core(struc
664 }
665 EXPORT_SYMBOL_GPL(bcma_find_core);
666
667 +static struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
668 + u8 unit)
669 +{
670 + struct bcma_device *core;
671 +
672 + list_for_each_entry(core, &bus->cores, list) {
673 + if (core->id.id == coreid && core->core_unit == unit)
674 + return core;
675 + }
676 + return NULL;
677 +}
678 +
679 static void bcma_release_core_dev(struct device *dev)
680 {
681 struct bcma_device *core = container_of(dev, struct bcma_device, dev);
682 @@ -153,6 +165,12 @@ static int bcma_register_cores(struct bc
683 }
684 #endif
685
686 + if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
687 + err = bcma_chipco_watchdog_register(&bus->drv_cc);
688 + if (err)
689 + bcma_err(bus, "Error registering watchdog driver\n");
690 + }
691 +
692 return 0;
693 }
694
695 @@ -165,6 +183,8 @@ static void bcma_unregister_cores(struct
696 if (core->dev_registered)
697 device_unregister(&core->dev);
698 }
699 + if (bus->hosttype == BCMA_HOSTTYPE_SOC)
700 + platform_device_unregister(bus->drv_cc.watchdog);
701 }
702
703 int __devinit bcma_bus_register(struct bcma_bus *bus)
704 @@ -183,6 +203,20 @@ int __devinit bcma_bus_register(struct b
705 return -1;
706 }
707
708 + /* Early init CC core */
709 + core = bcma_find_core(bus, bcma_cc_core_id(bus));
710 + if (core) {
711 + bus->drv_cc.core = core;
712 + bcma_core_chipcommon_early_init(&bus->drv_cc);
713 + }
714 +
715 + /* Try to get SPROM */
716 + err = bcma_sprom_get(bus);
717 + if (err == -ENOENT) {
718 + bcma_err(bus, "No SPROM available\n");
719 + } else if (err)
720 + bcma_err(bus, "Failed to get SPROM: %d\n", err);
721 +
722 /* Init CC core */
723 core = bcma_find_core(bus, bcma_cc_core_id(bus));
724 if (core) {
725 @@ -198,10 +232,17 @@ int __devinit bcma_bus_register(struct b
726 }
727
728 /* Init PCIE core */
729 - core = bcma_find_core(bus, BCMA_CORE_PCIE);
730 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 0);
731 if (core) {
732 - bus->drv_pci.core = core;
733 - bcma_core_pci_init(&bus->drv_pci);
734 + bus->drv_pci[0].core = core;
735 + bcma_core_pci_init(&bus->drv_pci[0]);
736 + }
737 +
738 + /* Init PCIE core */
739 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 1);
740 + if (core) {
741 + bus->drv_pci[1].core = core;
742 + bcma_core_pci_init(&bus->drv_pci[1]);
743 }
744
745 /* Init GBIT MAC COMMON core */
746 @@ -211,13 +252,6 @@ int __devinit bcma_bus_register(struct b
747 bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn);
748 }
749
750 - /* Try to get SPROM */
751 - err = bcma_sprom_get(bus);
752 - if (err == -ENOENT) {
753 - bcma_err(bus, "No SPROM available\n");
754 - } else if (err)
755 - bcma_err(bus, "Failed to get SPROM: %d\n", err);
756 -
757 /* Register found cores */
758 bcma_register_cores(bus);
759
760 @@ -275,18 +309,18 @@ int __init bcma_bus_early_register(struc
761 return -1;
762 }
763
764 - /* Init CC core */
765 + /* Early init CC core */
766 core = bcma_find_core(bus, bcma_cc_core_id(bus));
767 if (core) {
768 bus->drv_cc.core = core;
769 - bcma_core_chipcommon_init(&bus->drv_cc);
770 + bcma_core_chipcommon_early_init(&bus->drv_cc);
771 }
772
773 - /* Init MIPS core */
774 + /* Early init MIPS core */
775 core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
776 if (core) {
777 bus->drv_mips.core = core;
778 - bcma_core_mips_init(&bus->drv_mips);
779 + bcma_core_mips_early_init(&bus->drv_mips);
780 }
781
782 bcma_info(bus, "Early bus registered\n");
783 --- a/drivers/bcma/sprom.c
784 +++ b/drivers/bcma/sprom.c
785 @@ -595,8 +595,11 @@ int bcma_sprom_get(struct bcma_bus *bus)
786 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
787
788 err = bcma_sprom_valid(sprom);
789 - if (err)
790 + if (err) {
791 + bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
792 + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
793 goto out;
794 + }
795
796 bcma_sprom_extract_r8(bus, sprom);
797
798 --- a/include/linux/bcma/bcma.h
799 +++ b/include/linux/bcma/bcma.h
800 @@ -157,6 +157,7 @@ struct bcma_host_ops {
801
802 /* Chip IDs of SoCs */
803 #define BCMA_CHIP_ID_BCM4706 0x5300
804 +#define BCMA_PKG_ID_BCM4706L 1
805 #define BCMA_CHIP_ID_BCM4716 0x4716
806 #define BCMA_PKG_ID_BCM4716 8
807 #define BCMA_PKG_ID_BCM4717 9
808 @@ -166,7 +167,11 @@ struct bcma_host_ops {
809 #define BCMA_CHIP_ID_BCM4749 0x4749
810 #define BCMA_CHIP_ID_BCM5356 0x5356
811 #define BCMA_CHIP_ID_BCM5357 0x5357
812 +#define BCMA_PKG_ID_BCM5358 9
813 +#define BCMA_PKG_ID_BCM47186 10
814 +#define BCMA_PKG_ID_BCM5357 11
815 #define BCMA_CHIP_ID_BCM53572 53572
816 +#define BCMA_PKG_ID_BCM47188 9
817
818 struct bcma_device {
819 struct bcma_bus *bus;
820 @@ -251,7 +256,7 @@ struct bcma_bus {
821 u8 num;
822
823 struct bcma_drv_cc drv_cc;
824 - struct bcma_drv_pci drv_pci;
825 + struct bcma_drv_pci drv_pci[2];
826 struct bcma_drv_mips drv_mips;
827 struct bcma_drv_gmac_cmn drv_gmac_cmn;
828
829 --- a/include/linux/bcma/bcma_driver_chipcommon.h
830 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
831 @@ -1,6 +1,8 @@
832 #ifndef LINUX_BCMA_DRIVER_CC_H_
833 #define LINUX_BCMA_DRIVER_CC_H_
834
835 +#include <linux/platform_device.h>
836 +
837 /** ChipCommon core registers. **/
838 #define BCMA_CC_ID 0x0000
839 #define BCMA_CC_ID_ID 0x0000FFFF
840 @@ -510,6 +512,7 @@ struct bcma_chipcommon_pmu {
841
842 #ifdef CONFIG_BCMA_DRIVER_MIPS
843 struct bcma_pflash {
844 + bool present;
845 u8 buswidth;
846 u32 window;
847 u32 window_size;
848 @@ -532,6 +535,7 @@ struct mtd_info;
849
850 struct bcma_nflash {
851 bool present;
852 + bool boot; /* This is the flash the SoC boots from */
853
854 struct mtd_info *mtd;
855 };
856 @@ -552,6 +556,7 @@ struct bcma_drv_cc {
857 u32 capabilities;
858 u32 capabilities_ext;
859 u8 setup_done:1;
860 + u8 early_setup_done:1;
861 /* Fast Powerup Delay constant */
862 u16 fast_pwrup_delay;
863 struct bcma_chipcommon_pmu pmu;
864 @@ -567,6 +572,8 @@ struct bcma_drv_cc {
865 int nr_serial_ports;
866 struct bcma_serial_port serial_ports[4];
867 #endif /* CONFIG_BCMA_DRIVER_MIPS */
868 + u32 ticks_per_ms;
869 + struct platform_device *watchdog;
870 };
871
872 /* Register access */
873 @@ -583,14 +590,14 @@ struct bcma_drv_cc {
874 bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
875
876 extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
877 +extern void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);
878
879 extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
880 extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
881
882 void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
883
884 -extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
885 - u32 ticks);
886 +extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
887
888 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
889
890 @@ -606,6 +613,7 @@ u32 bcma_chipco_gpio_polarity(struct bcm
891
892 /* PMU support */
893 extern void bcma_pmu_init(struct bcma_drv_cc *cc);
894 +extern void bcma_pmu_early_init(struct bcma_drv_cc *cc);
895
896 extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
897 u32 value);
898 --- a/include/linux/bcma/bcma_driver_mips.h
899 +++ b/include/linux/bcma/bcma_driver_mips.h
900 @@ -35,13 +35,16 @@ struct bcma_device;
901 struct bcma_drv_mips {
902 struct bcma_device *core;
903 u8 setup_done:1;
904 + u8 early_setup_done:1;
905 unsigned int assigned_irqs;
906 };
907
908 #ifdef CONFIG_BCMA_DRIVER_MIPS
909 extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
910 +extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
911 #else
912 static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
913 +static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
914 #endif
915
916 extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
917 --- a/include/linux/bcma/bcma_regs.h
918 +++ b/include/linux/bcma/bcma_regs.h
919 @@ -85,6 +85,9 @@
920 * (2 ZettaBytes), high 32 bits
921 */
922
923 -#define BCMA_SFLASH 0x1c000000
924 +#define BCMA_SOC_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
925 +#define BCMA_SOC_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
926 +#define BCMA_SOC_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
927 +#define BCMA_SOC_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
928
929 #endif /* LINUX_BCMA_REGS_H_ */
930 --- a/drivers/net/wireless/b43/main.c
931 +++ b/drivers/net/wireless/b43/main.c
932 @@ -4652,7 +4652,7 @@ static int b43_wireless_core_init(struct
933 switch (dev->dev->bus_type) {
934 #ifdef CONFIG_B43_BCMA
935 case B43_BUS_BCMA:
936 - bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
937 + bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
938 dev->dev->bdev, true);
939 break;
940 #endif
941 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
942 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
943 @@ -692,7 +692,7 @@ void ai_pci_up(struct si_pub *sih)
944 sii = container_of(sih, struct si_info, pub);
945
946 if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
947 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, true);
948 + bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], true);
949 }
950
951 /* Unconfigure and/or apply various WARs when going down */
952 @@ -703,7 +703,7 @@ void ai_pci_down(struct si_pub *sih)
953 sii = container_of(sih, struct si_info, pub);
954
955 if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
956 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, false);
957 + bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], false);
958 }
959
960 /* Enable BT-COEX & Ex-PA for 4313 */
961 --- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
962 +++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
963 @@ -5077,7 +5077,7 @@ static int brcms_b_up_prep(struct brcms_
964 * Configure pci/pcmcia here instead of in brcms_c_attach()
965 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
966 */
967 - bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci, wlc_hw->d11core,
968 + bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core,
969 true);
970
971 /*
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