projects / openwrt / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
kernel: add missing bcma defines and header file for bcrmfmac
[openwrt/openwrt.git] / target / linux / generic / patches-3.7 / 025-bcma_backport.patch
1 --- a/drivers/bcma/Kconfig
2 +++ b/drivers/bcma/Kconfig
3 @@ -65,6 +65,14 @@ config BCMA_DRIVER_GMAC_CMN
4
5 If unsure, say N
6
7 +config BCMA_DRIVER_GPIO
8 + bool "BCMA GPIO driver"
9 + depends on BCMA && GPIOLIB
10 + help
11 + Driver to provide access to the GPIO pins of the bcma bus.
12 +
13 + If unsure, say N
14 +
15 config BCMA_DEBUG
16 bool "BCMA debugging"
17 depends on BCMA
18 --- a/drivers/bcma/Makefile
19 +++ b/drivers/bcma/Makefile
20 @@ -6,6 +6,7 @@ bcma-y += driver_pci.o
21 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
22 bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
23 bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
24 +bcma-$(CONFIG_BCMA_DRIVER_GPIO) += driver_gpio.o
25 bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o
26 bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o
27 obj-$(CONFIG_BCMA) += bcma.o
28 --- a/drivers/bcma/bcma_private.h
29 +++ b/drivers/bcma/bcma_private.h
30 @@ -31,6 +31,8 @@ int __init bcma_bus_early_register(struc
31 int bcma_bus_suspend(struct bcma_bus *bus);
32 int bcma_bus_resume(struct bcma_bus *bus);
33 #endif
34 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
35 + u8 unit);
36
37 /* scan.c */
38 int bcma_bus_scan(struct bcma_bus *bus);
39 @@ -48,8 +50,8 @@ void bcma_chipco_serial_init(struct bcma
40 #endif /* CONFIG_BCMA_DRIVER_MIPS */
41
42 /* driver_chipcommon_pmu.c */
43 -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
44 -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
45 +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
46 +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
47
48 #ifdef CONFIG_BCMA_SFLASH
49 /* driver_chipcommon_sflash.c */
50 @@ -84,9 +86,21 @@ extern void __exit bcma_host_pci_exit(vo
51 /* driver_pci.c */
52 u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
53
54 +extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc);
55 +
56 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
57 bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
58 void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
59 #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
60
61 +#ifdef CONFIG_BCMA_DRIVER_GPIO
62 +/* driver_gpio.c */
63 +int bcma_gpio_init(struct bcma_drv_cc *cc);
64 +#else
65 +static inline int bcma_gpio_init(struct bcma_drv_cc *cc)
66 +{
67 + return -ENOTSUPP;
68 +}
69 +#endif /* CONFIG_BCMA_DRIVER_GPIO */
70 +
71 #endif
72 --- a/drivers/bcma/driver_chipcommon.c
73 +++ b/drivers/bcma/driver_chipcommon.c
74 @@ -4,12 +4,15 @@
75 *
76 * Copyright 2005, Broadcom Corporation
77 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
78 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
79 *
80 * Licensed under the GNU/GPL. See COPYING for details.
81 */
82
83 #include "bcma_private.h"
84 +#include <linux/bcm47xx_wdt.h>
85 #include <linux/export.h>
86 +#include <linux/platform_device.h>
87 #include <linux/bcma/bcma.h>
88
89 static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
90 @@ -22,20 +25,120 @@ static inline u32 bcma_cc_write32_masked
91 return value;
92 }
93
94 -void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
95 +u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
96 {
97 - u32 leddc_on = 10;
98 - u32 leddc_off = 90;
99 + if (cc->capabilities & BCMA_CC_CAP_PMU)
100 + return bcma_pmu_get_alp_clock(cc);
101
102 - if (cc->setup_done)
103 + return 20000000;
104 +}
105 +EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock);
106 +
107 +static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
108 +{
109 + struct bcma_bus *bus = cc->core->bus;
110 + u32 nb;
111 +
112 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
113 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
114 + nb = 32;
115 + else if (cc->core->id.rev < 26)
116 + nb = 16;
117 + else
118 + nb = (cc->core->id.rev >= 37) ? 32 : 24;
119 + } else {
120 + nb = 28;
121 + }
122 + if (nb == 32)
123 + return 0xffffffff;
124 + else
125 + return (1 << nb) - 1;
126 +}
127 +
128 +static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
129 + u32 ticks)
130 +{
131 + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
132 +
133 + return bcma_chipco_watchdog_timer_set(cc, ticks);
134 +}
135 +
136 +static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
137 + u32 ms)
138 +{
139 + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
140 + u32 ticks;
141 +
142 + ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
143 + return ticks / cc->ticks_per_ms;
144 +}
145 +
146 +static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
147 +{
148 + struct bcma_bus *bus = cc->core->bus;
149 +
150 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
151 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
152 + /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */
153 + return bcma_chipco_get_alp_clock(cc) / 4000;
154 + else
155 + /* based on 32KHz ILP clock */
156 + return 32;
157 + } else {
158 + return bcma_chipco_get_alp_clock(cc) / 1000;
159 + }
160 +}
161 +
162 +int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
163 +{
164 + struct bcm47xx_wdt wdt = {};
165 + struct platform_device *pdev;
166 +
167 + wdt.driver_data = cc;
168 + wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
169 + wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
170 + wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
171 +
172 + pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
173 + cc->core->bus->num, &wdt,
174 + sizeof(wdt));
175 + if (IS_ERR(pdev))
176 + return PTR_ERR(pdev);
177 +
178 + cc->watchdog = pdev;
179 +
180 + return 0;
181 +}
182 +
183 +void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
184 +{
185 + if (cc->early_setup_done)
186 return;
187
188 + spin_lock_init(&cc->gpio_lock);
189 +
190 if (cc->core->id.rev >= 11)
191 cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
192 cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
193 if (cc->core->id.rev >= 35)
194 cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
195
196 + if (cc->capabilities & BCMA_CC_CAP_PMU)
197 + bcma_pmu_early_init(cc);
198 +
199 + cc->early_setup_done = true;
200 +}
201 +
202 +void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
203 +{
204 + u32 leddc_on = 10;
205 + u32 leddc_off = 90;
206 +
207 + if (cc->setup_done)
208 + return;
209 +
210 + bcma_core_chipcommon_early_init(cc);
211 +
212 if (cc->core->id.rev >= 20) {
213 bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
214 bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
215 @@ -56,15 +159,33 @@ void bcma_core_chipcommon_init(struct bc
216 ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
217 (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
218 }
219 + cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
220
221 cc->setup_done = true;
222 }
223
224 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
225 -void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
226 +u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
227 {
228 - /* instant NMI */
229 - bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
230 + u32 maxt;
231 + enum bcma_clkmode clkmode;
232 +
233 + maxt = bcma_chipco_watchdog_get_max_timer(cc);
234 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
235 + if (ticks == 1)
236 + ticks = 2;
237 + else if (ticks > maxt)
238 + ticks = maxt;
239 + bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
240 + } else {
241 + clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC;
242 + bcma_core_set_clockmode(cc->core, clkmode);
243 + if (ticks > maxt)
244 + ticks = maxt;
245 + /* instant NMI */
246 + bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
247 + }
248 + return ticks;
249 }
250
251 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
252 @@ -84,28 +205,99 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_
253
254 u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
255 {
256 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
257 + unsigned long flags;
258 + u32 res;
259 +
260 + spin_lock_irqsave(&cc->gpio_lock, flags);
261 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
262 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
263 +
264 + return res;
265 }
266 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out);
267
268 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
269 {
270 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
271 + unsigned long flags;
272 + u32 res;
273 +
274 + spin_lock_irqsave(&cc->gpio_lock, flags);
275 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
276 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
277 +
278 + return res;
279 }
280 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen);
281
282 +/*
283 + * If the bit is set to 0, chipcommon controlls this GPIO,
284 + * if the bit is set to 1, it is used by some part of the chip and not our code.
285 + */
286 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
287 {
288 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
289 + unsigned long flags;
290 + u32 res;
291 +
292 + spin_lock_irqsave(&cc->gpio_lock, flags);
293 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
294 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
295 +
296 + return res;
297 }
298 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
299
300 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
301 {
302 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
303 + unsigned long flags;
304 + u32 res;
305 +
306 + spin_lock_irqsave(&cc->gpio_lock, flags);
307 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
308 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
309 +
310 + return res;
311 }
312
313 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
314 {
315 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
316 + unsigned long flags;
317 + u32 res;
318 +
319 + spin_lock_irqsave(&cc->gpio_lock, flags);
320 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
321 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
322 +
323 + return res;
324 +}
325 +
326 +u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value)
327 +{
328 + unsigned long flags;
329 + u32 res;
330 +
331 + if (cc->core->id.rev < 20)
332 + return 0;
333 +
334 + spin_lock_irqsave(&cc->gpio_lock, flags);
335 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value);
336 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
337 +
338 + return res;
339 +}
340 +
341 +u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value)
342 +{
343 + unsigned long flags;
344 + u32 res;
345 +
346 + if (cc->core->id.rev < 20)
347 + return 0;
348 +
349 + spin_lock_irqsave(&cc->gpio_lock, flags);
350 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value);
351 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
352 +
353 + return res;
354 }
355
356 #ifdef CONFIG_BCMA_DRIVER_MIPS
357 @@ -118,8 +310,7 @@ void bcma_chipco_serial_init(struct bcma
358 struct bcma_serial_port *ports = cc->serial_ports;
359
360 if (ccrev >= 11 && ccrev != 15) {
361 - /* Fixed ALP clock */
362 - baud_base = bcma_pmu_alp_clock(cc);
363 + baud_base = bcma_chipco_get_alp_clock(cc);
364 if (ccrev >= 21) {
365 /* Turn off UART clock before switching clocksource. */
366 bcma_cc_write32(cc, BCMA_CC_CORECTL,
367 --- a/drivers/bcma/driver_chipcommon_nflash.c
368 +++ b/drivers/bcma/driver_chipcommon_nflash.c
369 @@ -32,6 +32,9 @@ int bcma_nflash_init(struct bcma_drv_cc
370 }
371
372 cc->nflash.present = true;
373 + if (cc->core->id.rev == 38 &&
374 + (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT))
375 + cc->nflash.boot = true;
376
377 /* Prepare platform device, but don't register it yet. It's too early,
378 * malloc (required by device_private_init) is not available yet. */
379 --- a/drivers/bcma/driver_chipcommon_pmu.c
380 +++ b/drivers/bcma/driver_chipcommon_pmu.c
381 @@ -13,12 +13,13 @@
382 #include <linux/export.h>
383 #include <linux/bcma/bcma.h>
384
385 -static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
386 +u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
387 {
388 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
389 bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
390 return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
391 }
392 +EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
393
394 void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
395 {
396 @@ -144,7 +145,7 @@ static void bcma_pmu_workarounds(struct
397 }
398 }
399
400 -void bcma_pmu_init(struct bcma_drv_cc *cc)
401 +void bcma_pmu_early_init(struct bcma_drv_cc *cc)
402 {
403 u32 pmucap;
404
405 @@ -153,7 +154,10 @@ void bcma_pmu_init(struct bcma_drv_cc *c
406
407 bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
408 cc->pmu.rev, pmucap);
409 +}
410
411 +void bcma_pmu_init(struct bcma_drv_cc *cc)
412 +{
413 if (cc->pmu.rev == 1)
414 bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
415 ~BCMA_CC_PMU_CTL_NOILPONW);
416 @@ -165,24 +169,40 @@ void bcma_pmu_init(struct bcma_drv_cc *c
417 bcma_pmu_workarounds(cc);
418 }
419
420 -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
421 +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
422 {
423 struct bcma_bus *bus = cc->core->bus;
424
425 switch (bus->chipinfo.id) {
426 + case BCMA_CHIP_ID_BCM4313:
427 + case BCMA_CHIP_ID_BCM43224:
428 + case BCMA_CHIP_ID_BCM43225:
429 + case BCMA_CHIP_ID_BCM43227:
430 + case BCMA_CHIP_ID_BCM43228:
431 + case BCMA_CHIP_ID_BCM4331:
432 + case BCMA_CHIP_ID_BCM43421:
433 + case BCMA_CHIP_ID_BCM43428:
434 + case BCMA_CHIP_ID_BCM43431:
435 case BCMA_CHIP_ID_BCM4716:
436 - case BCMA_CHIP_ID_BCM4748:
437 case BCMA_CHIP_ID_BCM47162:
438 - case BCMA_CHIP_ID_BCM4313:
439 - case BCMA_CHIP_ID_BCM5357:
440 + case BCMA_CHIP_ID_BCM4748:
441 case BCMA_CHIP_ID_BCM4749:
442 + case BCMA_CHIP_ID_BCM5357:
443 case BCMA_CHIP_ID_BCM53572:
444 + case BCMA_CHIP_ID_BCM6362:
445 /* always 20Mhz */
446 return 20000 * 1000;
447 - case BCMA_CHIP_ID_BCM5356:
448 case BCMA_CHIP_ID_BCM4706:
449 + case BCMA_CHIP_ID_BCM5356:
450 /* always 25Mhz */
451 return 25000 * 1000;
452 + case BCMA_CHIP_ID_BCM43460:
453 + case BCMA_CHIP_ID_BCM4352:
454 + case BCMA_CHIP_ID_BCM4360:
455 + if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ)
456 + return 40000 * 1000;
457 + else
458 + return 20000 * 1000;
459 default:
460 bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
461 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
462 @@ -193,7 +213,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
463 /* Find the output of the "m" pll divider given pll controls that start with
464 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
465 */
466 -static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
467 +static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
468 {
469 u32 tmp, div, ndiv, p1, p2, fc;
470 struct bcma_bus *bus = cc->core->bus;
471 @@ -222,14 +242,14 @@ static u32 bcma_pmu_clock(struct bcma_dr
472 ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
473
474 /* Do calculation in Mhz */
475 - fc = bcma_pmu_alp_clock(cc) / 1000000;
476 + fc = bcma_pmu_get_alp_clock(cc) / 1000000;
477 fc = (p1 * ndiv * fc) / p2;
478
479 /* Return clock in Hertz */
480 return (fc / div) * 1000000;
481 }
482
483 -static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
484 +static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
485 {
486 u32 tmp, ndiv, p1div, p2div;
487 u32 clock;
488 @@ -260,7 +280,7 @@ static u32 bcma_pmu_clock_bcm4706(struct
489 }
490
491 /* query bus clock frequency for PMU-enabled chipcommon */
492 -static u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
493 +static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
494 {
495 struct bcma_bus *bus = cc->core->bus;
496
497 @@ -268,40 +288,42 @@ static u32 bcma_pmu_get_clockcontrol(str
498 case BCMA_CHIP_ID_BCM4716:
499 case BCMA_CHIP_ID_BCM4748:
500 case BCMA_CHIP_ID_BCM47162:
501 - return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
502 - BCMA_CC_PMU5_MAINPLL_SSB);
503 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
504 + BCMA_CC_PMU5_MAINPLL_SSB);
505 case BCMA_CHIP_ID_BCM5356:
506 - return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
507 - BCMA_CC_PMU5_MAINPLL_SSB);
508 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
509 + BCMA_CC_PMU5_MAINPLL_SSB);
510 case BCMA_CHIP_ID_BCM5357:
511 case BCMA_CHIP_ID_BCM4749:
512 - return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
513 - BCMA_CC_PMU5_MAINPLL_SSB);
514 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
515 + BCMA_CC_PMU5_MAINPLL_SSB);
516 case BCMA_CHIP_ID_BCM4706:
517 - return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
518 - BCMA_CC_PMU5_MAINPLL_SSB);
519 + return bcma_pmu_pll_clock_bcm4706(cc,
520 + BCMA_CC_PMU4706_MAINPLL_PLL0,
521 + BCMA_CC_PMU5_MAINPLL_SSB);
522 case BCMA_CHIP_ID_BCM53572:
523 return 75000000;
524 default:
525 - bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
526 + bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
527 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
528 }
529 return BCMA_CC_PMU_HT_CLOCK;
530 }
531
532 /* query cpu clock frequency for PMU-enabled chipcommon */
533 -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
534 +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
535 {
536 struct bcma_bus *bus = cc->core->bus;
537
538 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
539 return 300000000;
540
541 + /* New PMUs can have different clock for bus and CPU */
542 if (cc->pmu.rev >= 5) {
543 u32 pll;
544 switch (bus->chipinfo.id) {
545 case BCMA_CHIP_ID_BCM4706:
546 - return bcma_pmu_clock_bcm4706(cc,
547 + return bcma_pmu_pll_clock_bcm4706(cc,
548 BCMA_CC_PMU4706_MAINPLL_PLL0,
549 BCMA_CC_PMU5_MAINPLL_CPU);
550 case BCMA_CHIP_ID_BCM5356:
551 @@ -316,10 +338,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
552 break;
553 }
554
555 - return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
556 + return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
557 }
558
559 - return bcma_pmu_get_clockcontrol(cc);
560 + /* On old PMUs CPU has the same clock as the bus */
561 + return bcma_pmu_get_bus_clock(cc);
562 }
563
564 static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
565 @@ -365,7 +388,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
566 tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
567 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
568
569 - tmp = 1 << 10;
570 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
571 break;
572
573 case BCMA_CHIP_ID_BCM4331:
574 @@ -386,7 +409,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
575 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
576 0x03000a08);
577 }
578 - tmp = 1 << 10;
579 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
580 break;
581
582 case BCMA_CHIP_ID_BCM43224:
583 @@ -419,7 +442,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
584 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
585 0x88888815);
586 }
587 - tmp = 1 << 10;
588 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
589 break;
590
591 case BCMA_CHIP_ID_BCM4716:
592 @@ -453,7 +476,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
593 0x88888815);
594 }
595
596 - tmp = 3 << 9;
597 + tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
598 break;
599
600 case BCMA_CHIP_ID_BCM43227:
601 @@ -489,7 +512,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
602 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
603 0x88888815);
604 }
605 - tmp = 1 << 10;
606 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
607 break;
608 default:
609 bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
610 --- a/drivers/bcma/driver_chipcommon_sflash.c
611 +++ b/drivers/bcma/driver_chipcommon_sflash.c
612 @@ -12,7 +12,7 @@
613
614 static struct resource bcma_sflash_resource = {
615 .name = "bcma_sflash",
616 - .start = BCMA_SFLASH,
617 + .start = BCMA_SOC_FLASH2,
618 .end = 0,
619 .flags = IORESOURCE_MEM | IORESOURCE_READONLY,
620 };
621 @@ -31,15 +31,42 @@ struct bcma_sflash_tbl_e {
622 };
623
624 static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
625 - { "", 0x14, 0x10000, 32, },
626 + { "M25P20", 0x11, 0x10000, 4, },
627 + { "M25P40", 0x12, 0x10000, 8, },
628 +
629 + { "M25P16", 0x14, 0x10000, 32, },
630 + { "M25P32", 0x15, 0x10000, 64, },
631 + { "M25P64", 0x16, 0x10000, 128, },
632 + { "M25FL128", 0x17, 0x10000, 256, },
633 { 0 },
634 };
635
636 static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
637 + { "SST25WF512", 1, 0x1000, 16, },
638 + { "SST25VF512", 0x48, 0x1000, 16, },
639 + { "SST25WF010", 2, 0x1000, 32, },
640 + { "SST25VF010", 0x49, 0x1000, 32, },
641 + { "SST25WF020", 3, 0x1000, 64, },
642 + { "SST25VF020", 0x43, 0x1000, 64, },
643 + { "SST25WF040", 4, 0x1000, 128, },
644 + { "SST25VF040", 0x44, 0x1000, 128, },
645 + { "SST25VF040B", 0x8d, 0x1000, 128, },
646 + { "SST25WF080", 5, 0x1000, 256, },
647 + { "SST25VF080B", 0x8e, 0x1000, 256, },
648 + { "SST25VF016", 0x41, 0x1000, 512, },
649 + { "SST25VF032", 0x4a, 0x1000, 1024, },
650 + { "SST25VF064", 0x4b, 0x1000, 2048, },
651 { 0 },
652 };
653
654 static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
655 + { "AT45DB011", 0xc, 256, 512, },
656 + { "AT45DB021", 0x14, 256, 1024, },
657 + { "AT45DB041", 0x1c, 256, 2048, },
658 + { "AT45DB081", 0x24, 256, 4096, },
659 + { "AT45DB161", 0x2c, 512, 4096, },
660 + { "AT45DB321", 0x34, 512, 8192, },
661 + { "AT45DB642", 0x3c, 1024, 8192, },
662 { 0 },
663 };
664
665 @@ -84,6 +111,8 @@ int bcma_sflash_init(struct bcma_drv_cc
666 break;
667 }
668 break;
669 + case 0x13:
670 + return -ENOTSUPP;
671 default:
672 for (e = bcma_sflash_st_tbl; e->name; e++) {
673 if (e->id == id)
674 @@ -116,7 +145,7 @@ int bcma_sflash_init(struct bcma_drv_cc
675 return -ENOTSUPP;
676 }
677
678 - sflash->window = BCMA_SFLASH;
679 + sflash->window = BCMA_SOC_FLASH2;
680 sflash->blocksize = e->blocksize;
681 sflash->numblocks = e->numblocks;
682 sflash->size = sflash->blocksize * sflash->numblocks;
683 --- /dev/null
684 +++ b/drivers/bcma/driver_gpio.c
685 @@ -0,0 +1,98 @@
686 +/*
687 + * Broadcom specific AMBA
688 + * GPIO driver
689 + *
690 + * Copyright 2011, Broadcom Corporation
691 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
692 + *
693 + * Licensed under the GNU/GPL. See COPYING for details.
694 + */
695 +
696 +#include <linux/gpio.h>
697 +#include <linux/export.h>
698 +#include <linux/bcma/bcma.h>
699 +
700 +#include "bcma_private.h"
701 +
702 +static inline struct bcma_drv_cc *bcma_gpio_get_cc(struct gpio_chip *chip)
703 +{
704 + return container_of(chip, struct bcma_drv_cc, gpio);
705 +}
706 +
707 +static int bcma_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
708 +{
709 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
710 +
711 + return !!bcma_chipco_gpio_in(cc, 1 << gpio);
712 +}
713 +
714 +static void bcma_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
715 + int value)
716 +{
717 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
718 +
719 + bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
720 +}
721 +
722 +static int bcma_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
723 +{
724 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
725 +
726 + bcma_chipco_gpio_outen(cc, 1 << gpio, 0);
727 + return 0;
728 +}
729 +
730 +static int bcma_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
731 + int value)
732 +{
733 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
734 +
735 + bcma_chipco_gpio_outen(cc, 1 << gpio, 1 << gpio);
736 + bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
737 + return 0;
738 +}
739 +
740 +static int bcma_gpio_request(struct gpio_chip *chip, unsigned gpio)
741 +{
742 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
743 +
744 + bcma_chipco_gpio_control(cc, 1 << gpio, 0);
745 + /* clear pulldown */
746 + bcma_chipco_gpio_pulldown(cc, 1 << gpio, 0);
747 + /* Set pullup */
748 + bcma_chipco_gpio_pullup(cc, 1 << gpio, 1 << gpio);
749 +
750 + return 0;
751 +}
752 +
753 +static void bcma_gpio_free(struct gpio_chip *chip, unsigned gpio)
754 +{
755 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
756 +
757 + /* clear pullup */
758 + bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
759 +}
760 +
761 +int bcma_gpio_init(struct bcma_drv_cc *cc)
762 +{
763 + struct gpio_chip *chip = &cc->gpio;
764 +
765 + chip->label = "bcma_gpio";
766 + chip->owner = THIS_MODULE;
767 + chip->request = bcma_gpio_request;
768 + chip->free = bcma_gpio_free;
769 + chip->get = bcma_gpio_get_value;
770 + chip->set = bcma_gpio_set_value;
771 + chip->direction_input = bcma_gpio_direction_input;
772 + chip->direction_output = bcma_gpio_direction_output;
773 + chip->ngpio = 16;
774 + /* There is just one SoC in one device and its GPIO addresses should be
775 + * deterministic to address them more easily. The other buses could get
776 + * a random base number. */
777 + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
778 + chip->base = 0;
779 + else
780 + chip->base = -1;
781 +
782 + return gpiochip_add(chip);
783 +}
784 --- a/drivers/bcma/driver_mips.c
785 +++ b/drivers/bcma/driver_mips.c
786 @@ -74,11 +74,16 @@ static u32 bcma_core_mips_irqflag(struct
787 return dev->core_index;
788 flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
789
790 - return flag & 0x1F;
791 + if (flag)
792 + return flag & 0x1F;
793 + else
794 + return 0x3f;
795 }
796
797 /* Get the MIPS IRQ assignment for a specified device.
798 * If unassigned, 0 is returned.
799 + * If disabled, 5 is returned.
800 + * If not supported, 6 is returned.
801 */
802 unsigned int bcma_core_mips_irq(struct bcma_device *dev)
803 {
804 @@ -87,13 +92,15 @@ unsigned int bcma_core_mips_irq(struct b
805 unsigned int irq;
806
807 irqflag = bcma_core_mips_irqflag(dev);
808 + if (irqflag == 0x3f)
809 + return 6;
810
811 - for (irq = 1; irq <= 4; irq++)
812 + for (irq = 0; irq <= 4; irq++)
813 if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
814 (1 << irqflag))
815 return irq;
816
817 - return 0;
818 + return 5;
819 }
820 EXPORT_SYMBOL(bcma_core_mips_irq);
821
822 @@ -114,7 +121,7 @@ static void bcma_core_mips_set_irq(struc
823 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
824 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
825 ~(1 << irqflag));
826 - else
827 + else if (oldirq != 5)
828 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
829
830 /* assign the new one */
831 @@ -123,9 +130,9 @@ static void bcma_core_mips_set_irq(struc
832 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
833 (1 << irqflag));
834 } else {
835 - u32 oldirqflag = bcma_read32(mdev,
836 - BCMA_MIPS_MIPS74K_INTMASK(irq));
837 - if (oldirqflag) {
838 + u32 irqinitmask = bcma_read32(mdev,
839 + BCMA_MIPS_MIPS74K_INTMASK(irq));
840 + if (irqinitmask) {
841 struct bcma_device *core;
842
843 /* backplane irq line is in use, find out who uses
844 @@ -133,7 +140,7 @@ static void bcma_core_mips_set_irq(struc
845 */
846 list_for_each_entry(core, &bus->cores, list) {
847 if ((1 << bcma_core_mips_irqflag(core)) ==
848 - oldirqflag) {
849 + irqinitmask) {
850 bcma_core_mips_set_irq(core, 0);
851 break;
852 }
853 @@ -143,15 +150,31 @@ static void bcma_core_mips_set_irq(struc
854 1 << irqflag);
855 }
856
857 - bcma_info(bus, "set_irq: core 0x%04x, irq %d => %d\n",
858 - dev->id.id, oldirq + 2, irq + 2);
859 + bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n",
860 + dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2);
861 +}
862 +
863 +static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq,
864 + u16 coreid, u8 unit)
865 +{
866 + struct bcma_device *core;
867 +
868 + core = bcma_find_core_unit(bus, coreid, unit);
869 + if (!core) {
870 + bcma_warn(bus,
871 + "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n",
872 + coreid, unit);
873 + return;
874 + }
875 +
876 + bcma_core_mips_set_irq(core, irq);
877 }
878
879 static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
880 {
881 int i;
882 static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
883 - printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
884 + printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
885 for (i = 0; i <= 6; i++)
886 printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
887 printk("\n");
888 @@ -171,7 +194,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
889 struct bcma_bus *bus = mcore->core->bus;
890
891 if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
892 - return bcma_pmu_get_clockcpu(&bus->drv_cc);
893 + return bcma_pmu_get_cpu_clock(&bus->drv_cc);
894
895 bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
896 return 0;
897 @@ -181,85 +204,109 @@ EXPORT_SYMBOL(bcma_cpu_clock);
898 static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
899 {
900 struct bcma_bus *bus = mcore->core->bus;
901 + struct bcma_drv_cc *cc = &bus->drv_cc;
902
903 - switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
904 + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
905 case BCMA_CC_FLASHT_STSER:
906 case BCMA_CC_FLASHT_ATSER:
907 bcma_debug(bus, "Found serial flash\n");
908 - bcma_sflash_init(&bus->drv_cc);
909 + bcma_sflash_init(cc);
910 break;
911 case BCMA_CC_FLASHT_PARA:
912 bcma_debug(bus, "Found parallel flash\n");
913 - bus->drv_cc.pflash.window = 0x1c000000;
914 - bus->drv_cc.pflash.window_size = 0x02000000;
915 + cc->pflash.present = true;
916 + cc->pflash.window = BCMA_SOC_FLASH2;
917 + cc->pflash.window_size = BCMA_SOC_FLASH2_SZ;
918
919 - if ((bcma_read32(bus->drv_cc.core, BCMA_CC_FLASH_CFG) &
920 + if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
921 BCMA_CC_FLASH_CFG_DS) == 0)
922 - bus->drv_cc.pflash.buswidth = 1;
923 + cc->pflash.buswidth = 1;
924 else
925 - bus->drv_cc.pflash.buswidth = 2;
926 + cc->pflash.buswidth = 2;
927 break;
928 default:
929 bcma_err(bus, "Flash type not supported\n");
930 }
931
932 - if (bus->drv_cc.core->id.rev == 38 ||
933 + if (cc->core->id.rev == 38 ||
934 bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
935 - if (bus->drv_cc.capabilities & BCMA_CC_CAP_NFLASH) {
936 + if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
937 bcma_debug(bus, "Found NAND flash\n");
938 - bcma_nflash_init(&bus->drv_cc);
939 + bcma_nflash_init(cc);
940 }
941 }
942 }
943
944 +void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
945 +{
946 + struct bcma_bus *bus = mcore->core->bus;
947 +
948 + if (mcore->early_setup_done)
949 + return;
950 +
951 + bcma_chipco_serial_init(&bus->drv_cc);
952 + bcma_core_mips_flash_detect(mcore);
953 +
954 + mcore->early_setup_done = true;
955 +}
956 +
957 void bcma_core_mips_init(struct bcma_drv_mips *mcore)
958 {
959 struct bcma_bus *bus;
960 struct bcma_device *core;
961 bus = mcore->core->bus;
962
963 - bcma_info(bus, "Initializing MIPS core...\n");
964 + if (mcore->setup_done)
965 + return;
966
967 - if (!mcore->setup_done)
968 - mcore->assigned_irqs = 1;
969 + bcma_debug(bus, "Initializing MIPS core...\n");
970
971 - /* Assign IRQs to all cores on the bus */
972 - list_for_each_entry(core, &bus->cores, list) {
973 - int mips_irq;
974 - if (core->irq)
975 - continue;
976 -
977 - mips_irq = bcma_core_mips_irq(core);
978 - if (mips_irq > 4)
979 - core->irq = 0;
980 - else
981 - core->irq = mips_irq + 2;
982 - if (core->irq > 5)
983 - continue;
984 - switch (core->id.id) {
985 - case BCMA_CORE_PCI:
986 - case BCMA_CORE_PCIE:
987 - case BCMA_CORE_ETHERNET:
988 - case BCMA_CORE_ETHERNET_GBIT:
989 - case BCMA_CORE_MAC_GBIT:
990 - case BCMA_CORE_80211:
991 - case BCMA_CORE_USB20_HOST:
992 - /* These devices get their own IRQ line if available,
993 - * the rest goes on IRQ0
994 - */
995 - if (mcore->assigned_irqs <= 4)
996 - bcma_core_mips_set_irq(core,
997 - mcore->assigned_irqs++);
998 - break;
999 + bcma_core_mips_early_init(mcore);
1000 +
1001 + switch (bus->chipinfo.id) {
1002 + case BCMA_CHIP_ID_BCM4716:
1003 + case BCMA_CHIP_ID_BCM4748:
1004 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1005 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1006 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
1007 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0);
1008 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1009 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
1010 + break;
1011 + case BCMA_CHIP_ID_BCM5356:
1012 + case BCMA_CHIP_ID_BCM47162:
1013 + case BCMA_CHIP_ID_BCM53572:
1014 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1015 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1016 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1017 + break;
1018 + case BCMA_CHIP_ID_BCM5357:
1019 + case BCMA_CHIP_ID_BCM4749:
1020 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1021 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1022 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
1023 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1024 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
1025 + break;
1026 + case BCMA_CHIP_ID_BCM4706:
1027 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0);
1028 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT,
1029 + 0);
1030 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1);
1031 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0);
1032 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON,
1033 + 0);
1034 + break;
1035 + default:
1036 + list_for_each_entry(core, &bus->cores, list) {
1037 + core->irq = bcma_core_mips_irq(core) + 2;
1038 }
1039 + bcma_err(bus,
1040 + "Unknown device (0x%x) found, can not configure IRQs\n",
1041 + bus->chipinfo.id);
1042 }
1043 - bcma_info(bus, "IRQ reconfiguration done\n");
1044 + bcma_debug(bus, "IRQ reconfiguration done\n");
1045 bcma_core_mips_dump_irq(bus);
1046
1047 - if (mcore->setup_done)
1048 - return;
1049 -
1050 - bcma_chipco_serial_init(&bus->drv_cc);
1051 - bcma_core_mips_flash_detect(mcore);
1052 mcore->setup_done = true;
1053 }
1054 --- a/drivers/bcma/driver_pci_host.c
1055 +++ b/drivers/bcma/driver_pci_host.c
1056 @@ -35,11 +35,6 @@ bool __devinit bcma_core_pci_is_in_hostm
1057 chipid_top != 0x5300)
1058 return false;
1059
1060 - if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
1061 - bcma_info(bus, "This PCI core is disabled and not working\n");
1062 - return false;
1063 - }
1064 -
1065 bcma_core_enable(pc->core, 0);
1066
1067 return !mips_busprobe32(tmp, pc->core->io_addr);
1068 @@ -396,6 +391,11 @@ void __devinit bcma_core_pci_hostmode_in
1069
1070 bcma_info(bus, "PCIEcore in host mode found\n");
1071
1072 + if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
1073 + bcma_info(bus, "This PCIE core is disabled and not working\n");
1074 + return;
1075 + }
1076 +
1077 pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
1078 if (!pc_host) {
1079 bcma_err(bus, "can not allocate memory");
1080 @@ -452,6 +452,8 @@ void __devinit bcma_core_pci_hostmode_in
1081 pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
1082 pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
1083 BCMA_SOC_PCI_MEM_SZ - 1;
1084 + pc_host->io_resource.start = 0x100;
1085 + pc_host->io_resource.end = 0x47F;
1086 pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
1087 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1088 tmp | BCMA_SOC_PCI_MEM);
1089 @@ -459,6 +461,8 @@ void __devinit bcma_core_pci_hostmode_in
1090 pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
1091 pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
1092 BCMA_SOC_PCI_MEM_SZ - 1;
1093 + pc_host->io_resource.start = 0x480;
1094 + pc_host->io_resource.end = 0x7FF;
1095 pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
1096 pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
1097 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1098 @@ -534,7 +538,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_
1099 static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
1100 {
1101 struct resource *res;
1102 - int pos;
1103 + int pos, err;
1104
1105 if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
1106 /* This is not a device on the PCI-core bridge. */
1107 @@ -547,8 +551,12 @@ static void bcma_core_pci_fixup_addresse
1108
1109 for (pos = 0; pos < 6; pos++) {
1110 res = &dev->resource[pos];
1111 - if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM))
1112 - pci_assign_resource(dev, pos);
1113 + if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) {
1114 + err = pci_assign_resource(dev, pos);
1115 + if (err)
1116 + pr_err("PCI: Problem fixing up the addresses on %s\n",
1117 + pci_name(dev));
1118 + }
1119 }
1120 }
1121 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
1122 --- a/drivers/bcma/host_pci.c
1123 +++ b/drivers/bcma/host_pci.c
1124 @@ -238,7 +238,7 @@ static void __devexit bcma_host_pci_remo
1125 pci_set_drvdata(dev, NULL);
1126 }
1127
1128 -#ifdef CONFIG_PM
1129 +#ifdef CONFIG_PM_SLEEP
1130 static int bcma_host_pci_suspend(struct device *dev)
1131 {
1132 struct pci_dev *pdev = to_pci_dev(dev);
1133 @@ -261,11 +261,11 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
1134 bcma_host_pci_resume);
1135 #define BCMA_PM_OPS (&bcma_pm_ops)
1136
1137 -#else /* CONFIG_PM */
1138 +#else /* CONFIG_PM_SLEEP */
1139
1140 #define BCMA_PM_OPS NULL
1141
1142 -#endif /* CONFIG_PM */
1143 +#endif /* CONFIG_PM_SLEEP */
1144
1145 static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
1146 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
1147 --- a/drivers/bcma/main.c
1148 +++ b/drivers/bcma/main.c
1149 @@ -81,6 +81,18 @@ struct bcma_device *bcma_find_core(struc
1150 }
1151 EXPORT_SYMBOL_GPL(bcma_find_core);
1152
1153 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
1154 + u8 unit)
1155 +{
1156 + struct bcma_device *core;
1157 +
1158 + list_for_each_entry(core, &bus->cores, list) {
1159 + if (core->id.id == coreid && core->core_unit == unit)
1160 + return core;
1161 + }
1162 + return NULL;
1163 +}
1164 +
1165 static void bcma_release_core_dev(struct device *dev)
1166 {
1167 struct bcma_device *core = container_of(dev, struct bcma_device, dev);
1168 @@ -152,6 +164,17 @@ static int bcma_register_cores(struct bc
1169 bcma_err(bus, "Error registering NAND flash\n");
1170 }
1171 #endif
1172 + err = bcma_gpio_init(&bus->drv_cc);
1173 + if (err == -ENOTSUPP)
1174 + bcma_debug(bus, "GPIO driver not activated\n");
1175 + else if (err)
1176 + bcma_err(bus, "Error registering GPIO driver: %i\n", err);
1177 +
1178 + if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
1179 + err = bcma_chipco_watchdog_register(&bus->drv_cc);
1180 + if (err)
1181 + bcma_err(bus, "Error registering watchdog driver\n");
1182 + }
1183
1184 return 0;
1185 }
1186 @@ -165,6 +188,8 @@ static void bcma_unregister_cores(struct
1187 if (core->dev_registered)
1188 device_unregister(&core->dev);
1189 }
1190 + if (bus->hosttype == BCMA_HOSTTYPE_SOC)
1191 + platform_device_unregister(bus->drv_cc.watchdog);
1192 }
1193
1194 int __devinit bcma_bus_register(struct bcma_bus *bus)
1195 @@ -183,6 +208,20 @@ int __devinit bcma_bus_register(struct b
1196 return -1;
1197 }
1198
1199 + /* Early init CC core */
1200 + core = bcma_find_core(bus, bcma_cc_core_id(bus));
1201 + if (core) {
1202 + bus->drv_cc.core = core;
1203 + bcma_core_chipcommon_early_init(&bus->drv_cc);
1204 + }
1205 +
1206 + /* Try to get SPROM */
1207 + err = bcma_sprom_get(bus);
1208 + if (err == -ENOENT) {
1209 + bcma_err(bus, "No SPROM available\n");
1210 + } else if (err)
1211 + bcma_err(bus, "Failed to get SPROM: %d\n", err);
1212 +
1213 /* Init CC core */
1214 core = bcma_find_core(bus, bcma_cc_core_id(bus));
1215 if (core) {
1216 @@ -198,10 +237,17 @@ int __devinit bcma_bus_register(struct b
1217 }
1218
1219 /* Init PCIE core */
1220 - core = bcma_find_core(bus, BCMA_CORE_PCIE);
1221 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 0);
1222 if (core) {
1223 - bus->drv_pci.core = core;
1224 - bcma_core_pci_init(&bus->drv_pci);
1225 + bus->drv_pci[0].core = core;
1226 + bcma_core_pci_init(&bus->drv_pci[0]);
1227 + }
1228 +
1229 + /* Init PCIE core */
1230 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 1);
1231 + if (core) {
1232 + bus->drv_pci[1].core = core;
1233 + bcma_core_pci_init(&bus->drv_pci[1]);
1234 }
1235
1236 /* Init GBIT MAC COMMON core */
1237 @@ -211,13 +257,6 @@ int __devinit bcma_bus_register(struct b
1238 bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn);
1239 }
1240
1241 - /* Try to get SPROM */
1242 - err = bcma_sprom_get(bus);
1243 - if (err == -ENOENT) {
1244 - bcma_err(bus, "No SPROM available\n");
1245 - } else if (err)
1246 - bcma_err(bus, "Failed to get SPROM: %d\n", err);
1247 -
1248 /* Register found cores */
1249 bcma_register_cores(bus);
1250
1251 @@ -275,18 +314,18 @@ int __init bcma_bus_early_register(struc
1252 return -1;
1253 }
1254
1255 - /* Init CC core */
1256 + /* Early init CC core */
1257 core = bcma_find_core(bus, bcma_cc_core_id(bus));
1258 if (core) {
1259 bus->drv_cc.core = core;
1260 - bcma_core_chipcommon_init(&bus->drv_cc);
1261 + bcma_core_chipcommon_early_init(&bus->drv_cc);
1262 }
1263
1264 - /* Init MIPS core */
1265 + /* Early init MIPS core */
1266 core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
1267 if (core) {
1268 bus->drv_mips.core = core;
1269 - bcma_core_mips_init(&bus->drv_mips);
1270 + bcma_core_mips_early_init(&bus->drv_mips);
1271 }
1272
1273 bcma_info(bus, "Early bus registered\n");
1274 --- a/drivers/bcma/sprom.c
1275 +++ b/drivers/bcma/sprom.c
1276 @@ -595,8 +595,11 @@ int bcma_sprom_get(struct bcma_bus *bus)
1277 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
1278
1279 err = bcma_sprom_valid(sprom);
1280 - if (err)
1281 + if (err) {
1282 + bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
1283 + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
1284 goto out;
1285 + }
1286
1287 bcma_sprom_extract_r8(bus, sprom);
1288
1289 --- a/include/linux/bcma/bcma.h
1290 +++ b/include/linux/bcma/bcma.h
1291 @@ -134,6 +134,7 @@ struct bcma_host_ops {
1292 #define BCMA_CORE_I2S 0x834
1293 #define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */
1294 #define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */
1295 +#define BCMA_CORE_ARM_CR4 0x83e
1296 #define BCMA_CORE_DEFAULT 0xFFF
1297
1298 #define BCMA_MAX_NR_CORES 16
1299 @@ -157,6 +158,7 @@ struct bcma_host_ops {
1300
1301 /* Chip IDs of SoCs */
1302 #define BCMA_CHIP_ID_BCM4706 0x5300
1303 +#define BCMA_PKG_ID_BCM4706L 1
1304 #define BCMA_CHIP_ID_BCM4716 0x4716
1305 #define BCMA_PKG_ID_BCM4716 8
1306 #define BCMA_PKG_ID_BCM4717 9
1307 @@ -166,7 +168,11 @@ struct bcma_host_ops {
1308 #define BCMA_CHIP_ID_BCM4749 0x4749
1309 #define BCMA_CHIP_ID_BCM5356 0x5356
1310 #define BCMA_CHIP_ID_BCM5357 0x5357
1311 +#define BCMA_PKG_ID_BCM5358 9
1312 +#define BCMA_PKG_ID_BCM47186 10
1313 +#define BCMA_PKG_ID_BCM5357 11
1314 #define BCMA_CHIP_ID_BCM53572 53572
1315 +#define BCMA_PKG_ID_BCM47188 9
1316
1317 struct bcma_device {
1318 struct bcma_bus *bus;
1319 @@ -251,7 +257,7 @@ struct bcma_bus {
1320 u8 num;
1321
1322 struct bcma_drv_cc drv_cc;
1323 - struct bcma_drv_pci drv_pci;
1324 + struct bcma_drv_pci drv_pci[2];
1325 struct bcma_drv_mips drv_mips;
1326 struct bcma_drv_gmac_cmn drv_gmac_cmn;
1327
1328 @@ -345,6 +351,7 @@ extern void bcma_core_set_clockmode(stru
1329 enum bcma_clkmode clkmode);
1330 extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status,
1331 bool on);
1332 +extern u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset);
1333 #define BCMA_DMA_TRANSLATION_MASK 0xC0000000
1334 #define BCMA_DMA_TRANSLATION_NONE 0x00000000
1335 #define BCMA_DMA_TRANSLATION_DMA32_CMT 0x40000000 /* Client Mode Translation for 32-bit DMA */
1336 --- a/include/linux/bcma/bcma_driver_chipcommon.h
1337 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
1338 @@ -1,6 +1,9 @@
1339 #ifndef LINUX_BCMA_DRIVER_CC_H_
1340 #define LINUX_BCMA_DRIVER_CC_H_
1341
1342 +#include <linux/platform_device.h>
1343 +#include <linux/gpio.h>
1344 +
1345 /** ChipCommon core registers. **/
1346 #define BCMA_CC_ID 0x0000
1347 #define BCMA_CC_ID_ID 0x0000FFFF
1348 @@ -101,6 +104,7 @@
1349 #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
1350 #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
1351 #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
1352 +#define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001
1353 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
1354 #define BCMA_CC_JCMD_START 0x80000000
1355 #define BCMA_CC_JCMD_BUSY 0x80000000
1356 @@ -312,6 +316,9 @@
1357 #define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
1358 #define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
1359 #define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
1360 +#define BCMA_CC_PMU_CTL_RES 0x00006000 /* reset control mask */
1361 +#define BCMA_CC_PMU_CTL_RES_SHIFT 13
1362 +#define BCMA_CC_PMU_CTL_RES_RELOAD 0x2 /* reload POR values */
1363 #define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
1364 #define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
1365 #define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
1366 @@ -510,6 +517,7 @@ struct bcma_chipcommon_pmu {
1367
1368 #ifdef CONFIG_BCMA_DRIVER_MIPS
1369 struct bcma_pflash {
1370 + bool present;
1371 u8 buswidth;
1372 u32 window;
1373 u32 window_size;
1374 @@ -532,6 +540,7 @@ struct mtd_info;
1375
1376 struct bcma_nflash {
1377 bool present;
1378 + bool boot; /* This is the flash the SoC boots from */
1379
1380 struct mtd_info *mtd;
1381 };
1382 @@ -552,6 +561,7 @@ struct bcma_drv_cc {
1383 u32 capabilities;
1384 u32 capabilities_ext;
1385 u8 setup_done:1;
1386 + u8 early_setup_done:1;
1387 /* Fast Powerup Delay constant */
1388 u16 fast_pwrup_delay;
1389 struct bcma_chipcommon_pmu pmu;
1390 @@ -567,6 +577,14 @@ struct bcma_drv_cc {
1391 int nr_serial_ports;
1392 struct bcma_serial_port serial_ports[4];
1393 #endif /* CONFIG_BCMA_DRIVER_MIPS */
1394 + u32 ticks_per_ms;
1395 + struct platform_device *watchdog;
1396 +
1397 + /* Lock for GPIO register access. */
1398 + spinlock_t gpio_lock;
1399 +#ifdef CONFIG_BCMA_DRIVER_GPIO
1400 + struct gpio_chip gpio;
1401 +#endif
1402 };
1403
1404 /* Register access */
1405 @@ -583,14 +601,16 @@ struct bcma_drv_cc {
1406 bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
1407
1408 extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
1409 +extern void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);
1410
1411 extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
1412 extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
1413
1414 void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
1415
1416 -extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
1417 - u32 ticks);
1418 +extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
1419 +
1420 +extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
1421
1422 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
1423
1424 @@ -603,9 +623,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
1425 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
1426 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
1427 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
1428 +u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value);
1429 +u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value);
1430
1431 /* PMU support */
1432 extern void bcma_pmu_init(struct bcma_drv_cc *cc);
1433 +extern void bcma_pmu_early_init(struct bcma_drv_cc *cc);
1434
1435 extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
1436 u32 value);
1437 --- a/include/linux/bcma/bcma_driver_mips.h
1438 +++ b/include/linux/bcma/bcma_driver_mips.h
1439 @@ -35,13 +35,15 @@ struct bcma_device;
1440 struct bcma_drv_mips {
1441 struct bcma_device *core;
1442 u8 setup_done:1;
1443 - unsigned int assigned_irqs;
1444 + u8 early_setup_done:1;
1445 };
1446
1447 #ifdef CONFIG_BCMA_DRIVER_MIPS
1448 extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
1449 +extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
1450 #else
1451 static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
1452 +static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
1453 #endif
1454
1455 extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
1456 --- a/include/linux/bcma/bcma_regs.h
1457 +++ b/include/linux/bcma/bcma_regs.h
1458 @@ -37,6 +37,7 @@
1459 #define BCMA_IOST_BIST_DONE 0x8000
1460 #define BCMA_RESET_CTL 0x0800
1461 #define BCMA_RESET_CTL_RESET 0x0001
1462 +#define BCMA_RESET_ST 0x0804
1463
1464 /* BCMA PCI config space registers. */
1465 #define BCMA_PCI_PMCSR 0x44
1466 @@ -85,6 +86,9 @@
1467 * (2 ZettaBytes), high 32 bits
1468 */
1469
1470 -#define BCMA_SFLASH 0x1c000000
1471 +#define BCMA_SOC_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
1472 +#define BCMA_SOC_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
1473 +#define BCMA_SOC_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
1474 +#define BCMA_SOC_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
1475
1476 #endif /* LINUX_BCMA_REGS_H_ */
1477 --- a/drivers/net/wireless/b43/main.c
1478 +++ b/drivers/net/wireless/b43/main.c
1479 @@ -4684,7 +4684,7 @@ static int b43_wireless_core_init(struct
1480 switch (dev->dev->bus_type) {
1481 #ifdef CONFIG_B43_BCMA
1482 case B43_BUS_BCMA:
1483 - bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
1484 + bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
1485 dev->dev->bdev, true);
1486 break;
1487 #endif
1488 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
1489 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
1490 @@ -692,7 +692,7 @@ void ai_pci_up(struct si_pub *sih)
1491 sii = container_of(sih, struct si_info, pub);
1492
1493 if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
1494 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, true);
1495 + bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], true);
1496 }
1497
1498 /* Unconfigure and/or apply various WARs when going down */
1499 @@ -703,7 +703,7 @@ void ai_pci_down(struct si_pub *sih)
1500 sii = container_of(sih, struct si_info, pub);
1501
1502 if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
1503 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, false);
1504 + bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], false);
1505 }
1506
1507 /* Enable BT-COEX & Ex-PA for 4313 */
1508 --- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
1509 +++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
1510 @@ -5077,7 +5077,7 @@ static int brcms_b_up_prep(struct brcms_
1511 * Configure pci/pcmcia here instead of in brcms_c_attach()
1512 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
1513 */
1514 - bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci, wlc_hw->d11core,
1515 + bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core,
1516 true);
1517
1518 /*
OpenWrt Source Repository