1 From 0f669e10ede7f06bb998373de6a9d169f47fcc66 Mon Sep 17 00:00:00 2001
2 From: Russell King <rmk+kernel@armlinux.org.uk>
3 Date: Tue, 5 Nov 2019 11:54:30 +0000
4 Subject: [PATCH 655/660] net: phy: add Broadcom BCM84881 PHY driver
6 Add a rudimentary Clause 45 driver for the BCM84881 PHY, found on
9 Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
11 drivers/net/phy/Kconfig | 5 +
12 drivers/net/phy/Makefile | 1 +
13 drivers/net/phy/bcm84881.c | 290 +++++++++++++++++++++++++++++++++++++
14 3 files changed, 296 insertions(+)
15 create mode 100644 drivers/net/phy/bcm84881.c
17 --- a/drivers/net/phy/Kconfig
18 +++ b/drivers/net/phy/Kconfig
19 @@ -280,6 +280,11 @@ config BROADCOM_PHY
20 Currently supports the BCM5411, BCM5421, BCM5461, BCM54616S, BCM5464,
21 BCM5481, BCM54810 and BCM5482 PHYs.
24 + tristate "Broadcom BCM84881 PHY"
26 + Support the Broadcom BCM84881 PHY.
29 tristate "Cicada PHYs"
31 --- a/drivers/net/phy/Makefile
32 +++ b/drivers/net/phy/Makefile
33 @@ -54,6 +54,7 @@ obj-$(CONFIG_BCM87XX_PHY) += bcm87xx.o
34 obj-$(CONFIG_BCM_CYGNUS_PHY) += bcm-cygnus.o
35 obj-$(CONFIG_BCM_NET_PHYLIB) += bcm-phy-lib.o
36 obj-$(CONFIG_BROADCOM_PHY) += broadcom.o
37 +obj-$(CONFIG_BCM84881_PHY) += bcm84881.o
38 obj-$(CONFIG_CICADA_PHY) += cicada.o
39 obj-$(CONFIG_CORTINA_PHY) += cortina.o
40 obj-$(CONFIG_DAVICOM_PHY) += davicom.o
42 +++ b/drivers/net/phy/bcm84881.c
44 +// SPDX-License-Identifier: GPL-2.0
45 +// Broadcom BCM84881 NBASE-T PHY driver, as found on a SFP+ module.
46 +// Copyright (C) 2019 Russell King, Deep Blue Solutions Ltd.
48 +// Like the Marvell 88x3310, the Broadcom 84881 changes its host-side
49 +// interface according to the operating speed between 10GBASE-R,
50 +// 2500BASE-X and SGMII (but unlike the 88x3310, without the control
53 +// This driver only supports those aspects of the PHY that I'm able to
54 +// observe and test with the SFP+ module, which is an incomplete subset
55 +// of what this PHY is able to support. For example, I only assume it
56 +// supports a single lane Serdes connection, but it may be that the PHY
57 +// is able to support more than that.
58 +#include <linux/delay.h>
59 +#include <linux/module.h>
60 +#include <linux/phy.h>
63 + MDIO_AN_C22 = 0xffe0,
66 +static int bcm84881_wait_init(struct phy_device *phydev)
68 + unsigned int tries = 20;
72 + val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
77 + if (!(val & MDIO_CTRL1_RESET)) {
89 + phydev_err(phydev, "%s failed: %d\n", __func__, ret);
94 +static int bcm84881_config_init(struct phy_device *phydev)
96 + switch (phydev->interface) {
97 + case PHY_INTERFACE_MODE_SGMII:
98 + case PHY_INTERFACE_MODE_2500BASEX:
99 + case PHY_INTERFACE_MODE_10GKR:
107 +static int bcm84881_probe(struct phy_device *phydev)
109 + /* This driver requires PMAPMD and AN blocks */
110 + const u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
112 + if (!phydev->is_c45 ||
113 + (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
119 +static int genphy_c45_an_config_aneg(struct phy_device *phydev)
121 + bool changed = false;
125 + phydev->advertising &= phydev->supported;
126 + advertising = phydev->advertising;
128 + ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
129 + ADVERTISE_ALL | ADVERTISE_100BASE4 |
130 + ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
131 + ethtool_adv_to_mii_adv_t(advertising));
137 + ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
138 + MDIO_AN_10GBT_CTRL_ADV10G,
139 + advertising & ADVERTISED_10000baseT_Full ?
140 + MDIO_AN_10GBT_CTRL_ADV10G : 0);
146 + return genphy_c45_check_and_restart_aneg(phydev, changed);
149 +static int bcm84881_config_aneg(struct phy_device *phydev)
151 + bool changed = false;
155 + /* Wait for the PHY to finish initialising, otherwise our
156 + * advertisement may be overwritten.
158 + ret = bcm84881_wait_init(phydev);
162 + /* We don't support manual MDI control */
163 + phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
165 + /* disabled autoneg doesn't seem to work with this PHY */
166 + if (phydev->autoneg == AUTONEG_DISABLE)
169 + ret = genphy_c45_an_config_aneg(phydev);
175 + adv = ethtool_adv_to_mii_ctrl1000_t(phydev->advertising);
176 + ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN,
177 + MDIO_AN_C22 + MII_CTRL1000,
178 + ADVERTISE_1000FULL | ADVERTISE_1000HALF,
185 + return genphy_c45_check_and_restart_aneg(phydev, changed);
188 +static int bcm84881_aneg_done(struct phy_device *phydev)
192 + val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
196 + bmsr = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_C22 + MII_BMSR);
200 + return !!(val & MDIO_AN_STAT1_COMPLETE) &&
201 + !!(bmsr & BMSR_ANEGCOMPLETE);
204 +static int bcm84881_read_status(struct phy_device *phydev)
206 + bool autoneg_complete;
210 + val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
214 + if (val & MDIO_AN_CTRL1_RESTART) {
219 + val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
223 + bmsr = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_C22 + MII_BMSR);
227 + autoneg_complete = !!(val & MDIO_AN_STAT1_COMPLETE) &&
228 + !!(bmsr & BMSR_ANEGCOMPLETE);
229 + phydev->link = !!(val & MDIO_STAT1_LSTATUS) &&
230 + !!(bmsr & BMSR_LSTATUS);
231 + if (phydev->autoneg == AUTONEG_ENABLE && !autoneg_complete)
232 + phydev->link = false;
237 + phydev->lp_advertising = 0;
238 + phydev->speed = SPEED_UNKNOWN;
239 + phydev->duplex = DUPLEX_UNKNOWN;
241 + phydev->asym_pause = 0;
244 + if (autoneg_complete) {
245 + val = genphy_c45_read_lpa(phydev);
249 + val = phy_read_mmd(phydev, MDIO_MMD_AN,
250 + MDIO_AN_C22 + MII_STAT1000);
254 + phydev->lp_advertising |= mii_stat1000_to_ethtool_lpa_t(val);
256 + if (phydev->autoneg == AUTONEG_ENABLE)
257 + phy_resolve_aneg_linkmode(phydev);
260 + if (phydev->autoneg == AUTONEG_DISABLE) {
261 + /* disabled autoneg doesn't seem to work, so force the link
268 + /* Set the host link mode - we set the phy interface mode and
269 + * the speed according to this register so that downshift works.
270 + * We leave the duplex setting as per the resolution from the
273 + val = phy_read_mmd(phydev, MDIO_MMD_VEND1, 0x4011);
274 + mode = (val & 0x1e) >> 1;
275 + if (mode == 1 || mode == 2)
276 + phydev->interface = PHY_INTERFACE_MODE_SGMII;
277 + else if (mode == 3)
278 + phydev->interface = PHY_INTERFACE_MODE_10GKR;
279 + else if (mode == 4)
280 + phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
281 + switch (mode & 7) {
283 + phydev->speed = SPEED_100;
286 + phydev->speed = SPEED_1000;
289 + phydev->speed = SPEED_10000;
292 + phydev->speed = SPEED_2500;
295 + phydev->speed = SPEED_5000;
299 + return genphy_c45_read_mdix(phydev);
302 +static struct phy_driver bcm84881_drivers[] = {
304 + .phy_id = 0xae025150,
305 + .phy_id_mask = 0xfffffff0,
306 + .name = "Broadcom BCM84881",
307 + .features = SUPPORTED_100baseT_Full |
308 + SUPPORTED_100baseT_Half |
309 + SUPPORTED_1000baseT_Full |
310 + SUPPORTED_Autoneg |
313 + SUPPORTED_10000baseT_Full |
314 + SUPPORTED_Backplane,
315 + .config_init = bcm84881_config_init,
316 + .probe = bcm84881_probe,
317 + .config_aneg = bcm84881_config_aneg,
318 + .aneg_done = bcm84881_aneg_done,
319 + .read_status = bcm84881_read_status,
323 +module_phy_driver(bcm84881_drivers);
325 +/* FIXME: module auto-loading for Clause 45 PHYs seems non-functional */
326 +static struct mdio_device_id __maybe_unused bcm84881_tbl[] = {
327 + { 0xae025150, 0xfffffff0 },
330 +MODULE_AUTHOR("Russell King");
331 +MODULE_DESCRIPTION("Broadcom BCM84881 PHY driver");
332 +MODULE_DEVICE_TABLE(mdio, bcm84881_tbl);
333 +MODULE_LICENSE("GPL");