1 From 9daea9b71d060d93d7394ac465b2e5ee0b7e7bca Mon Sep 17 00:00:00 2001
2 From: Alexander Couzens <lynxis@fe80.eu>
3 Date: Mon, 15 Aug 2022 16:02:01 +0200
4 Subject: [PATCH 06/10] net: mtk_sgmii: ensure the SGMII PHY is powered down on
7 The code expect the PHY to be in power down (which is only true after reset).
8 Allow the changes of SGMII parameters more than once.
10 drivers/net/ethernet/mediatek/mtk_sgmii.c | 16 +++++++++++++++-
11 1 file changed, 15 insertions(+), 1 deletion(-)
13 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
14 +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
19 +#include <linux/delay.h>
20 #include <linux/mfd/syscon.h>
22 #include <linux/phylink.h>
23 @@ -24,6 +25,9 @@ static int mtk_pcs_setup_mode_an(struct
27 + /* PHYA power down */
28 + regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
30 /* Setup the link timer and QPHY power up inside SGMIISYS */
31 regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER,
32 SGMII_LINK_TIMER_DEFAULT);
33 @@ -36,6 +40,10 @@ static int mtk_pcs_setup_mode_an(struct
34 val |= SGMII_AN_RESTART;
35 regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
37 + /* Release PHYA power down state
38 + * unknown how much the QPHY needs but it is racy without a sleep
40 + usleep_range(50, 100);
41 regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
44 @@ -50,6 +58,9 @@ static int mtk_pcs_setup_mode_force(stru
48 + /* PHYA power down */
49 + regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
51 regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val);
52 val &= ~RG_PHY_SPEED_MASK;
53 if (interface == PHY_INTERFACE_MODE_2500BASEX)
54 @@ -67,7 +78,10 @@ static int mtk_pcs_setup_mode_force(stru
55 val |= SGMII_SPEED_1000;
56 regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
58 - /* Release PHYA power down state */
59 + /* Release PHYA power down state
60 + * unknown how much the QPHY needs but it is racy without a sleep
62 + usleep_range(50, 100);
63 regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);