1 /*******************************************************************************
2 Copyright (C) Marvell International Ltd. and its affiliates
4 This software file (the "File") is owned and distributed by Marvell
5 International Ltd. and/or its affiliates ("Marvell") under the following
6 alternative licensing terms. Once you have made an election to distribute the
7 File under one of the following license alternatives, please (i) delete this
8 introductory statement regarding license alternatives, (ii) delete the two
9 license alternatives that you have not elected to use and (iii) preserve the
10 Marvell copyright notice above.
12 ********************************************************************************
13 Marvell Commercial License Option
15 If you received this File from Marvell and you have entered into a commercial
16 license agreement (a "Commercial License") with Marvell, the File is licensed
17 to you under the terms of the applicable Commercial License.
19 ********************************************************************************
20 Marvell GPL License Option
22 If you received this File from Marvell, you may opt to use, redistribute and/or
23 modify this File in accordance with the terms and conditions of the General
24 Public License Version 2, June 1991 (the "GPL License"), a copy of which is
25 available along with the File in the license.txt file or by writing to the Free
26 Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
27 on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
29 THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
30 WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
31 DISCLAIMED. The GPL License provides additional details about this warranty
33 ********************************************************************************
34 Marvell BSD License Option
36 If you received this File from Marvell, you may opt to use, redistribute and/or
37 modify this File under the following licensing terms.
38 Redistribution and use in source and binary forms, with or without modification,
39 are permitted provided that the following conditions are met:
41 * Redistributions of source code must retain the above copyright notice,
42 this list of conditions and the following disclaimer.
44 * Redistributions in binary form must reproduce the above copyright
45 notice, this list of conditions and the following disclaimer in the
46 documentation and/or other materials provided with the distribution.
48 * Neither the name of Marvell nor the names of its contributors may be
49 used to endorse or promote products derived from this software without
50 specific prior written permission.
52 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
53 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
54 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
55 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
56 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
57 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
58 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
59 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
60 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
61 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *******************************************************************************/
68 #include "mvCtrlEnvLib.h"
69 #include "ctrlEnv/sys/mvCpuIf.h"
71 #if defined(MV_INCLUDE_PEX)
72 #include "pex/mvPex.h"
73 #include "ctrlEnv/sys/mvSysPex.h"
76 #if defined(MV_INCLUDE_GIG_ETH)
77 #include "ctrlEnv/sys/mvSysGbe.h"
80 #if defined(MV_INCLUDE_XOR)
81 #include "ctrlEnv/sys/mvSysXor.h"
84 #if defined(MV_INCLUDE_SATA)
85 #include "ctrlEnv/sys/mvSysSata.h"
88 #if defined(MV_INCLUDE_USB)
89 #include "ctrlEnv/sys/mvSysUsb.h"
92 #if defined(MV_INCLUDE_AUDIO)
93 #include "ctrlEnv/sys/mvSysAudio.h"
96 #if defined(MV_INCLUDE_CESA)
97 #include "ctrlEnv/sys/mvSysCesa.h"
100 #if defined(MV_INCLUDE_TS)
101 #include "ctrlEnv/sys/mvSysTs.h"
111 /*******************************************************************************
112 * mvCtrlEnvInit - Initialize Marvell controller environment.
115 * This function get environment information and initialize controller
116 * internal/external environment. For example
117 * 1) MPP settings according to board MPP macros.
118 * NOTE: It is the user responsibility to shut down all DMA channels
119 * in device and disable controller sub units interrupts during
131 *******************************************************************************/
132 MV_STATUS
mvCtrlEnvInit(MV_VOID
)
138 MV_U32 maxMppGrp
= 1;
141 MV_U32 mppGroupType
= 0;
142 MV_U32 mppGroup1
[][3] = MPP_GROUP_1_TYPE
;
143 MV_U32 mppGroup2
[][3] = MPP_GROUP_2_TYPE
;
145 devId
= mvCtrlModelGet();
146 boardId
= mvBoardIdGet();
150 maxMppGrp
= MV_6281_MPP_MAX_GROUP
;
153 maxMppGrp
= MV_6192_MPP_MAX_GROUP
;
156 maxMppGrp
= MV_6190_MPP_MAX_GROUP
;
159 maxMppGrp
= MV_6180_MPP_MAX_GROUP
;
164 /* We split mpp init to 3 phases:
165 * 1. We init mpp[19:0] from the board info. mpp[23:20] will be over write
167 * 2. We detect the mpp group type and according the mpp values [35:20].
168 * 3. We detect the mpp group type and according the mpp values [49:36].
170 /* Mpp phase 1 mpp[19:0] */
171 /* Read MPP group from board level and assign to MPP register */
172 for (mppGroup
= 0; mppGroup
< 3; mppGroup
++)
174 mppVal
= mvBoardMppGet(mppGroup
);
177 bootVal
= MV_REG_READ(mvCtrlMppRegGet(mppGroup
));
178 if (mvCtrlIsBootFromSPI())
184 else if (mvCtrlIsBootFromSPIUseNAND())
186 mppVal
&= ~0xf0000000;
187 bootVal
&= 0xf0000000;
190 else if (mvCtrlIsBootFromNAND())
200 bootVal
= MV_REG_READ(mvCtrlMppRegGet(mppGroup
));
201 if (mvCtrlIsBootFromNAND())
209 MV_REG_WRITE(mvCtrlMppRegGet(mppGroup
), mppVal
);
212 /* Identify MPPs group */
213 mvBoardMppGroupIdUpdate();
215 /* Update MPPs mux relevent only on Marvell DB */
216 if ((boardId
== DB_88F6281A_BP_ID
) ||
217 (boardId
== DB_88F6180A_BP_ID
))
220 mppGroupType
= mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_1
);
223 /* Read MPP group from board level and assign to MPP register */
224 if (devId
!= MV_6180_DEV_ID
)
227 for (mppGroup
= 2; mppGroup
< 5; mppGroup
++)
229 if ((mppGroupType
== MV_BOARD_OTHER
) ||
230 (boardId
== RD_88F6281A_ID
) ||
231 (boardId
== RD_88F6192A_ID
) ||
232 (boardId
== RD_88F6190A_ID
) ||
233 (boardId
== RD_88F6281A_PCAC_ID
) ||
234 (boardId
== SHEEVA_PLUG_ID
))
235 mppVal
= mvBoardMppGet(mppGroup
);
238 mppVal
= mppGroup1
[mppGroupType
][i
];
242 /* Group 2 is shared mpp[23:16] */
245 bootVal
= MV_REG_READ(mvCtrlMppRegGet(mppGroup
));
251 MV_REG_WRITE(mvCtrlMppRegGet(mppGroup
), mppVal
);
255 if ((devId
== MV_6192_DEV_ID
) || (devId
== MV_6190_DEV_ID
))
259 mppGroupType
= mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_2
);
260 /* Read MPP group from board level and assign to MPP register */
262 for (mppGroup
= 4; mppGroup
< 7; mppGroup
++)
264 if ((mppGroupType
== MV_BOARD_OTHER
) ||
265 (boardId
== RD_88F6281A_ID
) ||
266 (boardId
== RD_88F6281A_PCAC_ID
) ||
267 (boardId
== SHEEVA_PLUG_ID
))
268 mppVal
= mvBoardMppGet(mppGroup
);
271 mppVal
= mppGroup2
[mppGroupType
][i
];
275 /* Group 4 is shared mpp[35:32] */
278 bootVal
= MV_REG_READ(mvCtrlMppRegGet(mppGroup
));
284 MV_REG_WRITE(mvCtrlMppRegGet(mppGroup
), mppVal
);
286 /* Update SSCG configuration register*/
287 if(mvBoardIdGet() == DB_88F6281A_BP_ID
|| mvBoardIdGet() == DB_88F6192A_BP_ID
||
288 mvBoardIdGet() == DB_88F6190A_BP_ID
|| mvBoardIdGet() == DB_88F6180A_BP_ID
)
289 MV_REG_WRITE(0x100d8, 0x53);
294 /*******************************************************************************
295 * mvCtrlMppRegGet - return reg address of mpp group
300 * mppGroup - MPP group.
306 * MV_U32 - Register address.
308 *******************************************************************************/
309 MV_U32
mvCtrlMppRegGet(MV_U32 mppGroup
)
314 case (0): ret
= MPP_CONTROL_REG0
;
316 case (1): ret
= MPP_CONTROL_REG1
;
318 case (2): ret
= MPP_CONTROL_REG2
;
320 case (3): ret
= MPP_CONTROL_REG3
;
322 case (4): ret
= MPP_CONTROL_REG4
;
324 case (5): ret
= MPP_CONTROL_REG5
;
326 case (6): ret
= MPP_CONTROL_REG6
;
328 default: ret
= MPP_CONTROL_REG0
;
333 #if defined(MV_INCLUDE_PEX)
334 /*******************************************************************************
335 * mvCtrlPexMaxIfGet - Get Marvell controller number of PEX interfaces.
338 * This function returns Marvell controller number of PEX interfaces.
347 * Marvell controller number of PEX interfaces. If controller
348 * ID is undefined the function returns '0'.
350 *******************************************************************************/
351 MV_U32
mvCtrlPexMaxIfGet(MV_VOID
)
354 return MV_PEX_MAX_IF
;
358 #if defined(MV_INCLUDE_GIG_ETH)
359 /*******************************************************************************
360 * mvCtrlEthMaxPortGet - Get Marvell controller number of etherent ports.
363 * This function returns Marvell controller number of etherent port.
372 * Marvell controller number of etherent port.
374 *******************************************************************************/
375 MV_U32
mvCtrlEthMaxPortGet(MV_VOID
)
379 devId
= mvCtrlModelGet();
383 return MV_6281_ETH_MAX_PORTS
;
386 return MV_6192_ETH_MAX_PORTS
;
389 return MV_6190_ETH_MAX_PORTS
;
392 return MV_6180_ETH_MAX_PORTS
;
400 #if defined(MV_INCLUDE_XOR)
401 /*******************************************************************************
402 * mvCtrlXorMaxChanGet - Get Marvell controller number of XOR channels.
405 * This function returns Marvell controller number of XOR channels.
414 * Marvell controller number of XOR channels.
416 *******************************************************************************/
417 MV_U32
mvCtrlXorMaxChanGet(MV_VOID
)
419 return MV_XOR_MAX_CHAN
;
423 #if defined(MV_INCLUDE_USB)
424 /*******************************************************************************
425 * mvCtrlUsbHostMaxGet - Get number of Marvell Usb controllers
436 * returns number of Marvell USB controllers.
438 *******************************************************************************/
439 MV_U32
mvCtrlUsbMaxGet(void)
441 return MV_USB_MAX_PORTS
;
446 #if defined(MV_INCLUDE_NAND)
447 /*******************************************************************************
448 * mvCtrlNandSupport - Return if this controller has integrated NAND flash support
459 * MV_TRUE if NAND is supported and MV_FALSE otherwise
461 *******************************************************************************/
462 MV_U32
mvCtrlNandSupport(MV_VOID
)
466 devId
= mvCtrlModelGet();
487 #if defined(MV_INCLUDE_SDIO)
488 /*******************************************************************************
489 * mvCtrlSdioSupport - Return if this controller has integrated SDIO flash support
500 * MV_TRUE if SDIO is supported and MV_FALSE otherwise
502 *******************************************************************************/
503 MV_U32
mvCtrlSdioSupport(MV_VOID
)
507 devId
= mvCtrlModelGet();
528 #if defined(MV_INCLUDE_TS)
529 /*******************************************************************************
530 * mvCtrlTsSupport - Return if this controller has integrated TS flash support
541 * MV_TRUE if TS is supported and MV_FALSE otherwise
543 *******************************************************************************/
544 MV_U32
mvCtrlTsSupport(MV_VOID
)
548 devId
= mvCtrlModelGet();
568 #if defined(MV_INCLUDE_AUDIO)
569 /*******************************************************************************
570 * mvCtrlAudioSupport - Return if this controller has integrated AUDIO flash support
581 * MV_TRUE if AUDIO is supported and MV_FALSE otherwise
583 *******************************************************************************/
584 MV_U32
mvCtrlAudioSupport(MV_VOID
)
588 devId
= mvCtrlModelGet();
592 return MV_6281_AUDIO
;
595 return MV_6192_AUDIO
;
598 return MV_6190_AUDIO
;
601 return MV_6180_AUDIO
;
609 #if defined(MV_INCLUDE_TDM)
610 /*******************************************************************************
611 * mvCtrlTdmSupport - Return if this controller has integrated TDM flash support
622 * MV_TRUE if TDM is supported and MV_FALSE otherwise
624 *******************************************************************************/
625 MV_U32
mvCtrlTdmSupport(MV_VOID
)
629 devId
= mvCtrlModelGet();
650 /*******************************************************************************
651 * mvCtrlModelGet - Get Marvell controller device model (Id)
654 * This function returns 16bit describing the device model (ID) as defined
655 * in PCI Device and Vendor ID configuration register offset 0x0.
664 * 16bit desscribing Marvell controller ID
666 *******************************************************************************/
667 MV_U16
mvCtrlModelGet(MV_VOID
)
671 devId
= MV_REG_READ(CHIP_BOND_REG
);
672 devId
&= PCKG_OPT_MASK
;
676 return MV_6281_DEV_ID
;
679 if (((MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID
))& 0xffff0000) >> 16)
681 return MV_6190_DEV_ID
;
683 return MV_6192_DEV_ID
;
686 return MV_6180_DEV_ID
;
692 /*******************************************************************************
693 * mvCtrlRevGet - Get Marvell controller device revision number
696 * This function returns 8bit describing the device revision as defined
697 * in PCI Express Class Code and Revision ID Register.
706 * 8bit desscribing Marvell controller revision number
708 *******************************************************************************/
709 MV_U8
mvCtrlRevGet(MV_VOID
)
712 #if defined(MV_INCLUDE_CLK_PWR_CNTRL)
713 /* Check pex power state */
715 pexPower
= mvCtrlPwrClckGet(PEX_UNIT_ID
,0);
716 if (pexPower
== MV_FALSE
)
717 mvCtrlPwrClckSet(PEX_UNIT_ID
, 0, MV_TRUE
);
719 revNum
= (MV_U8
)MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PCI_CLASS_CODE_AND_REVISION_ID
));
720 #if defined(MV_INCLUDE_CLK_PWR_CNTRL)
721 /* Return to power off state */
722 if (pexPower
== MV_FALSE
)
723 mvCtrlPwrClckSet(PEX_UNIT_ID
, 0, MV_FALSE
);
725 return ((revNum
& PCCRIR_REVID_MASK
) >> PCCRIR_REVID_OFFS
);
728 /*******************************************************************************
729 * mvCtrlNameGet - Get Marvell controller name
732 * This function returns a string describing the device model and revision.
738 * pNameBuff - Buffer to contain device name string. Minimum size 30 chars.
742 * MV_ERROR if informantion can not be read.
743 *******************************************************************************/
744 MV_STATUS
mvCtrlNameGet(char *pNameBuff
)
746 mvOsSPrintf (pNameBuff
, "%s%x Rev %d", SOC_NAME_PREFIX
,
747 mvCtrlModelGet(), mvCtrlRevGet());
752 /*******************************************************************************
753 * mvCtrlModelRevGet - Get Controller Model (Device ID) and Revision
756 * This function returns 32bit value describing both Device ID and Revision
757 * as defined in PCI Express Device and Vendor ID Register and device revision
758 * as defined in PCI Express Class Code and Revision ID Register.
768 * 32bit describing both controller device ID and revision number
770 *******************************************************************************/
771 MV_U32
mvCtrlModelRevGet(MV_VOID
)
773 return ((mvCtrlModelGet() << 16) | mvCtrlRevGet());
776 /*******************************************************************************
777 * mvCtrlModelRevNameGet - Get Marvell controller name
780 * This function returns a string describing the device model and revision.
786 * pNameBuff - Buffer to contain device name string. Minimum size 30 chars.
790 * MV_ERROR if informantion can not be read.
791 *******************************************************************************/
793 MV_STATUS
mvCtrlModelRevNameGet(char *pNameBuff
)
796 switch (mvCtrlModelRevGet())
799 mvOsSPrintf (pNameBuff
, "%s",MV_6281_A0_NAME
);
802 mvOsSPrintf (pNameBuff
, "%s",MV_6192_A0_NAME
);
805 mvOsSPrintf (pNameBuff
, "%s",MV_6180_A0_NAME
);
808 mvOsSPrintf (pNameBuff
, "%s",MV_6190_A0_NAME
);
811 mvOsSPrintf (pNameBuff
, "%s",MV_6281_A1_NAME
);
814 mvOsSPrintf (pNameBuff
, "%s",MV_6192_A1_NAME
);
817 mvOsSPrintf (pNameBuff
, "%s",MV_6180_A1_NAME
);
820 mvOsSPrintf (pNameBuff
, "%s",MV_6190_A1_NAME
);
823 mvCtrlNameGet(pNameBuff
);
831 /*******************************************************************************
832 * ctrlWinOverlapTest - Test address windows for overlaping.
835 * This function checks the given two address windows for overlaping.
838 * pAddrWin1 - Address window 1.
839 * pAddrWin2 - Address window 2.
846 * MV_TRUE if address window overlaps, MV_FALSE otherwise.
847 *******************************************************************************/
848 MV_STATUS
ctrlWinOverlapTest(MV_ADDR_WIN
*pAddrWin1
, MV_ADDR_WIN
*pAddrWin2
)
850 MV_U32 winBase1
, winBase2
;
851 MV_U32 winTop1
, winTop2
;
853 /* check if we have overflow than 4G*/
854 if (((0xffffffff - pAddrWin1
->baseLow
) < pAddrWin1
->size
-1)||
855 ((0xffffffff - pAddrWin2
->baseLow
) < pAddrWin2
->size
-1))
860 winBase1
= pAddrWin1
->baseLow
;
861 winBase2
= pAddrWin2
->baseLow
;
862 winTop1
= winBase1
+ pAddrWin1
->size
-1;
863 winTop2
= winBase2
+ pAddrWin2
->size
-1;
866 if (((winBase1
<= winTop2
) && ( winTop2
<= winTop1
)) ||
867 ((winBase1
<= winBase2
) && (winBase2
<= winTop1
)))
877 /*******************************************************************************
878 * ctrlWinWithinWinTest - Test address windows for overlaping.
881 * This function checks the given win1 boundries is within
885 * pAddrWin1 - Address window 1.
886 * pAddrWin2 - Address window 2.
893 * MV_TRUE if found win1 inside win2, MV_FALSE otherwise.
894 *******************************************************************************/
895 MV_STATUS
ctrlWinWithinWinTest(MV_ADDR_WIN
*pAddrWin1
, MV_ADDR_WIN
*pAddrWin2
)
897 MV_U32 winBase1
, winBase2
;
898 MV_U32 winTop1
, winTop2
;
900 winBase1
= pAddrWin1
->baseLow
;
901 winBase2
= pAddrWin2
->baseLow
;
902 winTop1
= winBase1
+ pAddrWin1
->size
-1;
903 winTop2
= winBase2
+ pAddrWin2
->size
-1;
905 if (((winBase1
>= winBase2
) && ( winBase1
<= winTop2
)) ||
906 ((winTop1
>= winBase2
) && (winTop1
<= winTop2
)))
916 static const char* cntrlName
[] = TARGETS_NAME_ARRAY
;
918 /*******************************************************************************
919 * mvCtrlTargetNameGet - Get Marvell controller target name
922 * This function convert the trget enumeration to string.
931 * Target name (const MV_8 *)
932 *******************************************************************************/
933 const MV_8
* mvCtrlTargetNameGet( MV_TARGET target
)
936 if (target
>= MAX_TARGETS
)
938 return "target unknown";
941 return cntrlName
[target
];
944 /*******************************************************************************
945 * mvCtrlAddrDecShow - Print the Controller units address decode map.
948 * This function the Controller units address decode map.
959 *******************************************************************************/
960 MV_VOID
mvCtrlAddrDecShow(MV_VOID
)
963 mvAhbToMbusAddDecShow();
964 #if defined(MV_INCLUDE_PEX)
967 #if defined(MV_INCLUDE_USB)
970 #if defined(MV_INCLUDE_GIG_ETH)
973 #if defined(MV_INCLUDE_XOR)
976 #if defined(MV_INCLUDE_SATA)
979 #if defined(MV_INCLUDE_AUDIO)
980 mvAudioAddrDecShow();
982 #if defined(MV_INCLUDE_TS)
987 /*******************************************************************************
988 * ctrlSizeToReg - Extract size value for register assignment.
991 * Address decode size parameter must be programed from LSB to MSB as
992 * sequence of 1's followed by sequence of 0's. The number of 1's
993 * specifies the size of the window in 64 KB granularity (e.g. a
994 * value of 0x00ff specifies 256x64k = 16 MB).
995 * This function extract the size value from the size parameter according
996 * to given aligment paramter. For example for size 0x1000000 (16MB) and
997 * aligment 0x10000 (64KB) the function will return 0x00FF.
1001 * alignment - Size alignment. Note that alignment must be power of 2!
1007 * 32bit describing size register value correspond to size parameter.
1008 * If value is '-1' size parameter or aligment are invalid.
1009 *******************************************************************************/
1010 MV_U32
ctrlSizeToReg(MV_U32 size
, MV_U32 alignment
)
1014 /* Check size parameter alignment */
1015 if ((0 == size
) || (MV_IS_NOT_ALIGN(size
, alignment
)))
1017 DB(mvOsPrintf("ctrlSizeToReg: ERR. Size is zero or not aligned.\n"));
1021 /* Take out the "alignment" portion out of the size parameter */
1022 alignment
--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */
1023 /* and size is 0x1000000 (16MB) for example */
1024 while(alignment
& 1) /* Check that alignmet LSB is set */
1026 size
= (size
>> 1); /* If LSB is set, move 'size' one bit to right */
1027 alignment
= (alignment
>> 1);
1030 /* If after the alignment first '0' was met we still have '1' in */
1031 /* it then aligment is invalid (not power of 2) */
1034 DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n",
1035 (MV_U32
)alignment
));
1039 /* Now the size is shifted right according to aligment: 0x0100 */
1040 size
--; /* Now the size is a sequance of '1': 0x00ff */
1044 /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */
1045 while(size
& 1) /* Check that LSB is set */
1047 size
= (size
>> 1); /* If LSB is set, move one bit to the right */
1050 if (size
) /* Sequance of 1's is over. Check that we have no other 1's */
1052 DB(mvOsPrintf("ctrlSizeToReg: ERR. Size parameter 0x%x invalid.\n",
1061 /*******************************************************************************
1062 * ctrlRegToSize - Extract size value from register value.
1065 * This function extract a size value from the register size parameter
1066 * according to given aligment paramter. For example for register size
1067 * value 0xff and aligment 0x10000 the function will return 0x01000000.
1070 * regSize - Size as in register format. See ctrlSizeToReg.
1071 * alignment - Size alignment. Note that alignment must be power of 2!
1077 * 32bit describing size.
1078 * If value is '-1' size parameter or aligment are invalid.
1079 *******************************************************************************/
1080 MV_U32
ctrlRegToSize(MV_U32 regSize
, MV_U32 alignment
)
1084 /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */
1085 temp
= regSize
; /* Now the size is a sequance of '1': 0x00ff */
1087 while(temp
& 1) /* Check that LSB is set */
1089 temp
= (temp
>> 1); /* If LSB is set, move one bit to the right */
1092 if (temp
) /* Sequance of 1's is over. Check that we have no other 1's */
1094 DB(mvOsPrintf("ctrlRegToSize: ERR. Size parameter 0x%x invalid.\n",
1100 /* Check that aligment is a power of two */
1101 temp
= alignment
- 1;/* Now the alignmet is a sequance of '1' (0xffff) */
1103 while(temp
& 1) /* Check that alignmet LSB is set */
1105 temp
= (temp
>> 1); /* If LSB is set, move 'size' one bit to right */
1108 /* If after the 'temp' first '0' was met we still have '1' in 'temp' */
1109 /* then 'temp' is invalid (not power of 2) */
1112 DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n",
1117 regSize
++; /* Now the size is 0x0100 */
1119 /* Add in the "alignment" portion to the register size parameter */
1120 alignment
--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */
1122 while(alignment
& 1) /* Check that alignmet LSB is set */
1124 regSize
= (regSize
<< 1); /* LSB is set, move 'size' one bit left */
1125 alignment
= (alignment
>> 1);
1132 /*******************************************************************************
1133 * ctrlSizeRegRoundUp - Round up given size
1136 * This function round up a given size to a size that fits the
1137 * restrictions of size format given an aligment parameter.
1138 * to given aligment paramter. For example for size parameter 0xa1000 and
1139 * aligment 0x1000 the function will return 0xFF000.
1143 * alignment - Size alignment. Note that alignment must be power of 2!
1149 * 32bit describing size value correspond to size in register.
1150 *******************************************************************************/
1151 MV_U32
ctrlSizeRegRoundUp(MV_U32 size
, MV_U32 alignment
)
1156 /* Check if size parameter is already comply with restriction */
1157 if (!(-1 == ctrlSizeToReg(size
, alignment
)))
1168 retSize
= (1 << msbBit
);
1170 if (retSize
< alignment
)
1179 /*******************************************************************************
1180 * mvCtrlSysRstLengthCounterGet - Return number of milliseconds the reset button
1181 * was pressed and clear counter
1189 * RETURN: number of milliseconds the reset button was pressed
1190 *******************************************************************************/
1191 MV_U32
mvCtrlSysRstLengthCounterGet(MV_VOID
)
1193 static volatile MV_U32 Count
= 0;
1196 Count
= (MV_REG_READ(SYSRST_LENGTH_COUNTER_REG
) & SLCR_COUNT_MASK
);
1197 Count
= (Count
/ (MV_BOARD_REFCLK_25MHZ
/ 1000));
1198 /* clear counter for next boot */
1199 MV_REG_BIT_SET(SYSRST_LENGTH_COUNTER_REG
, SLCR_CLR_MASK
);
1202 DB(mvOsPrintf("mvCtrlSysRstLengthCounterGet: Reset button was pressed for %u milliseconds\n", Count
));
1207 MV_BOOL
mvCtrlIsBootFromSPI(MV_VOID
)
1210 satr
= MV_REG_READ(MPP_SAMPLE_AT_RESET
);
1211 if(mvCtrlModelGet() == MV_6180_DEV_ID
)
1213 if (MSAR_BOOT_MODE_6180(satr
) == MSAR_BOOT_SPI_WITH_BOOTROM_6180
)
1218 satr
= satr
& MSAR_BOOT_MODE_MASK
;
1219 if (satr
== MSAR_BOOT_SPI_WITH_BOOTROM
)
1225 MV_BOOL
mvCtrlIsBootFromSPIUseNAND(MV_VOID
)
1228 if(mvCtrlModelGet() == MV_6180_DEV_ID
)
1230 satr
= MV_REG_READ(MPP_SAMPLE_AT_RESET
);
1231 satr
= satr
& MSAR_BOOT_MODE_MASK
;
1233 if (satr
== MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM
)
1239 MV_BOOL
mvCtrlIsBootFromNAND(MV_VOID
)
1242 satr
= MV_REG_READ(MPP_SAMPLE_AT_RESET
);
1243 if(mvCtrlModelGet() == MV_6180_DEV_ID
)
1245 if (MSAR_BOOT_MODE_6180(satr
) == MSAR_BOOT_NAND_WITH_BOOTROM_6180
)
1250 satr
= satr
& MSAR_BOOT_MODE_MASK
;
1251 if ((satr
== MSAR_BOOT_NAND_WITH_BOOTROM
))
1257 #if defined(MV_INCLUDE_CLK_PWR_CNTRL)
1258 /*******************************************************************************
1259 * mvCtrlPwrSaveOn - Set Power save mode
1268 *******************************************************************************/
1269 MV_VOID
mvCtrlPwrSaveOn(MV_VOID
)
1271 unsigned long old
,temp
;
1273 __asm__
__volatile__("mrs %0, cpsr\n"
1274 "orr %1, %0, #0xc0\n"
1276 : "=r" (old
), "=r" (temp
)
1280 /* Set SoC in power save */
1281 MV_REG_BIT_SET(POWER_MNG_CTRL_REG
, BIT11
);
1283 __asm__
__volatile__("mcr p15, 0, r0, c7, c0, 4");
1286 __asm__
__volatile__("msr cpsr_c, %0"
1294 /*******************************************************************************
1295 * mvCtrlPwrSaveOff - Go out of power save mode
1304 *******************************************************************************/
1305 MV_VOID
mvCtrlPwrSaveOff(MV_VOID
)
1307 unsigned long old
,temp
;
1309 __asm__
__volatile__("mrs %0, cpsr\n"
1310 "orr %1, %0, #0xc0\n"
1312 : "=r" (old
), "=r" (temp
)
1316 /* Set SoC in power save */
1317 MV_REG_BIT_RESET(POWER_MNG_CTRL_REG
, BIT11
);
1319 __asm__
__volatile__("mcr p15, 0, r0, c7, c0, 4");
1322 __asm__
__volatile__("msr cpsr_c, %0"
1328 /*******************************************************************************
1329 * mvCtrlPwrClckSet - Set Power State for specific Unit
1338 *******************************************************************************/
1339 MV_VOID
mvCtrlPwrClckSet(MV_UNIT_ID unitId
, MV_U32 index
, MV_BOOL enable
)
1343 #if defined(MV_INCLUDE_PEX)
1345 if (enable
== MV_FALSE
)
1347 MV_REG_BIT_RESET(POWER_MNG_CTRL_REG
, PMC_PEXSTOPCLOCK_MASK
);
1351 MV_REG_BIT_SET(POWER_MNG_CTRL_REG
, PMC_PEXSTOPCLOCK_MASK
);
1355 #if defined(MV_INCLUDE_GIG_ETH)
1356 case ETH_GIG_UNIT_ID
:
1357 if (enable
== MV_FALSE
)
1359 MV_REG_BIT_RESET(POWER_MNG_CTRL_REG
, PMC_GESTOPCLOCK_MASK(index
));
1363 MV_REG_BIT_SET(POWER_MNG_CTRL_REG
, PMC_GESTOPCLOCK_MASK(index
));
1367 #if defined(MV_INCLUDE_INTEG_SATA)
1369 if (enable
== MV_FALSE
)
1371 MV_REG_BIT_RESET(POWER_MNG_CTRL_REG
, PMC_SATASTOPCLOCK_MASK(index
));
1375 MV_REG_BIT_SET(POWER_MNG_CTRL_REG
, PMC_SATASTOPCLOCK_MASK(index
));
1379 #if defined(MV_INCLUDE_CESA)
1381 if (enable
== MV_FALSE
)
1383 MV_REG_BIT_RESET(POWER_MNG_CTRL_REG
, PMC_SESTOPCLOCK_MASK
);
1387 MV_REG_BIT_SET(POWER_MNG_CTRL_REG
, PMC_SESTOPCLOCK_MASK
);
1391 #if defined(MV_INCLUDE_USB)
1393 if (enable
== MV_FALSE
)
1395 MV_REG_BIT_RESET(POWER_MNG_CTRL_REG
, PMC_USBSTOPCLOCK_MASK
);
1399 MV_REG_BIT_SET(POWER_MNG_CTRL_REG
, PMC_USBSTOPCLOCK_MASK
);
1403 #if defined(MV_INCLUDE_AUDIO)
1405 if (enable
== MV_FALSE
)
1407 MV_REG_BIT_RESET(POWER_MNG_CTRL_REG
, PMC_AUDIOSTOPCLOCK_MASK
);
1411 MV_REG_BIT_SET(POWER_MNG_CTRL_REG
, PMC_AUDIOSTOPCLOCK_MASK
);
1415 #if defined(MV_INCLUDE_TS)
1417 if (enable
== MV_FALSE
)
1419 MV_REG_BIT_RESET(POWER_MNG_CTRL_REG
, PMC_TSSTOPCLOCK_MASK
);
1423 MV_REG_BIT_SET(POWER_MNG_CTRL_REG
, PMC_TSSTOPCLOCK_MASK
);
1427 #if defined(MV_INCLUDE_SDIO)
1429 if (enable
== MV_FALSE
)
1431 MV_REG_BIT_RESET(POWER_MNG_CTRL_REG
, PMC_SDIOSTOPCLOCK_MASK
);
1435 MV_REG_BIT_SET(POWER_MNG_CTRL_REG
, PMC_SDIOSTOPCLOCK_MASK
);
1439 #if defined(MV_INCLUDE_TDM)
1441 if (enable
== MV_FALSE
)
1443 MV_REG_BIT_RESET(POWER_MNG_CTRL_REG
, PMC_TDMSTOPCLOCK_MASK
);
1447 MV_REG_BIT_SET(POWER_MNG_CTRL_REG
, PMC_TDMSTOPCLOCK_MASK
);
1459 /*******************************************************************************
1460 * mvCtrlPwrClckGet - Get Power State of specific Unit
1469 ******************************************************************************/
1470 MV_BOOL
mvCtrlPwrClckGet(MV_UNIT_ID unitId
, MV_U32 index
)
1472 MV_U32 reg
= MV_REG_READ(POWER_MNG_CTRL_REG
);
1473 MV_BOOL state
= MV_TRUE
;
1477 #if defined(MV_INCLUDE_PEX)
1479 if ((reg
& PMC_PEXSTOPCLOCK_MASK
) == PMC_PEXSTOPCLOCK_STOP
)
1483 else state
= MV_TRUE
;
1487 #if defined(MV_INCLUDE_GIG_ETH)
1488 case ETH_GIG_UNIT_ID
:
1489 if ((reg
& PMC_GESTOPCLOCK_MASK(index
)) == PMC_GESTOPCLOCK_STOP(index
))
1493 else state
= MV_TRUE
;
1496 #if defined(MV_INCLUDE_SATA)
1498 if ((reg
& PMC_SATASTOPCLOCK_MASK(index
)) == PMC_SATASTOPCLOCK_STOP(index
))
1502 else state
= MV_TRUE
;
1505 #if defined(MV_INCLUDE_CESA)
1507 if ((reg
& PMC_SESTOPCLOCK_MASK
) == PMC_SESTOPCLOCK_STOP
)
1511 else state
= MV_TRUE
;
1514 #if defined(MV_INCLUDE_USB)
1516 if ((reg
& PMC_USBSTOPCLOCK_MASK
) == PMC_USBSTOPCLOCK_STOP
)
1520 else state
= MV_TRUE
;
1523 #if defined(MV_INCLUDE_AUDIO)
1525 if ((reg
& PMC_AUDIOSTOPCLOCK_MASK
) == PMC_AUDIOSTOPCLOCK_STOP
)
1529 else state
= MV_TRUE
;
1532 #if defined(MV_INCLUDE_TS)
1534 if ((reg
& PMC_TSSTOPCLOCK_MASK
) == PMC_TSSTOPCLOCK_STOP
)
1538 else state
= MV_TRUE
;
1541 #if defined(MV_INCLUDE_SDIO)
1543 if ((reg
& PMC_SDIOSTOPCLOCK_MASK
)== PMC_SDIOSTOPCLOCK_STOP
)
1547 else state
= MV_TRUE
;
1550 #if defined(MV_INCLUDE_TDM)
1552 if ((reg
& PMC_TDMSTOPCLOCK_MASK
) == PMC_TDMSTOPCLOCK_STOP
)
1556 else state
= MV_TRUE
;
1568 /*******************************************************************************
1569 * mvCtrlPwrMemSet - Set Power State for memory on specific Unit
1578 *******************************************************************************/
1579 MV_VOID
mvCtrlPwrMemSet(MV_UNIT_ID unitId
, MV_U32 index
, MV_BOOL enable
)
1583 #if defined(MV_INCLUDE_PEX)
1585 if (enable
== MV_FALSE
)
1587 MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG
, PMC_PEXSTOPMEM_MASK
);
1591 MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG
, PMC_PEXSTOPMEM_MASK
);
1595 #if defined(MV_INCLUDE_GIG_ETH)
1596 case ETH_GIG_UNIT_ID
:
1597 if (enable
== MV_FALSE
)
1599 MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG
, PMC_GESTOPMEM_MASK(index
));
1603 MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG
, PMC_GESTOPMEM_MASK(index
));
1607 #if defined(MV_INCLUDE_INTEG_SATA)
1609 if (enable
== MV_FALSE
)
1611 MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG
, PMC_SATASTOPMEM_MASK(index
));
1615 MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG
, PMC_SATASTOPMEM_MASK(index
));
1619 #if defined(MV_INCLUDE_CESA)
1621 if (enable
== MV_FALSE
)
1623 MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG
, PMC_SESTOPMEM_MASK
);
1627 MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG
, PMC_SESTOPMEM_MASK
);
1631 #if defined(MV_INCLUDE_USB)
1633 if (enable
== MV_FALSE
)
1635 MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG
, PMC_USBSTOPMEM_MASK
);
1639 MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG
, PMC_USBSTOPMEM_MASK
);
1643 #if defined(MV_INCLUDE_AUDIO)
1645 if (enable
== MV_FALSE
)
1647 MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG
, PMC_AUDIOSTOPMEM_MASK
);
1651 MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG
, PMC_AUDIOSTOPMEM_MASK
);
1655 #if defined(MV_INCLUDE_XOR)
1657 if (enable
== MV_FALSE
)
1659 MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG
, PMC_XORSTOPMEM_MASK(index
));
1663 MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG
, PMC_XORSTOPMEM_MASK(index
));
1674 /*******************************************************************************
1675 * mvCtrlPwrMemGet - Get Power State of memory on specific Unit
1684 ******************************************************************************/
1685 MV_BOOL
mvCtrlPwrMemGet(MV_UNIT_ID unitId
, MV_U32 index
)
1687 MV_U32 reg
= MV_REG_READ(POWER_MNG_MEM_CTRL_REG
);
1688 MV_BOOL state
= MV_TRUE
;
1692 #if defined(MV_INCLUDE_PEX)
1694 if ((reg
& PMC_PEXSTOPMEM_MASK
) == PMC_PEXSTOPMEM_STOP
)
1698 else state
= MV_TRUE
;
1702 #if defined(MV_INCLUDE_GIG_ETH)
1703 case ETH_GIG_UNIT_ID
:
1704 if ((reg
& PMC_GESTOPMEM_MASK(index
)) == PMC_GESTOPMEM_STOP(index
))
1708 else state
= MV_TRUE
;
1711 #if defined(MV_INCLUDE_SATA)
1713 if ((reg
& PMC_SATASTOPMEM_MASK(index
)) == PMC_SATASTOPMEM_STOP(index
))
1717 else state
= MV_TRUE
;
1720 #if defined(MV_INCLUDE_CESA)
1722 if ((reg
& PMC_SESTOPMEM_MASK
) == PMC_SESTOPMEM_STOP
)
1726 else state
= MV_TRUE
;
1729 #if defined(MV_INCLUDE_USB)
1731 if ((reg
& PMC_USBSTOPMEM_MASK
) == PMC_USBSTOPMEM_STOP
)
1735 else state
= MV_TRUE
;
1738 #if defined(MV_INCLUDE_AUDIO)
1740 if ((reg
& PMC_AUDIOSTOPMEM_MASK
) == PMC_AUDIOSTOPMEM_STOP
)
1744 else state
= MV_TRUE
;
1747 #if defined(MV_INCLUDE_XOR)
1749 if ((reg
& PMC_XORSTOPMEM_MASK(index
)) == PMC_XORSTOPMEM_STOP(index
))
1753 else state
= MV_TRUE
;
1766 MV_VOID
mvCtrlPwrClckSet(MV_UNIT_ID unitId
, MV_U32 index
, MV_BOOL enable
) {return;}
1767 MV_BOOL
mvCtrlPwrClckGet(MV_UNIT_ID unitId
, MV_U32 index
) {return MV_TRUE
;}
1768 #endif /* #if defined(MV_INCLUDE_CLK_PWR_CNTRL) */
1771 /*******************************************************************************
1772 * mvMPPConfigToSPI - Change MPP[3:0] configuration to SPI mode
1781 ******************************************************************************/
1782 MV_VOID
mvMPPConfigToSPI(MV_VOID
)
1787 if(!mvCtrlIsBootFromSPIUseNAND())
1789 mppVal
= 0x00002220; /* Set MPP [3:1] to SPI mode */
1790 bootVal
= MV_REG_READ(mvCtrlMppRegGet(0));
1791 bootVal
&= 0xffff000f;
1794 MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal
);
1798 /*******************************************************************************
1799 * mvMPPConfigToDefault - Change MPP[7:0] configuration to default configuration
1808 ******************************************************************************/
1809 MV_VOID
mvMPPConfigToDefault(MV_VOID
)
1814 if(!mvCtrlIsBootFromSPIUseNAND())
1816 mppVal
= mvBoardMppGet(0);
1817 bootVal
= MV_REG_READ(mvCtrlMppRegGet(0));
1818 mppVal
&= ~0xffff000f;
1819 bootVal
&= 0xffff000f;
1822 MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal
);